Usage level identification of memory device addresses

Abstract

Methods, systems, and devices for usage level identification of memory device addresses are described. Systems, techniques, and devices are described herein in which a memory device can determine where to store data according to a usage level of the data. The memory device can receive a write command indicating data to be written, a type of the data, and a logical address of a memory array to write the data. The memory device can identify an entry in a table associated with the logical address, the table mapping the logical address to a physical address of the memory array. The entry can include a field configured to maintain a usage level of the logical address. The memory device can update the usage level value according to a process and write the data to the physical address of the memory array based on the usage level value.

Description

[0001] Cross-referencing

[0002] This patent application claims priority to U.S. Patent Application No. 17 / 241,877, filed April 27, 2021, entitled “Use Level Identification for Memory Device Addresses”, which is assigned to the assignee and is expressly incorporated herein by reference in its entirety. Technical Field

[0003] The technical field relates to the use level identifier of memory device addresses. Background Technology

[0004] Memory devices are widely used to store information in various electronic devices such as computers, wireless communication devices, cameras, and digital displays. Information is stored by programming memory cells within the memory device to different states. For example, a binary memory cell can be programmed to one of two supported states, typically corresponding to logic 1 or logic 0. In some instances, a single memory cell can support more than two possible states, and the memory cell can store any of those possible states. To access the information stored by the memory device, a component can read or sense the state of one or more memory cells within the memory device. To store information, a component can write or program one or more memory cells within the memory device to corresponding states.

[0005] Various types of memory devices exist, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), static RAM (SRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase-change memory (PCM), 3D crosspoint memory, NOR (Non-OR), and NAND (NAND) memory devices. Memory devices can be volatile or non-volatile. Volatile memory cells (e.g., DRAM cells) may lose their programmed state over time unless periodically refreshed by an external power supply. Non-volatile memory cells (e.g., NAND memory cells) can maintain their programmed state for a long period of time even without an external power supply. Summary of the Invention

[0006] Describe a device. The device may include a memory device and a controller coupled to the memory device. The controller may be configured such that the device: receives at the device a write command indicating data to be written, the type of data, and a logical address of a memory array for writing the data; identifies a first entry in a table associated with the logical address, the table containing a mapping between logical addresses and physical addresses of the memory array, the first entry containing a first field indicating a usage level of the logical address; sets a value of the first field based on the type of data to indicate the usage level; and writes the data to the physical address of the memory array based on the write command and the set value of the first field.

[0007] A non-transitory computer-readable medium is described. The non-transitory computer-readable medium may store code containing instructions that, when executed by a processor of an electronic device, cause the electronic device to: receive at the electronic device a write command indicating data to be written, the type of data, and a logical address of a memory array for writing the data; identify a first entry in a table associated with the logical address, the table containing a mapping between logical addresses and physical addresses of the memory array, the first entry containing a first field indicating a usage level of the logical address; set a value of the first field based on the type of data to indicate the usage level; and write the data to the physical address of the memory array based on the write command and the set value of the first field.

[0008] Describe a method. The method may include: receiving at a memory device a write command indicating data to be written, a data type, and a logical address of a memory array for writing the data; identifying a first entry in a table associated with the logical address, the table containing a mapping between logical addresses and physical addresses of the memory array, the first entry containing a first field indicating a usage level of the logical address; setting a value of the first field based on the data type to indicate the usage level; and writing the data to the physical address of the memory array based on the write command and the set value of the first field. Attached Figure Description

[0009] Figure 1 This describes an example of a system that supports the use level identification of memory device addresses, as disclosed in the examples herein.

[0010] Figure 2 This describes an instance of a logical-to-physical (L2P) table that supports the use level identifier of memory device addresses, as disclosed in the examples herein.

[0011] Figure 3 This document describes an example of a flowchart illustrating the use level identification of a memory device address, as disclosed herein.

[0012] Figure 4This document describes an example of a flowchart illustrating the use level identification of a memory device address, as disclosed herein.

[0013] Figure 5 This describes an instance of a data log table that supports the use level identification of memory device addresses, as disclosed in the examples herein.

[0014] Figure 6 A block diagram showing a memory device with a usage level identifier that supports memory device addresses, as disclosed in the examples herein.

[0015] Figure 7 The flowchart illustrates one or more methods for supporting the use level identification of memory device addresses, as shown in the examples disclosed herein. Detailed Implementation

[0016] A memory system may contain a subset of memory cells (e.g., in an array) for storing data or other information. Some subsets of the memory array may support relatively higher performance storage and access operations than other portions. For example, a relatively higher performance memory portion may be associated with higher reliability, faster access operations, smaller data sizes, etc., compared to a relatively lower performance memory portion. In one instance, the memory array may contain one or more subsets of single-level cells (SLC) and one or more subsets of multi-level cells (MLC) (e.g., two-level cells, three-level cells (TLC), four-level cells (QLC), or five-level cells (PLC)), wherein the SLC subset supports higher performance storage and access operations than the MLC subset.

[0017] In some cases, a memory device (e.g., a NAND flash memory device or other types of memory devices) may determine the location of data within a memory array based on or in response to the size of the data to be stored. For example, a memory device may determine to write data with a relatively large size to lower-performance memory (e.g., TLC, MLC) and data with a relatively small size to higher-performance memory (e.g., SLC). The memory device may map logical addresses (e.g., logical block addresses (LBAs)) associated with data to physical addresses (e.g., physical block addresses (PBAs)) within the memory array, where physical addresses (e.g., a subset of the memory array) may be based on or in response to the size of the data. However, some logical addresses of the memory device with a higher usage level (e.g., those that may be overwritten more frequently) may be written to lower-performance memory (e.g., based on or in response to the data size). Similarly, some logical addresses with a lower usage level (e.g., those that may not be overwritten so frequently) may be written to higher-performance memory (e.g., based on or in response to the data size). In such cases, relatively frequent writes to lower-performance memory and relatively infrequent writes to higher-performance memory may affect the performance of the memory device.

[0018] As described herein, a memory device may identify the usage level of a logical address, and other aspects, and write data associated with a logical address to higher-performance or lower-performance memory based on or in response to the identified usage level. A logical-to-physical (L2P) mapping table (e.g., mapping logical addresses to physical addresses) may be configured with fields for storing values ​​indicating the usage level. The memory device may determine the usage level and update the fields based on or in response to the type of data (e.g., some types of data may be associated with a higher frequency of overwriting), based on or in response to whether a logical address is mapped or unmapped, based on or in response to the amount of time a logical address has been remapped, or based on or in response to whether a logical address is associated with an open data log (e.g., or a combination thereof), and other instances. The memory device may write data to a certain type of memory (e.g., higher-performance or lower-performance memory) based on or in response to the usage level indicated by the fields in the L2P table. For example, the memory device may determine whether to write data to higher-performance memory in response to determining whether the value indicating the usage level exceeds a threshold.

[0019] First, refer to Figure 1 The features of this disclosure are described within the context of the system. (Referencing...) Figures 2 to 5 The features of this disclosure are described in the context of L2P tables, flowcharts, and data log tables. (See references...) Figures 6 to 7These and other features of this disclosure are further illustrated and described in the context of device diagrams and flowcharts involving the use level identification of memory device addresses.

[0020] Figure 1 This describes an example of a system 100 that supports usage level identification of memory device addresses, as disclosed herein. System 100 includes a host system 105 coupled to a memory system 110.

[0021] The memory system 110 may be or include any device or set of devices, wherein the device or set of devices includes at least one memory array. For example, the memory system 110 may be or include a universal flash memory (UFS) device, an embedded multimedia controller (eMMC) device, a flash device, a universal serial bus (USB) flash device, a secure digital card (SD card), a solid-state drive (SSD), a hard disk drive (HDD), a dual in-line memory module (DIMM), a small form factor DIMM (SO-DIMM), or a non-volatile DIMM (NVDIMM), and other possibilities.

[0022] System 100 may be included in a computing device, such as a desktop computer, laptop computer, web server, mobile device, vehicle (e.g., airplane, drone, train, car or other means of transport), device with Internet of Things (IoT) capability, embedded computer (e.g., embedded computer included in a vehicle, industrial equipment or networked business device), or any other computing device that includes memory and processing means.

[0023] System 100 may include a host system 105 that can be coupled to a memory system 110. In some instances, this coupling may include an interface to a host system controller 106, which may be an instance of a controller or control component configured to cause the host system 105 to perform various operations as described herein. The host system 105 may include one or more devices, and in some cases may include a processor chipset and a software stack executed via the processor chipset. For example, the host system 105 may include an application configured to communicate with the memory system 110 or devices therein. The processor chipset may include one or more cores, one or more caches (e.g., memory native to the host system 105 or included in the host system 105), a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a Peripheral Component Interconnect High Speed ​​(PCIe) controller, a Serial Advanced Technology Attachment (SATA) controller). The host system 105 may use the memory system 110, for example, to write data to and read data from the memory system 110. Although in Figure 1The image shows a memory system 110, but the host system 105 can be coupled to any amount of memory system 110.

[0024] Host system 105 may be coupled to memory system 110 via at least one physical host interface. In some cases, host system 105 and memory system 110 may be configured to communicate via the physical host interface using associated protocols (e.g., to exchange or otherwise convey control, address, data, and other signals between memory system 110 and host system 105). Examples of physical host interfaces may include, but are not limited to, SATA interfaces, UFS interfaces, eMMC interfaces, PCIe interfaces, USB interfaces, Fibre Channel interfaces, Small Computer System Interface (SCSI), Serial Attached SCSI (SAS), Dual Data Rate (DDR) interfaces, DIMM interfaces (e.g., DDR-enabled DIMM sockets), Open NAND Flash Interface (ONFI), and Low Power Dual Data Rate (LPDDR) interfaces. In some instances, one or more of these interfaces may be contained in or otherwise supported between host system controller 106 of host system 105 and memory system controller 115 of memory system 110. In some instances, host system 105 may be coupled to memory system 110 via a corresponding physical host interface for each memory device 130 included in memory system 110 or via a corresponding physical host interface for each type of memory device 130 included in memory system 110 (e.g., host system controller 106 may be coupled to memory system controller 115).

[0025] Memory system 110 may include memory system controller 115 and one or more memory devices 130. Memory device 130 may include one or more memory arrays of any type of memory cells (e.g., non-volatile memory cells, volatile memory cells, or any combination thereof). Although in Figure 1 The example shows two memory devices 130-a and 130-b, but the memory system 110 may contain any number of memory devices 130. Furthermore, if the memory system 110 contains more than one memory device 130, then the different memory devices 130 within the memory system 110 may contain the same or different types of memory cells.

[0026] The memory system controller 115 may be coupled and communicate with the host system 105 (e.g., via a physical host interface) and may be an example of a controller or control component configured to cause the memory system 110 to perform various operations as described herein. The memory system controller 115 may also be coupled and communicate with the memory device 130 to perform operations at the memory device 130 that are generally referred to as access operations, such as reading data, writing data, erasing data, or refreshing data, and other such operations. In some cases, the memory system controller 115 may receive commands from the host system 105 and communicate with one or more memory devices 130 to execute such commands (e.g., at a memory array within one or more memory devices 130). For example, the memory system controller 115 may receive commands or operations from the host system 105 and may translate these commands or operations into instructions or appropriate commands to implement the desired access to the memory device 130. In some cases, the memory system controller 115 may exchange data with the host system 105 and one or more memory devices 130 (e.g., in response to or otherwise in conjunction with commands from the host system 105). For example, the memory system controller 115 may translate responses (e.g., data packets or other signals) associated with the memory device 130 into corresponding signals for the host system 105.

[0027] The memory system controller 115 can be configured for other operations associated with the memory device 130. For example, the memory system controller 115 can perform or manage operations such as wear leveling, garbage collection, error control operations such as error detection or error correction, encryption, caching, media management, background refresh, health monitoring, and address translation between logical addresses (e.g., LBAs) associated with commands from the host system 105 and physical addresses (e.g., PBAs) associated with memory cells within the same memory device 130.

[0028] The memory system controller 115 may include hardware, such as one or more integrated circuits or discrete components, buffer memories, or combinations thereof. The hardware may include circuitry with dedicated (e.g., hard-decoded) logic for performing the operations attributed herein to the memory system controller 115. The memory system controller 115 may be or include a microcontroller, a dedicated logic circuitry (e.g., a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), a digital signal processor (DSP)), or any other suitable processor or processing circuitry.

[0029] The memory system controller 115 may also include local memory 120. In some cases, local memory 120 may include read-only memory (ROM) or other memory that can store operational code (e.g., executable instructions) that can be executed by the memory system controller 115 to perform the functions attributed herein to the memory system controller 115. In some cases, local memory 120 may additionally or alternatively include static random access memory (SRAM) or other memory that can be used by the memory system controller 115 for, for example, internal storage or computation related to the functions attributed herein to the memory system controller 115. Additionally or alternatively, local memory 120 may act as a cache for the memory system controller 115. For example, if data is read from or written to memory device 130, then the data may be stored in local memory 120, and the data may be available within local memory 120 for subsequent retrieval or manipulation (e.g., updating) by the host system 105 according to a caching strategy (e.g., with reduced latency relative to memory device 130).

[0030] although Figure 1 The example of memory system 110 described herein includes memory system controller 115; however, in some cases, memory system 110 may not include memory system controller 115. For example, memory system 110 may additionally or alternatively rely on an external controller (e.g., implemented by host system 105) or one or more local controllers 135, each located within memory device 130, to perform the functions attributed herein to memory system controller 115. Generally, one or more functions attributed herein to memory system controller 115 may, in some cases, be performed by host system 105, local controller 135, or any combination thereof. In some cases, memory device 130, at least partially managed by memory system controller 115, may be referred to as a managed memory device. An example of a managed memory device is a managed NAND (MNAND) device.

[0031] Memory device 130 may include one or more arrays of non-volatile memory cells. For example, memory device 130 may include NAND (e.g., NAND flash) memory, ROM, phase-change memory (PCM), auto-select memory, other chalcogenide-based memories, ferroelectric random access memory (RAM) (FeRAM), magnetic RAM (MRAM), NOR (e.g., NOR flash) memory, spin-transfer torque (STT)-MRAM, conductive bridged RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), electrically erasable programmable ROM (EEPROM), or any combination thereof. Alternatively or additionally, memory device 130 may include one or more arrays of volatile memory cells. For example, memory device 130 may include RAM memory cells, such as dynamic RAM (DRAM) memory cells and synchronous DRAM (SDRAM) memory cells.

[0032] In some instances, memory device 130 may (e.g., on the same die or within the same package) include a local controller 135, which may operate on one or more memory cells of the respective memory device 130. The local controller 135 may operate in conjunction with memory system controller 115, or may perform one or more functions attributed herein to memory system controller 115. For example, such as Figure 1 As described herein, memory device 130-a may include local controller 135-a, and memory device 130-b may include local controller 135-b.

[0033] In some cases, memory device 130 may be or include a NAND device (e.g., a NAND flash device). Memory device 130 may be or include a memory die 160. For example, in some cases, memory device 130 may be a package including one or more dies 160. In some instances, die 160 may be a block of electronic-grade semiconductor diced from a wafer (e.g., a silicon die diced from a silicon wafer). Each die 160 may include one or more planes 165, and each plane 165 may include a corresponding set of blocks 170, wherein each block 170 may include a corresponding set of pages 175, and each page 175 may include a set of memory cells.

[0034] In some cases, the NAND memory device 130 may include memory cells configured to each store one bit of information, which may be referred to as SLC. Alternatively, the NAND memory device 130 may include memory cells configured to each store multiple bits of information; if configured to store two bits of information, it may be referred to as MLC; if configured to store three bits of information, it may be referred to as TLC; if configured to store four bits of information, it may be referred to as QLC, or more generally, a multilevel memory cell. Multilevel memory cells can provide greater storage density compared to SLC memory cells, but in some cases, this may involve narrower read or write margins or greater complexity for supporting circuitry.

[0035] In some cases, plane 165 may refer to a group of blocks 170, and in some cases, parallel operations may occur within different planes 165. For example, memory cells within different blocks 170 can be operated on in parallel, as long as the different blocks 170 are in different planes 165. In some cases, parallel operations in different planes 165 may be subject to one or more limitations, such as performing the same operation on memory cells within different pages 175, which have the same page address within their respective planes 165 (e.g., related to command decoding, page address decoding circuitry, or other circuitry shared across planes 165).

[0036] In some cases, block 170 may contain memory cells organized into rows (page 175) and columns (e.g., strings, not shown). For example, memory cells in the same page 175 may share a common word line (e.g., coupled thereto), and memory cells in the same string may share a common digital line (which may alternatively be called a bit line) (e.g., coupled thereto).

[0037] For some NAND architectures, memory cells can be read and programmed (e.g., written) at a first granularity level (e.g., at the page granularity level), but can be erased at a second granularity level (e.g., at the block granularity level). That is, page 175 may be the smallest unit of memory (e.g., a collection of memory cells) that can be independently programmed or read (e.g., simultaneously programmed or read as part of a single programming or reading operation), and block 170 may be the smallest unit of memory (e.g., a collection of memory cells) that can be independently erased (e.g., simultaneously erased as part of a single erase operation). Furthermore, in some cases, NAND memory cells can be erased before they can be rewritten with new data. Therefore, for example, in some cases, the used page 175 may not be updated until the entire block 170 containing page 175 has been erased.

[0038] In some cases, to update some data within block 170 while retaining other data within block 170, memory device 130 may copy the data to be retained to a new block 170 and write the updated data to one or more remaining pages of the new block 170. Memory device 130 (e.g., local controller 135) or memory system controller 115 may mark or otherwise represent data retained in the old block 170 as invalid or obsolete, and may update the L2P mapping table so that the logical address (e.g., LBA) of the data is associated with the new valid block 170 instead of the old invalid block 170. In some cases, for example, this copying and remapping may be performed due to latency or wear considerations, rather than erasing and rewriting the entire old block 170. In some cases, one or more copies of the L2P mapping table may be stored within memory cells of memory device 130 (e.g., within one or more blocks 170 or plane 165) for use by local controller 135 or memory system controller 115 (e.g., for reference and updating).

[0039] In some cases, an L2P mapping table can be maintained, and data can be marked as valid or invalid at the page granularity level. Page 175 may contain valid data, invalid data, or no data. Invalid data may be outdated data because the latest version or a newer version of the data is stored in a different page 175 of memory device 130. Invalid data may have been previously programmed into an invalid page 175 but may no longer be associated with a valid logical address, such as a logical address referenced by host system 105. Valid data may be the latest version of such data stored on memory device 130. Page 175 that does not contain data may be a page 175 that has never been written to or has been erased.

[0040] In some cases, the memory system controller 115 or the local controller 135 may operate the memory device 130 (e.g., as part of one or more media management processes), such as wear leveling, background refresh, garbage collection, scrubbing, block scanning, health monitoring, or others, or any combination thereof. For example, within the memory device 130, a block 170 may have some pages 175 containing valid data and some pages 175 containing invalid data. To avoid waiting for all pages 175 in block 170 to have invalid data in order to erase and reuse block 170, a process called “garbage collection” may be invoked to allow block 170 to be erased and freed up as a free block for subsequent write operations. Garbage collection may refer to a set of media management operations that include, for example, selecting block 170 containing valid and invalid data, selecting pages 175 in the block containing valid data, copying the valid data from the selected pages 175 to a new location (e.g., a free page 175 in another block 170), marking the data in the previously selected pages 175 as invalid, and erasing the selected block 170. Therefore, the amount of erased blocks 170 can be increased, so that more blocks 170 can be used to store subsequent data (e.g., data subsequently received from the host system 105).

[0041] To access information stored in memory device 130, host system 105 may communicate one or more access commands to memory system 110. Host system 105 may use logical addresses (e.g., LBAs) for the access commands (e.g., to indicate the logical address associated with information), while memory system 110 may use physical addresses (e.g., PBAs) to execute the access commands (e.g., to read information or write information to the memory array). Each logical address and each physical address may be associated with data of the same granularity (e.g., 4kB), and multiple physical addresses may be associated with a page 175. A physical address may refer to the location of a set of memory cells within page 175 (e.g., may be different from the address of block 170).

[0042] Memory system 110 enables the association of logical addresses with physical addresses to execute access commands from host system 105. For address association, memory system 110 may use one or more L2P tables, each indicating a set of logical addresses and their corresponding physical addresses, as described herein and referenced. Figure 2 To describe in more detail. In some instances, the logical addresses in the L2P table can be numerically ordered (e.g., each L2P table can provide a physical address mapping for a set of numerically ordered logical addresses).

[0043] The L2P table used by memory system 110 may be stored in one or more of memory devices 130 (e.g., based on or in response to the size of the L2P table). In some cases, to avoid accessing memory device 130 whenever memory system 110 uses the L2P table for address association (e.g., translation between logical and physical addresses), memory system 110 may move the L2P table from memory device 130 to another location, such as a cache memory, which may have a faster access time than the memory in memory device 130.

[0044] As described herein, each L2P entry in the L2P table may contain a field indicating the usage level of the corresponding logical address (e.g., the frequency of overwrites associated with the logical address). This field may be referred to as a usage level field and may contain an amount of bits used to store a value indicating the usage level associated with the logical address. In some instances, this field may be referred to as a hot / cold field (e.g., an HC field indicating a hot or cold logical address). For each write request received from host system 105, memory system 110 may determine whether to update the usage level field of the indicated logical address. The usage level of the logical address may be determined by the type of data to be written, the mapping status of the logical address (e.g., as indicated by a mapping indication field in the L2P entry), the number of times the logical address has been remapped, whether the logical address is associated with an open data log (e.g., or any combination thereof), and other instances. Memory system 110 may determine whether to write data to higher-performance memory (e.g., SLC) or lower-performance memory (e.g., TLC, QLC, MLC) based on or in response to the value of the usage level field of the corresponding logical address.

[0045] System 100 may contain any amount of non-transitory computer-readable media that supports usage level identifiers for memory device addresses. For example, host system 105, memory system controller 115, or memory device 130 may contain or otherwise access one or more non-transitory computer-readable media that store instructions (e.g., firmware) to perform the functions attributed herein to host system 105, memory system controller 115, or memory device 130. For example, if executed by host system 105 (e.g., by host system controller 106), memory system controller 115, or memory device 130 (e.g., by local controller 135), such instructions may cause host system 105, memory system controller 115, or memory device 130 to perform one or more associated functions as described herein.

[0046] In some cases, memory system 110 may utilize memory system controller 115 to provide a managed memory system, which may include, for example, one or more memory arrays and related circuitry combined with a local (e.g., on-die or in-package) controller (e.g., local controller 135). An example of a managed memory system is a managed NAND (MNAND) system.

[0047] Figure 2 This describes an example of an L2P table 200 that supports the use level identification of memory device addresses, based on examples disclosed herein. Memory devices, such as those mentioned in the references... Figure 1 The described memory device 130 (e.g., one or more components of memory system 110) is capable of receiving a write command indicating data to be written and a logical address of a memory array for writing said data. The memory device can translate logical addresses to physical addresses using a mapping provided by L2P table 200, as generally referenced. Figure 1 As described. L2P table 200 may contain L2P entries 210 corresponding to logical addresses of the memory array. L2P table 200 may also contain one or more other L2P entries 210 corresponding to other logical addresses of the memory array. In some instances, L2P entries 210 may be associated with numerically ordered logical addresses.

[0048] In some cases, each L2P entry 210 may include at least a mapping indicator field 215 and a physical address field 225. Each field may contain a certain number of bits represented by each box within the field. The mapping indicator field 215 may indicate whether a logical address is mapped (e.g., associated with data stored in the memory array, associated with the physical address used). The physical address field 225 may contain a pointer to the physical address associated with the logical address. The number of bits within the physical address field 225 may correspond to the density of the memory array of the memory device (e.g., the amount of available memory within the memory device). The memory device may determine the location for writing data within the memory array based on or in response to fields within the L2P entry 210 corresponding to the logical address and one or more other parameters (e.g., data block size) associated with the logical address.

[0049] A memory array may contain portions of high-performance memory (e.g., SLC) and portions of low-performance memory (e.g., MLC or TLC). High-performance memory, such as SLC, can be associated with higher reliability, faster read and write operations, smaller data sizes, etc., compared to low-performance memory such as MLC or TLC. In some instances, high-performance memory may be available in a smaller quantity within the memory array compared to low-performance memory (e.g., due to higher cost or complexity).

[0050] In some cases, if a memory device receives a write command indicating data to be written and a logical address associated with said data, the memory device can determine the location to write the data (e.g., the mapping between the logical address and the physical address of the memory array) based on or in response to the size of the data to be written (e.g., a write operation). For example, if the write command indicates that a relatively large amount of data is to be written to the array, the memory device can determine to write the data to a lower-performance portion of the memory array, such as TLC or MLC. If the write command indicates that a relatively small amount of data is to be written to the array, the memory device can determine to write the data to a higher-performance portion of the memory array, such as SLC.

[0051] Techniques for mapping logical addresses to physical addresses based on or in response to data size (e.g., block size) may not consider the usage level associated with the logical address (e.g., the frequency of overwrites associated with written data). Thus, in some cases, logical addresses associated with frequently accessed data (e.g., frequently used by a client platform) may be mapped to lower-performance portions of the memory array (e.g., based on or in response to data size), which can increase latency and reduce reliability associated with accessed data. Similarly, in some cases, logical addresses associated with infrequently accessed data (e.g., infrequently used by a client platform) may be mapped to higher-performance portions of the memory array (e.g., based on or in response to data size), which can reduce the amount of storage within higher-performance portions for more frequently accessed data. Relatively frequent writes to lower-performance portions of the memory array and relatively infrequent writes to higher-performance portions can degrade the performance level of the memory device.

[0052] Different types of data can be associated with different usage levels (e.g., some types of data may be overwritten more frequently than others). In some instances, data traffic associated with the daily usage of an average device (e.g., a NAND device) can be organized into three categories: metadata, hot data, and cold data. Metadata (e.g., file system control data) can be overwritten relatively frequently (e.g., corresponding logical addresses between writes that do not unmap to logical addresses). Metadata can be used to define file headers, indexes, or search contents within a storage system, other control data, or combinations thereof. Response times associated with writing to or retrieving data from a storage system can improve as the speed at which metadata is accessed from the storage system increases. Therefore, metadata can be associated with high usage levels (e.g., high overwrite frequency). In some instances, metadata can be associated with a relatively small number of logical addresses (e.g., a small logical address footprint of 300 megabytes (MB)).

[0053] Data that is overwritten relatively frequently, unlike metadata (e.g., associated with a high overwrite statistic), can be called hot data. In some instances, hot data may be associated with more logical addresses than metadata (e.g., a medium or large logical address footprint of 32GB). Other data that may not be overwritten relatively frequently or may not be overwritten at all can be called cold data. For example, some data may not be overwritten until a demapping operation (e.g., an operation that resets one or more logical addresses in response to removed data) resets the mapping state of the logical addresses associated with the data.

[0054] Writing metadata, hot data, or both (e.g., depending on storage space) to a higher-performance portion of a memory array can lead to increased memory device performance due to the relatively high usage levels associated with them. For example, a higher-performance portion of a memory array (e.g., SLC) can be associated with more efficient garbage collection operations compared to a lower-performance portion (e.g., TLC, MLC, QLC, etc.). Storing hot data and metadata in higher-performance memory can result in faster and more reliable data access (e.g., based on or in response to garbage collection) because more frequent garbage collection operations can be performed on the logical addresses associated with the metadata and hot data. However, by determining the location of data writes based on or in response to data size or using one or more other techniques, the memory device may not be able to consider the usage levels associated with the data, which can increase latency and reduce the reliability associated with operations performed by the memory device (e.g., in cases where more frequently rewritten data is stored in lower-performance memory, or vice versa).

[0055] As described herein, a memory device can identify the usage level of a logical address and determine, based on or in response to the usage level and other factors, whether to write data associated with the logical address to higher-performance memory or lower-performance memory. As illustrated in L2P table 200, an L2P entry 210 associated with a logical address may contain a usage level field 220. The usage level field 220, which may be referred to as the HC field, can be configured to store a value indicating the amount (e.g., frequency) of writes or overwrites associated with the logical address (e.g., the number of times the logical address has been remapped). The memory device can determine the location of the data to be written (e.g., the physical address used to write the data) based on or in response to the value of the usage level field 220 corresponding to the logical address within the L2P entry 210.

[0056] The memory device may update the usage level field 220 in response to each write command received for a logical address (e.g., for the corresponding L2P entry 210). For example, if the memory device receives a write command, it may determine the data type indicated in the write command, the mapping state associated with the logical address indicated in the write command, the alignment of the logical address with a data range or data log within the memory array, or a combination thereof, which may represent one or more parameters associated with the logical address. The memory device may utilize one or more procedures to determine the value of the usage level field 220, or to determine whether to change the value. The procedures may include one or more parameters associated with the logical address. The memory device may then perform a write operation using the updated L2P entry 210 and the value of the usage level field 220. In some instances, the memory device may not access the L2P entry 210 while servicing or performing a write command, and the memory device may update the usage level field 220 after (e.g., in response to) a write procedure. In such cases, the memory device can use the updated L2P entry 210 and the updated value of the usage level field 220 for subsequent write operations. (See also: [link to document]). Figure 3 and 4 Describe in more detail one or more procedures used to determine the level value.

[0057] Use level field 220 may contain a set of bits for transmitting overwrite information associated with a logical address. Although use level field 220 is described as containing four data bits, it should be understood that use level field 220 may contain any number of bits. The number of bits in use level field 220 may be determined by the density of the corresponding memory array, the number of bits in physical address field 225 used to transfer the pointer to the physical address, the size of L2P entry 210, or any combination thereof. In some instances (e.g., in memory devices with relatively high memory density), the number of bits in physical address field 225 may be greater than [a certain value]. Figure 2 The 11 bits described herein, and the number of bits within the level field 220 can be less than Figure 2 The four bits described herein (e.g., one, two, or three bits). Alternatively, if the memory device is associated with a relatively low memory density, the number of bits in the physical address field 225 may be reduced, and the number of bits in the usage level field 220 may be increased (e.g., five bits, nine bits). In some instances, the number of bits in the L2P entry 210 may be greater than or less than Figure 2 The 16 bits described herein. In some instances, the mapping indicator field may contain one or more bits indicating whether a logical address is mapped or unmapped.

[0058] The memory device may use one or more procedures and corresponding parameters associated with a logical address to determine whether to maintain the value of the usage level field 220, increment the value, decrement the value, or set each bit in the field to high or low (e.g., set the value to a maximum or minimum value). For example, if the memory device determines that the type of data indicated in the write command is metadata, forced cell access (FUA) data, or other priority-ordered data, then the memory device may set each bit in the usage level field 220 to high (e.g., a value '1') to indicate a relatively high usage level associated with the data. If the memory device determines that the logical address has been unmapped (e.g., setting the value of the mapping indication field 215 to low, or a value '0'), then the memory device may set each bit in the usage level field 220 to low (e.g., a value '0') to indicate a relatively low (e.g., zero) usage level associated with the data (e.g., because the logical address has been unmapped, the memory device may assume that the logical address has not yet been written). If the memory device determines that the data is not priority data and maps to a logical address (e.g., setting the value of the mapping indication field 215 low), then the memory device may increment the value of the usage level field 220 (e.g., incrementing the value of the bit transfer within said field by one). Reference Figure 3 and 4 Other methods for determining the level value are described in more detail.

[0059] The memory device can use the value transmitted in the usage level field 220 of L2P entry 210 to determine the location where data is stored (e.g., written). For example, if the bits in the usage level field are each set to low (e.g., in...), Figure 2 In an example, the bit can be set to '0000', which can indicate a usage level value of zero. Then the usage level value can indicate that a logical address may be rarely or never overwritten (e.g., a logical address may be associated with cold data). Therefore, the memory device can write the corresponding data to a lower-performance memory. If the bits in usage level field 220 are each set to high (e.g., in...),... Figure 2 In some instances, the bit can be set to '1111', which indicates a usage level value of 15. This usage level value indicates that the logical address can be frequently overwritten (e.g., associated with hot content, metadata, FUA data, or other prioritized data). The memory device can then write the corresponding data to higher-performance memory. In some instances, any non-zero value of the usage level field 220 indicates hot data, and in some instances, any value of the usage level field 220 exceeding a threshold indicates hot data.

[0060] Larger bits within the usage level field 220 can correspond to a higher granularity used to indicate hot data than smaller bits. For example, if the usage level field 220 contains one bit, it can indicate hot data when a bit is set (e.g., a relatively large footprint or chunk size for hot data, such as approximately 16 GB or more) and cold data when no bit is set. This reduces the granularity (e.g., accuracy level) associated with determining the usage level. If the usage level field 220 contains three bits, the usage level can deliver increased granularity compared to a single bit, providing a more accurate distinction between hot and cold data (e.g., this can provide a smaller footprint or chunk size associated with hot data, such as approximately 4 GB or less).

[0061] In some instances, memory devices may use thresholds to determine where data is written. For example, any logical address associated with a usage level field 220 that has a value that meets the threshold (e.g., at or above the threshold) may be considered a hot logical address and may be associated with higher-performance memory. Similarly, any logical address associated with a value below the threshold may be considered a cold logical address and may be associated with lower-performance memory.

[0062] The threshold can be configured based on the amount of available space (e.g., the amount of available physical addresses in the memory array). For example, the threshold can be based on or in response to the amount of space available within the higher-performance memory of the memory array (e.g., the amount of available SLC blocks), the amount of hot content generated (e.g., generated by the user during operation of the memory device), or both. The amount of available high-performance memory space can change during operation of the memory device in response to the amount of hot content written to the high-performance memory array, and the memory device can therefore dynamically change the threshold. The memory device can be configured with a relatively high starting threshold (e.g., each bit set to one), and the memory device can change (e.g., decrease) the threshold as the amount of available space changes.

[0063] If the memory device updates the usage level field 220 in response to a write command and subsequently identifies that the value transmitted by the usage level field 220 meets (e.g., equals or exceeds) a threshold, then the memory device may write the corresponding data to the higher-performance portion of the memory array. If the value transmitted by the usage level field 220 does not meet the threshold, then the memory device may write the corresponding data to the lower-performance portion of the memory array. In one example, the threshold may be set to a value of 14 (e.g., '1110'), and if the value transmitted by the usage level field is greater than or equal to 14 (e.g., greater than or equal to '1110'), then the memory device may write data to high-performance memory.

[0064] In some instances, if a memory device writes hot data or metadata to higher-performance memory, the hot data or metadata can remain in the higher-performance memory during one or more garbage collection operations. For example, if the usage level field associated with the corresponding logical address is relatively high (e.g., at or above a threshold), the memory device can keep the data within the higher-performance portion of the memory array for the entire lifetime of the data (e.g., until the corresponding logical address is unmapped), which improves the reliability of write data stored within the memory array.

[0065] Therefore, the memory device can maintain usage level information (e.g., write frequency information) associated with logical addresses by updating the field configured as usage level field 220 in L2P table 200. The memory device can determine whether to write data to a higher-performance portion or a lower-performance portion of the memory array based on the value of usage level field 220, which can provide efficient utilization of high-performance memory and improved reliability associated with the operation of the memory device.

[0066] Figure 3 This illustrates an example of flowchart 300 supporting the use level identification of memory device addresses, as disclosed herein. Flowchart 300 can perform operations on a memory device (e.g., one or more components of a memory system) in response to receiving a command, as referenced... Figures 1 to 2 As described. Flowchart 300 illustrates the operations performed by the memory device according to the first process to determine a value associated with the usage level of a logical address. The usage level value may be stored in a usage level field within an L2P entry, as shown in the reference. Figure 2 As described.

[0067] In some instances, the first process may be applied (e.g., configured for) one or more file systems (e.g., an EXT4 file system or another type of file system) to the storage device. The file system may operate according to the write pattern of the storage device. For example, the storage device may create a file to store data by allocating metadata to the file (e.g., an inode, index, data pre-allocation, or a combination thereof), and the storage device may write or overwrite data to the file (e.g., the file's contents). If the file is removed, the storage device may perform an unmapping operation to unmap and release the corresponding logical address (e.g., unmapping and reusing the logical address associated with the file's contents). In some instances, the file system may delay or predict write operations. For example, some file systems (e.g., an F2FS file system) may predict operations such as data write operations (e.g., before metadata updates).

[0068] Aspects of flowchart 300 may be implemented by a controller and other components. Alternatively, aspects of flowchart 300 may be implemented as instructions stored in memory (e.g., firmware stored in memory coupled to a memory device). For example, the instructions, when executed by a controller (e.g., local controller 135), may cause the controller to perform the operations of flowchart 300.

[0069] Alternative instances of flowchart 300 may be implemented, in which some operations are performed in a different order than described or not at all. In some cases, operations may include features not mentioned below, or additional operations may be added.

[0070] At 305, an access command is received. For example, the memory device may receive the access command from a host system. The access command may be received at the controller of the memory device or another component. At 310, it may be determined whether the command is a write command. In some instances, at 315, another operation may be performed based on or in response to determining that the command is not a write command. For example, the memory device may perform a read operation or an unmapping operation, the unmapping operation may include unmapping a logical address (e.g., if the file previously mapped to the logical address has been removed), and setting a mapping indicator field in the corresponding L2P entry to indicate the unmapping logical address.

[0071] At 320, if the storage device determines that the command is a write command, it can determine whether the data is metadata. In some instances, the storage device can identify the metadata flag within the issued write command and determine whether the metadata flag is set (e.g., in SCSI write operations, such as SCSI WRITE_10 or WRITE_16 operations, the storage device can determine whether the SYSTEM_DATA_TAG group ID number is set). At 325, if the storage device determines that the data is metadata (e.g., based on or in response to determining that a metadata flag is set), it can set the value of the usage level field to high. For example, the storage device can set each bit in the usage level field of the L2P table to high (e.g., the value '1') to indicate that the data is metadata (e.g., frequently accessed data).

[0072] At 330, if the memory device determines that the data is not metadata (e.g., other priority-ordered data), it can determine whether to unmap the logical address. For example, the memory device can identify whether to set one or more bits of the mapping indicator field in the L2P entry for the logical address (e.g., whether one or more bits of the mapping indicator field indicate mapping or unmapping of the logical address).

[0073] At 335, if the memory device determines that a logical address has been unmapped, the usage level value can be set to zero by setting each bit in the usage level field of the L2P entry to low (e.g., the value '0'). The memory device can set the usage level value to zero to indicate that a logical address has not yet been written to (e.g., because the logical address has been unmapped).

[0074] At 340, if the memory device determines the mapped logical address, the usage level value can be incremented from a first value to a second value. For example, the memory device can increment a bit of the usage level field (e.g., the HC bit) by one (e.g., or some other amount). The memory device can increment the usage level value to indicate that the data associated with the logical address will be remapped during the current write operation (e.g., after it has been previously mapped).

[0075] At 345, it can be determined whether the usage level value has overflowed. For example, the memory device can determine whether the usage level value has overflowed by determining whether the usage level value is greater than a value (e.g., the maximum value) that can be transmitted by the set of bits in the usage level field of the L2P entry. For example, if the number of bits in the usage level field is four, then the transmittable value is 15 (e.g., '1111'), and any value higher than 15 (e.g., '1111') can be considered to overflow, and the memory device can proceed to 325.

[0076] At 325, if the usage level value has overflowed, the usage level value can be set high (e.g., setting each bit in the field to high). In one instance, if the bit value in the usage level field is four and the usage level value is greater than 15 (e.g., '1111'), the memory device can determine that the usage level value has overflowed, and the memory device can set the usage level value to 15 (e.g., '1111') by setting each bit in the usage level field to high. In some instances, at 325, the memory device can indicate that the value of the usage level field is set high, and the memory device can maintain the value (e.g., '1111').

[0077] At 350, a flag can be set to update the L2P entry. The memory device can set the flag to update the usage level field within the L2P entry based on a value determined using the first process. In one instance, the memory device can set the flag to update the L2P entry with a usage level value of zero in response to determining that a logical address is unmapped at 330. In another instance, the memory device can set the flag to update the L2P entry with a high usage level value (e.g., the maximum value) in response to determining that data is metadata at 320 or that the usage level value overflows at 345. In yet another instance, the memory device can set the flag to update the L2P entry with another usage level value in response to incrementing the usage level value at 340 and determining that the usage level value has not overflowed at 345.

[0078] At position 355, a write operation can be performed based on the L2P entry and the corresponding usage level value. The memory device can determine the location of the data to be written based on or in response to the usage level value, as shown in the reference. Figure 2 As described. For example, if the usage level value meets the threshold, then the memory device can write data to the higher-performance portion of the memory array (e.g., the memory device can map a logical address to a physical address within the higher-performance portion of the memory array), and if the usage level value does not meet the threshold, then the memory device can write data to the lower-performance portion of the memory array (e.g., the memory device can map a logical address to a physical address within the lower-performance portion of the memory array).

[0079] At 360, the L2P entry can be updated in response to a flag set at 350. The memory device can update the value of the usage level field of the L2P entry according to the flag set at 350. In some instances, the L2P entry may not be available to the memory device while it is being serviced or a write command is being executed (e.g., after receiving a write command). Therefore, the L2P entry can be updated once after a write command is executed at 355. In some instances, the memory device can refer to the updated L2P entry and the corresponding usage level value for subsequent write procedures.

[0080] Therefore, a memory device can determine a usage level value associated with a logical address and map the logical address to a physical address based on or in response to the usage level. This improves the reliability of the data stored in the memory device and reduces latency compared to memory devices that map logical addresses based on or in response to data block size and other technologies.

[0081] Figure 4This illustrates an example of a flowchart 400 supporting the identification of usage levels for memory device addresses, as disclosed herein. Flowchart 400 may illustrate operations performed by a memory device (e.g., one or more components of a memory system) according to a second process to determine values ​​associated with the usage level of a logical address. (Except for reference...) Figure 3 In addition to or as an alternative to the first process described herein, the storage device may utilize a second process. The second process may be applicable (e.g., configured for) a second type of file system on the storage device (e.g., an F2FS file system, an EXT4 file system configured with file pre-allocation, or other types of file systems). For example, the second process may fully utilize a journaling system that the storage device can use for a second type of file system. See also the following: Figure 5 The journaling system is described in more detail. It should be understood that the second process may be applicable to (or used by) one or more other types of file systems not described or illustrated herein.

[0082] Aspects of flowchart 400 may be implemented by a controller and other components. Alternatively, aspects of flowchart 400 may be implemented as instructions stored in memory (e.g., firmware stored in memory coupled to a memory device). For example, the instructions, when executed by a controller (e.g., a local controller 135 of memory device 130), may cause the controller to perform the operations of flowchart 400.

[0083] Alternative instances of flowchart 400 may be implemented, in which some operations are performed in a different order than described or not at all. In some cases, operations may include features not mentioned below, or additional operations may be added.

[0084] At 405, an access command is received. For example, the memory device may receive the access command from a host system. The access command may be received at the memory device's controller or another component. At 410, it may be determined whether the command is a write command. In some instances, at 415, in response to determining that the command is not a write command, another operation may be performed. For example, if the command is an unmapping command, the memory device may perform an unmapping operation, which may include unmapping a logical address (e.g., if the file previously mapped to the logical address has been removed), and setting a mapping indicator field in the corresponding L2P entry to indicate the unmapping logical address. If the command is a read command, the memory device may read data from the memory array.

[0085] At 420, if the command is a write command, it can be determined whether the data is priority data, such as metadata, FUA, other priority data, or a combination thereof. In some instances, the storage device can identify the metadata flag within the issued write command and determine whether the metadata flag is set (e.g., in SCSI write operations, such as SCSIWRITE_10 or WRITE_16 operations, the storage device can determine whether the SYSTEM_DATA_TAG group ID number is set). Alternatively, the storage device can determine whether the write command instructs the setting of the FUA flag (e.g., in some file systems, the FUA flag may indicate whether the data will be stored directly in MNAND memory at the file system's write checkpoint). At 425, if the data is priority data, the usage level value can be set to high. For example, the storage device can set each bit in the usage level field of the L2P table to high (e.g., a value '1') to indicate that the data is priority data (e.g., frequently accessed data).

[0086] At 430, if the memory device determines that the data is not priority data, it can determine whether a logical address (e.g., LBA) is aligned with the data range. For example, the memory device can identify the end position of a logical address within the memory array of the logical address, and the memory device can determine whether the end position of the logical address is at or before the end of a data block within the data range (e.g., a 2MB data block, or some other data block size that can be configured as a data log within a second type of file system).

[0087] Determining whether a logical address is aligned with a data range based on or in response to a second process can reduce latency, processing resources, and power consumption for memory devices operating according to a second type of file system (e.g., F2FS, EXT4 with file pre-allocation, or other file systems). For example, such file systems can be configured to support file system logs that can be sequential data streams. The file system can store data within allocated segments (e.g., data ranges or data blocks) until the segment is full. The file system can store remaining data within the next segment associated with a sequential logical address. By determining whether a logical address is aligned with one of the data ranges (e.g., identifying and tracking write points within the file system), the memory device (e.g., the flash transition layer (FTL) of the memory device) can identify hot data from newly written data (e.g., cold data), and the memory device can avoid checking the mapping indicator field within the corresponding L2P entry for each write command, which reduces processing.

[0088] At 435, if the memory device determines that the logical address is not aligned with the data range (e.g., the end of the logical address is after the end of the data range), then it can determine whether the logical address is immediately adjacent to (e.g., adjacent to) the open data log within the file system. For example, the memory device can determine whether the logical address is the next sequential logical address in the open data log of the memory array (e.g., within the sequential log of the corresponding file system logical address). Relative to Figure 5 A more detailed description of the sequential log of logical addresses.

[0089] At 440, if the memory device determines that the logical address is the next sequential logical address for the open data log (e.g., an open log session within a file system), then the usage level value can be set to zero and the open data log can be updated. The memory device can use the update log function to update the open data log, which can update the open data log using the logical address and data size.

[0090] At 445, if the memory device determines that the logical address is aligned at or before the end of the data range, it can determine whether to unmap the logical address. The memory device can identify whether one or more bits of the mapping indicator field within the L2P entry used for the logical address are set to determine whether to unmap the logical address. The memory device can avoid checking the mapping indicator field within the L2P entry for every write command by determining whether the logical address is aligned with the data range at 430, which reduces processing and latency. In one example, if the data range is 2MB, the memory device can check the mapping indicator field for an average of one logical address out of every 512 logical addresses written (e.g., occurring in 0.2% of cases).

[0091] At 450, if the memory device determines to unmap a logical address, the usage level value can be set to zero (e.g., setting every bit in the usage level field to low), and a new data log can be opened for the memory array. The memory device can set the usage level value to zero to indicate that data has not yet been written to the logical address (e.g., because the logical address has been unmapped). The memory device can then perform an open logging function to open a new data log. The open logging function sets the logical address of the new data log to the logical address associated with the data to be written, allowing the memory device to write data to the new data log.

[0092] At 455, if the memory device determines that a mapped logical address is already included in the open data log, as determined at 445, or if the memory device determines that the logical address is not immediately adjacent to the open log (e.g., at 435), then the usage level value can be incremented from a first value to a second value. For example, the memory device can increment a bit in the usage level field (e.g., the HC bit) by one (e.g., or some other amount). The memory device can increment the usage level value to indicate that the logical address associated with the open data log will be remapped during the current write operation after it was previously mapped.

[0093] At 460, it can be determined whether the usage level value has overflowed. The memory device can determine whether the usage level value has overflowed by determining whether it is greater than a value (e.g., the maximum value) that can be transmitted by the set of bits in the usage level field of the L2P entry. For example, if the number of bits in the usage level field is four, then the transmittable value is 15 (e.g., '1111'). If the usage level value has overflowed, the memory device can proceed to 425.

[0094] At 425, if the usage level value has overflowed, the usage level value can be set to high (e.g., setting each bit in the field to high). In one instance, if the number of bits in the usage level field is four and the usage level value is greater than 15 (e.g., '1111'), the memory device can determine that the usage level value has overflowed, and the memory device can set the usage level value to 15 (e.g., '1111') by setting each bit in the usage level field to high. In some instances, at 425, the memory device can identify that the value of the usage level field is set to high (e.g., the maximum value), and the memory device can maintain said value.

[0095] At 470, a flag can be set to update the L2P entry. The memory device can set the flag to update the usage level field within the L2P entry based on or in response to a value determined using the second process. In one instance, the memory device can set the flag to update the L2P entry using a usage level value in response to determining that a logical address is unmapped or that a logical address is adjacent to an open data log. In another instance, the memory device can set the flag to update the L2P entry using a higher usage level value in response to determining that the data is priority data or that the usage level value overflows. In yet another instance, the memory device can set the flag to update the L2P entry using another usage level value in response to incrementing the usage level value at 455 and determining at 460 that the usage level value has not overflowed.

[0096] At position 475, a write operation can be performed based on the L2P entry and the corresponding usage level value. The memory device can determine the location of the data to be written based on or in response to the usage level value, as shown in the reference. Figure 2As described. For example, if the usage level value meets the threshold, then the memory device can write data to the higher-performance portion of the memory array (e.g., the memory device can map a logical address to a physical address within the higher-performance portion of the memory array), and if the usage level value does not meet the threshold, then the memory device can write data to the lower-performance portion of the memory array (e.g., the memory device can map a logical address to a physical address within the lower-performance portion of the memory array).

[0097] At 480, the L2P entry can be updated in response to the flag set at 470. The memory device can update the value of the usage level field of the L2P entry according to the flag set at 470. In some instances, the L2P entry may not be available to the memory device while a write command is being executed (e.g., after receiving a write command). Therefore, the L2P entry can be updated only once after a write command is executed at 475. In some instances, the memory device can refer to the updated L2P entry and the corresponding usage level value for subsequent write procedures.

[0098] Therefore, a memory device can determine a usage level value associated with a logical address based on or in response to one or more parameters associated with the logical address. The memory device can map logical addresses to physical addresses based on or in response to usage levels, which improves the reliability and reduces latency compared to memory devices that map logical addresses based on or in response to data block size or other techniques. Alternatively, by determining whether a logical address is aligned with a block of the memory array (e.g., a sequential range or stream of data within the memory array), the memory device (e.g., the memory device's FTL engine) can avoid checking L2P entries after each write command to determine whether a corresponding logical address is mapped, which provides reduced latency and power consumption.

[0099] Figure 5 This describes an instance of a data log table 500 that supports the usage level identification of a memory device address, as disclosed herein. The data log table 500 may be maintained by a memory device (e.g., one or more components of a memory system) operating according to a second type of file system (e.g., a file system that can utilize a data logging mechanism), as referenced... Figure 4 As described. The memory device may update one or more entries in the data log table 500 in response to one or more of the methods described with reference to the second process and flowchart 400.

[0100] For reference Figure 4As described, some file systems (e.g., F2FS, Verilog file system, or other file systems) can utilize a journaling system where data can be written to files using sequential data journals. Each data journal can be a sequential data stream, and the file system can maintain a certain amount of data journals at a time (e.g., six or some other amount). If data is being written, the memory device can write data to the first data journal of the file system until the data journal is full, at which point the memory device can close the first data journal and open a new data journal within the file system, or switch to an already opened data journal. The end logical address of the first data journal can be immediately adjacent to the sequential logical address of the new or opened data journal. The memory device can therefore write the remaining data to the new or opened data journal. The data journal can contain allocated data segments (e.g., 2MB of data, or data blocks of some other size). In some instances, each data journal within the memory system can contain the same data block size.

[0101] As described herein, the memory device and the corresponding file system within the memory device may maintain a data log table 500, which may contain a list of open data logs (e.g., logs opened by the file system during the file system's operating mode). The data log table 500 may contain a first list 505 of log indices and a second list 510 of the end logical address of each corresponding open data log. Each log index entry in the first list 505 may indicate the start logical address (e.g., LBA) of the corresponding data log, the data log size, or both. Each end logical address entry in the second list 510 may indicate the end logical address of the last write operation performed on the corresponding data log.

[0102] For reference Figure 4 As described, a memory device can reduce processing and power consumption by identifying whether data is hot data or newly written data (e.g., cold data) by aligning a logical address with one of the data ranges within a file system. For example, by identifying newly written data in response to determining that the end of the logical address associated with the data is at or after the data range, and by determining that the logical address is immediately adjacent to the sequential logical address of the opened data log (e.g., the logical address is associated with the beginning of the data log), the memory device can avoid checking the mapping indicator field of the corresponding L2P entry, which reduces latency and processing by the memory device.

[0103] The entries in the first list 505 and the second list 510 of the data log table 500 can be updated in response to one or more functions performed by the memory device. The memory device can update the data log table 500 during operation according to the second process, as shown in reference... Figure 4As described. For example, a memory device may open a new data log, update an existing data log (e.g., with a new logical address and a new data size), close a data log, or perform one or more other operations to manage the data log within the file system.

[0104] In one example, referring to flowchart 400, at 450, the memory device may perform an open data log function in response to determining an unmapped logical address. The open data log function (e.g., OpenLog(lba, block)) may instruct the memory device (e.g., the memory device's file system) to determine the size of the data log table 500 (e.g., the number of entries in the first list 505 and the second list 510), and enter a new log index entry in the first list 505 to indicate the index of the new data log to be opened (e.g., the index may be set to the logical address of the data to be written divided by the size of the data log). The open data log function may instruct the memory device to enter a new end logical address entry associated with the new log index entry in the second list 510. The memory device may set the new end logical address entry to a value equal to the start logical address of the data to be written, in addition to the size of the data to be written. The open data log function may increment the size of the data log table 500 by one after entering the new data log entry.

[0105] In another example, referring to flowchart 400, at 435 and 440, the memory device may perform an update data log function to determine whether the logical address of the data to be written is adjacent to the open data log, and update the open data log in response to determining that the logical address is adjacent to the sequential logical address of the open data log. The update data log function (e.g., UpdateLog(lba, block)) may instruct the memory device to calculate the log index of the open data log (e.g., the memory device may calculate the log index as the base value of the data to be written divided by the size of the data log). The update function may instruct the memory device to iterate through data log table 500 to determine whether the log index of the open data log is in the first list 505 and whether the end logical address in the second list 510 corresponding to the log index of the open data log is the same as the logical address of the data to be written. In response to determining that the logical address is adjacent to the end logical address of the open data log, the function may instruct the memory device to update the end logical address entry in the second list 510 to a value equal to the logical address of the data to be written, in addition to the size of the data to be written (e.g., LogTable[i].last_written_lba = lba + block).

[0106] In some instances, the memory device can disable the data logging function to close the data logging and unmap the logical addresses associated with the data log. The update log function can instruct the memory device to determine if the data log is full (e.g., the memory device can determine if the modulus of the last written logical address of the table divided by the size of the data log is zero). If the data log is full, the update log function can instruct the memory device to disable the data logging function. Disabling the data logging function (e.g., CloseLog(log, index)) can instruct the memory device to reduce the size of the data log table 500 by one (e.g., LogTable.size = LogTable.size - 1) and delete the last log index entry in the first list 505 and the last ending logical address entry in the second list 510.

[0107] Therefore, the memory device and corresponding file system can utilize data logs associated with sequential logical addresses to store data within the memory array. The memory device can determine the location to write data within the memory array in response to a comparison between the logical address associated with the data and the data range (e.g., block size) within each sequential data log. Unless the logical address and data range are aligned, the memory device can avoid checking L2P entries for corresponding logical addresses, which reduces the processing and power consumption of the memory device.

[0108] Figure 6 A block diagram 600 illustrates a memory device 620 (e.g., one or more components of a memory system) that supports memory device address usage level identification according to examples disclosed herein. The memory device 620 may be as described in the references... Figures 1 to 5 Examples of aspects of the described memory device. Memory device 620 or its various components may be examples of various aspects of components used for use level identification of memory device addresses, as described herein. For example, memory device 620 may include write command component 625, mapping component 630, use level component 635, write component 640, data type identifier 645, data alignment identifier 650, data log component 655, or any combination thereof. Each of these components may communicate with each other directly or indirectly (e.g., via one or more buses).

[0109] Write command component 625 may be configured or otherwise supported to receive a write command indicating data to be written, the type of data, and a logical address of the memory array for writing the data. Mapping component 630 may be configured or otherwise supported to identify a first entry associated with a logical address in a table containing a mapping between logical and physical addresses of the memory array, the first entry containing a first field indicating the usage level of the logical address. Usage level component 635 may be configured or otherwise supported to set the value of the first field based on the type of data to indicate the usage level. Write component 640 may be configured or otherwise supported to write data to the physical address of the memory array based on a write command and setting the value of the first field.

[0110] In some instances, to support setting the value, the level component 635 can be configured or otherwise supported to support a component for setting the first value of the first field based on the data's type as a first type of data. In some instances, the first type of data contains metadata or priority-ordered data. In some instances, the first field contains a set of bits indicating the level of use, and the first value contains a value of one for each bit in the set.

[0111] In some instances, the data type identifier 645 may be configured or otherwise supported to enable a component for determining whether to unmap a logical address based on a first type of data that is different from data containing metadata or priority ordering, wherein the determination of whether to unmap a logical address is based on the value of a second field of the first entry.

[0112] In some instances, to support setting the value, the level component 635 can be configured or otherwise supported to set the value of the first field to zero based on determining the unmapping logical address.

[0113] In some instances, to support setting the value, the level component 635 can be configured or otherwise supported to support a component for identifying that the first field has a first value. In some instances, to support setting the value, the level component 635 can be configured or otherwise supported to support a component for incrementing the first value to a second value based on a determined mapping logical address.

[0114] In some instances, to support setting the value, the level component 635 may be configured or otherwise supported to support means for identifying that the first field has a first value based on a determined mapped logical address. In some instances, to support setting the value, the level component 635 may be configured or otherwise supported to support means for maintaining the first value of the first field based on the identification that the first field has a first value. In some instances, the first field contains a set of bits for indicating the level of use, and the first value contains a value of one for each bit of the set.

[0115] In some instances, the data alignment identifier 650 may be configured or otherwise supported as a means for determining the end position of a logical address relative to the end of a first block of the memory array, the first block having a first size, wherein determining whether to unmap the logical address is based on determining that the end position of the logical address is at or before the end of the first block.

[0116] In some instances, the data log component 655 may be configured or otherwise support a component for opening a new data log of the memory array based on determining an unmapped logical address and the logical address ending at or before the end of the first block, wherein the logical address is associated with the new data log.

[0117] In some instances, the usage level component 635 may be configured or otherwise supported to include a component for determining whether a usage level meets a threshold, wherein the value of the threshold is a quantity based on the available physical addresses of the memory array.

[0118] In some instances, to support write operations, write component 640 may be configured or otherwise support components for writing data to a first portion of the memory array based on a determined usage level that meets a threshold, wherein the first portion of the memory array contains physical addresses and is associated with a first reliability level that is higher than a second reliability level associated with a second portion of the memory array.

[0119] In some instances, to support write operations, write component 640 may be configured or otherwise support components for writing data to a second portion of the memory array based on a determination that a usage level has failed to meet a threshold, wherein the second portion of the memory array contains physical addresses and is associated with a second reliability level that is lower than the first reliability level associated with the first portion of the memory array.

[0120] In some instances, the data alignment identifier 650 may be configured or otherwise supported to include means for determining the end position of a logical address relative to the end of a first block of the memory array, the first block having a first size. In some instances, the data log component 655 may be configured or otherwise supported to include means for determining whether a logical address is the next sequential logical address of an open data log of the memory array based on the determination that the end position of the logical address is after the end of the first block.

[0121] In some instances, to support setting the value, the level component 635 may be configured or otherwise supported to support a component for setting the first field to zero based on determining that the logical address is the next sequential logical address for opening the data log. In some instances, to support setting the value, the data log component 655 may be configured or otherwise supported to support a component for updating the open data log using the logical address and the size of the data based on determining that the first field is zero.

[0122] In some instances, to support setting the value, the level component 635 can be configured or otherwise supported to support a component for identifying that the first field has a first value. In some instances, to support setting the value, the level component 635 can be configured or otherwise supported to support a component for incrementing the first value to a second value based on determining that the logical address is different from the next sequential logical address of the opened data log.

[0123] In some instances, to support setting the value, the level component 635 can be configured or otherwise supported to support a component for identifying that the first field has a first value based on determining that the logical address is different from the next sequential logical address of the opened data log. In some instances, to support setting the value, the level component 635 can be configured or otherwise supported to support a component for maintaining the first value of the first field based on identifying that the first field has a first value.

[0124] Figure 7 The flowchart illustrates a method 700 for supporting the use level identification of memory device addresses according to examples disclosed herein. The operation of method 700 may be implemented by a memory device (e.g., one or more components of a memory system) or its components as described herein. For example, it may be implemented by, as referenced... Figures 1 to 6 The described memory device performs the operation of method 700. In some instances, the memory device may execute a set of instructions to control the functional elements of the device to perform the described functions. Alternatively, the memory device may use dedicated hardware to perform aspects of the described functions.

[0125] At 705, the method may include receiving a write command indicating data to be written, the type of data, and a logical address of the memory array for writing the data. Operation of 705 may be performed according to examples disclosed herein. In some instances, aspects of operation of 705 may be as described in the references... Figure 6 The write command component 625 is described.

[0126] At 710, the method may include a first entry in an identification table associated with a logical address, the table containing a mapping between logical addresses and physical addresses of the memory array, the first entry containing a first field indicating the usage level of the logical address. Operation of 710 may be performed according to examples disclosed herein. In some instances, aspects of operation of 710 may be as described in references... Figure 6 The mapping component 630 described is used.

[0127] At point 715, the method may include setting the value of a first field based on the data type to indicate the usage level. The operation of point 715 can be performed according to examples disclosed herein. In some instances, aspects of the operation of point 715 may be as described in the references... Figure 6 The described usage level component 635 is used.

[0128] At 720, the method may include writing data to a physical address of the memory array based on a write command and setting the value of a first field. Operation at 720 may be performed according to examples disclosed herein. In some instances, aspects of operation at 720 may be as described in the references... Figure 6 The writing component 640 described herein is used.

[0129] In some instances, the device as described herein may perform one or more methods, such as method 700. The device may include features, circuitry, logic, components, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for performing the following operations: receiving a write command indicating data to be written, the type of data, and a logical address of a memory array for writing the data; identifying a first entry in a table associated with the logical address, the table containing a mapping between logical addresses and physical addresses of the memory array, the first entry containing a first field indicating the usage level of the logical address; setting the value of the first field based on the type of data to indicate the usage level; and writing the data to the physical address of the memory array based on the write command and the set value of the first field.

[0130] In some instances of the method 700 and apparatus described herein, setting the value may include operations, features, circuit systems, logic, components, or instructions for setting a first value of a first field based on the data type being a first type of data. In some instances of the method 700 and apparatus described herein, the first type of data includes metadata or priority-ordered data. In some instances of the method 700 and apparatus described herein, the first field includes a set of bits indicating a usage level, and the first value includes a value of one for each bit of the bit set.

[0131] Some instances of the method 700 and device described herein may further include operations, features, circuit systems, logic, components, or instructions for determining whether to unmap logical addresses based on a first type of data whose data type differs from data containing metadata or priority ordering, wherein determining whether to unmap logical addresses may be based on the value of a second field of a first entry.

[0132] In some instances of the method 700 and device described herein, setting the value may include operations, features, circuitry, logic, components, or instructions for setting the first field to zero based on determining the unmapping logical address.

[0133] In some instances of the method 700 and device described herein, setting the value may include operations, features, circuitry, logic, components, or instructions for identifying that a first field may have a first value and for incrementing the first value to a second value based on a determined mapping logical address.

[0134] In some instances of the method 700 and apparatus described herein, setting the value may include operations, features, circuitry, logic, components, or instructions for identifying that a first field may have a first value based on determining a mapped logical address and for maintaining the first value of the first field based on the identification that the first field may have a first value. In some instances of the method 700 and apparatus described herein, the first field may include a set of bits for indicating a usage level, and the first value may include a value of one for each bit of the set.

[0135] Some examples of the method 700 and apparatus described herein may further include operations, features, circuitry, logic, components, or instructions for determining the end position of a logical address relative to the end of a first block of a memory array, the first block having a first size, wherein determining whether to unmap the logical address may be based on determining that the end position of the logical address may be at or before the end of the first block.

[0136] Some instances of the method 700 and device described herein may further include operations, features, circuitry, logic, components, or instructions for opening a new data log of a memory array based on determining an unmapped logical address and the end position of the logical address being at or before the end of the first block, wherein the logical address may be associated with the new data log.

[0137] Some examples of the methods 700 and devices described herein may further include operations, features, circuit systems, logic, components, or instructions for determining whether a usage level meets a threshold, wherein the value of the threshold may be based on the amount of available physical addresses of a memory array.

[0138] In some instances of the method 700 and apparatus described herein, writing data may include operations, features, circuitry, logic, components, or instructions for writing data to a first portion of a memory array based on determining that a usage level meets a threshold, wherein the first portion of the memory array contains a physical address and may be associated with a first reliability level that is higher than a second reliability level associated with a second portion of the memory array.

[0139] In some instances of the method 700 and apparatus described herein, writing data may include operations, features, circuitry, logic, components, or instructions for writing data to a second portion of a memory array based on determining that a usage level has failed to meet a threshold, wherein the second portion of the memory array contains a physical address and may be associated with a second reliability level lower than the first reliability level associated with the first portion of the memory array.

[0140] Some examples of the method 700 and apparatus described herein may further include operations, features, circuitry, logic, components, or instructions for determining the end position of a logical address relative to the end of a first block of a memory array having a first size, and determining whether the logical address can be the next sequential logical address of an open data log of the memory array based on determining that the end position of the logical address is after the end of the first block.

[0141] In some instances of the method 700 and apparatus described herein, setting the value may include setting a first field to zero based on determining that the logical address is the next sequential logical address for opening the data log, and updating the operation, feature, circuitry, logic, component, or instruction for opening the data log based on the value of the first field being zero, using the logical address and the size of the data.

[0142] In some instances of the method 700 and device described herein, setting the value may include operations, features, circuitry, logic, components, or instructions for identifying that a first field may have a first value and for incrementing the first value to a second value based on determining that the logical address may be different from the next sequential logical address for opening the data log.

[0143] In some instances of the method 700 and apparatus described herein, setting the value may include operations, features, circuitry, logic, components, or instructions for identifying that a first field may have a first value based on determining that a logical address may be different from the next sequential logical address of an open data log, and for maintaining the first value of the first field based on identifying that the first field may have a first value.

[0144] It should be noted that the methods described above describe possible implementations, and the operations and steps can be rearranged or otherwise modified, and other implementations are possible. Furthermore, two or more parts from the methods can be combined.

[0145] The information and signals described herein can be represented using any of a variety of different techniques and methods. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, light fields or light particles, or any combination thereof. Some diagrams may illustrate a signal as a single signal; however, the signal may represent a bus of signals, which may have various bit widths.

[0146] The terms "electronic communication," "conductive contact," "connection," and "coupling" refer to the relationship between components that enables the flow of signals between them. Components are considered to be in electronic communication (or in conductive contact, connected, or coupled) with each other if any conductive path exists between them that enables the flow of signals between them at any given time. At any given time, the conductive path between components that are in electronic communication (or in conductive contact, connected, or coupled) can be open or closed, depending on the operation of the device containing the connected components. The conductive path between connected components can be a direct conductive path between the components, or an indirect conductive path between connected components that may include intermediate components such as switches, transistors, or other components. In some instances, one or more intermediate components, such as switches or transistors, can be used to interrupt the signal flow between connected components for a period of time.

[0147] The term "coupling" refers to the condition that moves from an open-circuit relationship between components to a closed-circuit relationship, in which a signal is currently not allowed to travel between the components via a conductive path, and in which a signal can travel between the components via the conductive path. If, for example, a component of a controller couples other components together, then the component initiates a change that allows signals to flow between the other components via conductive paths that were previously not permitted.

[0148] The term "isolation" refers to a relationship between components where signals are currently unable to flow between them. If there is an open circuit between components, then those components are isolated from each other. For example, components separated by a switch positioned between two components are isolated from each other when the switch is open. If a controller isolates two components, then the controller achieves the following change: preventing signals from flowing between the components using previously permitted conductive paths.

[0149] The terms “if,” “when,” “based on,” or “at least partially based on” are used interchangeably. In some instances, the terms “if,” “when,” “based on,” or “at least partially based on” are used to describe a connection between conditional actions, conditional processes, or parts of a process.

[0150] The term "in response to" can refer to a condition or action that occurs at least partially (if not completely) as a result of a preceding condition or action. For example, a first condition or action may be performed, and a second condition or action may occur at least partially as a result of the preceding condition or action (whether directly after or following one or more other intermediate conditions or actions).

[0151] Additionally, the terms "directly in response to" or "directly in response to" can refer to a condition or action occurring as a direct result of a previous condition or action. In some instances, a first condition or action may be performed, and a second condition or action may occur directly as a result of a previous condition or action occurring regardless of whether other conditions or actions occur. In some instances, a first condition or action may be performed, and a second condition or action may occur directly as a result of a previous condition or action, such that no other intermediate conditions or actions occur between the earlier condition or action and the second condition or action, or a limited number of one or more intermediate steps or actions occur between the earlier condition or action and the second condition or action. Unless otherwise specified, any condition or action described herein as "based on," "at least in part based on," or "in response to" a certain other step, action, event, or condition may additionally or alternatively (e.g., in alternative instances) "directly in response to" or "directly in response to" such other conditions or actions.

[0152] The devices containing memory arrays discussed herein can be formed on semiconductor substrates, such as silicon, germanium, silicon-germanium alloys, gallium arsenide, gallium nitride, etc. In some instances, the substrate is a semiconductor wafer. In other instances, the substrate can be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or subregions of the substrate can be controlled by doping with various chemicals including, but not limited to, phosphorus, boron, or arsenic. Doping can be performed during the initial formation or growth of the substrate, by ion implantation or by any other doping method.

[0153] The switching components or transistors discussed herein may represent field-effect transistors (FETs) and include a three-terminal device comprising a source, drain, and gate. Terminals may be connected to other electronic components via a conductive material, such as a metal. The source and drain may be conductive and may comprise heavily doped (e.g., degenerate) semiconductor regions. The source and drain may be separated by lightly doped semiconductor regions or channels. If the channel is n-type (i.e., the majority of charge carriers are electrons), then the FET may be called an n-type FET. If the channel is p-type (i.e., the majority of charge carriers are holes), then the FET may be called a p-type FET. The channel may be end-capped by an insulating gate oxide. The conductivity of the channel can be controlled by applying a voltage to the gate. For example, applying a positive or negative voltage to an n-type FET or a p-type FET, respectively, makes the channel conductive. If a voltage greater than or equal to the transistor's threshold voltage is applied to the transistor's gate, then the transistor may be "on" or "activated." If a voltage less than the transistor's threshold voltage is applied to the transistor's gate, then the transistor may be "off" or "deactivated."

[0154] The descriptions herein, illustrated with reference to the accompanying drawings, depict exemplary configurations and do not represent all implementable or claim-scoped instances. The term "exemplary" as used herein means "serving as an example, illustration, or description" and is not "preferred" or "advantageous" over other instances. The detailed description includes specific details that provide an understanding of the described techniques. However, these techniques may be practiced without such specific details. In some instances, well-known structures and devices are shown in block diagram form to avoid obscuring the concepts of the described instances.

[0155] In the accompanying drawings, similar components or features may have the same reference numerals. Furthermore, various components of the same type can be distinguished by a hyphen following the reference numeral and a second numeral used to differentiate between similar components. If only the first reference numeral is used in the specification, the description applies to any similar component having the same first reference numeral, regardless of the second reference numeral.

[0156] The functionality described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functionality may be stored as one or more instructions or code on or transmitted via a computer-readable medium. Other examples and embodiments are within the scope of this disclosure and the appended claims. For example, due to the nature of software, the functionality described above may be implemented using software executed by a processor, hardware, firmware, hardwired, or any combination thereof. Features implementing the functionality may also be physically located in various locations, including being distributed such that different parts of the functionality are implemented in different physical locations.

[0157] For example, the various illustrative blocks and components described in connection with the disclosure herein may be implemented or carried out using a general-purpose processor, DSP, ASIC, FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware component or any combination thereof designed to perform the functions described herein. The general-purpose processor may be a microprocessor, but alternatively, the processor may be any processor, controller, microcontroller or state machine. The processor may be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors incorporating a DSP core, or any other such configuration).

[0158] As used herein (included in the claims), the word "or" as used in a list of items (e.g., a list of items followed by phrases such as "at least one of" or "one or more of") indicates a list containing endpoints, such that a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Furthermore, as used herein, the phrase "based on" should not be construed as referring to a closed set of conditions. For example, without departing from the scope of this disclosure, an exemplary step described as "based on condition A" may be based on both condition A and condition B. In other words, as used herein, the phrase "based on" should be interpreted in the same manner as the phrase "at least partially based on".

[0159] Computer-readable media includes both non-transitory computer storage media and communication media, with communication media encompassing any media that facilitates the transfer of a computer program from one place to another. Non-transitory storage media can be any available media accessible by a general-purpose or special-purpose computer. By way of example, and not limitation, non-transitory computer-readable media may include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), optical disc (CD) ROM or other optical disc storage devices, magnetic disk storage devices or other magnetic storage devices, or any other non-transitory media that can be used to carry or store desired program code components in the form of instructions or data structures and is accessible by a general-purpose or special-purpose computer or a general-purpose or special-purpose processor. Furthermore, any connection is appropriately referred to as computer-readable media. For example, if software is transmitted from a website, server, or another remote source using coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then such coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of media. As used herein, disks and optical discs include CDs, laser discs, optical discs, digital versatile discs (DVDs), floppy disks, and Blu-ray discs, where disks typically reproduce data magnetically, while optical discs reproduce data optically using lasers. Combinations of these are also included within the scope of computer-readable media.

[0160] The description herein is provided to enable those skilled in the art to make or use this disclosure. Various modifications to this disclosure will become apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the scope of this disclosure. Therefore, this disclosure is not limited to the examples and designs described herein, but is given the broadest scope consistent with the principles and novel features disclosed herein.

Claims

1. An apparatus comprising: Memory devices; and A controller, coupled to the memory device and configured such that the device: Receive a write command indicating data to be written, the type of the data, and a first logical address of the memory array for writing the data; The first entry in a plurality of entries in an identification table, the table including a mapping between logical addresses and physical addresses of the memory array, wherein each of the plurality of entries is associated with a corresponding logical address and includes: A pointer to the corresponding physical address associated with the corresponding logical address; and A first field indicating the corresponding use level of the corresponding logical address, wherein the first entry is associated with the first logical address; The value of the first field of the first entry is set at least in part based on the type of the data to indicate the corresponding usage level of the first logical address; and The data is written to the first physical address of the memory array, at least in part, based on receiving the write command and setting the value of the first field of the first entry.

2. The device of claim 1, wherein the controller configured to set the value is further configured such that the device: The first value of the first field is set at least in part based on the fact that the type of the data is a first type of data.

3. The device of claim 2, wherein the first type of data includes metadata or prioritized data.

4. The device of claim 2, wherein the first field includes a set of bits for indicating the corresponding usage level, and wherein the first value includes a value of one for each bit of the set of bits.

5. The device of claim 1, wherein the controller is further configured such that the device: Whether to unmap the logical address is determined at least in part based on the fact that the type of the data is different from a first type of data including metadata or priority data, wherein the determination of whether to unmap the logical address is at least in part based on the value of a second field of the first entry.

6. The device of claim 5, wherein the controller configured to set the value is further configured such that the device: The first field is set to zero at least in part based on the determination to unmap the logical address.

7. The device of claim 5, wherein the controller configured to set the value is further configured such that the device: The first field is identified as having a first value; and The first value is incremented to the second value, at least in part, based on determining the mapping of the logical address.

8. The device of claim 5, wherein the controller configured to set the value is further configured such that the device: The first field is identified to have a first value based at least in part on determining the mapping of the logical address; and The first value of the first field is maintained at least in part based on the fact that the first field has the first value.

9. The device of claim 8, wherein the first field includes a set of bits for indicating the corresponding usage level, and wherein the first value includes a value of one for each bit of the set of bits.

10. The device of claim 5, wherein the controller is further configured such that the device: Determine the end position of the logical address relative to the end of a first block of the memory array, the first block having a first size, wherein determining whether to unmap the logical address is based at least in part on determining that the end position of the logical address is at or before the end of the first block.

11. The device of claim 10, wherein the controller is further configured such that the device: A new data log of the memory array is opened at least in part based on determining that the logical address is unmapped and that the end position of the logical address is at or before the end of the first block, wherein the logical address is associated with the new data log.

12. The device of claim 1, wherein the controller is further configured such that the device: Determine whether the corresponding usage level meets a threshold, wherein the value of the threshold is based at least in part on the amount of available physical addresses of the memory array.

13. The device of claim 12, wherein the controller configured to write the data is further configured such that the device: The data is written to a first portion of the memory array at least in part based on determining that the corresponding usage level meets the threshold, wherein the first portion of the memory array includes the physical address and is associated with a first reliability level that is higher than a second reliability level associated with a second portion of the memory array.

14. The device of claim 12, wherein the controller configured to write the data is further configured such that the device: The data is written to a second portion of the memory array, at least in part, based on the determination that the corresponding usage level fails to meet the threshold, wherein the second portion of the memory array includes the physical address and is associated with a second reliability level that is lower than the first reliability level associated with the first portion of the memory array.

15. The device of claim 1, wherein the controller is further configured such that the device: Determine the end position of the logical address relative to the end of a first block of the memory array, the first block having a first size; and Whether the logical address is the next sequential logical address of the open data log of the memory array is determined at least in part based on the fact that the end position of the logical address is after the end of the first block.

16. The device of claim 15, wherein the controller configured to set the value is further configured such that the device: The value of the first field is set to zero at least in part based on determining that the logical address is the next sequential logical address of the opened data log; and The open data log is updated at least in part based on the value of the first field being determined to be zero, using the logical address and the size of the data.

17. The device of claim 15, wherein the controller configured to set the value is further configured such that the device: The first field is identified as having a first value; and The first value is incremented to the second value at least in part based on the determination that the logical address is different from the next sequential logical address of the opened data log.

18. The device of claim 15, wherein the controller configured to set the corresponding usage level is further configured such that the device: The first field is identified as having a first value based at least in part on the determination that the logical address is different from the next sequential logical address of the opened data log; and The first value of the first field is maintained at least in part based on the fact that the first field has the first value.

19. A non-transitory computer-readable medium storing code comprising instructions that, when executed by a processor of an electronic device, cause the electronic device to: Receive a write command indicating data to be written, the type of the data, and a first logical address of the memory array for writing the data; The first entry in a plurality of entries in an identification table, the table including a mapping between logical addresses and physical addresses of the memory array, wherein each of the plurality of entries is associated with a corresponding logical address and includes: A pointer to the corresponding physical address associated with the corresponding logical address; and The first field indicating the corresponding usage level of the corresponding logical address. The first entry is associated with the first logical address; The value of the first field of the first entry is set at least in part based on the type of the data to indicate the corresponding usage level of the first logical address; and The data is written to the first physical address of the memory array, at least in part, based on receiving the write command and setting the value of the first field of the first entry.

20. The non-transitory computer-readable medium of claim 19, wherein the instruction to set the value, when executed by the processor of the electronic device, further causes the electronic device to: The first value of the first field is set at least in part based on the fact that the type of the data is a first type of data.

21. The non-transitory computer-readable medium of claim 19, wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to: Whether to unmap the logical address is determined at least in part based on the fact that the type of the data is different from a first type of data including metadata or priority data, wherein the determination of whether to unmap the logical address is at least in part based on the value of a second field of the first entry.

22. The non-transitory computer-readable medium of claim 21, wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to: The first field is set to zero at least in part based on the determination to unmap the logical address.

23. The non-transitory computer-readable medium of claim 21, wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to: The first field is identified as having a first value; and The first value is incremented to the second value, at least in part, based on determining the mapping of the logical address.

24. The non-transitory computer-readable medium of claim 21, wherein the instruction to set the value, when executed by the processor of the electronic device, further causes the electronic device to: The first field is identified to have a first value based at least in part on determining the mapping of the logical address; and The first value of the first field is maintained at least in part based on the fact that the first field has the first value.

25. A method comprising: Receive a write command indicating data to be written, the type of the data, and a first logical address of the memory array for writing the data; The first entry in a plurality of entries in an identification table, the table including a mapping between logical addresses and physical addresses of the memory array, wherein each of the plurality of entries is associated with a corresponding logical address and includes: A pointer to the corresponding physical address associated with the corresponding logical address; and The first field indicating the corresponding usage level of the corresponding logical address. The first entry is associated with the first logical address; The value of the first field of the first entry is set at least in part based on the type of the data to indicate the corresponding usage level of the first logical address; and The data is written to the first physical address of the memory array, at least in part, based on receiving the write command and setting the value of the first field of the first entry.

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