一种通过算法控制单元进行调度计算的硬件结构
The hardware architecture that uses 'Algorithm Zoo' to schedule computation solves the problem of insufficient flexibility in deploying convolutional neural networks on FPGAs, enabling rapid adaptation and efficient computation for different neural network algorithms.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- XI AN JIAOTONG UNIV
- Filing Date
- 2022-08-02
- Publication Date
- 2026-07-17
AI Technical Summary
Existing FPGA-based convolutional neural networks lack flexibility and programmability, making it difficult to quickly adapt to changes in various network structures and parameters.
It adopts a hardware architecture that schedules computations via an 'Algorithm Zoo', including a system register control unit, an algorithm control unit, a computation array unit, an on-chip storage unit, a RISC-V processor, double-rate dynamic memory, and a vector processing unit. The RISC-V processor controls each module to complete computation tasks and supports operations such as traditional convolution, depthwise convolution, deconvolution, pooling, and data transformation.
It enables flexible support and rapid deployment of different neural network algorithms, improves the programming flexibility and computational efficiency of the hardware architecture, and is suitable for convolutional neural networks and parallel computing needs.
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Figure CN115374395B_ABST