Simulation method and system for low temperature multi-chip computing system

Abstract

The application discloses a simulation method for a low-temperature multi-chip computing system, and the method comprises the following steps: a cross-temperature-zone multi-chip simulation communication system building step, a low-temperature multi-chip function simulation step and a low-temperature multi-chip timing simulation step; a low-temperature multi-chip computing system and a room-temperature data communication system which are connected to communicate with each other are built, the functions of various chips used for computing in the low temperature and the interactive operation functions among the various chips are described by behavior level simulation based on the design specifications of the various chips, and the output execution results of the various chips are simulated; the period working timing of each chip inside the low temperature is simulated based on the design specifications of the various chips, the communication protocol among the various chips is simulated, the timing of the low-temperature multi-chip computing system is simulated, and the correctness of each timing is verified. The application simulates and analogs the complex low-temperature multi-chip computing, so that system problems can be found early and modified through simulation debugging before the chip is manufactured.

Description

Technical Field

[0001] This application relates to the field of low-temperature computing, and in particular to a simulation method and system for low-temperature multi-chip computing systems. Background Technology

[0002] Currently, to design and build a faster computer under the same power requirements, Moore's Law and Dennard's scaling law must be satisfied so that transistor size and operating voltage can be reduced simultaneously. Only in this way can architects place more logic and memory cells on the same chip size and increase chip frequency without increasing power consumption. However, the integrated circuit field is now experiencing the end of these two laws, mainly because it is difficult to reduce transistor supply voltage and threshold voltage without excessively increasing leakage power (i.e., the power wall problem). On the other hand, even if the power wall problem is solved, improving memory performance becomes another huge challenge because memory access latency is limited by line latency rather than transistor speed. Therefore, any architectural innovation will not help improve the overall system performance (memory wall problem). To solve the power wall and memory wall problems, various methods have been proposed, such as multi-core design and information processing near or within memory. However, these workarounds are affected by parallelization overhead, increasing on-chip power consumption, and the requirement for complete architectural innovation. Therefore, there is an urgent need to effectively solve the power consumption and memory problems.

[0003] To achieve this goal, the concept of operating computers at extremely low temperatures (e.g., -200°C) (or cryogenic computing) has become a very promising idea, as the decrease in temperature causes an exponential drop in leakage power, while the resistivity of the wires decreases linearly. Cryogenic computing operates computing systems at extremely low temperatures (e.g., 77K), which can significantly improve the performance and power efficiency of computers due to the significant reduction in leakage power and wire resistance. However, due to a lack of understanding of its cost-effectiveness and feasibility (e.g., equipment and cooling costs versus acceleration, energy, and area savings), computer architects face fundamental challenges in developing and deploying cryogenically optimized architectural units. Therefore, how to build such cryogenically optimal units is a problem that needs to be solved. With the dramatic increase in the functional complexity of cryogenic computing systems, researching efficient simulation methods and building robust simulation platforms to efficiently locate design errors is crucial for shortening the system design and verification cycle.

[0004] Cryogenic computing is a novel computing technology that has emerged in recent years and represents a highly promising solution for the post-Moore's Law era. Cryogenic systems may integrate multiple chips, such as cryogenic CPUs, cryogenic DRAM, and cryogenic accelerator chips. How to simulate and model complex cryogenic multi-chip systems to identify system problems early during tape-out is an urgent issue that needs to be addressed. Currently, no publicly available literature has solved this problem.

[0005] This invention is the first to propose a low-temperature multi-chip simulation method and system. It provides a simulation method and platform for designing multi-chip computing systems in low-temperature environments. This method simulates and models complex low-temperature multi-chip computing, enabling early detection and modification of system problems through simulation debugging before tape-out. This achieves the goals of assisting in the architecture design and functional verification of low-temperature processors, shortening the development cycle of low-temperature processors, and reducing tape-out failure rates. Summary of the Invention

[0006] This application provides a method and system for simulating a cryogenic multi-chip computing system, which enables early detection and modification of system problems through simulation debugging before tape-out, thereby assisting in the architecture design and functional verification of cryogenic processors, shortening the development cycle of cryogenic processors, and reducing the tape-out failure rate.

[0007] In a first aspect, embodiments of this application provide a simulation method for a cryogenic multi-chip computing system, the method comprising:

[0008] Steps for building a multi-chip analog communication system across temperature zones: Build a low-temperature multi-chip computing system and a room-temperature data communication system that are interconnected. The low-temperature multi-chip computing system contains various chips used for calculation at low temperatures. The room-temperature data communication system simulates input commands to the low-temperature multi-chip computing system and receives the execution results output by the low-temperature multi-chip computing system for verification.

[0009] Low-temperature multi-chip functional simulation steps: Based on the design specifications of multiple chips, behavioral simulation describes the functions of multiple chips used for computation in low temperature and the interactive operation functions between multiple chips, and simulates the output execution results of multiple chips;

[0010] The steps for low-temperature multi-chip timing simulation are as follows: Based on the design specifications of various chips, the internal cyclic operation timing of each chip is simulated at low temperatures, and the communication protocols between various chips are simulated to simulate the timing of the low-temperature multi-chip computing system and verify the correctness of each timing sequence.

[0011] Preferably, the above-mentioned simulation method for cryogenic multi-chip computing systems further includes:

[0012] Environment configuration steps: Different cryogenic multi-chip computing systems can be built by configuring different execution environment parameters, and different simulation modes of cryogenic multi-chip computing systems can be built by executing environment configuration. The simulation modes include: functional simulation mode, timing simulation mode and hybrid simulation mode.

[0013] Performance statistics steps: Perform functional correctness assessment and performance parameter evaluation on the cryogenic multi-chip computing system.

[0014] Preferably, the above-mentioned low-temperature multi-chip functional simulation step further includes:

[0015] The steps for simulating the function of a low-temperature CPU are as follows: Based on the CPU design specifications, the function of the low-temperature CPU is described by behavioral simulation. According to the architecture of the low-temperature CPU, the instruction set of the low-temperature CPU is input. According to the operation rules of the pipelined CPU, the low-temperature CPU's instruction fetching, instruction decoding, instruction execution, memory access and write-back operations are simulated periodically, and the output execution results of the low-temperature CPU are simulated.

[0016] Low-temperature DRAM functional simulation steps: Based on the DRAM design specifications, behavioral-level simulation describes the function of the low-temperature DRAM and simulates the output execution results of the low-temperature DRAM;

[0017] The steps for simulating the function of a cryogenic accelerator are as follows: Based on the accelerator's design specifications, behavioral simulations describe the function of the cryogenic accelerator and simulate the output execution results of the cryogenic accelerator.

[0018] The steps for simulating the function of a cryogenic amplifier are as follows: Based on the amplifier's design specifications, a behavioral simulation is performed to describe the function of the cryogenic amplifier and to simulate the output execution results of the cryogenic amplifier.

[0019] Preferably, the above-mentioned low-temperature multi-chip timing simulation step further includes:

[0020] Low-temperature CPU timing simulation steps: Based on the CPU design specifications, simulate the internal cyclic operation timing of the CPU at low temperatures and verify the correctness of the low-temperature CPU timing.

[0021] Low-temperature DRAM timing simulation steps: Based on the DRAM design specifications, simulate the first and second timings of the DRAM's internal cycle operation at low temperature according to the DRAM timing model, and verify the correctness of the low-temperature DRAM timings;

[0022] Cryogenic accelerator timing simulation steps: Based on the accelerator design specifications, simulate the periodic operation timing inside the accelerator at cryogenic temperatures, and verify the correctness of the cryogenic accelerator timing.

[0023] The timing simulation steps for cryogenic amplifiers are as follows: Based on the amplifier's design specifications, the internal cyclic operating timing of the amplifier at cryogenic temperatures is simulated, and the correctness of the cryogenic amplifier timing is verified.

[0024] Preferably, the above-mentioned environmental configuration steps further include:

[0025] Hybrid simulation mode steps: Set any one or more chips from a variety of chips operating at low temperature to functional simulation mode, and set the other chips to timing simulation mode. The various chips include: low temperature CPU, low temperature DRAM, low temperature accelerator and low temperature amplifier.

[0026] Environmental parameter simulation configuration steps: Different cryogenic multi-chip computing systems can be constructed by configuring different execution environment parameters for various chips.

[0027] Preferably, the above performance statistics steps further include:

[0028] Functional evaluation steps: The room temperature data communication system includes a host computer and a data communication module. The host computer connects to the low-temperature multi-chip computing system through the data communication module. The host computer simulates inputting instructions to various chips in the low temperature and receives the output execution results through the data communication module to verify the correctness of the functions of various chips.

[0029] Performance evaluation steps: The execution time of the cryogenic multi-chip computing system is evaluated by sending multiple data packets or instructions to various chips in the cryogenic environment via a host computer.

[0030] Preferably, the above functional evaluation steps further include:

[0031] Packet-by-packet testing steps: Send test data packets or commands to each of the various chips in the cryogenic environment via the host computer to verify the correctness of the functions of the cryogenic multi-chip computing system;

[0032] Massive packet testing steps: The host computer continuously and continuously sends test data packets or instructions to multiple chips in cryogenic environments for a long period of time to verify the functional stability of the cryogenic multi-chip computing system.

[0033] Secondly, embodiments of this application provide a simulation system for a cryogenic multi-chip computing system, employing the simulation method for a cryogenic multi-chip computing system as described above. The system includes:

[0034] Cross-temperature zone multi-chip analog communication system: includes a low-temperature multi-chip computing system and a room-temperature data communication system that are interconnected. The low-temperature multi-chip computing system contains multiple chips used for calculation at low temperatures. The room-temperature data communication system simulates input instructions to the low-temperature multi-chip computing system and receives the execution results output by the low-temperature multi-chip computing system for verification.

[0035] Low-Temperature Multi-Chip Functional Simulation Module: Used for behavioral-level simulation description of the functions of multiple chips used for computation in cryogenic environments based on the design specifications of multiple chips, as well as the interactive operation functions between multiple chips, and to simulate the output execution results of multiple chips;

[0036] Low-Temperature Multi-Chip Timing Simulation Module: Based on the design specifications of various chips, this module simulates the internal cyclic operating timing of each chip at low temperatures, and simulates the communication protocols between various chips to simulate the timing of a low-temperature multi-chip computing system and verify the correctness of each timing sequence.

[0037] Preferably, the above-mentioned simulation system for cryogenic multi-chip computing systems further includes:

[0038] Environment configuration module: This module is used to construct different cryogenic multi-chip computing systems by configuring different execution environment parameters, and to execute simulation modes for constructing different cryogenic multi-chip computing systems by executing environment configuration. The simulation modes include: functional simulation mode, timing simulation mode, and hybrid simulation mode.

[0039] Performance statistics module: used to evaluate the functional correctness and performance parameters of cryogenic multi-chip computing systems.

[0040] Preferably, the above-mentioned room temperature data communication system includes a host computer and a data communication module. The host computer connects to the low-temperature multi-chip computing system through the data communication module. The host computer sends control commands to the low-temperature multi-chip computing system and receives the execution results fed back by the low-temperature multi-chip computing system through the data communication module.

[0041] Compared with existing technologies, it has the following outstanding advantages:

[0042] 1. The simulation method and platform for low-temperature multi-chip computing systems of the present invention can simulate and model complex low-temperature multi-chip computing systems, and can detect functional and timing problems in a timely manner before tape-out, thereby improving the success rate of tape-out with minimal time and behavioral costs.

[0043] 2. This invention supports the functional simulation of individual chips in cryogenic computing systems. Cryogenic computing systems typically integrate multiple chips, such as cryogenic CPUs, cryogenic DRAM, cryogenic accelerators, and cryogenic amplifiers. A malfunction in any chip within the system can lead to system failure. The cryogenic multi-chip simulation system proposed in this invention can simulate the function of each chip individually, ensuring that the chip behavior conforms to design specifications.

[0044] 3. This invention supports timing simulation of each chip in a low-temperature computing system. Based on the chip design specifications containing timing information, this invention can accurately simulate the timing of each chip at low temperatures, achieving precise periodic simulation. At the same time, it can simulate the communication protocols between chips, thereby realizing timing simulation of the entire low-temperature computing system.

[0045] 4. This invention supports mixed-mode simulation of function and timing. By configuring the execution environment, the chip mode can be configured separately, which can be either functional mode simulation or timing mode simulation, thus enabling the invention to support functional simulation, timing simulation, and mixed simulation.

[0046] 5. This invention supports execution environment configuration. By configuring different execution environment parameters, such as low-temperature DRAM capacity, low-temperature CPU microarchitecture parameters (e.g., data cache capacity, instruction cache capacity, cache hit strategy, pipeline stage number, instruction prefetch strategy, etc.), and low-temperature accelerator architecture parameters (e.g., input feature map cache capacity, data flow mode, computing unit array size, etc.), different low-temperature computing systems can be constructed, thereby achieving performance, energy efficiency evaluation, and structural optimization for different low-temperature computing systems.

[0047] 6. This invention has performance statistics capabilities. The simulator of this invention can perform functional and performance evaluations on the cryogenic computing system. The functional evaluation mainly assesses the correctness of the functions of the cryogenic computing system, while the performance evaluation mainly evaluates the execution speed of the cryogenic computing system and the effect of the performance improvement before optimization. Attached Figure Description

[0048] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings:

[0049] Figure 1 This is a flowchart of the low-temperature multi-chip computing system simulation method of the present invention;

[0050] Figure 2 This is a schematic diagram of a cross-temperature zone multi-chip analog communication system architecture according to a specific embodiment of the present invention;

[0051] Figure 3 This is a schematic diagram of a low-temperature CPU structure according to a specific embodiment of the present invention;

[0052] Figure 4 This is a schematic representation of the CPU instruction pipeline state in a specific embodiment of the method of the present invention;

[0053] Figure 5 This is a schematic diagram of the tCL timing in a specific embodiment of the present invention;

[0054] Figure 6 This is a schematic diagram of the tRCD timing of a specific embodiment of the present invention;

[0055] Figure 7 This is a timing diagram of tRP according to a specific embodiment of the present invention;

[0056] Figure 8 This is a schematic diagram of the simulation system of the low-temperature multi-chip computing system of the present invention;

[0057] Figure 9 This is a schematic diagram of the system composition framework according to an embodiment of this application.

[0058] In the above image:

[0059] 10 Cross-temperature zone multi-chip analog communication system; 20 Low-temperature multi-chip functional analog modules

[0060] 30 Low-Temperature Multi-Chip Timing Simulation Module. Detailed Implementation

[0061] To make the objectives, technical solutions, and advantages of this application clearer, the application is described and illustrated below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application. All other embodiments obtained by those skilled in the art based on the embodiments provided in this application without inventive effort are within the scope of protection of this application.

[0062] Obviously, the accompanying drawings described below are merely some examples or embodiments of this application. Those skilled in the art can apply this application to other similar scenarios based on these drawings without any inventive effort. Furthermore, it is understood that although the efforts made in this development process may be complex and lengthy, for those skilled in the art related to the content disclosed in this application, any changes to design, manufacturing, or production based on the technical content disclosed in this application are merely conventional technical means and should not be construed as insufficient disclosure of the content of this application.

[0063] Details of one or more embodiments of this application are set forth in the following drawings and description to make other features, objects and advantages of this application more readily apparent.

[0064] In this application, the reference to "embodiment" means that a specific feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment that is mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described in this application may be combined with other embodiments without conflict.

[0065] Unless otherwise defined, the technical or scientific terms used in this application shall have the ordinary meaning understood by one of ordinary skill in the art to which this application pertains. The terms “a,” “an,” “an,” “the,” and similar words used in this application do not indicate quantity limitation and may indicate singular or plural. The terms “comprising,” “including,” “having,” and any variations thereof used in this application are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or device that includes a series of steps or modules (units) is not limited to the listed steps or units, but may also include steps or units not listed, or may include other steps or units inherent to these processes, methods, products, or devices. The terms “connected,” “linked,” “coupled,” and similar words used in this application are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. “Multiple” used in this application refers to two or more. “And / or” describes the relationship between related objects, indicating that three relationships may exist; for example, “A and / or B” can represent: A alone, A and B simultaneously, and B alone. The character " / " generally indicates that the preceding and following objects are in an "or" relationship. The terms "first," "second," and "third" used in this application are merely to distinguish similar objects and do not represent a specific ordering of the objects.

[0066] In order to realize the simulation method and system for low-temperature multi-chip computing systems, this application needs to overcome several specific challenges: 1) It needs to be able to support the functional mode simulation of each chip at low temperature; 2) It needs to be able to support the timing mode simulation of each chip at low temperature, as well as the mixed simulation of the two modes; 3) It needs to support the configuration of the execution environment; 4) It needs to have performance statistics function.

[0067] The simulation method and platform for cryogenic multi-chip computing systems proposed in this invention can simulate and model complex cryogenic multi-chip systems, increasing the flexibility and simplicity of debugging, making it easy to operate, greatly improving the efficiency of system design, verification and debugging, and enabling the discovery of system problems before tape-out for improvement, thereby increasing the success rate of tape-out.

[0068] like Figure 1As shown, this embodiment provides a first aspect, which provides a simulation method for a cryogenic multi-chip computing system, the method comprising:

[0069] Step S10 of building a multi-chip analog communication system across temperature zones: Build a low-temperature multi-chip computing system and a room-temperature data communication system that are interconnected. The low-temperature multi-chip computing system contains a variety of chips used for calculation at low temperatures. The room-temperature data communication system simulates input instructions to the low-temperature multi-chip computing system and receives the execution results output by the low-temperature multi-chip computing system for verification.

[0070] Low-temperature multi-chip functional simulation step S20: Based on the design specifications of multiple chips, behavioral-level simulation describes the functions of multiple chips used for computation in low temperature and the interactive operation functions between multiple chips, and simulates the output execution results of multiple chips;

[0071] Low-temperature multi-chip timing simulation step S30: Based on the design specifications of various chips, simulate the periodic working timing of each chip under low temperature, and simulate the communication protocols between various chips to simulate the timing of the low-temperature multi-chip computing system and verify the correctness of each timing sequence.

[0072] Preferably, the above-mentioned simulation method for cryogenic multi-chip computing systems further includes:

[0073] Environment configuration steps: Different cryogenic multi-chip computing systems can be built by configuring different execution environment parameters, and different simulation modes of cryogenic multi-chip computing systems can be built by executing environment configuration. The simulation modes include: functional simulation mode, timing simulation mode and hybrid simulation mode.

[0074] Performance statistics steps: Perform functional correctness assessment and performance parameter evaluation on the cryogenic multi-chip computing system.

[0075] Preferably, the above-mentioned low-temperature multi-chip functional simulation step S20 further includes:

[0076] The steps for simulating the function of a low-temperature CPU are as follows: Based on the CPU design specifications, the function of the low-temperature CPU is described by behavioral simulation. According to the architecture of the low-temperature CPU, the instruction set of the low-temperature CPU is input. According to the operation rules of the pipelined CPU, the low-temperature CPU's instruction fetching, instruction decoding, instruction execution, memory access and write-back operations are simulated periodically, and the output execution results of the low-temperature CPU are simulated.

[0077] Low-temperature DRAM functional simulation steps: Based on the DRAM design specifications, behavioral-level simulation describes the function of the low-temperature DRAM and simulates the output execution results of the low-temperature DRAM;

[0078] The steps for simulating the function of a cryogenic accelerator are as follows: Based on the accelerator's design specifications, behavioral simulations describe the function of the cryogenic accelerator and simulate the output execution results of the cryogenic accelerator.

[0079] The steps for simulating the function of a cryogenic amplifier are as follows: Based on the amplifier's design specifications, a behavioral simulation is performed to describe the function of the cryogenic amplifier and to simulate the output execution results of the cryogenic amplifier.

[0080] Preferably, the above-mentioned low-temperature multi-chip timing simulation step S30 further includes:

[0081] Low-temperature CPU timing simulation steps: Based on the CPU design specifications, simulate the internal cyclic operation timing of the CPU at low temperatures and verify the correctness of the low-temperature CPU timing.

[0082] Low-temperature DRAM timing simulation steps: Based on the DRAM design specifications, simulate the first and second timings of the DRAM's internal cycle operation at low temperature according to the DRAM timing model, and verify the correctness of the low-temperature DRAM timings;

[0083] Cryogenic accelerator timing simulation steps: Based on the accelerator design specifications, simulate the periodic operation timing inside the accelerator at cryogenic temperatures, and verify the correctness of the cryogenic accelerator timing.

[0084] The timing simulation steps for cryogenic amplifiers are as follows: Based on the amplifier's design specifications, the internal cyclic operating timing of the amplifier at cryogenic temperatures is simulated, and the correctness of the cryogenic amplifier timing is verified.

[0085] Preferably, the above-mentioned environmental configuration steps further include:

[0086] Hybrid simulation mode steps: Set any one or more chips from a variety of chips operating at low temperature to functional simulation mode, and set the other chips to timing simulation mode. The various chips include: low temperature CPU, low temperature DRAM, low temperature accelerator and low temperature amplifier.

[0087] Environmental parameter simulation configuration steps: Different cryogenic multi-chip computing systems can be constructed by configuring different execution environment parameters for various chips.

[0088] Preferably, the above performance statistics steps further include:

[0089] Functional evaluation steps: The room temperature data communication system includes a host computer and a data communication module. The host computer connects to the low-temperature multi-chip computing system through the data communication module. The host computer simulates inputting instructions to various chips in the low temperature and receives the output execution results through the data communication module to verify the correctness of the functions of various chips.

[0090] Performance evaluation steps: The execution time of the cryogenic multi-chip computing system is evaluated by sending multiple data packets or instructions to various chips in the cryogenic environment via a host computer.

[0091] Preferably, the above functional evaluation steps further include:

[0092] Packet-by-packet testing steps: Send test data packets or commands to each of the various chips in the cryogenic environment via the host computer to verify the correctness of the functions of the cryogenic multi-chip computing system;

[0093] Massive packet testing steps: The host computer continuously and continuously sends test data packets or instructions to multiple chips in cryogenic environments for a long period of time to verify the functional stability of the cryogenic multi-chip computing system.

[0094] The specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings:

[0095] In a specific embodiment of the present invention, the present invention addresses the problem of how to construct an optimal low-temperature computing system, and proposes a simulation method and system for low-temperature multi-chip computing systems, using the simulator as an important foundational support platform for low-temperature computing architecture, chip design, cross-temperature zone communication, and low-temperature signal processing.

[0096] 1. Simulation Platform Architecture for Low-Temperature Multi-Chip Computing Systems

[0097] Cryogenic multi-chip computing systems perform calculations in a cryogenic environment. The data for these calculations is provided by a data communication module located at room temperature. Therefore, a complete system comprises two temperature zones: room temperature and cryogenic temperature. The room temperature zone houses the data communication node, while the cryogenic zone contains multiple chips used for computation, such as cryogenic CPUs, cryogenic DRAM, and cryogenic accelerators. First, the requirements and performance of the simulator are analyzed. Based on this analysis and the cryogenic multi-chip architecture, a reasonable simulator architecture is designed. For example... Figure 2 As shown, Figure 2 It is a multi-chip analog communication system architecture that spans temperature zones.

[0098] The room temperature environment includes a host computer and a data communication module composed of FPGA or ASIC. The host computer mainly controls the chips in the low temperature computing system, while the data communication module forwards the data from the room temperature environment to the computing system in the low temperature environment.

[0099] 2. Supports functional simulation of various chips in low-temperature computing systems.

[0100] The simulator's functional simulation is a behavioral description of the target chip's functions and output execution results. It simulates the chip's behavior. For users, the simulator is like a black box; they only need to input instructions and pay attention to the simulator's execution results, and verify the correctness of its output.

[0101] In cryogenic computing systems, multiple chips are typically integrated to perform different functions, such as cryogenic CPUs, cryogenic DRAMs, cryogenic accelerators, and cryogenic amplifiers. For the system to function properly, each chip needs to operate stably and correctly; any unexpected error in any chip will cause system malfunctions. Therefore, ensuring the normal operation of each chip and the interconnected system in such a complex system is a problem that needs to be verified and solved. The cryogenic multi-chip simulation method and system proposed in this invention can simulate the functions of each chip individually, ensuring that the chip behavior fully conforms to design specifications.

[0102] During the design process, it is necessary to implement the design in a reasonable and standardized manner according to the structure, parameters, and other specifications in the user design manual. For ease of explanation, this patent uses a traditional 5-stage CPU to illustrate the function of the CPU. The fundamental task of the CPU is to execute instructions, which, from a computer's perspective, are ultimately a sequence of "0"s and "1"s. Logically, the CPU can be divided into three modules: the control unit, the arithmetic unit, and the storage unit. These three parts are connected by the CPU's internal bus. For example... Figure 3 As shown.

[0103] First, determine the CPU's instruction set, supporting instructions such as add, sub, and, or, addi, andi, ori, lw, sw, beq, and bne. Based on the instruction set, implement some basic instructions first. Pipelining is a method to improve system stability and operating speed in digital systems, widely used in the architecture of high-end CPUs. Based on the characteristics of the CPU, the overall processing is divided into five stages: instruction fetch (IF), instruction decode (ID), execution (EX), memory access (MEM), and register write (WB), corresponding to five processing phases in multiple cycles. The execution of one instruction requires five clock cycles. At the rising edge of each clock cycle, a series of data and control information represented by this instruction is transferred to the next processing stage.

[0104] The operating principle of a five-stage pipelined CPU, such as... Figure 4 As shown:

[0105] 1) Instruction Fetch (IF): The CPU controller is responsible for fetching the instruction code from the instruction memory based on the value of the PC register, and at the same time determining the address of the next instruction (the pointer points to the next instruction).

[0106] 2) Instruction Decoding (ID): The instruction in the instruction register is decoded to determine what operation the instruction should perform (that is, the opcode in the instruction) and where the operands are located (the address of the operands).

[0107] 3) Execute instruction (EX): Perform arithmetic or logical operations or calculate the jump target address of conditional branch instructions according to the instruction code, determine the ALU operation, select two ALU operands A and B, and determine the target register.

[0108] 4) Memory Access (MEM): The processor reads or writes data from the data memory.

[0109] 5) Write Back (WB): Saves the result of the operation to the destination register.

[0110] The CPU repeats this process continuously until a power outage. In the hardware implementation of the cryogenic computing simulation system, the CPU's addressing, decoding, ALU, and control functions were implemented using Verilog, consistent with the design manual specifications. The correctness of the functions was verified through a simulation platform.

[0111] 3. Supports timing simulation of various chips in low-temperature computing systems.

[0112] Timing simulation of cryogenic computing systems mainly simulates the internal working sequence of the chip. For R&D personnel, timing simulation of the chip can provide an accurate execution sequence model, which can truly reflect the execution information.

[0113] Cryogenic computing systems are implemented based on pulses, which are relatively weak with an amplitude of only 2.6mV. Furthermore, cryogenic computing systems are susceptible to interference from room temperature systems; even small delays can cause system malfunctions. Therefore, cryogenic computing systems require precise timing. Chip design specifications typically contain timing information for chip operation. This invention can accurately simulate the timing of each chip under cryogenic conditions based on chip design specifications containing timing information, achieving periodically accurate simulation. It can also simulate inter-chip communication protocols, thereby achieving timing simulation of the entire cryogenic computing system. For ease of explanation, this patent uses cryogenic DRAM as an example to illustrate chip timing simulation.

[0114] The main pin definitions for DRAM are as follows:

[0115]

[0116] DRAM timings are divided into two parts, categorized as follows: First timing sequence: tCL-tRCD-tRP-tRAS-CR, 5 main timings. Second timing sequence: CWL-tRC-tRFC, etc. (including all XMP timings).

[0117] DRAM uses row and column addressing. When a request is triggered, the initial step is tRAS (Active to precharge Delay). After precharging, the memory truly begins initializing the RAS (Row Address Strobe). Once tRAS is activated, the RAS begins addressing the required data. First, the row address is accessed, then tRCD (RAS to CAS Delay) is initialized. After the cycle ends, the hexadecimal address of the required data is accessed via CAS (Column Address Strobe). The time from the start to the end of CAS is the CAS latency (tCL). Therefore, CAS is the final step in finding the data, and tCL is the most important memory parameter.

[0118] DRAM read cycle timing: row address valid -> row address strobe -> column address valid -> column address strobe -> data output -> row strobe, column strobe and address cancellation.

[0119] DRAM write cycle timing: row address valid -> row address strobe -> column address, data valid -> column address strobe -> data input -> row strobe, column strobe and address cancellation.

[0120] DRAM refresh cycle: refresh row address valid -> nRAS valid -> refresh address and nRAS revoked.

[0121] The following section introduces several timing models for DRAM.

[0122] (1) tCL-CAS Lantency Control

[0123] The time interval between issuing a read command and reading data from the I / O interface. This refers to the latency of the column address controller before a memory read / write operation, typically measured in tCLK (t clock cycles). CAS controls the time between receiving an instruction and its execution. Because CAS primarily controls hexadecimal addresses, or column addresses in the memory matrix, it is the most important parameter and should be set as low as possible while maintaining stability. It has the greatest impact on memory read / write performance.

[0124] The specific time calculation formula is: tCL(ns) = (CL * 2000) / memory frequency. For example... Figure 5 As shown, the box containing "Read" indicates a read command, and the box containing "Data Read" indicates a read IO operation. The time interval between them is tCL.

[0125] (2) tRCD-RAS to CAS Delay

[0126] like Figure 6As shown, the row-to-column addressing latency is typically measured in tCLK (t clock cycles). It represents the time required for memory to operate on the row address after the row address activation command is issued. Simply put, given the row address location, finding the corresponding column address within that row completes the addressing and allows for read / write operations. The time from knowing the row address to finding the column address is tRCD. The diagram below shows the time interval between issuing a row address activation command and finding the column address and issuing a read instruction; this is tRCD. In the JEDEC specification, it is the second parameter; reducing this latency can improve system performance. If memory overclocking performance is poor, this value can be set to the memory's default value or the tRCD value can be increased. It has the greatest impact on the maximum memory frequency.

[0127] (3) tRP-Row Precharge Timing

[0128] like Figure 7 As shown, tRP is the precharge time before the next row address activation signal is issued. The figure below shows the time interval from the start of precharging for a row address that is about to be activated until it is activated; this is tRP.

[0129] tRP timing diagram

[0130] When implementing the low-temperature computing simulation system in hardware, the timing information of the aforementioned DRAM was implemented using the Verilog language, maintaining strict consistency with the specifications in the design manual, and the correctness of the timing was verified through a simulation platform.

[0131] 4. Supports mixed-mode simulation of function and timing.

[0132] This simulator allows users to input variables from a host computer to select between functional and timing simulations, improving simulation efficiency and flexibility. Through environment configuration, the simulation mode for each chip can be individually configured, selecting either functional or timing simulation mode. This enables the invention to support functional simulation, timing simulation, and mixed simulation. Taking a cryogenic computing system with three types of chips—cryo-crystal CPU, cryogenic DRAM, and cryogenic accelerator—as an example, the configurable mixed simulation options are shown in the table below.

[0133] Table 1 shows the configurable hybrid analog modes when the system has three types of chips.

[0134]

[0135]

[0136] Where F indicates configuration as functional simulation mode, and T indicates configuration as timing simulation mode.

[0137] 5. Supports execution environment configuration

[0138] The system proposed in this patent supports configuring chip operating parameters and modes by inputting parameters into a host computer, without requiring modifications at the underlying level, thus improving the flexibility and efficiency of simulation. For example, it allows configuring the data bit width and depth of low-temperature DRAM, the size of the cache, and the architecture of the low-temperature CPU.

[0139] 6. Includes performance statistics function

[0140] The performance of an emulator is primarily measured by its functionality, speed, flexibility, and code modifiability.

[0141] Functional performance is primarily verified by checking the received and transmitted data from the host computer to confirm the correctness of the simulation system's functions and whether the platform can quickly and accurately locate chip design problems. Functional testing consists of two parts: first, sending test data packets or commands one by one to verify the correctness of the function in order to quickly identify problems; second, sending test data packets or commands continuously, in large quantities, and for a long time in a loop to verify the functional stability.

[0142] Speed ​​performance refers to how quickly a simulation system executes a simulation program. It is typically measured by the time taken for a cryogenic multi-chip simulation platform to execute a certain number of data packets or instructions sent by a host computer. In this patent's simulation system, the speed of the room-temperature communication section is measured by recording the time (TimeTx) when the host computer sends a data packet and the time (TimeRx) when it receives a data packet. The difference between TimeRx and TimeTx is used to evaluate speed performance. For the cryogenic section, a clock counter (ClkCount) is set in the cryogenic chip to record the number of clock cycles required for the chip to execute commands. This count is read and displayed on the host computer, and multiplied by the clock cycle to obtain the cryogenic chip's running time, thus measuring speed performance.

[0143] A simulation platform needs to meet several conditions: correct functionality and timely problem detection; fast program execution speed; and simple, flexible adjustment of the structure according to development needs. Throughout the overall design process, the flexibility requirements for modifying the simulation platform code gradually change, but the platform's speed remains constant. The faster the simulation speed, the better throughout the entire development process, which has become a crucial factor limiting the application of simulation platforms. Due to their low R&D costs, high configurability, ease of maintenance, and short development time, simulators have a very wide range of applications.

[0144] Secondly, embodiments of this application provide a simulation system for a cryogenic multi-chip computing system, employing the simulation method for cryogenic multi-chip computing systems described above, such as... Figure 8As shown, the system includes:

[0145] Cross-temperature zone multi-chip analog communication system 10: includes a low-temperature multi-chip computing system and a room temperature data communication system that are interconnected. The low-temperature multi-chip computing system contains multiple chips used for calculation at low temperatures. The room temperature data communication system simulates input instructions to the low-temperature multi-chip computing system and receives the execution results output by the low-temperature multi-chip computing system for verification.

[0146] Low-temperature multi-chip functional simulation module 20: Based on the design specifications of multiple chips, it describes the functions of multiple chips used for computation in low temperature and the interactive operation functions between multiple chips, and simulates the output execution results of multiple chips.

[0147] Low-temperature multi-chip timing simulation module 30: It is used to simulate the periodic working timing of each chip under low temperature based on the design specifications of multiple chips, and to simulate the communication protocols between multiple chips, so as to simulate the timing of the low-temperature multi-chip computing system and verify the correctness of each timing sequence.

[0148] Preferably, the above-mentioned simulation system for cryogenic multi-chip computing systems further includes:

[0149] Environment configuration module: This module is used to construct different cryogenic multi-chip computing systems by configuring different execution environment parameters, and to execute simulation modes for constructing different cryogenic multi-chip computing systems by executing environment configuration. The simulation modes include: functional simulation mode, timing simulation mode, and hybrid simulation mode.

[0150] Performance statistics module: used to evaluate the functional correctness and performance parameters of cryogenic multi-chip computing systems.

[0151] Preferably, the above-mentioned room temperature data communication system includes a host computer and a data communication module. The host computer connects to the low-temperature multi-chip computing system through the data communication module. The host computer sends control commands to the low-temperature multi-chip computing system and receives the execution results fed back by the low-temperature multi-chip computing system through the data communication module.

[0152] The specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings:

[0153] like Figure 9 As shown, in a specific embodiment of the present invention, the simulation system includes: an execution environment configuration module, a functional mode module, a timing mode module, and a performance output statistics module.

[0154] Compared with existing technologies, the method of this invention provides a simulation method and platform for low-temperature multi-chip computing systems. It simulates and models complex low-temperature multi-chip systems, increases the flexibility and simplicity of debugging, is easy to operate, and greatly improves the efficiency of system design, verification, and debugging. It can identify system problems before tape-out for improvement, thereby increasing the success rate of tape-out.

[0155] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0156] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A simulation method for low-temperature multi-chip computing systems, characterized in that, The method includes: Steps for building a multi-chip analog communication system across temperature zones: Build a cryogenic multi-chip computing system and a room temperature data communication system that are interconnected. The cryogenic multi-chip computing system includes various chips used for computation at low temperatures. The room temperature data communication system simulates input instructions to the cryogenic multi-chip computing system and receives the execution results output by the cryogenic multi-chip computing system for verification. The various cryogenic multi-chips include: a cryogenic CPU, a cryogenic DRAM, a cryogenic accelerator, and a cryogenic amplifier. Low-temperature multi-chip functional simulation steps: Based on the design specifications of the various chips, behavioral-level simulation describes the functions of the various chips used for computation in low temperature and the interactive operation functions between the various chips, and simulates the output execution results of the various chips; Low-temperature multi-chip timing simulation steps: Based on the design specifications of the various chips, simulate the periodic working timing of each chip under low temperature, and simulate the communication protocol between the various chips to simulate the timing of the low-temperature multi-chip computing system, and verify the correctness of each timing sequence. Environment configuration steps: Different cryogenic multi-chip computing systems can be constructed by configuring different execution environment parameters, and different simulation modes of the cryogenic multi-chip computing systems can be constructed by executing environment configuration. The simulation modes include: functional simulation mode, timing simulation mode and hybrid simulation mode. In the hybrid simulation mode, one or more of the chips at low temperature are set to functional simulation mode, while the other chips are set to timing simulation mode.

2. The simulation method for low-temperature multi-chip computing systems according to claim 1, characterized in that, The method further includes: Performance statistics steps: Perform functional correctness assessment and performance parameter evaluation on the cryogenic multi-chip computing system.

3. The simulation method for low-temperature multi-chip computing systems according to claim 1 or 2, characterized in that, The cryogenic multi-chip functional simulation step further includes: The steps for simulating the function of a low-temperature CPU are as follows: Based on the CPU design specifications, the function of the low-temperature CPU is described by behavioral simulation. According to the architecture of the low-temperature CPU, the instruction set of the low-temperature CPU is input. According to the operating rules of the pipelined CPU, the instruction fetching, instruction decoding, instruction execution, memory access and write-back operations of the low-temperature CPU are simulated periodically, and the output execution results of the low-temperature CPU are simulated. Low-temperature DRAM functional simulation steps: Based on the DRAM design specifications, behavioral-level simulation describes the function of the low-temperature DRAM and simulates the output execution results of the low-temperature DRAM; The functional simulation steps for cryogenic accelerators are as follows: Based on the accelerator's design specifications, behavioral-level simulations describe the function of the cryogenic accelerator and simulate the output execution results of the cryogenic accelerator. The steps for simulating the function of a cryogenic amplifier are as follows: Based on the amplifier's design specifications, a behavioral-level simulation describes the function of the cryogenic amplifier and simulates the output execution results of the cryogenic amplifier.

4. The simulation method for low-temperature multi-chip computing systems according to claim 1 or 2, characterized in that, The low-temperature multi-chip timing simulation step further includes: Low-temperature CPU timing simulation steps: Based on the CPU design specifications, simulate the periodic working timing of the CPU at low temperatures, and verify the correctness of the low-temperature CPU timing. Low-temperature DRAM timing simulation steps: Based on the DRAM design specifications, simulate the first and second timings of the DRAM's internal cyclic operation at low temperatures according to the DRAM timing model, and verify the correctness of the low-temperature DRAM timings; Cryogenic accelerator timing simulation steps: Based on the accelerator's design specifications, simulate the periodic operating timing of the accelerator's internal components at cryogenic temperatures, and verify the correctness of the cryogenic accelerator timing. The timing simulation steps for a cryogenic amplifier are as follows: Based on the amplifier's design specifications, the periodic operating timing of the amplifier at cryogenic temperatures is simulated, and the correctness of the cryogenic amplifier timing is verified.

5. The simulation method for low-temperature multi-chip computing systems according to claim 2, characterized in that, The environment configuration step further includes: Hybrid simulation mode steps: Set any one or more of the various chips under low temperature to functional simulation mode, and set the other various chips to timing simulation mode. The various chips include: low temperature CPU, low temperature DRAM, low temperature accelerator and low temperature amplifier. Environmental parameter simulation configuration steps: Different cryogenic multi-chip computing systems can be constructed by configuring different execution environment parameters of the various chips.

6. The simulation method for low-temperature multi-chip computing systems according to claim 2, characterized in that, The performance statistics step further includes: Functional evaluation steps: The room temperature data communication system includes a host computer and a data communication module. The host computer is connected to the low-temperature multi-chip computing system through the data communication module. The host computer simulates inputting instructions to the various chips in the low temperature and receives the output execution results through the data communication module to verify the correctness of the functions of the various chips. Performance evaluation steps: The host computer sends multiple data packets or instructions to the various chips in the cryogenic environment to evaluate the execution time of the cryogenic multi-chip computing system.

7. The simulation method for low-temperature multi-chip computing systems according to claim 6, characterized in that, The functional evaluation steps further include: Packet-by-packet testing steps: The host computer sends test data packets or instructions to each of the various chips in the cryogenic environment to verify the correctness of the functions of the cryogenic multi-chip computing system. Massive packet testing steps: The host computer continuously and continuously sends test data packets or instructions to the various chips in the cryogenic environment for a long period of time to verify the functional stability of the cryogenic multi-chip computing system.

8. A simulation system for a cryogenic multi-chip computing system, employing the simulation method for a cryogenic multi-chip computing system as described in any one of claims 1-7, characterized in that, The system includes: A multi-chip analog communication system spanning temperature zones includes a cryogenic multi-chip computing system and a room-temperature data communication system that are interconnected. The cryogenic multi-chip computing system contains various chips used for computation at low temperatures. The room-temperature data communication system simulates input instructions to the cryogenic multi-chip computing system and receives the execution results output by the cryogenic multi-chip computing system for verification. The various cryogenic multi-chips include: a cryogenic CPU, a cryogenic DRAM, a cryogenic accelerator, and a cryogenic amplifier. Low-temperature multi-chip functional simulation module: Based on the design specifications of the multiple chips, it performs behavioral-level simulation to describe the functions of the multiple chips used for calculation in low temperature and the interactive operation functions between the multiple chips, and simulates the output execution results of the multiple chips; Low-temperature multi-chip timing simulation module: used to simulate the periodic working timing of each chip at low temperature based on the design specifications of the various chips, and to simulate the communication protocol between the various chips, so as to simulate the timing of the low-temperature multi-chip computing system and verify the correctness of each timing sequence. Environment configuration module: Different cryogenic multi-chip computing systems can be constructed by configuring different execution environment parameters, and different simulation modes of the cryogenic multi-chip computing systems can be constructed by executing environment configuration. The simulation modes include: functional simulation mode, timing simulation mode and hybrid simulation mode. In the hybrid simulation mode, one or more of the chips at low temperature are set to functional simulation mode, while the other chips are set to timing simulation mode.

9. The simulation system for a low-temperature multi-chip computing system according to claim 8, characterized in that, The system also includes: Performance statistics module: used to evaluate the functional correctness and performance parameters of the cryogenic multi-chip computing system.

10. The simulation system for a low-temperature multi-chip computing system according to claim 8, characterized in that, The room temperature data communication system includes a host computer and a data communication module. The host computer is connected to the low-temperature multi-chip computing system through the data communication module. The host computer sends control commands to the low-temperature multi-chip computing system and receives the execution results fed back by the low-temperature multi-chip computing system through the data communication module.

Images