Method for converting binary files to produce discrete loaded simulation memory models

Abstract

The application discloses a method for converting a binary file to generate a discrete loaded simulation memory model, which extracts SREC file information and converts the SREC file information into a plurality of VHX memory model HEX files, and specifically comprises the following steps: S1, linking an executable file of a system program into a loaded form; S2, converting the executable file in the loaded form into an SREC hexadecimal format file; S3, parsing the SREC hexadecimal format file, extracting the type, base address and length in each segment information, and converting the SREC hexadecimal format file into a VHX memory hexadecimal format file; and S4, when simulating a chip, analyzing the VHX memory hexadecimal format file through a script, and splitting and loading the VHX memory hexadecimal format file into different memory simulation model files according to the differences of different segment loading addresses.

Description

Technical Field

[0001] This invention relates to the field of chip simulation technology, and more specifically, to a method for converting binary files to generate discrete loaded simulation memory models, and more specifically to a method for converting Motorola srec format binary files to generate discrete loaded simulation memory models. Background Technology

[0002] The system program of a CPU chip needs to provide a self-loading process from ROM to RAM. In chip simulation, this loading process can be omitted by directly loading the executable file symbol table into the memory model, thereby accelerating the chip simulation process.

[0003] Chip system test cases are typically represented as binary programs, linked according to specifications into .text / .rodata / .data / .bss segments. The .text segment contains code, the .rodata segment contains read-only data, the .data segment contains initialized data, and the .bss segment contains uninitialized data. Since the chip's system program does not include other previously executed programs, a self-loading function is required to load the program into the corresponding CPU address space according to the linked segment space. Generally, executing the system program requires read-only ROM and read-write RAM. In a non-simulated chip operating environment, the system program is pre-loaded in ROM by default (because RAM is volatile storage, it cannot be pre-loaded). The self-loading process of the system program loads its read-write segments (.data / .bss segments) into RAM, and sometimes even its read-only segments (.text / .rodata segments) into RAM for execution. Since the loading process involves copying data from ROM to RAM, it is time-consuming. Therefore, chip simulation employs methods to accelerate this process and eliminate it. Existing chip simulation generally uses the following schemes:

[0004] 1) Using a RAM model, all data is pre-converted into a hexadecimal HEX format file suitable for chip simulation. This HEX file (also known as a VHX hexadecimal format file, see VHX format description below) is loaded into the RAM model via a backdoor using the readmemh function of the RTL (Registry Transfer Level) circuit. During simulation, a RAM boot mode is provided to execute the test program already stored in the RAM model. Because of this pre-loading, the system program can skip the self-loading process. However, this method has the drawback that the .text / .rodata segments in the pre-loaded file also occupy RAM space, making it unusable for simulations of chips with extremely limited RAM. Furthermore, the program in the real-world scenario is actually modified, and the functionality of the executable program in ROM cannot be tested during simulation, posing a risk of missed tests.

[0005] VHX is a Verilog-specific simulation memory model file, which can be loaded into a Verilog memory model by the Verilog system function $readmemX. Please refer to the following example of a VHX format file:

[0006]

[0007]

[0008] Compared to ordinary HEX files, VHX format files have an additional "@offset" marker, which indicates the offset address in the memory model where the subsequent hexadecimal data is located. Therefore, multiple "@offset" markers can be used to represent discrete data content.

[0009] 2) Minimize the use of data segments, operating only in registers and on the stack. The drawback of this approach is that the test cases do not execute programs from real-world scenarios, and it's impossible to write powerful test cases for simulation. Since the executed program only uses a portion of the CPU chip's functionality, many CPU bugs cannot be fully detected during simulation, posing a risk of missing bugs.

[0010] Therefore, the industry needs a method that can eliminate the loading process and save RAM during simulation, while still allowing testing using programs from real-world scenarios. Summary of the Invention

[0011] To address the aforementioned issues, this invention provides a method for converting binary files to generate discrete loaded simulation memory models. This method employs a discrete backdoor loading scheme, namely, an offline loader, to split the binary program into ROM and RAM models. The binary program can be directly loaded into the memory model without analyzing the symbol table, thus eliminating the loading process during simulation and saving RAM overhead. This allows for simulation testing using programs from real-world scenarios.

[0012] To achieve the above objectives, this invention provides a method for converting binary files to generate discrete loaded simulation memory models. This method extracts SREC file information and converts it into HEX files containing multiple VHX memory models, specifically including:

[0013] Step S1: Link the executable files of the system programs into a loaded form;

[0014] Step S2: Convert the loaded executable file into an SREC hexadecimal format file;

[0015] Step S3: Parse the SREC hexadecimal format file, extract the type, base address and length from each segment information, and convert the SREC hexadecimal format file into a VHX memory hexadecimal format file;

[0016] Step S4: During chip simulation, the hexadecimal format file of VHX memory is analyzed by script, and the hexadecimal format file of VHX memory is split and loaded into different memory simulation model files according to the different load addresses of different segments.

[0017] In one embodiment of the present invention, the linking method in step S1 involves processing the linking script, specifically as follows:

[0018] Edit the linker script to make the link address the same as the load address.

[0019] In one embodiment of the present invention, step S2 involves format conversion using a standard binary tool, including objcopy.

[0020] In one embodiment of the present invention, the tool used for parsing in step S3 is an SREC parser.

[0021] In one embodiment of the present invention, each segment in step S3 includes: a .text segment, a .rodata segment, a .data segment, and a .bss segment.

[0022] In one embodiment of the present invention, the process of loading different memory model files in step S4 specifically involves:

[0023] The split VHX memory hexadecimal format files are loaded into different memory simulation models through a backdoor, which includes the RTL readmemh function.

[0024] The method for generating discrete loaded simulation memory models by converting binary files provided by this invention, compared with the prior art, can directly load the data into the memory model without analyzing the symbol table. It also eliminates the loading process during simulation, saves RAM overhead, and allows simulation testing using programs from real-world scenarios, reducing the risk of some programs not being detected during simulation. Attached Figure Description

[0025] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0026] Figure 1 This is a flowchart of an embodiment of the present invention. Detailed Implementation

[0027] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0028] Normally, converting binary files to HEX files is a standard function of linkers and loaders, which will not be elaborated here. However, ordinary hexadecimal HEX only converts the binary file itself into continuous hexadecimal data, without address information or the ability to distinguish program segments. SREC format, created by Motorola, differs from ordinary binary formats. It converts the program itself into discrete hexadecimal segments, containing start addresses and size information. Motorola's original intention was to reduce the size of binary files using this format. When link addresses are not contiguous, padding between segments is not generated in the hexadecimal file. Therefore, SREC format HEX files can contain segment base addresses and size information. This embodiment uses the Motorola SREC hexadecimal format. However, since the address information in SREC format is a link address and not a load address, that is, it is the offset of the program stored in the storage medium (such as ROM) and not the address finally used by the CPU, this embodiment is a tool to extract the SREC format file information and convert it into multiple VHX memory model HEX files in order to realize the conversion of binary files to generate discrete loaded simulation memory models. Figure 1 This is a flowchart of an embodiment of the present invention, as follows: Figure 1 As shown, this embodiment provides a method for converting binary files to generate discrete loaded simulation memory models. This method extracts SREC file information and converts it into multiple VHX memory model HEX files (HEX files for Verilog HDL memory models), specifically including:

[0029] Step S1: Link the executable files of the system programs as loaded files to achieve offline loading;

[0030] In this embodiment, the linking method in step S1 involves processing the linking script, specifically as follows:

[0031] Make the linker address the same as the load address by editing the linker script (e.g., the LDS script).

[0032] Step S2: Convert the loaded executable file into Motorola SREC hexadecimal format;

[0033] In this embodiment, step S2 involves format conversion using standard binary tools, including objcopy (a GNU utility program).

[0034] Step S3: Parse the SREC hexadecimal format file, extract the type, base address and length from each segment information, and convert the SREC hexadecimal format file into a VHX memory hexadecimal format file;

[0035] In this embodiment, the tool used for parsing in step S3 is the SREC parser.

[0036] In this embodiment, each segment in step S3 includes: a .text segment, a .rodata segment, a .data segment, and a .bss segment.

[0037] Since the executable file is already loaded at this point, and the VHX format is a standard format, after the hexadecimal format of the VHX memory has been generated, the readmemh function of RTL can be called for automatic loading. Therefore, the base address of the link address is consistent with the loading address of the final symbol table, and it can be directly loaded into the memory model without analyzing the symbol table. At this point, it can be seen that the generated hexadecimal format file of the VHX memory is in discrete form, and different segments can be marked with "@load address".

[0038] Step S4: During chip simulation, the hexadecimal format file of VHX memory is analyzed by script, and the hexadecimal format file of VHX memory is split and loaded into different memory simulation model files (HEX files) according to the different load addresses of different segments.

[0039] In this embodiment, the process of loading different memory model files in step S4 specifically involves:

[0040] The split VHX memory hexadecimal format files are loaded into different memory simulation models through a backdoor, which includes the RTL readmemh function.

[0041] At this point, the .text and .rodata segments can remain in the ROM memory model, while the .data and .bss segments can remain in the RAM memory model.

[0042] The method for generating discrete loaded simulation memory models by converting binary files provided by this invention, compared with the prior art, can directly load the data into the memory model without analyzing the symbol table. It also eliminates the loading process during simulation, saves RAM overhead, and allows simulation testing using programs from real-world scenarios, reducing the risk of some programs not being detected during simulation.

[0043] Those skilled in the art will understand that the accompanying drawings are merely schematic diagrams of one embodiment, and the modules or processes shown in the drawings are not necessarily essential for implementing the present invention.

[0044] Those skilled in the art will understand that the modules in the apparatus of the embodiments can be distributed in the apparatus of the embodiments as described in the embodiments, or they can be located in one or more devices different from this embodiment with corresponding changes. The modules of the above embodiments can be combined into one module, or they can be further divided into multiple sub-modules.

[0045] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for converting binary files to generate discrete loaded simulation memory models, characterized in that: SREC file information is extracted and converted into hexadecimal format files of multiple Verilog simulation memory models; Specifically, it includes: Step S1: Link the executable file of the system program into a loaded form. The executable file is a binary file. The linking method is to process the linker script, specifically by editing the linker script LDS to make the link address the same as the load address. Step S2: Convert the loaded executable file into SREC hexadecimal format file. Specifically, the format conversion is performed using standard binary tools, including objcopy. Step S3: Parse the SREC hexadecimal format file, extract the type, base address and length from each segment information, and convert the SREC hexadecimal format file into a hexadecimal format file for the Verilog simulation memory model, where each segment includes: .text segment, .rodata segment, .data segment and .bss segment; Step S4: During chip simulation, the hexadecimal format file of the Verilog simulation memory model is analyzed by script, and the hexadecimal format file of the Verilog simulation memory model is split according to the different load addresses of different segments. The split hexadecimal format file of the Verilog simulation memory model is then loaded into different memory simulation model files through a backdoor, wherein the backdoor includes the readmemh function of RTL.

2. The method for generating a discrete loaded simulation memory model by converting binary files according to claim 1, characterized in that, The tool used for parsing in step S3 is the SREC parser.

Images