Method and device for training convolution kernel in pulse convolution neural network

Abstract

A method and device for training a convolution kernel in a pulse convolutional neural network, the method comprising: obtaining a first count value of a first counter and a second count value of a second counter, wherein the first count value is a number of input pulse signals in a training period, and the second count value is a number of output pulse signals emitted by an output neuron in the training period; and adjusting a weight of a memristor synapse corresponding to the output neuron in a memristor synapse array according to the first count value, and increasing a threshold value of the output neuron according to the second count value, if the second count value is greater than a training threshold value. In the method, synapses and neurons in the pulse convolutional neural network are implemented based on a memristor, and the synapse weight and the threshold value of the neuron are dynamically adjusted by counting frequencies of input pulse signals and output pulse signals, so that the training of the convolution kernel based on a frequency learning rule under a specific input can be realized.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of neural networks, and particularly relates to a method and device for training a convolution kernel in a spiking convolutional neural network. BACKGROUND

[0002] In recent years, deep neural networks (DNN) based on deep learning have achieved remarkable results in many aspects, such as image recognition, natural language processing, and autonomous driving. However, this deep learning-based neural network only draws on the topological structure of the brain, models the brain using mathematical methods, converts various situations to be processed into digital information through a certain coding method, and then processes this information using matrices containing different numerical values (including matrix operations, result normalization, data mapping, etc.), finally obtaining a set of data containing recognition result information. In the entire process, the matrix containing different numerical values is an artificial synapse network, and each numerical value in the matrix is a synaptic weight.

[0003] This deep learning-based neural network still has a large difference from the biological brain in principle, belongs to the second generation of artificial neural networks, and has a considerable distance from the biological brain in coding method and function implementation. In order to obtain a computing method closer to the function of the biological brain and realize brain-like computing, researchers have proposed the next generation of artificial neural networks, spiking neural networks (SNN). Spiking neural networks draw on the structure and principles of the biological brain, and information is stored in the timing and spatial relationship of pulses in spiking neural networks. Currently, the spiking neural networks using unsupervised learning methods are mostly two-layer networks containing only input and output layers, which are insufficient to handle complex problems. Therefore, by adding convolution operations commonly used in DNNs to the network, people have proposed spiking convolutional neural networks (SCNN). A five-layer convolutional spiking neural network is shown in Figure 1 The structure is the same as the current numerical calculation-based convolutional neural network structure, and contains multiple convolutional layers, pooling layers, and fully connected layers.

[0004] However, training SCNNs remains a significant challenge. Several different training methods exist for SCNNs. One method borrows the backpropagation algorithm from DNNs. While this achieves similar recognition accuracy to traditional neural networks, the training is supervised, requiring a large number of training samples, and the error propagates throughout the network, making the training process very slow. Another method utilizes the learning rules of biological synapses to train SNNs. This is unsupervised learning, not relying on large amounts of labeled data, and the update of synaptic weights is only related to the states of preceding and following neurons, thus eliminating the need for data propagation throughout the network and making training more efficient. However, this synapse-based training method is incompatible with existing computer architectures, lacking hardware support like graphics processing units (GPUs) to accelerate traditional neural networks, resulting in low training efficiency and low recognition accuracy. Summary of the Invention

[0005] This application provides a method and apparatus for training convolution kernels in a spiking convolutional neural network. Based on the frequency learning rules of synapses, it realizes the unsupervised learning process of the spiking convolutional neural network, thereby effectively improving training efficiency.

[0006] In a first aspect, embodiments of this application provide a method for training convolutional kernels in a spiking convolutional neural network. This method is applied to convolutional layers in the spiking convolutional neural network. For each training cycle, the method includes: acquiring a first count value of a first counter and a second count value of a second counter, wherein the first count value is the number of input pulse signals within the training cycle, the input pulse signals are input to the output neuron via a memristor synaptic array, and the input pulse signals are used to control the increase of the membrane potential of the output neuron; the second count value is the number of output pulse signals emitted by the output neuron within the training cycle, and the output neuron emits an output pulse signal when the membrane potential is greater than a threshold value for the output neuron; if the second count value is greater than a training threshold, then the weights of the memristor synapses corresponding to the output neurons in the memristor synaptic array are adjusted according to the first count value.

[0007] The above technical solution can dynamically adjust the synaptic weights and output neuron thresholds in the network by statistically analyzing the frequencies of the input and output pulse signals, thereby enabling memristor-based convolutional kernel training under specific inputs.

[0008] In one possible design of the first aspect, adjusting the weight of the memristor synapse corresponding to the output neuron in the memristor synaptic array according to the first count value includes: if the first count value is less than a set threshold, then decreasing the weight of the memristor synapse; if the first count value is greater than or equal to the set threshold, then increasing the weight of the memristor synapse.

[0009] In one possible design of the first aspect, the output neuron is a threshold-adjustable neuron; the method further includes: if a second count value is greater than a training threshold, then increasing the threshold of the output neuron according to the second count value, the threshold being used to control the output neuron to output a pulse signal.

[0010] In the above technical solution, the output neuron can have a post-training protection mechanism, so that the output neuron will not be excited by input signals with other characteristics for a period of time after weight adjustment, thus protecting the already trained weights.

[0011] In one possible design of the first aspect, the threshold of the output neuron is also controlled by the history of the output neuron emitting output pulse signals and the output pulse signals emitted by other output neurons.

[0012] In the above technical solution, the output neuron can have a refractory period function and a lateral competition function, so that the output neuron will not be excited within a certain step after it emits an output pulse signal, and will not be excited when other output neurons emit output pulse signals, thereby ensuring that only one output neuron is excited at each time point.

[0013] In one possible design of the first aspect, the method further includes: when the training period ends, clearing the first count value of the first counter and the second count value of the second counter.

[0014] In one possible design of the first aspect, each memristor synapse in the memristor synapse array is composed of a non-volatile memristor, and the output neuron is composed of a volatile memristor and associated circuit modules.

[0015] The above technical solution uses memristors as key components to realize synapses and neurons in pulsed convolutional neural networks, which can effectively reduce storage resource consumption and save the area occupied by synapses and neurons in the chip.

[0016] Secondly, embodiments of this application provide an apparatus for training convolutional kernels in a pulsed convolutional neural network. The apparatus includes: an input signal generation module, a signal generator, a memristor synapse, an output neuron, a first counter, a second counter, and a training signal generation module. The input signal generation module is used to pulse-encode input information to generate input pulse information and send the input pulse information to the signal generator. The signal generator is used to generate an input pulse signal based on the input pulse information and input the input pulse signal to the memristor synapse and the first counter. The memristor synapse is used to input the processed input pulse signal to the output neuron, and the input pulse signal is used to control the increase of the membrane potential of the output neuron. The output neuron is used to emit a signal when the membrane potential is greater than or equal to a threshold value of the output neuron. The system includes: an output pulse signal; a first counter for recording the number of input pulse signals within a training cycle and sending the recorded first count value to the training signal generation module; a second counter for recording the number of output pulse signals emitted by the output neuron within a training cycle and sending the recorded second count value to the training signal generation module; a training signal generation module for receiving the first count value from the first counter and the second count value from the second counter, and if the second count value is greater than a training threshold, generating training pulse information based on the first count value and sending the training pulse information to a signal generator; and a signal generator for generating a training pulse signal based on the training pulse information and inputting the training pulse signal into the memristor synapse, wherein the training pulse signal is used to adjust the weight of the memristor synapse.

[0017] In one possible design of the second aspect, if the first count value is less than a set threshold, the training pulse signal is used to decrease the weight of the memristor synapse; if the first count value is greater than or equal to the set threshold, the training pulse signal is used to increase the weight of the memristor synapse.

[0018] In one possible design of the second aspect, the output neuron is a threshold-adjustable neuron; the training signal generation module is further configured to: if the second count value is greater than the training threshold, generate a control signal based on the second count value, and input the control signal to the output neuron, the control signal being used to increase the threshold of the output neuron, the threshold being used to control the output neuron to emit an output pulse signal.

[0019] In one possible design of the second aspect, the threshold of the output neuron is also controlled by the history of the output neuron emitting output pulse signals and the output pulse signals emitted by other output neurons.

[0020] In one possible design of the second aspect, the output neuron consists of a volatile memristor and associated circuit modules.

[0021] In one possible design of the second aspect, the device further includes a gating switch; the gating switch is used to: connect the memristor synapse to a signal generator when the memristor synapse needs to receive a pulse signal; and ground the memristor synapse when the memristor synapse does not need to receive a pulse signal.

[0022] In one possible design of the second aspect, the device further includes a reset module; the reset module is configured to: send a first reset signal to a first counter and a second reset signal to a second counter at the end of each training cycle, wherein the first reset signal is used to clear a first count value of the first counter and the second reset signal is used to clear a second count value of the second counter.

[0023] The beneficial effects of any possible design in the second aspect and the second aspect can be referred to the corresponding description in the first aspect, and will not be repeated here.

[0024] Thirdly, embodiments of this application provide a computing device in which a spiking convolutional neural network is deployed for implementing the aforementioned method of training convolutional kernels in the spiking convolutional neural network. The computing device may include one or more apparatuses or circuit units for training convolutional kernels in the aforementioned spiking convolutional neural network. Attached Figure Description

[0025] Figure 1 This is a schematic diagram of the structure of a pulsed convolutional neural network applicable to the embodiments of this application;

[0026] Figure 2 A flowchart illustrating a method for training convolutional kernels in a pulsed convolutional neural network, provided in an embodiment of this application;

[0027] Figure 3 A schematic diagram of the training process for a method of training convolution kernels in a pulsed convolutional neural network, provided in an embodiment of this application;

[0028] Figure 4 This is a schematic diagram of the input signal and the hardware structure for implementing the above-described pulsed convolutional neural network in an embodiment of this application;

[0029] Figure 5 This is a schematic diagram of the weight distribution of the memristor synaptic array obtained by training six 5*5 images under different training times in an embodiment of this application.

[0030] Figure 6 This is an image of the MNIST dataset referenced in an embodiment of this application;

[0031] Figure 7 This is a schematic diagram of the weight distribution of the convolutional kernels obtained after training on the images in the MNIST dataset described above, according to an embodiment of this application.

[0032] Figure 8 A schematic diagram of a device for training convolutional kernels of a pulsed convolutional neural network, provided in an embodiment of this application;

[0033] Figure 9 This is another schematic diagram of a device for training convolutional kernels of a pulsed convolutional neural network, provided in an embodiment of this application. Detailed Implementation

[0034] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the embodiments of this application will be further described in detail below with reference to the accompanying drawings.

[0035] Convolution processing is a common operation in vision systems and neural network algorithms. Convolutional spiking neural networks based on convolution processing can be applied to application scenarios that require the extraction of input information features, such as image processing (e.g., image classification, recognition, and detection), speech processing (e.g., voice wake-up and keyword recognition), autonomous driving, and natural language processing.

[0036] The embodiments of this application are applicable to the convolutional layers of a convolutional spiking neural network. For example, a five-layer convolutional spiking neural network structure is as follows: Figure 1 As shown, the first layer is the input layer, the second and fourth layers are convolutional layers, and the third and fifth layers are pooling layers. The input layer converts the input information into pulse signals, which are then fed into the convolutional layers composed of memristor synapses and threshold-adjustable neurons. When a neuron is activated, it emits a pulse signal. The frequency of these pulse signals is recorded and used to modify the connection weights and propagate backward, allowing different convolutional layers to perform feature extraction based on different convolutional kernels.

[0037] The convolutional layer of the pulsed convolutional neural network in this embodiment may include an input signal generation module, a set of signal generators, a memristor synapse array, a set of output neurons, a first counter, a second counter corresponding to each output neuron, and a training signal generation module.

[0038] The input signal generation module encodes the input external information into pulses, generating input pulse information, which is then sent to the signal generator. The signal generator generates corresponding input pulse signals based on the input pulse information and inputs them to the memristor synaptic array and the corresponding first counter. The input pulse information describes parameters such as the amplitude, width, frequency, and number of input pulse signals. The memristor synaptic array inputs the processed input pulse signals to one or more output neurons. Each signal generator has a corresponding first counter to record the number of input pulse signals generated by the signal generator within a training cycle. The input pulse signal causes a change in the membrane potential of the output neuron. When there is an input pulse signal, the membrane potential of the output neuron increases; when there is no input pulse signal, the membrane potential of the output neuron gradually decreases. When the membrane potential of the output neuron is greater than or equal to its threshold (also called the activation threshold), the output neuron is activated and emits a pulse signal as the output pulse signal. After emitting the output pulse signal, the output neuron gradually returns to a resting state and does not activate again for a fixed period of time; this function is called the refractory period function of the output neuron. Each output neuron can have a corresponding second counter to record the number of output pulse signals emitted by that output neuron in a training cycle. The training signal generation module is used to train the weights of each memristor synapse in the memristor synapse array based on the frequencies of the input and output pulse signals. Specifically, the training signal generation module can generate training pulse information based on the count values ​​of the first and second counters and send it to the signal generator. The signal generator then generates corresponding training pulse signals based on the training pulse information and inputs them into the memristor synapse array to change the weights of the memristor synapses in the array. The training pulse information can be used to describe parameters such as the amplitude, width, frequency, and number of training pulse signals.

[0039] For example, the set of signal generators may include M signal generators, each corresponding to a first counter; the memristor synapse array may consist of M rows and N columns of memristor synapses; and the set of output neurons may include N output neurons, each corresponding to a second generator. Each signal generator corresponds to a row of memristor synapses in the memristor synapse array, and each output neuron corresponds to a column of memristor synapses in the memristor synapse array, where M and N are both positive integers.

[0040] Furthermore, the output neuron can be a threshold-adjustable neuron, possessing a refractory period function and a lateral competition function after pulse excitation. The refractory period function and lateral competition function can be achieved by adjusting the threshold of the output neuron. That is, the threshold of an output neuron is controlled by the history of its own output pulse signals; the closer the time since the last output pulse signal, the higher the threshold, and as the time since the last output pulse signal increases, the threshold gradually decreases. The threshold of an output neuron is also controlled by the output pulse signals emitted by other output neurons in the same layer. The threshold of this output neuron is higher when other output neurons emit output pulse signals, so that this output neuron will not be excited when other output neurons emit output pulse signals, thereby ensuring that only one output neuron is excited at each time point. In addition, the output neuron can also have a post-training protection mechanism. The training signal generation module can control the threshold of the output neuron to increase while changing the weights of the memristor synapse (for example, by providing a control signal to the digital-to-analog converter in the output neuron to control the digital-to-analog converter to output a higher voltage), thereby preventing the output neuron from being excited by input signals with other characteristics for a period of time after weight adjustment, protecting the already trained weights.

[0041] Optionally, the memristor synapses in the aforementioned memristor synapse array can be composed of non-volatile memristors, specifically, the memristors can have different resistance states, and these resistance states can be maintained for a long time. The aforementioned output neuron can be composed of volatile memristors and related circuit modules to support its threshold adjustable characteristic.

[0042] Optionally, the convolutional layer may also include a multiplexer (MUX) array, through which the signal generator is connected to the memristor synapses in the memristor synapse array. When the memristor synapse needs to receive a pulse signal, the MUX selects the signal generator to the memristor synapse; otherwise, the MUX selects the ground line to the memristor synapse.

[0043] Based on the convolutional layers described above, embodiments of this application provide a method for training convolutional kernels in a spiking convolutional neural network. This method can be executed by a training signal generation module and is used to dynamically adjust synaptic weights and neuron thresholds based on memristor synapse frequency learning rules, thereby realizing the unsupervised learning process of the spiking convolutional neural network.

[0044] The actual training process may include one or more training cycles, and for each training cycle, such as Figure 2 As shown, the method may include:

[0045] Step S201: Obtain the first count value of the first counter and the second count value of the second counter.

[0046] The first count value is the number of input pulse signals recorded by the first counter during the current training cycle. These input pulse signals are generated by a signal generator and then input to the output neuron via a memristor synaptic array, causing an increase in the membrane potential of the output neuron. The second count value is the number of output pulse signals emitted by the output neuron during the current training cycle, recorded by the second counter. The output neuron emits an output pulse signal when its membrane potential is greater than its threshold. The output neuron can be one of the output neurons in the aforementioned group.

[0047] Step S202: If the second count value is greater than the training threshold, then adjust the weight of the memristor synapse corresponding to the output neuron in the memristor synapse array according to the first count value.

[0048] In this embodiment, if the second count value is greater than the training threshold, it indicates that the output neuron emits a large number of output pulse signals in the current training cycle, i.e., the frequency of the output pulse signals is high. At this time, the training signal generation module can generate training pulse information based on the first count value, and then the signal generator can generate a specific training pulse signal based on this training pulse information to change the conductance value of the memristor synapse corresponding to the output neuron in the memristor synapse array, thereby adjusting the weight of the memristor synapse corresponding to the output neuron in the memristor synapse array.

[0049] Specifically, the training signal generation module can adjust the weights based on the frequency of the input pulse signal (i.e., the frequency learning rule). When the first count value is less than a set threshold (i.e., the frequency of the input pulse signal is relatively low), the weight of the corresponding memristor synapse can be reduced. Accordingly, the training pulse information and training pulse signal are used to reduce the weight of the memristor synapse corresponding to the output neuron in the memristor synapse array, or in other words, to reduce the conductance of the memristor synapse corresponding to the output neuron in the memristor synapse array.

[0050] When the first count value is greater than or equal to the set threshold (i.e., the frequency of the input pulse signal is relatively high), the weight of the corresponding memristor synapse can be increased. Accordingly, the training pulse information and training pulse signal are used to increase the weight of the memristor synapse corresponding to the output neuron in the memristor synapse array, or in other words, to increase the conductance value of the memristor synapse corresponding to the output neuron in the memristor synapse array.

[0051] Furthermore, if the second count value is greater than the training threshold, the training signal generation module can generate a control signal and input the control signal to the output neuron to raise the threshold of the output neuron. This makes it more difficult for the output neuron that has already emitted a lot of output pulse signals to emit output pulse signals, and makes the difficulty of emitting output pulse signals among the various output neurons similar, thereby ensuring that the array obtained through training includes more features.

[0052] As described above, each signal generator has a corresponding first counter to record the number of input pulse signals generated by the signal generator in one training cycle. Each output neuron has a corresponding second counter to record the number of output pulse signals generated by the output neuron in one training cycle. Thus, it can be understood that steps S201 to S202 above describe the weight adjustment mechanism from the perspective of a signal generator and an output neuron.

[0053] In practical applications, the training signal generation module can obtain the first count values ​​of the first counters corresponding to M signal generators and the second count values ​​of the second counters corresponding to N output neurons, and then adjust the M weights of each output neuron in the memristor synapse array and the threshold of each output neuron. Specifically, for a particular output neuron, after determining that the second count value of the second counter corresponding to that output neuron is greater than the training threshold, the training signal generation module can adjust the different weights corresponding to that output neuron to different degrees according to the first count values ​​of the first counters corresponding to different signal generators. For example, if the first count value of the first counter corresponding to the signal generator in the first row is less than the set threshold, the training signal generation module can correspondingly reduce the weight of the memristor synapse in the first row of the memristor synapse array corresponding to that output neuron; if the first count value of the first counter corresponding to the signal generator in the second row is greater than or equal to the set threshold, the training signal generation module can correspondingly increase the weight of the memristor synapse in the second row of the memristor synapse array corresponding to that output neuron.

[0054] At the end of a training cycle, the training signal generation module can reset the count values ​​of the first counter and the second counter to zero. Exemplarily, a first reset signal can also be sent to the first counter, and a second reset signal can be sent to the second counter, thereby causing the count values ​​of the first counter and the second counter to be reset to zero at regular intervals.

[0055] Figure 3 This example illustrates the adjustment mechanism of the weights of the memristor synaptic array and the threshold of the output neuron in the training method provided in this application. For example... Figure 3As shown, external information or pulse information from input neurons, after pulse encoding, can be input as input pulse signals 301 into the memristor synaptic array 302. Simultaneously, the first counter 306 records the number of input pulse signals within one training cycle T. The input pulse signals processed by the memristor synaptic array cause a change in the membrane potential of the output neuron 303. When there is a pulse, the membrane potential of the output neuron increases; when there is no pulse, the membrane potential gradually decreases. When the membrane potential of the output neuron exceeds its threshold 304, the output neuron emits a pulse, which serves as the output pulse signal 305. The second counter 307 records the number of output pulse signals emitted by the output neuron within one training cycle T. After emitting the output pulse signal, the output neuron gradually returns to a resting state and does not fire again within a fixed time step.

[0056] During training cycle T, when the value recorded by the second counter exceeds the set training threshold 308, according to the protection mechanism of the output neuron, the threshold of the output neuron will be increased 310 to increase the difficulty for the output neuron to emit an output pulse signal. Simultaneously, the training signal generation module generates a specific write pulse based on the value of the first counter to change the conductance of the memristors in the memristor synapse array, i.e., adjust the weights 309. The weight adjustment rule is controlled by the frequency of the input pulse signal (which can be called the frequency learning rule): when the input frequency is less than the set value, the weight of the corresponding synapse is reduced, i.e., the given training pulse signal causes the conductance of the memristor to decrease; when the input frequency is greater than the set value, the weight of the corresponding synapse is increased, i.e., the given training pulse signal causes the conductance of the memristor to increase. At the end of each training cycle T, the values ​​recorded by the first and second counters are periodically cleared 311. This application does not specifically limit the rule for changing the weights based on the change in pulse frequency. Figure 3 The pattern shown is only one example.

[0057] In a specific example, such as Figure 4 As shown, multiple 5×5 images can be used as input signals to train multiple 5×5 convolutional kernels. The core components are a training signal generation module connected to two counters and a set of output neurons. The key steps are to count the input and output pulse signals using counters and generate training pulse signals based on the counting results. Simultaneously, the output neurons must possess a refractory period after pulse excitation and lateral competition capabilities. A protection mechanism is activated after training to improve training effectiveness.

[0058] Specifically, 25 signal generators 410 are connected to a 25-row, 8-column memristor synaptic array 430 via a multiplexer (MUX) array 420. Each column of the memristor synaptic array 430 is connected to an output neuron 440. The signal generators can also be called input neuron pulse generators, and this is not a limitation.

[0059] The input pulse information, after being encoded from the six signals used as input signals, is processed by 25 signal generators 410 to generate corresponding input pulse signals. During training, the input pulse signals corresponding to the six images are sequentially input into the memristor synapse array 430 via the MUX array 420; the input pulse signals are simultaneously input into the first counter 460 to record the number of input pulse signals over a period of time, and are periodically reset to zero. Figure 4 The input signal is obtained by expanding the first input image. The frequency of the input pulse signal is encoded according to the grayscale of the pixels in the input signal. The whiter the pixel, the higher the frequency of the input pulse signal; the darker the pixel, the lower the frequency of the input pulse signal.

[0060] After the input pulse signals obtained from different image encodings pass through the memristor synaptic array 430, they cause the membrane potential of the corresponding output neurons 440 to change to different degrees. When the membrane potential of an output neuron 440 exceeds the threshold, the output neuron 440 is excited and emits an output pulse signal. The output pulse signal is simultaneously input into the second counter 450 to record the number of output pulse signals emitted by the output neuron 440 within a certain period of time, and is reset to zero at regular intervals.

[0061] During training, the training signal generation module 470 can acquire a first count value from the first counter 460 and a second count value from the second counter 450. For example, after its recorded first count value changes, the first counter 460 can send an updated first count value to the training signal generation module 470, thereby enabling the training signal generation module 470 to acquire the first count value. Similarly, after its recorded second count value changes, the second counter 450 can send an updated second count value to the training signal generation module 470, thereby enabling the training signal generation module 470 to acquire the second count value.

[0062] When the second count value of the second counter 450 corresponding to a certain output neuron 440 is greater than the training threshold, the 25 memristor synapses connected to that output neuron 440 need to modify their conductance values ​​(i.e., modify their weights) according to the first count value of their respective first counters 460. At this time, the training signal generation module 470 can generate training pulse information and send it to the signal generator 410. The signal generator 410 is selected and issues a write pulse to modify the conductance value of the memristor according to the received training pulse information. When the first count value of the first counter 460 is large, it indicates that the input pulse frequency is large, and the conductance value of the memristor synapse is increased accordingly; when the first count value of the first counter 460 is small, it indicates that the input pulse frequency is small, and the conductance value of the memristor synapse can be decreased accordingly. Finally, the conductance values ​​of each memristor synapse in the memristor synapse array are read, and the features obtained after training are stored in the conductance combination of each column of memristor synapses. In addition, when the second count value of the second counter 450 corresponding to the output neuron 440 is greater than the training threshold, the training signal generation module 470 can also activate the protection mechanism at the same time to increase the threshold of the corresponding output neuron 440.

[0063] Figure 5 This example illustrates the weight distribution of a 25×8 synaptic array after training on six 5×5 images, across different iterations—the training process. It can be seen that each 5×5 square is composed of 25 synaptic weight values. As the number of training iterations increases, the weight distribution within a convolutional kernel gradually changes from completely random at the beginning to having certain shape characteristics. After a certain number of training iterations, the shapes exhibited by six output neurons are identical to the input pattern, meaning the convolutional kernel has learned the features of the input pattern.

[0064] In this embodiment of the application, the training images for the convolution kernel can also be obtained from larger images (such as...). Figure 6 The handwritten digit recognition image from the MNIST dataset (shown) is obtained by windowing. For example, a 5x5 window can be used to window a 28×28 image with a step size of 2. Each pause is encoded as a pulse sequence and input into the memristor synaptic array. Considering that the input image contains more features in this scenario, a 25×16 memristor synaptic array can be selected and connected to more output neurons, thereby extracting features from the input containing more features. The 25×16 memristor synaptic array is trained using the same training method described above as for the 25×8 memristor synaptic array. After training, the conductance value of the memristor synaptic array is read.

[0065] Figure 7 An example is shown showing the weight distribution of the 16 convolutional kernels after training on images from the MNIST dataset, such as... Figure 7As shown, the 16 convolutional kernels exhibit a variety of different features, indicating that the training process of convolutional kernels for actual images can be completed through the training method based on frequency learning rules, which is beneficial for practical applications.

[0066] This application also provides an apparatus for training convolution kernels in a pulsed convolutional neural network, the logical structure of which is as follows: Figure 8 As shown, it consists of two main parts: SNN inference and SNN training, which are marked with dashed boxes. These two parts can be considered as two sets of functional modules.

[0067] The SNN inference part is used to encode the input information and generate input pulse signals 810. The input pulse signals are then input into a memristor synapse array 820 composed of non-volatile memristors. After passing through the synapse, the input pulse signals reach the volatile memristor neurons 830. These volatile memristor neurons 830 are threshold-adjustable neurons. After processing the signal, the volatile memristor neurons 830 output pulses. The processed information is encoded in the frequency or timing of the output pulses.

[0068] The SNN training section includes two sets of counters, a first counter 840 and a second counter 860, used to record the frequency of pulse signals emitted by neurons before and after the synapse. The count values ​​recorded by the two sets of counters are input to the training signal generation module 850. The training signal generation module 850 calculates based on the count values ​​of the two sets of counters and outputs training pulse signals to the non-volatile memristor synapse array 820, thereby adjusting the weight of the memristor synapses. At the same time, the training signal generation module 850 also outputs control signals to the volatile memristor neurons 830, thereby adjusting the threshold of the volatile memristor neurons 830.

[0069] As can be seen from the above, the convolution kernel training method based on frequency learning rules in this application embodiment can dynamically adjust the synaptic weights and the threshold of the output neuron by statistically analyzing the frequency of the pulse signals of the input memristor synaptic array and the pulse signals emitted by the output neuron, thereby realizing convolution kernel training based on memristor synapses under specific inputs.

[0070] Compared to existing spiking neural networks based on digital synaptic convolutional kernels, the training method provided in this application has higher computational efficiency and lower power consumption. Furthermore, by utilizing memristors as key components to implement synapses and neurons in the spiking convolutional neural network, it effectively saves the area of ​​synaptic and neuron circuitry on the chip. Compared to traditional fully connected spiking neural networks, the spiking convolutional neural network using a convolutional kernel structure in this application effectively reduces the number of synapses and neurons, reduces the resource overhead of synaptic weights, and helps to expand the scale and functionality of the spiking convolutional neural network.

[0071] This application also provides another device for training convolution kernels in a pulsed convolutional neural network, which can specifically be a memristor-based circuit unit. In practical use, multiple of these circuit units can be connected into a network as described above to complete the overall function of the pulsed convolutional neural network.

[0072] like Figure 9 As shown, the device includes: an input signal generation module 910, a signal generator 920, a gating switch 930, a memristor synapse 940, an output neuron 950, a first counter 970, a second counter 960, and a training signal generation module 980. Optionally, it also includes a reset module 990.

[0073] The input pulse generation module 910 encodes the input signal into pulse information, converting it into the required input pulse information, and sends it to the signal generator 920. The signal generator 920 generates the corresponding input pulse signal based on the input pulse information. For example, white pixels require high-frequency pulses, and black pixels require low-frequency pulses. It should be noted that the input signal can come from external input or from the output of the previous layer of neurons, and is not limited to any particular source.

[0074] The input pulse signal generated by the signal generator 920 is input to the memristor synapse 940 (as shown by memristor M1). The gating switch 930, which is part of the multiplexer MUX array, is used to select the path connected to the memristor synapse 940. When the memristor synapse 940 needs to receive a pulse signal, the gating switch 930 connects the memristor synapse 940 to the signal generator 920; otherwise, the memristor synapse 940 is grounded.

[0075] Output neuron 950 is a threshold-adjustable neuron, such as... Figure 9 As shown in the dashed box, the output neuron 950 may include a memristor M2, a voltage divider resistor R1, a digital-to-analog converter (DAC), and a comparator (CMP). The first terminal of the memristor synapse M1 is connected to the gating switch S1. The second terminal of the memristor synapse M1 is connected to the first terminal of the memristor M2. The second terminal of the memristor M2 is connected to the first input terminal of the comparator CMP and the first terminal of the voltage divider resistor R1. The second terminal of the voltage divider resistor R1 is grounded. The output terminal of the DAC is connected to the second input terminal of the comparator CMP. The voltage across the voltage divider resistor R1 is the membrane potential of the output neuron 950, and the output voltage of the DAC is the threshold voltage of the output neuron 950.

[0076] Specifically, the input pulse signal from the memristor synapse array M1 is input to the memristor M2, causing the conductance of the memristor M2 to increase, which in turn causes the voltage Vm across the voltage divider resistor R1 to increase, i.e., the membrane potential of the output neuron 950 to increase. When the membrane potential of the output neuron 950 is greater than the threshold Vth, the comparator CMP outputs an output pulse signal, indicating that the neuron is activated. It should be noted that the threshold of the output neuron 950 can be controlled by its own pulse firing history; the closer to the last pulse firing time, the higher its threshold, i.e., the higher the voltage output by the digital-to-analog converter DAC. The threshold of the output neuron 950 can also be controlled by other output neurons in the same layer. When other output neurons emit output pulse signals, the digital-to-analog converter DAC will output a very high voltage, indicating that the threshold of the output neuron 950 is very high at this time. This is used to control the output neuron 950 so that it will not be activated when other output neurons are activated, thus ensuring that only one output neuron is activated at each time point. In addition, after training, the neuron can activate a protection mechanism. The training signal generation module 980 will control its threshold to rise, for example, by controlling the digital-to-analog converter (DAC) to output a higher voltage, so that it will not be excited by input signals with other characteristics for a period of time after weight adjustment, thus protecting the already trained weights.

[0077] The input pulse signal generated by the signal generator 920 is also input to the first counter 970 to record the number of input pulse signals over a period of time, i.e., the input pulse frequency. The output pulse signal emitted by the comparator CMP is also input to the second counter 960 to record the number of output pulse signals over a period of time, i.e., the output pulse frequency. The values ​​recorded by the two counters are sent to the training signal generation module 980, which calculates the relevant information of the training pulse according to the weight change rule. The training pulse information is then transmitted to the signal generator 920, which emits a training pulse signal and inputs it to the memristor synapse 940 to adjust the weights of the memristor synapse 940.

[0078] The aforementioned device may further include a reset module 990, which periodically sends reset signals to the two counters. For example, at the end of each training cycle, a first reset signal is sent to the first counter 970 and a second reset signal is sent to the second counter 960, thereby periodically resetting the count values ​​recorded by the two counters to zero. The reset module may be part of the aforementioned training signal generation module (i.e., it can be understood as the training signal generation module sending reset signals to the two counters), or it may be independent of the training signal generation module but synchronized in time. This application does not limit this.

[0079] This application provides a circuit unit for implementing a training device for a spiking neural network convolution kernel based on memristors. Specifically, the input signal is processed by the input pulse generation module to obtain corresponding input pulse information, which is then transmitted to the signal generator to generate the input pulse signal. After the input pulse signal is processed by the memristor synapse, the change in the conductance of the memristor M2 causes a change in one of the input terminals of the comparator, thereby simulating the rise in the neuron's membrane potential. The threshold of the output neuron is generated by a digital-to-analog converter (DAC), and the output of the DAC is connected to the other input terminal of the comparator. The comparator compares the threshold with the membrane potential and generates a corresponding output signal. A periodic signal from the reset module resets the count values ​​recorded in the two counters to zero at regular intervals. The training signal generation module receives the count values ​​from the two counters, calculates the required training pulse signal information based on the count values ​​of the two counters, and transmits the information to the signal generator. The signal generator generates the training pulse signal, changes the weight value of the memristor synapse, and thus completes one cycle of training.

[0080] As described above, this application provides a hardware circuit structure for training the convolutional kernels of a spiking neural network. This hardware circuit structure uses memristors to implement synapses and neurons in the spiking convolutional neural network, and the corresponding convolutional kernels can be trained using unsupervised training methods. Implementing the spiking convolutional neural network based on this hardware circuit structure not only effectively saves the area of ​​the synaptic and neuron circuits in the chip and reduces computational resource overhead, but also facilitates the application of the aforementioned convolutional kernel training method to the inference computation of larger-scale spiking convolutional neural networks.

[0081] This application also provides a computing device in which a spiking convolutional neural network is deployed for implementing the aforementioned method of training convolutional kernels in the spiking convolutional neural network. The computing device may include one or more apparatuses or circuit units for training the convolutional kernels in the aforementioned spiking convolutional neural network.

[0082] It should be noted that the embodiments provided in this application are merely illustrative. Those skilled in the art will understand that, for the sake of convenience and brevity, the descriptions of each embodiment have different focuses, and parts not described in detail in a certain embodiment can be referred to in the relevant descriptions of other embodiments. The features disclosed in the embodiments, claims, and drawings of this invention can exist independently or in combination. Features described in hardware form in the embodiments of this invention can be executed by software, and vice versa. No limitations are imposed here.

Claims

1. A method for training convolutional kernels in a pulsed convolutional neural network, characterized in that, The method is applied to the convolutional layer in a pulsed convolutional neural network. For each training cycle of unsupervised learning, the method includes: Obtain a first count value from a first counter and a second count value from a second counter; the first count value is the number of input pulse signals during the training cycle, the input pulse signals are input to the output neuron via a memristor synaptic array, and the input pulse signals are used to control the increase of the membrane potential of the output neuron; the second count value is the number of output pulse signals emitted by the output neuron during the training cycle, the output neuron emits the output pulse signal when the membrane potential is greater than the threshold of the output neuron; If the second count value is greater than the training threshold, then the weight of the memristor synapse corresponding to the output neuron in the memristor synapse array is adjusted according to the first count value.

2. The method according to claim 1, characterized in that, Based on the first count value, the weights of the M memristor synapses corresponding to the output neurons in the memristor synapse array are adjusted, including: If the first count value is less than a set threshold, then the weight of the memristor synapse is reduced; If the first count value is greater than or equal to a set threshold, the weight of the memristor synapse is increased.

3. The method according to claim 1, characterized in that, The output neuron is a threshold-adjustable neuron; The method further includes: If the second count value is greater than the training threshold, then the threshold of the output neuron is increased according to the second count value, and the threshold is used to control the output neuron to emit an output pulse signal.

4. The method according to claim 3, characterized in that, The threshold of the output neuron is also controlled by the history of the output neuron emitting output pulse signals and the output pulse signals emitted by other output neurons.

5. The method according to any one of claims 1 to 4, characterized in that, The method further includes: When the training cycle ends, the first count value of the first counter and the second count value of the second counter are reset to zero.

6. The method according to any one of claims 1 to 4, characterized in that, Each memristor synapse in the memristor synapse array is composed of a non-volatile memristor, and the output neuron is composed of a volatile memristor and related circuit modules.

7. A device for training convolution kernels in a pulsed convolutional neural network, characterized in that, The device includes an input signal generation module, a signal generator, a memristor synapse, an output neuron, a first counter, a second counter, and a training signal generation module; Specifically, for each training cycle of unsupervised learning: The input signal generation module is used to perform pulse encoding on the input information, generate input pulse information, and send the input pulse information to the signal generator; The signal generator is used to generate an input pulse signal based on the input pulse information, and input the input pulse signal to the memristor synapse and the first counter; The memristor synapse is used to input the processed input pulse signal to the output neuron, and the input pulse signal is used to control the increase of the membrane potential of the output neuron; The output neuron is used to emit an output pulse signal when the membrane potential is greater than or equal to the threshold of the output neuron; The first counter is used to record the number of input pulse signals within a training cycle, and to send the recorded first count value to the training signal generation module; The second counter is used to record the number of output pulse signals emitted by the output neuron in one training cycle, and to send the recorded second count value to the training signal generation module; The training signal generation module is used to receive a first count value of the first counter and a second count value of the second counter. If the second count value is greater than the training threshold, training pulse information is generated according to the first count value, and the training pulse information is sent to the signal generator. The signal generator is further configured to generate a training pulse signal based on the training pulse information, and input the training pulse signal into the memristor synapse, wherein the training pulse signal is used to adjust the weight of the memristor synapse.

8. The apparatus according to claim 7, characterized in that, If the first count value is less than a set threshold, the training pulse signal is used to reduce the weight of the memristor synapse; If the first count value is greater than or equal to the set threshold, the training pulse signal is used to increase the weight of the memristor synapse.

9. The apparatus according to claim 7, characterized in that, The output neuron is a threshold-adjustable neuron; The training signal generation module is also used for: If the second count value is greater than the training threshold, a control signal is generated based on the second count value and input to the output neuron. The control signal is used to increase the threshold of the output neuron, and the threshold is used to control the output neuron to emit an output pulse signal.

10. The apparatus according to claim 9, characterized in that, The threshold of the output neuron is also controlled by the history of the output neuron emitting output pulse signals and the output pulse signals emitted by other output neurons.

11. The apparatus according to any one of claims 7 to 10, characterized in that, The output neuron consists of a volatile memristor and related circuit modules.

12. The apparatus according to any one of claims 7 to 10, characterized in that, The device also includes a gating switch; The selector switch is used to: connect the memristor synapse to the signal generator when the memristor synapse needs to receive a pulse signal; and ground the memristor synapse when the memristor synapse does not need to receive a pulse signal.

13. The apparatus according to any one of claims 7 to 10, characterized in that, The device also includes a reset module; The reset module is used to: send a first reset signal to the first counter and a second reset signal to the second counter at the end of each training cycle, wherein the first reset signal is used to clear the first count value of the first counter, and the second reset signal is used to clear the second count value of the second counter.

14. A computing device, characterized in that, The computing device includes the apparatus as described in any one of claims 7 to 13.

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