Circuits configured to output signals and shift registers

Abstract

This invention relates to a circuit and a shift register configured to output signals. The circuit includes: a first output signal supply line, a second output signal supply line, an output line, a first p-type thin-film transistor disposed between the first output signal supply line and the output line, an n-type thin-film transistor disposed between the second output signal supply line and the output line, and a second p-type thin-film transistor disposed between the second output signal supply line and the output line. The n-type and second p-type thin-film transistors are configured to be off when the first p-type thin-film transistor is on, so as to output the signal on the first output signal supply line to the output line. The first p-type thin-film transistor is configured to be off when the n-type and second p-type thin-film transistors are on, so as to supply the signal on the second output signal supply line to the output line.

Description

Technical Field

[0001] This invention relates to a circuit and a shift register configured to output signals. Background Technology

[0002] Liquid crystal displays (LCDs) and organic light-emitting diode (OLEDs) displays are widely used as display devices. These displays include shift registers for driving (selecting) scan lines. Furthermore, there are OLED display devices that measure the characteristics of elements within the display device (e.g., driving TFTs and OLEDs) and adjust data signals based on the measurement results. Such OLED display devices that perform external compensation on the data signals include shift registers for outputting control signals used for the measurements.

[0003] Devices manufactured using LTPO technology, which integrates low-temperature polycrystalline silicon (LTPS) thin-film transistors (TFTs) and oxide semiconductor TFTs (such as IGZO TFTs) on the same substrate, have been applied to display panels. Moreover, the applications of such devices are expanding.

[0004] Products incorporating such devices can be designed to utilize device characteristics, such as using IGZO TFTs where leakage current issues arise and LTPS TFTs where high drive capability is required. Furthermore, the possibility of fabricating complementary metal-oxide-semiconductor (CMOS) devices by combining PMOS-type LTPS TFTs and NMOS-type IGZO TFTs has been investigated.

[0005] In a shift register, the potential of a node connected to the gate of the output transistor changes to a high (or low) potential during the period from data input to data output. To ensure the node is always electrically connected to either a high or low power supply, it needs to be complementaryly connected to the power supply via complementary metal-oxide-semiconductor (CMOS) transistors, including both n-channel and p-channel transistors. Compared to circuits using TFTs with a single conductivity type, CMOS circuits can offer smaller circuit size and higher reliability. Summary of the Invention

[0006] However, CMOS circuits formed by combining LTPS TFTs and oxide semiconductor TFTs have some problems caused by the characteristics of TFTs. One problem is that the large difference in mobility between LTPS and oxide semiconductors causes oxide semiconductor TFTs to occupy a larger area in CMOS circuits. For example, the mobility of IGZO is about one digit lower than that of LTPS. Another problem is that residual charge in the output lines is difficult to remove, which contradicts the low leakage characteristics of oxide semiconductor TFTs. Therefore, operational failures may occur, thus compromising reliability.

[0007] One aspect of the present invention is a circuit configured to output an output signal from an output line. The circuit includes: a first output signal supply line; a second output signal supply line; an output line; a first p-type thin-film transistor disposed between the first output signal supply line and the output line and configured to be on and off; an n-type thin-film transistor disposed between the second output signal supply line and the output line and configured to be on and off; and a second p-type thin-film transistor disposed between the second output signal supply line and the output line and configured to be on and off. When the first p-type thin-film transistor is on, the n-type and second p-type thin-film transistors are configured to be off to output a signal from the first output signal supply line to the output line. When the n-type and second p-type thin-film transistors are on, the first p-type thin-film transistor is configured to be off to supply a signal from the second output signal supply line to the output line.

[0008] One aspect of the present invention improves the characteristics of CMOS circuits.

[0009] It should be understood that the above general description and the following detailed description are exemplary and explanatory, and not intended to limit the invention. Attached Figure Description

[0010] Figure 1 An example configuration of an OLED display device is illustrated schematically;

[0011] Figure 2A An example configuration of pixel circuitry in an OLED display device is shown;

[0012] Figure 2B An example of the configuration of pixel circuitry in a liquid crystal display device is shown;

[0013] Figure 2C Another example of a pixel circuit configuration in a liquid crystal display device is shown;

[0014] Figure 3A The configuration of the CMOS circuitry in one embodiment of this specification is shown;

[0015] Figure 3B schematically shown Figure 3A An example of device layout for a CMOS circuit is shown;

[0016] Figure 3C schematically shown Figure 3A Another example of device layout for a CMOS circuit is shown;

[0017] Figure 4The circuit configuration of a shift register cell that may be included in the shift register of the scan driver is schematically shown;

[0018] Figure 5 yes Figure 4 The timing diagram of the circuit shown;

[0019] Figure 6 This shows a portion of a shift register that can be applied to a scan driver;

[0020] Figure 7 It is going to and coming from Figure 6 The timing diagram of the shift register signals is shown.

[0021] Figure 8 The circuit configuration that may be included in another scan driver is shown;

[0022] Figure 9 yes Figure 8 The timing diagram of the circuit shown;

[0023] Figure 10 It is a timing diagram of signals going to and from the shift registers in the scan driver;

[0024] Figure 11 Another configuration example of a shift register unit is shown;

[0025] Figure 12 yes Figure 11 The timing diagram of the circuit shown;

[0026] Figure 13 The configuration of a portion of a shift register is shown, which includes a reference... Figure 11 and Figure 12 The described shift register unit;

[0027] Figure 14 Another configuration example of a shift register unit is shown;

[0028] Figure 15 yes Figure 14 The timing diagram of the circuit shown; and

[0029] Figure 16 The configuration of a portion of a shift register is shown, which includes a reference... Figure 14 and Figure 15 The shift register unit described. Detailed Implementation

[0030] In the following description, embodiments of the present invention will be illustrated with reference to the accompanying drawings. It should be noted that these embodiments are merely examples of implementing the present invention and are not intended to limit the scope of the invention.

[0031] Overview

[0032] The following describes a circuit configuration for a shift register that can be applied to devices such as liquid crystal display (LCD) devices and organic light-emitting diode (OLED) display devices. The circuit disclosed below can be applied to devices other than display devices.

[0033] One embodiment of this specification describes a circuit that utilizes LTPO technology to integrate low-temperature polycrystalline silicon (LTPS) thin-film transistors (TFTs) and oxide semiconductor TFTs (e.g., IGZO TFTs). The circuit comprises complementary metal-oxide-semiconductor (CMOS) circuitry configured by combining PMOS-type (also referred to as p-type) LTPS TFTs and NMOS-type (also referred to as n-type) IGZO TFTs.

[0034] Compared to circuits that include TFTs with only a single conductivity type, CMOS circuits achieve a smaller circuit size. Circuits with TFTs of a single conductivity type require bootstrapping to lower the gate potential of the pull-down TFT in order to generate a high-voltage output signal. For bootstrapping, a capacitor must be placed between the gate and source of the pull-down TFT.

[0035] In addition, TFTs for isolation are included to prevent high voltage from being applied between the drain and source of a specific control TFT during bootstrapping. These components expand the scale of circuits with TFTs of a single conductivity type. Furthermore, electrical stress applied to the TFT can reduce reliability.

[0036] CMOS circuits do not require bootstrapping in circuits with TFTs of a single conductivity type; the circuit elements used for bootstrapping can be eliminated to achieve a smaller circuit size. However, existing CMOS circuits, which include combinations of LTPS TFTs and oxide semiconductor TFTs, have some problems. One problem is that oxide semiconductor TFTs occupy a large area in CMOS circuits. This is because there is a large mobility difference between LTPS and oxide semiconductors. For example, the mobility of IGZO is about 1 / 10 of that of LTPS.

[0037] Another problem is that residual charge on the output lines of CMOS circuits is difficult to remove, potentially causing operational malfunctions and compromising reliability. This is due to the low leakage characteristics of oxide semiconductor TFTs. For example, automotive displays are required to have fault protection features to prevent abnormal displays by displaying a black screen when the input signal supplied to the operating CMOS circuitry becomes unstable due to unexpected changes in the power supply voltage. Because of the low off-leakage of oxide semiconductor TFTs, display defects caused by residual charge may occur.

[0038] In one embodiment of this specification, the CMOS circuit includes a p-type pull-up TFT for supplying a high potential to the output line and an n-type pull-down TFT for supplying a low potential to the output line, and further includes a p-type pull-down TFT. The p-type TFT may be an LTPS TFT, and the n-type TFT may be an oxide semiconductor TFT, such as an IGZO TFT. This configuration is particularly effective for CMOS circuits where the p-type TFT has higher mobility than the n-type TFT and the n-type TFT generates less leakage current than the p-type TFT. The semiconductor of the p-type TFT may be a material other than polysilicon, and the semiconductor of the n-type TFT may be a material other than oxide semiconductor.

[0039] As described above, the output line potential is pulled up to a predetermined high level (VH) by a p-type pull-up TFT. The p-type pull-down TFT pulls the output line potential down to a potential higher than the predetermined low level (VL), specifically, to a potential (VL+Vth) higher than the threshold voltage of the p-type pull-down TFT than the potential VL. The n-type pull-down TFT continuously pulls the output line potential down from the potential (VL+Vth) to the predetermined potential level VL.

[0040] Because the p-type pull-down TFT lowers the output line potential to (VL+Vth), the n-type pull-down TFT does not require a large driving capability to pull down the output line potential. Therefore, compared with the CMOS structure, it can suppress the increase in circuit area.

[0041] In the following description, embodiments will be detailed with reference to the accompanying drawings. Common elements in the drawings are denoted by the same reference numerals, and some elements in the drawings are exaggerated in size or shape for clarity of understanding.

[0042] Implementation Method 1

[0043] Overall configuration

[0044] Figure 1 An example configuration of an OLED display device 10 is schematically shown. Although the OLED display device (to which the shift register of the present invention is applied) is described by way of example, the shift register of the present invention can be applied to other types of display devices and devices different from display devices. The OLED display device 10 includes a thin-film transistor (TFT) substrate 100 on which OLED elements are fabricated and a structural packaging unit 200 for encapsulating the OLED elements.

[0045] Around the cathode electrode region 114 outside the display region 125 of the TFT substrate 100, scan drivers 131 and 132, driver IC 134, and demultiplexer 136 are disposed. The first scan driver 131 drives the scan lines on the TFT substrate 100. The second scan driver 132 drives the measurement control lines to measure the characteristics of elements such as organic light-emitting elements and TFTs.

[0046] The driver IC 134 is connected to an external device via a flexible printed circuit (FPC) 135. The driver IC 134 may be mounted with an anisotropic conductive film (ACF).

[0047] Driver IC 134 provides power and timing signals (control signals) to scan drivers 131 and 132, and also provides power and data signals to demultiplexer 136. Demultiplexer 136 serially outputs the output of one pin of driver IC 134 to d (d is an integer greater than 1) data lines. Demultiplexer 136 changes the output data lines of the data signal from driver IC 134 d times during each scan period to drive d times the number of data lines of the output pin of driver IC 134.

[0048] Pixel circuit configuration

[0049] Multiple pixel circuits are formed on the TFT substrate 100 to control the current supplied to the anode electrode of the sub-pixel. Figure 2A An example configuration of the pixel circuitry is shown. Each pixel circuit includes a driving transistor 21, a selection transistor 22, a measurement transistor 24, and a storage capacitor C. The pixel circuitry controls the emission of light from the OLED element E1. The transistors are field-effect transistors, more specifically, TFTs.

[0050] Select transistor 22 is a switch used to select sub-pixels. Figure 2A In the configuration example, selection transistor 22 is an n-type TFT, and its gate terminal is connected to scan line 106. One source / drain terminal is connected to data line 105. The other source / drain terminal is connected to the gate terminal of drive transistor 21.

[0051] Driving transistor 21 is a transistor (driving TFT) used to drive OLED element E1. Driving transistor 21 is a p-type TFT, and its gate terminal is connected to a source / drain terminal of select transistor 22. The source terminal of driving transistor 21 is connected to power line (Vdd) 108. The drain terminal is connected to the anode of OLED element E1. Storage capacitor C is disposed between the gate terminal and the source terminal of driving transistor 21.

[0052] The measuring transistor 24 is a p-type TFT and controls the electrical connection between the reference voltage supply line 110 and the anode of the OLED element E1. This control is executed according to a control signal supplied to the gate of the measuring transistor 24 from the measuring control line 109. The measuring transistor 24 is used to measure the characteristics of the driving transistor 21 and the OLED element E1.

[0053] Next, the operation of the pixel circuit is described. Scan driver 131 outputs a selection pulse to scan line 106 to turn on selection transistor 22. The data voltage supplied from driver IC 134 via data line 105 is stored in storage capacitor C. Storage capacitor C maintains the stored voltage for the duration of one frame. The conductance of driving transistor 21 changes analogously according to the stored voltage, thereby driving transistor 21 to supply a forward bias current corresponding to the emission level to OLED element E1.

[0054] The measuring transistor 24 can be used to measure the characteristics of the driving transistor 21. For example, the voltage-current characteristics of the driving transistor 21 can be accurately measured by measuring the current flowing from the power supply line 108 (Vdd) to the reference voltage supply line 110 (Vref) under bias conditions selected such that the driving transistor 21 operates in the saturation region and the measuring transistor 24 operates in the linear region. If the differences in voltage-current characteristics between the driving transistors 21 of each sub-pixel are compensated by generating a data signal in an external circuit, a very uniform display image can be obtained.

[0055] Simultaneously, when the driving transistor 21 is turned off and the measuring transistor 24 operates in the linear region, the voltage-current characteristics of the OLED element E1 can be accurately measured by applying a voltage that causes the OLED element E1 to emit light from the reference voltage supply line 110. In the event that the OLED element E1 deteriorates due to, for example, long-term use, the display device can have a long lifespan if this deterioration is compensated for by generating a data signal in an external circuit.

[0056] Figure 2A The circuit configuration shown is an example; pixel circuits can have different circuit configurations. Based on the TFT substrate design, determine the number of TFTs and capacitors included in the pixel circuit, as well as the conductivity type of each TFT.

[0057] Next, an example of a pixel circuit in a liquid crystal display device will be described. Figure 2B and Figure 2C Each of these illustrates an example of a pixel circuit in a liquid crystal display device. Figure 2BAn example of the pixel circuitry includes an n-type switching thin-film transistor 202, a storage capacitor Cst, and a liquid crystal LC between a common electrode and a pixel electrode. The common electrode is supplied with a common potential Vcom. The scan driver outputs a selection pulse to scan line 206 to turn on the n-type switching thin-film transistor 202. Data line 205 supplies the data signal Vdata to the pixel electrode and the storage capacitor Cst by turning on the n-type switching thin-film transistor 202.

[0058] Figure 2C An example of the pixel circuitry includes a p-type switching thin-film transistor 212, a storage capacitor Cst, and a liquid crystal LC between a common electrode and a pixel electrode. The common electrode is supplied with a common potential Vcom. The scan driver outputs a selection pulse to scan line 206 to turn on the p-type switching thin-film transistor 212. Data line 205 supplies the data signal Vdata to the pixel electrode and the storage capacitor Cst by turning on the p-type switching thin-film transistor 212.

[0059] Scan drivers 131 and 132 include shift registers for serially selecting scan line 106 and measurement control line 109, respectively. The shift registers described below can be applied to one or both of scan drivers 131 and 132.

[0060] CMOS circuit configuration

[0061] Figure 3A This specification illustrates a configuration of a CMOS circuit according to one embodiment. For example, the CMOS circuit may be included in one or both of scan drivers 131 and 132. The CMOS circuit includes a first p-type TFT 311, a second p-type TFT 312, and an n-type TFT 315. The first p-type TFT 311 is a pull-up TFT, and the second p-type TFT 312 and n-type TFT 315 are pull-down TFTs. Figure 3A In the configuration example, p-type TFTs 311 and 312 are LTPS TFTs, and n-type TFT 315 is an oxide semiconductor TFT (e.g., IGZO TFT).

[0062] The p-type pull-up TFT 311 is located between the high-potential line 331, which supplies a high potential VH, and the output line 321, which outputs the output signal OUT. The source and drain of the p-type pull-up TFT 311 are connected to the high-potential line 331 and the output line 321. The high-potential line 331 is part of the first output signal supply line.

[0063] The p-type pull-down TFT 312 is located between the low-potential line 333, which supplies a low-potential line VL (lower than the high potential VH), and the output line 321. The source and drain of the p-type pull-down TFT 312 are connected to the low-potential line 333 and the output line 321. The low-potential line 333 is part of the second output signal supply line.

[0064] The n-type pull-down TFT 315 is located between the low-potential line 332, which supplies the low potential VL, and the output line 321. The source and drain of the n-type pull-down TFT 315 are connected to the low-potential line 332 and the output line 321. The low-potential line 332, like the low-potential line 333, supplies the low potential VL and is part of the second output signal supply line. The low-potential line 332 can be connected to the low-potential line 333. The potential at the intermediate node between one source / drain of the p-type pull-up TFT 311 and one source / drain of the pull-down TFT 312, or the potential at the intermediate node between one source / drain of the p-type pull-up TFT 311 and one source / drain of the pull-down TFT 315, is the potential of the signal OUT on the output line 321.

[0065] The gates of the p-type pull-up TFT 311 and the n-type pull-down TFT 315 are supplied with the same control signal (first gate signal) IN1. The gate of the p-type pull-down TFT 312 is supplied with a different control signal (second gate signal) IN2, which is different from the control signal IN1. As will be described later, when the p-type pull-up TFT 311 is turned on, the pull-down TFTs 312 and 315 are turned off. Conversely, when the pull-down TFTs 312 and 315 are turned on, the p-type pull-up TFT 311 is turned off.

[0066] exist Figure 3A In the example, control signals IN1 and IN2 exhibit opposite time changes. Although in Figure 3A In the example, the same control signal IN1 is supplied to the gate of the p-type pull-up TFT 311 and the gate of the n-type pull-down TFT 315, but different control signals with the same variation can be supplied to the gate of the p-type pull-up TFT 311 and the gate of the n-type pull-down TFT 315 via separate lines.

[0067] Pulling the output line 321 up to a high potential VH is performed by the p-type pull-up TFT 311. When the p-type pull-up TFT 311 is turned on, it supplies the high potential VH of the high potential line 331 to the output line 321.

[0068] The p-type pull-down TFT 312 has a higher driving capability than the n-type pull-down TFT 315. The p-type pull-down TFT 312 pulls the potential of the output line 321 down to a potential higher than the low potential VL by a predetermined voltage. This predetermined voltage is essentially equal to the threshold voltage Vth of the p-type pull-down TFT 312. In other words, the p-type pull-down TFT 312 pulls the potential of the output line 321 down to the potential (VL + Vth). The n-type pull-down TFT 315 then successively pulls the potential of the output line 321 down to the low potential VL.

[0069] Compared to LTPS TFTs, oxide semiconductor TFTs produce lower cutoff leakage current. Figure 3A The configuration example includes a p-type pull-down TFT 312 between the output line 321 and the low-potential line 333. This means that there is a leakage path through the LTPS TFT 312 between the power line 321 and the low-potential line 333. Therefore, when the display is turned off, the p-type pull-down TFT 312 can reduce operational malfunctions or reliability impairments caused by residual charge 341 in the output line 321.

[0070] Since the n-type pull-down TFT 315 does not require high drive capability, its size can be reduced. For example, the n-type pull-down TFT 315 can have a channel width equal to or less than that of the p-type pull-up TFT 311. Two p-type TFTs 311 and 312 can have the same channel width and can have the same structure. In another example, the p-type pull-up TFT 311 can have a wider channel width than the p-type pull-down TFT 312.

[0071] Figure 3B and Figure 3C schematically shown Figure 3A The image shows an example of a device layout for a CMOS circuit. Figure 3B and Figure 3C In the device layout, the size (channel width) of the n-type pull-down TFT 315 of the oxide semiconductor TFT is smaller than the size of the n-type pull-down TFT in the conventional configuration excluding the p-type pull-down TFT 312.

[0072] exist Figure 3B In this design, p-type pull-up TFTs 311 and 312 have top-gate structures, while n-type pull-down TFTs 315 have bottom-gate structures. The channels of p-type TFTs 311 and 312 are contained in LTPS films 351 and 352, respectively. The channel of n-type TFT 315 is contained in an oxide semiconductor film 353. Figure 3B In the configuration example, the channel width of the p-type pull-up TFT 311 is greater than the channel width of the p-type pull-down TFT 312.

[0073] exist Figure 3C In this design, the channels of p-type TFTs 311 and 312 are contained in LTPS films 361 and 362, respectively. The channel of n-type TFT 315 is contained in oxide semiconductor film 363. Figure 3C In the configuration example, the channel width of the p-type pull-up TFT 311 can be equal to the channel width of the p-type pull-down TFT 312.

[0074] Implementation Method 2

[0075] The following describes the configuration of the gate signal for the p-type TFT in the output pixel circuit. Figure 4 The circuit configuration of the first stage (also known as a flip-flop or shift register unit) of a shift register is shown schematically. Figure 4 The shift register unit in the middle includes Figure 3A The CMOS circuit shown. For example. Figure 4 The shift register unit in the OLED display device may include the scan driver 132 or Figure 2C The shift register in the scan driver of the liquid crystal pixel circuit shown.

[0076] For example, the output of the shift register unit. Figure 2A p-type TFT 24 or Figure 2C The shift register unit supplies a low-level output signal pulse to the gate of the p-type TFT 24 or 212. In the circuit described below, the p-type TFT can be an LTPS TFT, and the n-type TFT can be an oxide semiconductor TFT. The TFTs in the shift register unit are operated by turning on and off.

[0077] The inputs to the shift register unit are a high power supply level VGH, a low power supply level VGL, the input signal IN from the previous shift register unit, and clock signals CLK_DRV and CLK_RST that periodically change between high and low levels over time. The input signal IN and the clock signals CLK_DRV and CLK_RST vary between a high level (high level) equal to the high power supply level VGH and a low level (low level) equal to the low power supply level VGL. The output from output line 321 is the signal destined for the next shift register unit.

[0078] The shift register unit includes a reference Figure 3A The description includes p-type pull-up TFT 311, p-type pull-down TFT 312, and n-type pull-down TFT 315. The gates of the p-type pull-up TFT 311 and the n-type pull-down TFT 315 are connected via node N2. These gates are supplied with the same potential. The shift register unit also includes p-type TFTs 411 to 415.

[0079] One of the p-type TFTs 412 and 415 is an example of a first control switch TFT, and the other is an example of a second control switch TFT. The p-type TFT 414 is an example of a third control switch TFT, and the p-type TFT 413 is an example of a fourth control switch TFT.

[0080] One source / drain of the p-type pull-up TFT 311 is supplied with a constant high power supply potential VGH. One source / drain of the pull-down TFT 312 and one source / drain of the pull-down TFT 315 are supplied with a clock signal CLK_DRV. As will be described later, when the pull-down TFTs 312 and 315 are turned on, the clock signal CLK_DRV is at a low potential level, lower than the high power supply potential VGH. Its potential is equal to the low power supply potential VGL.

[0081] The gate of the p-type TFT 411 is connected to the output line 321, and they are at the same potential. One source / drain of the p-type TFT 411 is connected to the gate of the p-type pull-up TFT 311, and they are at the same potential. The other source / drain of the p-type TFT 411 is supplied with a high power supply potential VGH. The high power supply potential VGH is constant. The p-type TFT 411 prevents node N2 from floating or the circuit operation from becoming unstable. The p-type TFT 411 is optional.

[0082] The gate of the p-type TFT 412 is supplied with the signal IN. One source / drain of the p-type TFT 412 is connected to the gate of the p-type pull-up TFT 311, and they are at the same potential. The other source / drain of the p-type TFT 412 is supplied with a high power supply potential VGH.

[0083] The source of the p-type TFT 413 is connected to the gate of the p-type pull-up TFT 311, and they are at the same potential. The gate and drain of the p-type TFT 413 are connected, therefore the p-type TFT 413 is diode-connected. The drain is supplied with the clock signal CLK_RST.

[0084] The gate of p-type TFT 414 is connected to the gate of p-type pull-up TFT 311, and they are at the same potential. One source / drain of p-type TFT 414 is connected to the gate of p-type pull-down TFT 312 through node N1, and they are at the same potential. The other source / drain of p-type TFT 414 is supplied with a high power supply potential VGH.

[0085] The gate of the p-type TFT 415 is supplied with the signal IN. One source / drain of the p-type TFT 415 is connected to the gate of the p-type pull-down TFT 312 through node N1, and they are at the same potential. The other source / drain of the p-type TFT 415 is supplied with a low power supply potential VGL. The low power supply potential VGL is constant.

[0086] In the following text, the description Figure 4 The operation of the circuit shown. Figure 5 yes Figure 4 The timing diagram of the circuit is shown. In the following description, the high potential level of a signal is represented by H, and the low potential level by L. For all signals, their high potential level is the high supply potential VGH, and their low potential level is the low supply potential VGL. Figure 5 All signals are synchronized.

[0087] First, describe the state immediately preceding time T1. Input signal IN is H; clock signal CLK_DRV is H; clock signal CLK_RST is L. Node N1 has a potential of H, and node N2 has a potential of L. p-type TFTs 415 and 412 are off. Diode-connected p-type TFT 413 is forward biased. p-type pull-down TFT 312 is off. n-type pull-down TFT 315 is off. p-type pull-up TFTs 311 and 414 are on. p-type TFT 411 is off. Output signal OUT is H.

[0088] Next, the operation of the component at time T1 is described. The input signal IN changes from H to L. During the time interval from time T1 to time T2, a transition pulse (the low potential level L in the input signal IN) is input from the previous shift register unit. The clock signal CLK_RST changes from L to H.

[0089] p-type TFTs 415 and 412 turn on in response to the aforementioned change in the input signal IN. p-type TFT 413 becomes reverse biased in response to the aforementioned change in the clock signal CLK_RST. The potential of node N1 changes from H to L, and the potential of node N2 changes from L to H.

[0090] Because the potential of node N1 changes from H to L, the p-type pull-down TFT 312 is turned on. Because the potential of node N2 changes from L to H, the n-type pull-down TFT 315 is turned on. Because the clock signal CLK_DRV remains at H, the output signal OUT remains at H. Because the output signal OUT remains at H, the p-type TFT 411 remains off.

[0091] Next, the operation of the components at time T2 is described. The input signal IN changes from L to H. The p-type TFTs 415 and 412 are cut off. The clock signal CLK_RST remains at H. The potential of node N1 is L, and node N1 is in a floating state.

[0092] The clock signal CLK_DRV changes from H to L. In response, the output signal OUT changes from H to L, and further, the p-type TFT 411 turns on. The potential of node N2 remains at H. During the time period from time T2 to time T3, the shift register unit outputs pulses to be transmitted to the control lines for display area 125 and the next shift register unit.

[0093] Next, the operation of the components at time T3 is described. The input signal IN remains at H and the p-type TFTs 415 and 412 remain off. The clock signal CLK_DRV changes from L to H, and the clock signal CLK_RST changes from H to L. The p-type TFT 413 becomes forward biased.

[0094] Node N2 is supplied with the clock signal CLK_RST and its potential changes from H to L. The p-type TFT 414 is turned on and the potential of node N1 changes from L to H.

[0095] In response to the change in potential of node N2 from H to L, the n-type pull-down TFT 315 is turned off and the p-type pull-up TFT 311 is turned on. In response to the change in potential of node N1 from L to H, the p-type pull-down TFT 312 is turned off. The output signal OUT changes from L to H. The p-type TFT 411 is turned off. The time period from time T2 to time T3 is the output period of the output signal pulse.

[0096] After time T3, the clock signals CLK_DRV and CLK_RST change periodically. Since the potential of node N2 is L, the change in clock signal CLK_RST does not change the potential of node N2. The potentials of nodes N1 and N2 remain unchanged. Because TFTs 312 and 315 are off, the change in clock signal CLK_DRV does not change the potential of output signal OUT. Therefore, the potential of output signal OUT remains at H. The node potentials in the shift register unit change in response to the next change in input signal IN.

[0097] For reference Figure 5 As described, Figure 4 The shift register unit shown does not require bootstrapping for operation. Therefore, no capacitor is needed for bootstrapping, and thus a small circuit area can be achieved.

[0098] Figure 6 A portion of a shift register applicable to scan driver 132 is shown. Specifically, Figure 6The diagram shows the first-stage shift register unit SR1, the second-stage shift register unit SR2, and the third-stage shift register unit SR3. Each of the shift register units SR1, SR2, and SR3 can have a reference... Figure 4 and Figure 5 The circuit configuration is described. A shift register may include n shift register units (n is a positive integer) connected sequentially according to the design.

[0099] Each shift register unit includes multiple signal terminals, specifically including VGH terminal 611, IN terminal 612, VGL terminal 613, CLK_RST terminal 614, OUT terminal 615, and CLK_DRV terminal 616. Figure 6 In the figure, as an example, the terminals of the first shift register unit SR1 are provided with reference numerals.

[0100] OUT terminal 615 output Figure 5 The output signal OUT is provided in the VGH terminal 611. Figure 4 The constant high power supply potential VGH is described. Terminal 613 of VGL is supplied for reference. Figure 4 The described constant low power supply potential VGL. The signal to be input to the IN terminal 612 is... Figure 5 The input signal IN is required. The signal to be input to the CLK_RST terminal 614 is... Figure 5 The clock signal CLK_RST is used. The signal to be input to the CLK_DRV terminal 616 is... Figure 5 The clock signal CLK_DRV is used in the shift register unit. Some input signals of the shift register unit are supplied from the driver IC 134.

[0101] Shift register units SR1, SR2, and SR3 output output signals OUT1, OUT2, and OUT3 from their respective OUT terminals 615. Each output signal is supplied to the gate of the TFT 24 in the pixel circuit and further supplied to the IN terminal 612 of the next shift register unit. The IN terminal 612 of the first shift register unit SR1 is supplied with a start signal ST.

[0102] The CLK_RST terminal 614 of the (3k-2)th stage (k is a positive integer) is supplied with clock signal C2. The CLK_DRV terminal 616 of the (3k-2)th stage is supplied with clock signal C1. The CLK_RST terminal 614 of the (3k-1)th stage is supplied with clock signal C3. The CLK_DRV terminal 616 of the (3k-1)th stage is supplied with clock signal C2. The CLK_RST terminal 614 of the 3kth stage is supplied with clock signal C1. The CLK_DRV terminal 616 of the 3kth stage is supplied with clock signal C3.

[0103] Figure 7 It is going to and coming from Figure 6 The timing diagram of the shift register signals is shown. The start signal ST supplies low-level pulses with a period of one frame. Each of the clock signals C1, C2, and C3 supplies low-level pulses with a regular period within one frame. The pulse widths of the clock signals C1, C2, and C3 are equal, and further, they are equal to the pulse width of the start signal ST.

[0104] Clock signals C1, C2, and C3 have the same pulse period but different phases. The phases of clock signals C1, C2, and C3 are each offset by one pulse width. That is, the pulse of clock signal C2 is generated simultaneously with the end of the pulse of clock signal C1; the pulse of clock signal C3 is generated simultaneously with the end of the pulse of clock signal C2; and another pulse of clock signal C1 is generated simultaneously with the end of the pulse of clock signal C3. The start and end times of each pulse of the start signal ST coincide with the start and end times of one pulse of clock signal C3.

[0105] Figure 7 The diagram illustrates the time variation of the output signals OUT1 to OUTn from the first shift register unit to the nth shift register unit. Output signals OUT1 to OUTn sequentially generate low-level pulses. The pulse widths of output signals OUT1 to OUTn are the same as the pulse widths of other signals. The output signal pulse of each shift register unit is generated simultaneously with the end of the output signal pulse of the previous shift register unit.

[0106] Implementation Method 3

[0107] The following describes the configuration of the gate signals used to illustrate the n-type TFT in the pixel circuit. Figure 8 The circuit configuration of the first stage (also known as a flip-flop or shift register unit) of a shift register is shown schematically. Figure 8 The shift register unit in the middle includes Figure 3A The CMOS circuit shown. For example. Figure 8 The shift register unit in the OLED display device may be included in the scan driver 131 or Figure 2B The shift register in the scan driver of the liquid crystal pixel circuit shown.

[0108] For reference Figure 2A As described, the scan driver 131 outputs the gate signal of the n-type TFT 22 in the pixel circuit. Figure 2B The pixel circuitry includes an n-type TFT 202 as a switching transistor to be controlled. The shift register unit supplies a high-level output signal pulse to the gate of either the n-type TFT 22 or 202.

[0109] In the circuit described below, the p-type TFT can be an LTPS TFT, and the n-type TFT can be an oxide semiconductor TFT. The TFTs in the shift register unit are operated by turning on and off.

[0110] The inputs to the shift register unit are a high power supply level VGH, a low power supply level VGL, the input signal IN from the previous shift register unit, and clock signals CLK_DRV and CLK_RST. The input signal IN and the clock signals CLK_DRV and CLK_RST vary between a high level (high level) equal to the high power supply level VGH and a low level (low level) equal to the low power supply level VGL. The output from output line 321 is the signal destined for the next shift register unit.

[0111] The shift register unit includes a reference Figure 3A The p-type pull-up TFT 311, p-type pull-down TFT 312, and n-type pull-down TFT 315 are described. The gates of the p-type pull-up TFT 311 and the n-type pull-down TFT 315 are connected via node N4. These gates are supplied with the same potential. The shift register unit further includes p-type TFTs 513 and 514 and n-type TFTs 511, 512, and 515.

[0112] One of the n-type TFTs 512 and 515 is an example of a first control switch TFT, and the other is an example of a second control switch TFT. The p-type TFT 514 is an example of a third control switch TFT, and the p-type TFT 513 is an example of a fourth control switch TFT.

[0113] One source / drain of the p-type pull-up TFT 311 is supplied with the clock signal CLK_DRV. One source / drain of the pull-down TFT 312 and one source / drain of the pull-down TFT 315 are supplied with a constant low power supply potential VGL. As will be described later, when the p-type pull-up TFT 311 is turned on, the clock signal CLK_DRV is at a high level. Its potential is equal to the high power supply potential VGH.

[0114] The gate of the n-type TFT 511 is connected to the output line 321, and they are at the same potential. One source / drain of the n-type TFT 511 is connected to the gate of the p-type pull-down TFT 312 through node N3, and they are at the same potential. The other source / drain of the n-type TFT 511 is supplied with a high power supply potential VGH. The high power supply potential VGH is constant. The n-type TFT 511 prevents node N3 from floating or the circuit operation from becoming unstable. The n-type TFT 511 is optional.

[0115] The gate of the n-type TFT 512 is supplied with the signal IN. One source / drain of the n-type TFT 512 is connected to the gate of the p-type pull-down TFT 312, and they are at the same potential. The other source / drain of the n-type TFT 512 is supplied with a high power supply potential VGH.

[0116] The source of the p-type TFT 513 is connected to the gate of the p-type pull-down TFT 312, and they are at the same potential. The gate and drain of the p-type TFT 513 are connected, therefore the p-type TFT 513 is diode-connected. The drain is supplied with the clock signal CLK_RST.

[0117] The gate of p-type TFT 514 is connected to the gate of p-type pull-down TFT 312, and they are at the same potential. One source / drain of p-type TFT 514 is connected to the gate of p-type pull-up TFT 311 and the gate of n-type pull-down TFT 315 through node N4, and they are at the same potential. The other source / drain of p-type TFT 514 is supplied with a high power supply potential VGH.

[0118] The gate of the n-type TFT 515 is supplied with the signal IN. One source / drain of the n-type TFT 515 is connected to the gate of the p-type pull-up TFT 311 and the gate of the n-type pull-down TFT 315 through node N4, and they are at the same potential. The other source / drain of the n-type TFT 515 is supplied with a low power supply potential VGL. The low power supply potential VGL is constant.

[0119] exist Figure 8 In the circuit, the potential of node N3 is equal to the gate potential of p-type pull-down TFT 312, and the potential of node N4 is equal to the gate potential of p-type pull-up TFT 311 and n-type pull-down TFT 315.

[0120] In the following text, the description Figure 8 The operation of the circuit shown. Figure 9 yes Figure 8 The timing diagram of the circuit is shown. In the following description, the high potential level of a signal is represented by H, and the low potential level by L. For all signals, their high potential level is the high supply potential VGH, and their low potential level is the low supply potential VGL. Figure 9 All signals are synchronized.

[0121] First, describe the state immediately preceding time T1. Input signal IN is L; clock signal CLK_DRV is H; clock signal CLK_RST is L. Node N3 has a potential of L, and node N4 has a potential of H. n-type TFTs 515 and 512 are off. Diode-connected p-type TFT 513 is forward biased. p-type pull-down TFT 312 is on. n-type pull-down TFT 315 is on. p-type pull-up TFTs 311 and 514 are off. n-type TFT 511 is off. Output signal OUT is L.

[0122] Next, the operation of the component at time T1 is described. The input signal IN changes from L to H. During the time interval from time T1 to time T2, a transition pulse (the high potential level H in the input signal IN) is input from the previous shift register unit. The clock signal CLK_DRV changes from H to L, and the clock signal CLK_RST changes from L to H.

[0123] n-type TFTs 515 and 512 turn on in response to the aforementioned change in the input signal IN. p-type TFT 513 becomes reverse biased in response to the aforementioned change in the clock signal CLK_RST. The potential of node N3 changes from L to H, and the potential of node N4 changes from H to L. Because the potential of node N3 changes from L to H, p-type pull-down TFTs 312 and 514 are turned off.

[0124] As the potential of node N4 changes from H to L, the n-type pull-down TFT 315 is turned off and the p-type pull-up TFT 311 is turned on. Since the clock signal CLK_DRV is L, the output signal OUT remains L. The output signal OUT remains L and the n-type TFT 511 remains off.

[0125] Next, the operation of the component at time T2 is described. The input signal IN changes from H to L. The clock signal CLK_RST remains at H. The clock signal CLK_DRV changes from L to H.

[0126] n-type TFTs 515 and 512 are turned off in response to changes in the input signal IN. The potential of node N3 remains at H and the potential of node N4 remains at L. Pull-down TFTs 312 and 315 remain off and p-type pull-up TFT 311 remains on.

[0127] The clock signal CLK_DRV changes from L to H. In response, the output signal OUT changes from L to H, and further, the n-type TFT 511 is turned on. The potential of node N3 remains at H. During the time interval from time T2 to time T3, the shift register unit outputs the control lines to be transmitted to display area 125 and the pulses to the next shift register unit.

[0128] Next, the operation of the components at time T3 is described. The input signal IN remains at L, and the clock signal CLK_DRV remains at H. The clock signal CLK_RST changes from H to L. Since the input signal IN remains at L, the n-type TFTs 515 and 512 remain off.

[0129] The p-type TFT 513 becomes forward biased in response to a change in the clock signal CLK_RST. Therefore, node N3 is supplied with the clock signal CLK_RST and its potential changes from H to L. The p-type TFT 514 turns on and the potential of node N4 changes from L to H.

[0130] In response to the change in potential at node N4 from L to H, the n-type pull-down TFT 315 turns on and the p-type pull-up TFT 311 turns off. In response to the change in potential at node N3 from H to L, the p-type pull-down TFT 312 turns on. The output signal OUT changes from H to L. The time period from time T2 to time T3 is the output period of the output signal pulse.

[0131] After time T3, the clock signals CLK_DRV and CLK_RST change periodically. Since the potential of node N3 is L, the change in the clock signal CLK_RST does not change the potential of node N3. Because the n-type TFT 515 is off and the p-type TFT 514 is on, the potential of node N4 remains H. The potentials of nodes N3 and N4 remain unchanged.

[0132] Because the p-type pull-up TFT 311 is off, changes in the clock signal CLK_DRV do not alter the potential of the output signal OUT. Therefore, the potential of the output signal OUT remains at L. The node potential within the shift register cell changes in response to the next change in the input signal IN.

[0133] For reference Figure 9 As described, Figure 8 The shift register unit shown does not require bootstrapping for operation. Therefore, a small circuit area can be achieved.

[0134] The shift register of scan driver 131 can have the same characteristics as... Figure 6 The configuration shown is the same. Each shift register unit has... Figure 8 The circuit configuration shown is based on the reference. Figure 9 The described signal is used for operation.

[0135] Figure 10This is a timing diagram of the signals going to and from the shift register of scan driver 131. The start signal ST supplies a high-level pulse with a period of one frame. Each of the clock signals C1, C2, and C3 supplies a low-level pulse with a regular period within one frame. The pulse widths of clock signals C1, C2, and C3 are equal, and further, they are equal to the pulse width of the start signal ST.

[0136] Clock signals C1, C2, and C3 have the same period but different phases. The phases of clock signals C1, C2, and C3 are each offset by one pulse width. That is, the pulse of clock signal C2 is generated simultaneously with the end of the pulse of clock signal C1; the pulse of clock signal C3 is generated simultaneously with the end of the pulse of clock signal C2; and another pulse of clock signal C1 is generated simultaneously with the end of the pulse of clock signal C3. The start and end times of each pulse of the start signal ST coincide with the start and end times of one pulse of clock signal C3.

[0137] Figure 10 The diagram illustrates the time variation of the output signals OUT1 to OUTn from the first shift register unit to the nth shift register unit. Output signals OUT1 to OUTn sequentially generate high-level pulses. The pulse widths of output signals OUT1 to OUTn are the same as the pulse widths of other signals. The output signal pulse of each shift register unit is generated simultaneously with the end of the output signal pulse of the previous shift register unit.

[0138] Implementation Method 4

[0139] Figure 11 Another configuration example of a shift register unit is shown. For example, Figure 11 The shift register unit 11 in the OLED display device may be included in the scan driver 132 or Figure 2C The shift register in the scan driver of the liquid crystal pixel circuit shown.

[0140] For example, the output of the shift register unit. Figure 2A p-type TFT 24 or Figure 2C The shift register unit supplies a low-level output signal pulse to the gate of the p-type TFT 24 or 212. In the circuit described below, the p-type TFT can be an LTPS TFT, and the n-type TFT can be an oxide semiconductor TFT. The TFTs in the shift register unit are operated by turning them on and off.

[0141] The inputs to the shift register unit are a high power supply level VGH, a low power supply level VGL, an input signal IN1 from the previous shift register unit, an input signal IN2 from the next shift register unit, and clock signals CLK_DRV and CLK_RST that periodically change between high and low levels over time. The input signals IN1 and IN2, as well as the clock signals CLK_DRV and CLK_RST, change between a high level (high level) equal to the high power supply level VGH and a low level (low level) equal to the low power supply level VGL. The output from output line 321 is a signal destined for the previous and next shift register units.

[0142] The shift register unit includes a p-type pull-up TFT 311, a p-type pull-down TFT 312, and an n-type pull-down TFT 315, as described with reference to FIG3. The gates of the p-type pull-up TFT 311 and the n-type pull-down TFT 315 are connected via node N6. These gates are supplied with the same potential. The shift register unit also includes p-type TFTs 552 to 555 and a capacitor 559. The p-type TFT 554 is an example of a third control switch TFT.

[0143] One source / drain of the p-type pull-up TFT 311 is supplied with a constant high power supply potential VGH. One source / drain of the pull-down TFT 312 and one source / drain of the pull-down TFT 315 are supplied with a clock signal CLK_DRV. When pull-down TFTs 312 and 315 are turned on, the clock signal CLK_DRV is at a low potential level below the high power supply potential VGH. Its potential is equal to the low power supply potential VGL.

[0144] The gate of p-type TFT 552 is connected to the gate of p-type pull-down TFT 312, and they are at the same potential. One source / drain of p-type TFT 552 is connected to the gate of p-type pull-up TFT 311 and the gate of n-type pull-down TFT 315, and they are at the same potential. The other source / drain of p-type TFT 552 is supplied with a high power supply potential VGH. The high power supply potential VGH is constant.

[0145] One source / drain of the p-type TFT 553 is connected to the gate of the p-type pull-down TFT 312, and they are at the same potential. The gate of the p-type TFT 553 is supplied with signal IN2. Signal IN2 is the output signal of the next shift register unit.

[0146] The gate of p-type TFT 554 is connected to the gate of p-type pull-up TFT 311, and they are at the same potential. One source / drain of p-type TFT 554 is connected to the gate of p-type pull-down TFT 312 through node N5, and they are at the same potential. The other source / drain of p-type TFT 554 is supplied with a high power supply potential VGH. The gates of p-type TFT 554, p-type TFT 311, and n-type TFT 315 are connected to node N6; they are supplied with the clock signal CLK_DRV through capacitor 559.

[0147] The gate of the p-type TFT 555 is supplied with signal IN1. One source / drain of the p-type TFT 555 is connected to the gate of the p-type pull-down TFT 312 through node N5, and they are at the same potential. The other source / drain of the p-type TFT 555 is supplied with a low power supply potential VGL. The low power supply potential VGL is constant.

[0148] In the following text, the description Figure 11 The operation of the circuit shown. Figure 12 yes Figure 11 The timing diagram of the circuit is shown. In the following description, the high potential level of a signal is represented by H, and the low potential level by L. For all signals, their high potential level is the high supply potential VGH, and their low potential level is the low supply potential VGL. Figure 12 All signals are synchronized.

[0149] First, describe the state immediately preceding time T11. Input signal IN1 is H; clock signal CLK_DRV is L; input signal IN2 is H. The potential of node N5 is H, and the potential of node N6 is L. p-type pull-down TFT 312 is off. p-type TFTs 553 and 555 are off. n-type pull-down TFT 315 is off. p-type pull-up TFT 311 and p-type TFT 554 are on. Output signal OUT is H.

[0150] Next, the operation of the components at time T11 and immediately following time T12 is described. At time T11, the clock signal CLK_DRV changes from L to H, and at time T12, immediately following time T11, the input signal IN1 changes from H to L. The potential of node N6 changes from L to H in response to the change in the clock signal CLK_DRV. The p-type TFT 554 and the p-type pull-up TFT 311 are turned off. The n-type pull-down TFT 315 is turned on.

[0151] In response to the change in input signal IN1, p-type TFT 555 turns on, and the potential of node N5 changes from H to L. p-type TFT 552 turns on, and the potential of node N6 remains at H. p-type pull-down TFT 312 turns on. Since the clock signal CLK_DRV is H, the output signal OUT remains at H.

[0152] Next, the operation of the component at time T21, following time T12, and at time T22, immediately after time T21, is described. At time T21, there is no signal change. At time T22, the input signal IN1 changes from L to H, and the clock signal CLK_DRV changes from H to L.

[0153] The p-type TFT 555 turns off in response to a change in the input signal IN1. The p-type TFT 553 remains off. Node N5 is in a floating state and its potential remains at L. Therefore, the p-type pull-down TFT 312 remains on.

[0154] Although the clock signal CLK_DRV changes to L as described above, the potential of node N6 is maintained at H through capacitor 559 and the conduction of p-type TFT 552. Therefore, p-type TFT 554 and p-type pull-up TFT 311 remain off, while n-type pull-down TFT 315 remains on. As the clock signal CLK_DRV changes from H to L, the output signal OUT changes from H to L.

[0155] Next, the operation of the element at time T31 after time T22 and at time T32 immediately following time T31 is described. At time T31, the clock signal CLK_DRV changes from L to H. The output signal OUT changes from L to H in response to the change of the clock signal CLK_DRV from L to H.

[0156] At time T32, the input signal IN2 changes from H to L. In response to the change in input signal IN2 from H to L, the p-type TFT 553 turns on and the potential of node N5 changes from L to H. In response to the potential change of node N5, the p-type TFT 552 turns off and the p-type pull-down TFT 312 turns off.

[0157] Node N6 is in a floating state and its potential remains at H. Therefore, the p-type pull-up TFT 311 remains off and the n-type pull-down TFT 315 remains on. Since the clock signal CLK_DRV is H, the output signal OUT is H.

[0158] Next, the operation of the element at time T41 after time T32 and immediately following time T42 is described. At time T41, the input signal IN2 changes from L to H. In response to the change of the input signal IN2 from L to H, the p-type TFT 553 is turned off.

[0159] At time T42, the clock signal CLK_DRV changes from H to L. In response to this change in clock signal CLK_DRV, the potential of node N6 changes from H to L. Consequently, p-type TFT 554 and p-type pull-up TFT 311 turn on, and n-type pull-down TFT 315 turns off. Because p-type pull-up TFT 311 is on and pull-down TFTs 312 and 315 are off, the output signal OUT remains at H.

[0160] Next, the operation of the element at time T51, following time T42, and at time T52, immediately after time T51, is described. At time T51, the clock signal CLK_DRV changes from L to H. At time T52, the signal remains unchanged.

[0161] In response to the clock signal CLK_DRV changing from L to H, the potential of node N6 changes from L to H. In response to this change in potential, p-type TFT 554 and p-type pull-up TFT 311 are turned off, while n-type pull-down TFT 315 is turned on. p-type pull-down TFT 312 remains off. Since the clock signal CLK_DRV is H, the output signal OUT remains at H.

[0162] Next, the operation of the element at time T61, following time T52, and at time T62 immediately after time T61, is described. At time T61, the signal remains unchanged. At time T62, the clock signal CLK_DRV changes from H to L. In response, the potential of node N6 changes from H to L.

[0163] In response to the change in potential at node N6 from H to L, p-type TFT 554 and p-type pull-up TFT 311 are turned on, while n-type pull-down TFT 315 is turned off. p-type pull-down TFT 312 remains off. Since p-type pull-up TFT 311 supplies potential VGH to output line 321, the output signal OUT remains at H.

[0164] After time T62, the operation from time T42 to time T62 is repeated until the start of the next frame. As described above, the p-type TFT 554 and the p-type pull-up TFT 311 are turned on and off during the time period from time T42 to time T62. These two p-type TFTs are turned on from time T42 to time T51 and turned off from time T51 to time T62 (T42).

[0165] When the p-type TFT remains on, a positive Vg stress is applied to cause a Vt (threshold) shift. The above configuration, which synchronizes the two p-type TFTs 554 and 311 on and off with the clock signal CLK_DRV, mitigates the positive Vg stress and reduces the instability in circuit operation caused by the Vt shift.

[0166] The time intervals from time T11 to time T12, from time T21 to time T22, from time T31 to time T32, from time T41 to time T42, from time T51 to time T52, and from time T61 to time T62 are very short compared to the clock cycle. The clock cycle can be the time interval (length) from time T11 to time T31.

[0167] exist Figure 12 In one cycle of the clock signal CLK_DRV shown, the H period is slightly longer than the L period, but the difference is very small. Therefore, the duty cycle of the clock signal CLK_DRV is approximately 50%. The clock signal CLK_DRV appropriately generates the output signal OUT and further effectively suppresses the Vt offset of the TFT.

[0168] Figure 13 It shows a reference Figure 11 and Figure 12 The configuration of a portion of the shift register in the described shift register unit. Figure 13 The diagram shows a first-stage shift register unit SR11, a second-stage shift register unit SR12, and a third-stage shift register unit SR13. Each of the shift register units SR11, SR12, and SR13 may have a reference... Figure 11 and Figure 12 The circuit configuration is described. A shift register may include n shift register units (n is a positive integer) connected sequentially according to the design.

[0169] Each shift register unit includes multiple signal terminals, specifically including VGH terminal 631, IN1 terminal 632, VGL terminal 633, OUT terminal 635, CLK_DRV terminal 636, and IN2 terminal 637. Figure 13 In the figure, as an example, the terminals of the first shift register unit SR11 are provided with reference numerals.

[0170] OUT terminal 635 output Figure 12 The output signal OUT is provided. Terminal VGH 631 is supplied with a constant high power supply potential VGH. Terminal VGL 633 is supplied with a constant low power supply potential VGL. The signal to be input to terminal IN1 632 is... Figure 12 The input signal IN1 is the signal to be input to the CLK_DRV terminal 636. Figure 12 The clock signal CLK_DRV is used. The signal to be input to the IN2 terminal of 637 is... Figure 12 The input signal IN2 is supplied to the shift register unit. Some input signals are supplied from the driver IC 134.

[0171] Shift register units SR11, SR12, and SR13 output output signals OUT11, OUT12, and OUT13 from their respective OUT terminals 635. Each output signal is supplied to the gate of the TFT 24 in the pixel circuit, and further supplied to the IN1 terminal 632 of the next shift register unit and the IN2 terminal 637 of the previous shift register unit. The IN1 terminal 632 of the first shift register unit SR11 is supplied with the start signal ST.

[0172] The CLK_DRV terminal 636 of the (2k-1)th stage (where k is a positive integer) is supplied with clock signal C11, and the CLK_DRV terminal 636 of the 2kth stage is supplied with clock signal C12. Clock signals C11 and C12 are used in the shift register unit in conjunction with a reference... Figure 12 The clock signal CLK_DRV described changes in the same way.

[0173] Another configuration example of a shift register unit is described. Figure 14 Another configuration example of a shift register unit is shown. The following mainly describes the... Figure 11 The differences from the configuration examples in [the original text]. Figure 14 In addition to the shift register unit in Figure 11 In addition to the configuration examples, p-type TFTs 557 and 558 are also included. The gate of n-type pull-down TFT 315 is not connected to the gate of p-type pull-up TFT 311. Node N7 is provided on the line connecting the gates of p-type TFT 554 and p-type pull-up TFT 311.

[0174] The gate of the p-type TFT 557 is connected to the output line 321, and they are at the same potential. One source / drain of the p-type TFT 557 is supplied with a high power supply potential VGH. The other source / drain of the p-type TFT 557 is connected to the gate of the n-type pull-down TFT 315 through node N8, and they are at the same potential.

[0175] The gate of the p-type TFT 558 is supplied with the clock signal CLK_RST. One source / drain of the p-type TFT 558 is supplied with a low power supply potential VGL. The other source / drain of the p-type TFT 558 is connected to the gate of the n-type pull-down TFT 315 through node N8, and they are at the same potential.

[0176] Figure 15 yes Figure 14 The timing diagram of the circuit shown is included. Figure 12 Compared to the previous timing diagram, the time change of the potential of node N6 has been removed, and the time changes of the clock signal CLK_RST and the potentials of nodes N7 and N8 have been added.

[0177] First, describe the state immediately preceding time T11. Input signal IN1 is H; clock signal CLK_DRV is L; clock signal CLK_RST is H; input signal IN2 is H. The potential of node N5 is H; the potential of node N7 is L; the potential of node N8 is L.

[0178] P-type pull-down TFT 312 is off. P-type TFTs 553 and 555 are off. P-type TFT 558 is off. P-type pull-up TFTs 311 and 554 are on, and n-type pull-down TFT 315 is off. The output signal OUT is H, and P-type TFT 557 is off.

[0179] Next, the operation of the components at time T11 and immediately following time T12 is described. At time T11, the clock signal CLK_DRV changes from L to H. The potential of node N7 changes from L to H in response to the change in the clock signal CLK_DRV. The p-type TFT 554 and the p-type pull-up TFT 311 are turned off.

[0180] At time T12, the input signal IN1 changes from H to L and the clock signal CLK_RST changes from H to L. In response to the change in the clock signal CLK_RST, the p-type TFT 558 turns on. The potential of node N8 remains at L and the n-type pull-down TFT 315 remains off.

[0181] In response to the change in input signal IN1, the p-type TFT 555 turns on, and the potential of node N5 changes from H to L. The p-type pull-down TFT 312 turns on. Since the clock signal CLK_DRV is H, the output signal OUT remains H.

[0182] At time T21, following time T12, the clock signal CLK_RST changes from L to H. The p-type TFT 558 turns off in response to the change in the clock signal CLK_RST. The potential of node N8 remains at L and the n-type pull-down TFT 315 remains off.

[0183] At time T22, immediately following time T21, the input signal IN1 changes from L to H and the clock signal CLK_DRV changes from H to L. In response to the change in input signal IN1, the p-type TFT 555 is turned off. The p-type TFT 553 remains off. Node N5 is in a floating state and its potential remains at L. Therefore, the p-type pull-down TFT 312 remains on.

[0184] Although the clock signal CLK_DRV changes to L as described above, the potential of node N7 remains H due to the conduction of capacitor 559 and p-type TFT 552. Therefore, p-type TFT 554 and p-type pull-up TFT 311 remain off. As the clock signal CLK_DRV changes from H to L, the output signal OUT changes from H to L. p-type TFT 557 turns on; the potential of node N8 changes from L to H; n-type pull-down TFT 315 turns on.

[0185] At time T31, following time T22, the clock signal CLK_DRV changes from L to H. The potential of node N7 remains at H, and p-type TFT 554 and p-type pull-up TFT 311 remain off. The potential of node N5 remains at L, and the potential of node N8 remains at H. Therefore, p-type pull-down TFT 312 and n-type pull-down TFT 315 remain on.

[0186] The output signal OUT changes from L to H along with the clock signal CLK_DRV as it changes from L to H. In response to the change in the output signal OUT, the p-type TFT 557 is turned off. Node N8 becomes floating and its potential remains at H.

[0187] At time T32, immediately following time T31, the input signal IN2 changes from H to L, and the clock signal CLK_RST also changes from H to L. In response to the change in input signal IN2 from H to L, p-type TFT 553 turns on, and the potential of node N5 changes from L to H. In response to the change in the potential of node N5, p-type TFT 552 and p-type pull-down TFT 312 turn off.

[0188] In response to the clock signal CLK_RST changing from H to L, the p-type TFT 558 turns on. The potential of node N8 changes from H to L, and the n-type pull-down TFT 315 turns off. Output line 321 becomes floating, and the output signal OUT remains at H.

[0189] At time T41, following time T32, the input signal IN2 changes from L to H, and the clock signal CLK_RST also changes from L to H. In response to the change in input signal IN2 from L to H, p-type TFT 553 is turned off. Node N5 becomes floating and its potential remains at H. In response to the change in clock signal CLK_RST from L to H, p-type TFT 558 is turned off. Node N8 becomes floating and its potential remains at L.

[0190] At time T42, immediately following time T41, the clock signal CLK_DRV changes from H to L. In response to this change in clock signal CLK_DRV, the potential of node N7 changes from H to L. Consequently, p-type TFT 554 and p-type pull-up TFT 311 turn on. The potential of node N5 remains at H. Node N8 is in a floating state, and its potential remains at L. Therefore, pull-down TFTs 312 and 315 remain off, resulting in the output signal OUT remaining at H.

[0191] At time T51, following time T42, the clock signal CLK_DRV changes from L to H. In response, the potential at node N7 changes from L to H. In response to the change in potential at node N7 from L to H, p-type TFT 554 and p-type pull-up TFT 311 are turned off. Node N5 is in a floating state, and its potential remains at H. Node N8 is in a floating state, and its potential remains at L. Therefore, pull-down TFTs 312 and 315 remain off. Output line 321 is in a floating state, and the output signal OUT remains at H.

[0192] At time T52, immediately following time T51, the clock signal CLK_RST changes from H to L. The P-type TFT 558 turns on. The potential of node N8 remains at L. Other TFTs, including the n-type pull-down TFT 315, remain off. Output line 321 is in a floating state, and the output signal OUT remains at H.

[0193] At time T61, following time T52, the clock signal CLK_RST changes from L to H. The p-type TFT 558 is turned off. Node N8 becomes floating and its potential remains at L. All other TFTs remain off. Output line 321 is floating, and the output signal OUT remains at H.

[0194] At time T62, immediately following time T61, the clock signal CLK_DRV changes from H to L. In response, the potential of node N7 changes from H to L. In response to the change in potential of node N7 from H to L, p-type TFT 554 and p-type pull-up TFT 311 turn on. The other TFTs remain off. p-type pull-up TFT 311 supplies potential VGH to output line 321, and the output signal OUT remains at H.

[0195] After time T62, the operation from time T42 to time T62 is repeated until the start of the next frame. As described above, the p-type TFT 554 and the p-type pull-up TFT 311 are turned on and off during the time period from time T42 to time T62. These two p-type TFTs are turned on from time T42 to time T51 and turned off from time T51 to time T62 (T42). The configuration of turning the two p-type TFTs 554 and 311 on and off synchronously with the clock signal CLK_DRV alleviates the positive Vg stress and reduces the instability of circuit operation caused by Vt offset.

[0196] Figure 16 It shows a reference Figure 14 and Figure 15 The configuration of a portion of the shift register in the described shift register unit. Figure 16 The diagram shows the first-stage shift register unit SR21, the second-stage shift register unit SR22, and the third-stage shift register unit SR23. Each of the shift register units SR21, SR22, and SR23 can have a reference... Figure 14 and Figure 15 The circuit configuration is described. A shift register may include n shift register units (n is a positive integer) connected sequentially according to the design.

[0197] Each shift register unit includes multiple signal terminals, specifically including VGH terminal 651, IN1 terminal 652, VGL terminal 653, CLK_RST terminal 654, OUT terminal 655, CLK_DRV terminal 656, and IN2 terminal 657. Figure 16 In the figure, as an example, the terminals of the first shift register unit SR21 are provided with reference numerals.

[0198] OUT terminal 655 output Figure 14 The output signal OUT is supplied to the VGH terminal 651, which is supplied with a constant high power supply potential VGH. The VGL terminal 653 is supplied with a constant low power supply potential VGL. The signal to be input to the IN1 terminal 652 is... Figure 15 The input signal IN1 is the signal to be input to the CLK_RST terminal 654. Figure 15 The clock signal CLK_RST is used. The signal to be input to the CLK_DRV terminal 656 is... Figure 15 The clock signal CLK_DRV is used. The signal to be input to the IN2 terminal of 657 is... Figure 15 The input signal IN2 is supplied to the shift register unit. Some input signals are supplied from the driver IC 134.

[0199] Shift register units SR21, SR22, and SR23 output output signals OUT21, OUT22, and OUT23 from their respective OUT terminals 655. These output signals are supplied to the gate of the TFT 24 in the pixel circuit, and further supplied to the IN1 terminal 652 of the next shift register unit and the IN2 terminal 657 of the previous shift register unit. The IN1 terminal 652 of the first shift register unit SR21 is supplied with the start signal ST.

[0200] The CLK_DRV terminal 656 of the (2k-1)th stage (k is a positive integer) is supplied with clock signal C21, and the CLK_DRV terminal 656 of the 2kth stage is supplied with clock signal C22. The CLK_RST terminal 654 of the (2k-1)th stage is supplied with clock signal C22, and the CLK_RST terminal 654 of the 2kth stage is supplied with clock signal C21. Clock signals C21 and C22 are used in the shift register unit in conjunction with a reference clock signal. Figure 15 The clock signal CLK_DRV described changes in the same way.

[0201] As described above, embodiments of the present invention have been presented; however, the present invention is not limited to the foregoing embodiments. Those skilled in the art can readily modify, add to, or transform each element of the foregoing embodiments within the scope of the present invention. A portion of the configuration of one embodiment may be replaced with the configuration of another embodiment, or the configuration of one embodiment may be incorporated into the configuration of another embodiment.

Claims

1. A shift register, comprising: Multiple shift register units are connected in sequence and configured to output signals sequentially. Each of the plurality of shift register units includes circuitry configured to output an output signal from an output line. The circuit includes: First output signal supply line; Second output signal supply line; Output line; A first p-type thin-film transistor is disposed between the first output signal supply line and the output line and is configured to be on and off. An n-type thin-film transistor, the n-type thin-film transistor being disposed between the second output signal supply line and the output line and configured to be on and off; and A second p-type thin-film transistor is disposed between the second output signal supply line and the output line and is configured to be on and off. The n-type thin-film transistor and the second p-type thin-film transistor are configured to be turned off when the first p-type thin-film transistor is turned on, so as to output the signal on the first output signal supply line to the output line. The first p-type thin-film transistor is configured to be turned off when the n-type thin-film transistor and the second p-type thin-film transistor are turned on, so as to supply the signal on the second output signal supply line to the output line. Each of the plurality of shift register units further includes: First control switch thin-film transistor; and The second control switch is a thin-film transistor. The first control switch thin-film transistor and the second control switch thin-film transistor are of the same conductivity type and are configured to be controlled to turn on / off according to the same input signal. Wherein, one of the first and second control switch thin-film transistors is configured to supply a gate signal to the first p-type thin-film transistor and the n-type thin-film transistor when the first control switch thin-film transistor is turned on, and The first control switch thin-film transistor and the second control switch thin-film transistor are configured to supply a gate signal to the second p-type thin-film transistor when the other control switch thin-film transistor is turned on.

2. The shift register according to claim 1, in, One of the first output signal supply line and the second output signal supply line is configured to supply a constant potential signal, and The other of the first output signal supply line and the second output signal supply line is configured to supply a signal that changes periodically between a low potential and a high potential.

3. The shift register according to claim 1, in, Each of the plurality of shift register units also includes a third control switch thin-film transistor. In this configuration, the gate of the first p-type thin-film transistor and the gate of the n-type thin-film transistor are supplied with a first gate signal. In this embodiment, the gate of the second p-type thin-film transistor is supplied with a second gate signal. The gate of the third control switch thin-film transistor is supplied with one of the first gate signal and the second gate signal. The third control switch thin-film transistor is configured to supply the other of the first gate signal and the second gate signal when the third control switch thin-film transistor is turned on.

4. The shift register according to claim 1, in, Each of the plurality of shift register units further includes a fourth control switch thin-film transistor. In this configuration, the gate of the first p-type thin-film transistor and the gate of the n-type thin-film transistor are supplied with a first gate signal. In this embodiment, the gate of the second p-type thin-film transistor is supplied with a second gate signal. The fourth control switch thin-film transistor is in a diode-connected state. In this embodiment, the drain of the fourth control switch thin-film transistor is supplied with a periodically changing signal, and The fourth control switch thin-film transistor is configured to supply one of the first gate signal and the second gate signal when the fourth control switch thin-film transistor is in a forward bias state.

5. The shift register according to claim 1, in, Each of the plurality of shift register units further includes: The third control switch thin-film transistor; and The fourth control switch is a thin-film transistor. In this configuration, the gate of the first p-type thin-film transistor and the gate of the n-type thin-film transistor are supplied with a first gate signal. In this embodiment, the gate of the second p-type thin-film transistor is supplied with a second gate signal. The gate of the third control switch thin-film transistor is supplied with one of the first gate signal and the second gate signal. The third control switch thin-film transistor is configured to supply the other of the first gate signal and the second gate signal when the third control switch thin-film transistor is turned on. The fourth control switch thin-film transistor is in a diode-connected state. In this embodiment, the drain of the fourth control switch thin-film transistor is supplied with a periodically changing signal, and The fourth control switch thin-film transistor is configured to supply one of the first gate signal and the second gate signal when the fourth control switch thin-film transistor is in a forward bias state.

6. The shift register according to claim 1, wherein, The first p-type thin-film transistor and the second p-type thin-film transistor are p-type polycrystalline silicon thin-film transistors.

7. The shift register according to claim 6, in, A first gate signal is supplied to the gate of the first p-type thin-film transistor and the gate of the n-type thin-film transistor, and A second gate signal, exhibiting a time variation opposite to that of the first gate signal, is supplied to the gate of the second p-type thin-film transistor.

8. The shift register according to claim 1 or 6, in, The second p-type thin-film transistor is configured to raise the potential of the output line to a potential that is a predetermined voltage higher than the potential of the second output signal supply line, and The n-type thin-film transistor is configured to reduce the potential of the output line from a potential that is higher than the potential of the second output signal supply line by a predetermined voltage to the potential of the second output signal supply line.

9. A shift register, comprising: Multiple shift register units are connected in sequence and configured to output signals sequentially. Each of the plurality of shift register units includes circuitry configured to output an output signal from an output line. The circuit includes: First output signal supply line; Second output signal supply line; Output line; A first p-type thin-film transistor is disposed between the first output signal supply line and the output line and is configured to be on and off. An n-type thin-film transistor, the n-type thin-film transistor being disposed between the second output signal supply line and the output line and configured to be on and off; and A second p-type thin-film transistor is disposed between the second output signal supply line and the output line and is configured to be on and off. The n-type thin-film transistor and the second p-type thin-film transistor are configured to be turned off when the first p-type thin-film transistor is turned on, so as to output the signal on the first output signal supply line to the output line. The first p-type thin-film transistor is configured to be turned off when the n-type thin-film transistor and the second p-type thin-film transistor are turned on, so as to supply the signal on the second output signal supply line to the output line. Each of the plurality of shift register units is configured to output an L-level signal pulse. Wherein, the first output signal supply line supplies a constant H-level signal, and The first p-type thin-film transistor is configured to repeatedly turn on and off during a predetermined time period within a frame after the output line outputs the H-level signal pulse following the output of the L-level signal pulse.

10. The shift register according to claim 9, in, The first p-type thin-film transistor and the n-type thin-film transistor are configured to turn on / off according to a clock signal, and The second output signal supply line supplies the clock signal.

11. The shift register according to claim 9, in, The first p-type thin-film transistor is configured to turn on / off according to a clock signal, and During the predetermined time period, the n-type thin-film transistor and the second p-type thin-film transistor are turned off.

12. The shift register according to claim 9, in, The second output signal supply line is configured to supply a signal that changes periodically between a low potential and a high potential.

13. The shift register according to claim 9, wherein, The first p-type thin-film transistor and the second p-type thin-film transistor are p-type polycrystalline silicon thin-film transistors.

14. The shift register according to claim 13, in, A first gate signal is supplied to the gate of the first p-type thin-film transistor and the gate of the n-type thin-film transistor, and A second gate signal, exhibiting a time variation opposite to that of the first gate signal, is supplied to the gate of the second p-type thin-film transistor.

15. The shift register according to claim 9 or 13, in, The second p-type thin-film transistor is configured to raise the potential of the output line to a potential that is a predetermined voltage higher than the potential of the second output signal supply line, and The n-type thin-film transistor is configured to reduce the potential of the output line from a potential that is higher than the potential of the second output signal supply line by a predetermined voltage to the potential of the second output signal supply line.

16. A circuit configured to output an output signal from an output line, the circuit comprising: First output signal supply line; Second output signal supply line; Output line; A first p-type thin-film transistor is disposed between the first output signal supply line and the output line and is configured to be on and off. An n-type thin-film transistor is disposed between the second output signal supply line and the output line and is configured to be on and off. as well as A second p-type thin-film transistor is disposed between the second output signal supply line and the output line and is configured to be on and off. The n-type thin-film transistor and the second p-type thin-film transistor are configured to be turned off when the first p-type thin-film transistor is turned on, so as to output the signal on the first output signal supply line to the output line. The first p-type thin-film transistor is configured to be turned off when the n-type thin-film transistor and the second p-type thin-film transistor are turned on, so as to supply the signal on the second output signal supply line to the output line. The second p-type thin-film transistor is configured to raise the potential of the output line to a predetermined voltage higher than the potential of the second output signal supply line. Wherein, the n-type thin-film transistor is configured to reduce the potential of the output line from a potential that is higher than the potential of the second output signal supply line by a predetermined voltage to the potential of the second output signal supply line, and There is a period in which the control terminal of the second p-type thin film transistor is in a floating state while the n-type thin film transistor and the second p-type thin film transistor are turned on.

17. The circuit according to claim 16, wherein, The first p-type thin-film transistor and the second p-type thin-film transistor are p-type polycrystalline silicon thin-film transistors.

18. The circuit according to claim 17, in, A first gate signal is supplied to the gate of the first p-type thin-film transistor and the gate of the n-type thin-film transistor, and A second gate signal, exhibiting a time variation opposite to that of the first gate signal, is supplied to the gate of the second p-type thin-film transistor.

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