Memory device and operating method thereof

Abstract

A memory device and an operating method thereof are disclosed. The memory device includes a memory array including a plurality of memory cells, a first region signal line decoder coupled to the memory array, a second region signal line decoder coupled to the memory array, and a controller coupled to and controlling the memory array, the first region signal line decoder, and the second region signal line decoder. A threshold voltage distribution of the memory cells is lower than a read voltage when programmed. A threshold voltage distribution of the memory cells is higher than the read voltage when erased.

Description

Technical Field

[0001] This invention relates to a memory device and a method of operating the same. Background Technology

[0002] Currently, memory devices are moving towards 3D stacking to increase memory density.

[0003] In terms of 3D structure, in addition to 3D NAND flash memory and 3D NOR flash memory, 3D AND flash memory has now been developed. In terms of transistor connection method, in 3D NAND flash memory, the memory transistors are connected in series; conversely, in 3D AND flash memory, the memory transistors are connected in parallel.

[0004] Currently, erasing memory can lead to over-erasure issues and is relatively slow. Furthermore, the slow erasure speed results in a wider threshold voltage distribution. This negatively impacts the performance of 3D memory. Summary of the Invention

[0005] According to one embodiment of the present invention, a memory device is provided, comprising: a memory array including a plurality of memory cells; a first region signal line decoder coupled to the memory array; a second region signal line decoder coupled to the memory array; and a controller coupled to and controlling the memory array, the first region signal line decoder, and the second region signal line decoder. During programming, a threshold voltage distribution of these memory cells is lower than a read voltage. During erasure, a threshold voltage distribution of these memory cells is higher than the read voltage.

[0006] According to another embodiment of the present invention, a method for operating a memory device is provided, the memory device including a memory array having a plurality of memory cells, the method comprising: during programming, applying a second overall signal line voltage to a first target memory cell of the memory cells such that a first threshold voltage distribution of the first target memory cell is lower than a read voltage; and during erasure, applying a first overall signal line voltage to a second target memory cell of the memory cells such that a second threshold voltage distribution of the second target memory cell is higher than the read voltage.

[0007] To provide a better understanding of the above and other aspects of the present invention, specific embodiments are described below in conjunction with the accompanying drawings: Attached Figure Description

[0008] Figure 1 A circuit diagram of a memory device according to an embodiment of the present invention is shown.

[0009] Figure 2 This diagram illustrates the operation of reading according to an embodiment of the present invention.

[0010] Figure 3 This diagram illustrates the operation of programming according to an embodiment of the present invention.

[0011] Figure 4 This diagram illustrates the operation of erasing according to an embodiment of the present invention.

[0012] Figure 5 This diagram illustrates the operation of stress recovery according to an embodiment of the present invention.

[0013] Figure 6 The diagram shows the distribution of the threshold voltage Vt according to an embodiment of the present invention.

[0014] [Symbol Explanation]

[0015] 100: Memory device

[0016] 110: Memory Array

[0017] 120: Controller

[0018] D_LSL: Region source-pole decoder

[0019] D_LBL: Region Bit Line Decoder

[0020] MC: Memory Unit

[0021] WL(Y, Z), WL(Y, Z+1), WL(Y+1, Z), WL(Y+1, Z+1): word line

[0022] LSL1~LSL4: Regional source lines

[0023] LBL1~LBL4: Regional bit lines

[0024] P11~P14, P21~P24: PMOS transistors

[0025] N11~N14, N21~N24: NMOS transistors

[0026] GBLN: Overall Bit Line

[0027] GSLN: Overall Source Line

[0028] SMC: Selected Memory Cell Detailed Implementation

[0029] The technical terms used in this invention refer to conventional terms in the art. Where this invention provides explanations or definitions for certain terms, the interpretation of those terms shall be based on the explanations or definitions provided in this invention. Each embodiment of this invention has one or more technical features. Where feasible, those skilled in the art may selectively implement some or all of the technical features in any embodiment, or selectively combine some or all of the technical features in these embodiments.

[0030] Please refer to Figure 1 The diagram illustrates a circuit diagram of a memory device according to an embodiment of the present invention. Figure 1 As shown, a memory device 100 according to an embodiment of the present invention includes: a memory array 110, a controller 120, a region source line decoder D_LSL, and a region bit line decoder D_LBL. The memory array 110 includes a plurality of memory cells MC arranged in an array. These memory cells MC are coupled to a plurality of word lines (such as WL(Y, Z), WL(Y, Z+1), WL(Y+1, Z), WL(Y+1, Z+1), etc.), a plurality of region source lines (such as LSL1 to LSL4), and a plurality of region bit lines (such as LBL1 to LBL4). The controller 120 is coupled to the memory array 110, the region source line decoder D_LSL, and the region bit line decoder D_LBL, and is used to control the memory array 110, the region source line decoder D_LSL, and the region bit line decoder D_LBL. For example, but not limited to, controller 120 controls read operations, programming operations, erase operations and stress recovery operations of memory array 110.

[0031] The region source line decoder D_LSL is coupled to the memory array 110. The region source line decoder D_LSL includes PMOS transistors P11 to P14 and NMOS transistors N11 to N14. These PMOS transistors P11 to P14 and NMOS transistors N11 to N14 form multiple CMOS (Complementary Metal-Oxide-Semiconductor) decoders (also called multiple first CMOS cells), each CMOS decoder including one PMOS transistor and one NMOS transistor.

[0032] Similarly, the region bit-line decoder D_LBL is coupled to the memory array 110. The region bit-line decoder D_LBL includes PMOS transistors P21 to P24 and NMOS transistors N21 to N24. The PMOS transistors P21 to P24 and the NMOS transistors N21 to N24 form multiple CMOS decoders (also called multiple second CMOS cells), each CMOS decoder including both PMOS and NMOS transistors.

[0033] Taking PMOS transistor P11 as an example, PMOS transistor P11 has: a first terminal (such as the source) coupled to the region source line LSL1, a second terminal (such as the drain) coupled to one of the overall bit lines (such as GBLN), and a control terminal (such as the gate) receiving a control signal (not shown). The coupling relationship of PMOS transistors P12 to P14 is similar to that of PMOS transistor P11.

[0034] Similarly, taking PMOS transistor P21 as an example, PMOS transistor P21 has: a first terminal (such as the source) coupled to the region bit line LBL1, a second terminal (such as the drain) coupled to one of the overall bit lines (such as GBLN), and a control terminal (such as the gate) receiving a control signal (not shown). The coupling relationship of PMOS transistors P22 to P24 is similar to that of PMOS transistor P21.

[0035] Taking NMOS transistor N11 as an example, NMOS transistor N11 has: a first terminal (such as the source) coupled to the regional source line LSL1, a second terminal (such as the drain) coupled to one of the overall source lines (such as GSLN), and a control terminal (such as the gate) receiving a control signal (not shown). The coupling relationship of NMOS transistors N12 to N14 is similar to that of NMOS transistor N11.

[0036] Taking NMOS transistor N21 as an example, NMOS transistor N21 has: a first terminal (such as the source) coupled to the region bit line LBL1, a second terminal (such as the drain) coupled to one of the overall source lines (such as GSLN), and a control terminal (such as the gate) receiving a control signal (not shown). The coupling relationship of NMOS transistors N22 to N24 is similar to that of NMOS transistor N21.

[0037] Each of these PMOS transistors P11-P14, PMOS transistors P21-P24, NMOS transistors N11-N14, and NMOS transistors N22-N24 is independently controlled to read, erase, program, and perform stress recovery on these memory cells MC.

[0038] The operation of the region source-to-line decoder D_LSL and the region bit-to-line decoder D_LBL will now be explained.

[0039] Taking the region-source line decoder D_LSL as an example, when at least one of the NMOS transistors N11 to N14 of the region-source line decoder D_LSL is turned on, the voltage on the overall source line GSLN can be conducted to the region source line, thereby pulling down the first terminal voltage of the memory cell MC to the voltage on the overall source line GSLN. Similarly, when at least one of the PMOS transistors P11 to P14 of the region-source line decoder D_LSL is turned on, the voltage on the overall bit line GBLN can be conducted to the region source line, thereby pulling up the first terminal voltage of the memory cell MC to the voltage on the overall bit line GBLN.

[0040] Similarly, taking the region bit line decoder D_LBL as an example, when at least one of the NMOS transistors N21 to N24 of the region bit line decoder D_LBL is turned on, the voltage on the overall source line GSLN can be conducted to the region bit line, thereby pulling down the voltage at the second terminal of the memory cell MC to the voltage on the overall source line GSLN. Similarly, when at least one of the PMOS transistors P21 to P24 of the region bit line decoder D_LBL is turned on, the voltage on the overall bit line GBLN can be conducted to the region bit line, thereby pulling up the voltage at the second terminal of the memory cell MC to the voltage on the overall bit line GBLN.

[0041] Figure 2 This diagram illustrates the operation of reading according to an embodiment of the present invention. Figure 2As shown, in the region source line decoder D_LSL, the PMOS transistor (e.g., P11) coupled to the selected memory cell SMC is not turned on, and other PMOS transistors (e.g., P12-P14) are not turned on; and the NMOS transistor (e.g., N11) coupled to the selected memory cell SMC is turned on, but other NMOS transistors (e.g., N12-N14) are not turned on. In the region bit line decoder D_LBL, the PMOS transistor (e.g., P21) coupled to the selected memory cell SMC is turned on, but other PMOS transistors (e.g., P22-P24) are not turned on; and the NMOS transistor (e.g., N11) coupled to the selected memory cell SMC is not turned on, and other NMOS transistors (e.g., N12-N14) are also not turned on. Therefore, the first terminal voltage of the selected memory cell SMC is the voltage of the overall source line GSLN (e.g., but not limited to 0V), and the second terminal voltage of the selected memory cell SMC is the voltage of the overall bit line GBLN (e.g., but not limited to 1.5V). Furthermore, the voltage coupled to the bit line (e.g., WL(Y+1, Z+1)) of the selected memory cell SMC (e.g., 5V) is used to turn on the selected memory cell SMC, while the voltages of other unselected word lines are, for example, but not limited to, 0V. This operation allows the selected memory cell SMC to be read. It should be understood that the above voltage values ​​are for illustrative purposes only, and the invention is not limited thereto.

[0042] That is, in the embodiments of the present invention, when reading, the region source line decoder conducts an overall source line voltage to a first target memory cell of these memory cells; and the region bit line decoder conducts an overall bit line voltage to the first target memory cell.

[0043] Figure 3 This diagram illustrates the operation of programming according to an embodiment of the present invention. Figure 3As shown, in the region source line decoder D_LSL, the PMOS transistor (e.g., P11) coupled to the selected memory cell SMC is turned on, while other PMOS transistors (e.g., P12-P14) are not turned on; and the NMOS transistor (e.g., N11) coupled to the selected memory cell SMC is not turned on, while other NMOS transistors (e.g., N12-N14) are turned on. In the region bit line decoder D_LBL, the PMOS transistor (e.g., P21) coupled to the selected memory cell SMC is turned on, while other PMOS transistors (e.g., P22-P24) are not turned on; and the NMOS transistor (e.g., N21) coupled to the selected memory cell SMC is not turned on, while other NMOS transistors (e.g., N22-N24) are turned on. Therefore, the first terminal voltage of the selected memory cell SMC is the voltage of the entire bit line GBLN (e.g., but not limited to +11V), and the second terminal voltage of the selected memory cell SMC is the voltage on the entire bit line GBLN (e.g., but not limited to +11V). Furthermore, the voltage on the selected bit line (e.g., WL(Y+1, Z+1)) coupled to the selected memory cell SMC is (e.g., but not limited to -11V), while the voltages of other unselected word lines are (e.g., but not limited to 3V). Therefore, the gate-source voltage of the selected memory cell SMC is -11V - 11V = -22V, which allows the selected memory cell SMC to be programmed. The gate-source voltages of other unselected memory cells (e.g., -8V or +6V) cannot be so low that they cannot be programmed. Through this programming operation, the selected memory cell SMC can be programmed. It should be understood that the above voltage values ​​are for illustrative purposes only, and the invention is not limited thereto.

[0044] In other words, in this embodiment of the invention, when programming, the gate-source voltage of the selected memory cell is set to a low level (e.g., -22V).

[0045] That is, in the embodiments of the present invention, during programming, the region source line decoder conducts an overall bit line voltage to a second target memory cell of these memory cells; and the region bit line decoder conducts the overall bit line voltage to the second target memory cell.

[0046] Figure 4 This diagram illustrates the operation of erasing according to an embodiment of the present invention. During erasing, multiple word lines of coupled memory cells can be erased simultaneously. For example... Figure 4As shown, in the region source line decoder D_LSL, PMOS transistors P11-P14 are not turned on, while NMOS transistors N11-N14 are turned on. In the region bit line decoder D_LBL, PMOS transistors P21-P24 are not turned on, and NMOS transistors N21-N24 are turned on. Therefore, the first terminal voltage of the selected memory cell SMC is the voltage of the overall source line GSLN (e.g., but not limited to -10V), and the second terminal voltage of the selected memory cell SMC is the voltage on the overall source line GSLN (e.g., but not limited to -10V). Furthermore, the voltage on the selected bit lines (such as WL(Y+1, Z+1) and WL(Y+1, Z)) coupled to the selected memory cell SMC is, for example, but not limited to +12V, while the voltage on other unselected word lines is, for example, but not limited to -2V. Therefore, the gate-source voltage of the selected memory cell SMC is +12 - (-10V) = +22V, which allows the selected memory cell SMC to be erased. The gate-source voltage of the other unselected memory cells is -2V - (-10V) = +8V, which cannot be erased. This erasure operation can erase the selected memory cell SMC. It should be understood that the above voltage values ​​are for illustrative purposes only, and the present invention is not limited thereto.

[0047] In other words, in this embodiment of the invention, when erasing is performed, the gate-source voltage of the selected memory cell is set to a high level (e.g., +22V).

[0048] That is, in the embodiments of the present invention, during erasure, the region source line decoder conducts an overall source line voltage to a third target memory cell of these memory cells; and the region bit line decoder conducts the overall source line voltage to the third target memory cell.

[0049] Figure 5 This diagram illustrates the operation of stress recovery according to an embodiment of the present invention. Figure 5As shown, in the region source line decoder D_LSL, the PMOS transistor (e.g., P11) coupled to the selected memory cell SMC is not turned on, but other PMOS transistors (e.g., P12-P14) are turned on; and the NMOS transistor (e.g., N11) coupled to the selected memory cell SMC is turned on, but other NMOS transistors (e.g., N12-N14) are not turned on. In the region bit line decoder D_LBL, the PMOS transistor (e.g., P21) coupled to the selected memory cell SMC is not turned on, but other PMOS transistors (e.g., P22-P24) are turned on; and the NMOS transistor (e.g., N21) coupled to the selected memory cell SMC is turned on, but other NMOS transistors (e.g., N22-N24) are not turned on. Therefore, the first terminal voltage of the selected memory cell SMC is the voltage of the entire source line GSLN (e.g., but not limited to -10V), and the second terminal voltage of the selected memory cell SMC is the voltage of the entire source line GSLN (e.g., but not limited to -10V). Furthermore, the voltage coupled to the selected bit line (e.g., WL(Y+1, Z+1)) of the selected memory cell SMC is, for example, but not limited to +12V, while the voltages of other unselected word lines are, for example, but not limited to 0V. Therefore, the gate-source voltage of the selected memory cell SMC is +12V - (-10V) = +22V, which allows the selected memory cell SMC to be stress-recovered. The gate-source voltages of other unselected memory cells are, for example, +10V, +8V, or -4V, and cannot be stress-recovered. Through this stress recovery operation, the selected memory cell SMC can be stress-recovered. It should be understood that the above voltage values ​​are for illustrative purposes only, and the present invention is not limited thereto.

[0050] In other words, in this embodiment of the invention, when stress recovery is performed, the gate-source voltage of the selected memory cell is set to a high level (e.g., +22V).

[0051] That is, in the embodiments of the present invention, during stress recovery, the region source line decoder conducts an overall source line voltage to a fourth target memory cell of these memory cells; and the region bit line decoder conducts the overall source line voltage to the fourth target memory cell.

[0052] Figure 6 The diagram shows the distribution of the threshold voltage Vt according to an embodiment of the present invention. Figure 6 As shown, in this embodiment of the invention, during programming (PGM), the threshold voltage Vt of the memory cell is distributed between approximately 2V and 3V, which is lower than the read voltage Vread (e.g., but not limited to 5V); and during erasure (ERS), the threshold voltage Vt of the memory cell is distributed between approximately 8V and 10V, which is higher than the read voltage Vread.

[0053] Therefore, in this embodiment of the invention, the problem of over-erasing will not be encountered, and the threshold voltage Vt distribution of the memory cell can even be improved with the application of a single erase pulse. Thus, this embodiment of the invention has the advantage of fast erasure.

[0054] Furthermore, in embodiments of the present invention, such as Figure 6 As shown, a narrower threshold voltage Vt helps improve the accuracy of reading and interpretation.

[0055] The embodiments of the present invention have now been described in detail with reference to the accompanying drawings.

[0056] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above descriptions are merely specific embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A memory device, wherein, include: A memory array comprising multiple memory cells; A first region signal line decoder is coupled to the memory array, wherein the first region signal line decoder includes a plurality of first CMOS cells corresponding to a plurality of first local signal lines, each of the first CMOS cells including a first PMOS transistor and a first NMOS transistor, the first terminals of the first PMOS transistor and the first NMOS transistor being coupled to the corresponding first region signal line; A second region signal line decoder is coupled to the memory array, wherein the second region signal line decoder includes a plurality of second CMOS cells correspondingly coupled to a plurality of second local signal lines, each second CMOS cell including a second PMOS transistor and a second NMOS transistor, the first terminals of the second PMOS transistor and the second NMOS transistor being commonly coupled to the corresponding second region signal line; and A controller is coupled to and controls the memory array, the first region signal line decoder, and the second region signal line decoder. in, During programming, a threshold voltage distribution of these memory cells is lower than a read voltage, wherein the first PMOS transistor of the first CMOS cell coupled to the second target memory cell is turned on, and the second PMOS transistor of the second CMOS cell coupled to the second target memory cell is turned on; and, During erasure, a threshold voltage distribution of these memory cells is higher than the read voltage.

2. The memory device according to claim 1, wherein, During reading, the first region signal line decoder conducts a first overall signal line voltage to a first target memory cell of these memory cells; The second region signal line decoder transmits a second overall signal line voltage to the first target memory cell, and the second overall signal line voltage is higher than the first overall signal line voltage.

3. The memory device according to claim 1, wherein, During programming, the first region signal line decoder conducts a second overall signal line voltage to a second target memory cell of these memory cells; The second region signal line decoder transmits the second overall signal line voltage to the second target memory cell.

4. The memory device according to claim 1, wherein, During erasure, the first region signal line decoder conducts a first overall signal line voltage to a third target memory cell of these memory cells; and the second region signal line decoder conducts the first overall signal line voltage to the third target memory cell.

5. The memory device according to claim 1, wherein, During stress recovery, the first region signal line decoder conducts a first overall signal line voltage to a fourth target memory cell of these memory cells; The second region signal line decoder transmits the voltage of the first overall signal line to the fourth target memory cell.

6. A method of operating a memory device, wherein, The memory device includes a first region signal line decoder, a second region signal line decoder, and a memory array having multiple memory cells. The operation method includes: During programming, a second overall signal line voltage is applied to a first target memory cell of these memory cells, such that a first threshold voltage distribution of the first target memory cell is lower than a read voltage; and, During erasure, a first overall signal line voltage is applied to a second target memory cell of these memory cells, such that a second threshold voltage distribution of the second target memory cell is higher than the read voltage; The first region signal line decoder includes multiple first CMOS units that are coupled to multiple first local signal lines. Each first CMOS unit includes a first PMOS transistor and a first NMOS transistor. The first terminals of the first PMOS transistor and the first NMOS transistor are coupled to the corresponding first region signal line. The second region signal line decoder includes multiple second CMOS units correspondingly coupled to multiple second local signal lines. Each second CMOS unit includes a second PMOS transistor and a second NMOS transistor. The first terminals of the second PMOS transistor and the second NMOS transistor are commonly coupled to the corresponding second region signal line. During programming, the first PMOS transistor of the first CMOS cell coupled to the second target memory cell is turned on, and the second PMOS transistor of the second CMOS cell coupled to the second target memory cell is turned on.

7. The method of operating the memory device according to claim 6, wherein, During reading, the first overall signal line voltage is conducted to a first terminal of the first target memory cell; and the second overall signal line voltage is conducted to a second terminal of the first target memory cell, wherein the second overall signal line voltage is higher than the first overall signal line voltage.

8. The method of operating the memory device according to claim 6, wherein, During programming, the voltage of the second overall signal line is conducted to a first terminal of the second target memory cell; and the voltage of the second overall signal line is conducted to a second terminal of the second target memory cell.

9. The method of operating the memory device according to claim 6, wherein, During erasure, the first overall signal line voltage is conducted to a first terminal of a third target memory cell of these memory cells; and the first overall signal line voltage is conducted to a second terminal of the third target memory cell.

10. The method of operating the memory device according to claim 6, wherein, During stress recovery, the first overall signal line voltage is conducted to a first terminal of a fourth target memory cell of these memory cells; and the first overall signal line voltage is conducted to a second terminal of the fourth target memory cell.

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