Memory device and method of operation thereof

Abstract

Memory devices and methods of operating the same are provided herein. A memory device can include a plurality of memory cells, a peripheral circuit, and control logic. The memory cells can be coupled to a plurality of word lines. The peripheral circuit can perform a memory operation on a selected memory cell. The control logic can control, during the memory operation, the peripheral circuit to: apply an operation voltage to a selected word line among the plurality of word lines that is coupled with the selected memory cell; apply a first pass voltage to a target word line among unselected word lines that is adjacent to the selected word line based on whether the operation voltage is lower than or equal to a reference voltage; and apply a second pass voltage having a lower level than the first pass voltage to remaining unselected word lines other than the target word line.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2021-0064408, filed on May 18, 2021, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] Various embodiments of this disclosure generally relate to electronic devices, and more specifically to memory devices and methods of operating memory devices. Background Technology

[0004] A storage device is a device that stores data based on a host device (such as a computer or smartphone). A storage device may include a memory device that stores the data therein and a memory controller that controls the memory device. Such memory devices are classified as volatile memory devices and non-volatile memory devices.

[0005] Volatile memory devices are memory devices that store data only when powered on and lose the stored data when power is interrupted. Examples of volatile memory devices include static random access memory (SRAM) and dynamic random access memory (DRAM).

[0006] Non-volatile memory devices are memory devices that retain stored data even when power is interrupted. Examples of non-volatile memory devices include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), and flash memory. Summary of the Invention

[0007] One embodiment of this disclosure may provide a memory device. The memory device may include a plurality of memory cells, peripheral circuitry, and control logic. The plurality of memory cells may be coupled to a plurality of word lines. The peripheral circuitry may perform memory operations on a memory cell selected from the plurality of memory cells. During memory operations, the control logic may control the peripheral circuitry to: apply an operating voltage to a selected word line coupled to the selected memory cell among the plurality of word lines; apply a first pass voltage to a target word line adjacent to the selected word line among unselected word lines based on whether the operating voltage is lower than or equal to a reference voltage; and apply a second pass voltage to the remaining unselected word lines other than the target word line, the second pass voltage having a lower level than the first pass voltage.

[0008] Embodiments of this disclosure may provide a method for operating a memory device having a plurality of memory cells coupled to a plurality of word lines. The method may include: applying an operating voltage to a selected word line coupled to a memory cell selected from the plurality of memory cells; determining whether the operating voltage is lower than or equal to the reference voltage; and when the operating voltage is lower than or equal to the reference voltage, applying a first pass voltage to an unselected word line adjacent to the selected word line, and applying a second pass voltage to the unselected word lines other than the target word line, the second pass voltage having a lower level than the first pass voltage. Attached Figure Description

[0009] Figure 1 This is a schematic diagram of a storage device according to an embodiment of the present disclosure.

[0010] Figure 2 It's a diagram. Figure 1 A diagram illustrating the structure of a memory device.

[0011] Figure 3 It's a diagram. Figure 2 A diagram of a memory cell array.

[0012] Figure 4 It's a diagram. Figure 2 A diagram illustrating one embodiment of a memory cell array.

[0013] Figure 5 It's a diagram. Figure 4 The circuit diagram of any memory block BLKa among memory blocks BLK1 to BLKz.

[0014] Figure 6 It's a diagram. Figure 4 A circuit diagram of an example of any memory block BLKb among memory blocks BLK1 to BLKz.

[0015] Figure 7 This is a diagram illustrating Incremental Step Pulse Programming (ISPP).

[0016] Figure 8 This is a diagram illustrating multiple programming states categorized according to the reference voltage.

[0017] Figure 9 This is a diagram illustrating the distribution of threshold voltages based on the degree of retention degradation of memory cells.

[0018] Figure 10 This is a diagram illustrating the voltages applied to multiple word lines during memory operation according to one embodiment.

[0019] Figure 11This is a diagram illustrating the effective channel length, which varies with the magnitude of the through voltage applied to the target word line adjacent to the selected word line.

[0020] Figure 12 This is a diagram illustrating the difference between margins in adjacent threshold voltage distributions based on the effective channel length.

[0021] Figure 13A This is a timing diagram illustrating the operation of a memory device according to one embodiment.

[0022] Figure 13B This is a timing diagram illustrating the operation of a memory device according to one embodiment.

[0023] Figure 14 This is a flowchart illustrating the operation of a memory device according to one embodiment.

[0024] Figure 15 This is a flowchart illustrating the operation of a memory device according to one embodiment. Detailed Implementation

[0025] The specific structural or functional descriptions of the embodiments of this disclosure as presented in this specification or application are illustrative of embodiments based on the concept of this disclosure. Embodiments based on the concept of this disclosure may be practiced in various forms and should not be construed as limited to the embodiments described in this specification or application.

[0026] Various embodiments of this disclosure relate to memory devices and methods of operating such memory devices, in which read margins between threshold voltage distributions corresponding to respective programming states are increased.

[0027] Figure 1 This is a diagram illustrating a storage device according to an embodiment of the present disclosure.

[0028] refer to Figure 1 Storage device 50 may include memory device 100 and memory controller 200, with memory controller 200 controlling the operation of memory device 100. Storage device 50 may be a host-based data storage device, such as a mobile phone, smartphone, MP3 player, laptop computer, desktop computer, game console, television (TV), tablet PC, or in-vehicle infotainment system.

[0029] Storage device 50 can be manufactured as any of a variety of storage devices based on a host interface used for communication with the host. Storage device 50 can be implemented as any of a variety of storage devices, such as solid-state drives (SSDs), multimedia cards (such as MMC, embedded MMC (eMMC), miniaturized MMC (RS-MMC), or micro MMC), secure digital cards (such as SD, miniature SD, or micro SD), universal serial bus (USB) storage devices, universal flash memory (UFS) devices, PCMCIA card storage devices, peripheral component interconnect (PCI) card storage devices, PCI rapid (PCI-E) card storage devices, compact flash (CF) cards, smart media cards, and memory sticks.

[0030] Storage device 50 can be manufactured in any of a variety of package types. For example, storage device 50 can be manufactured in any of a variety of package types, such as POP, SIP, SOC, MCP, COB, WFP, and WSP.

[0031] The memory device 100 can store data. The memory device 100 can operate in response to the control of the memory controller 200. The memory device 100 may include a memory cell array, which includes a plurality of memory cells for storing data.

[0032] Each memory cell in the memory unit can be implemented as a single-level cell (SLC) capable of storing one data bit, a multi-level cell (MLC) capable of storing two data bits, a three-level cell (TLC) capable of storing three data bits, or a four-level cell (QLC) capable of storing four data bits.

[0033] The memory cell array may include multiple memory blocks. Each memory block may include multiple memory cells. A single memory block may include multiple pages. In one embodiment, each page may be a unit for storing data in or retrieving data stored in the memory device 100.

[0034] A memory block can be a unit through which data is erased. In one embodiment, the memory device 100 may take the form of various alternatives, such as Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM), Low Power Double Data Rate 4 (LPDDR4) SDRAM, Graphics Double Data Rate (GDDR) SDRAM, Low Power DDR (LPDDR) SDRAM, Rambus Dynamic Random Access Memory (RDRAM), NAND flash memory, Vertical NAND flash memory, NOR flash memory device, Resistive RAM (RRAM), Phase Change RAM (PRAM), Magnetoresistive RAM (MRAM), Ferroelectric RAM (FRAM), or Spin-Torque RAM (STT-RAM). In this specification, for ease of description, it will be described assuming that the memory device 100 is NAND flash memory.

[0035] Memory device 100 can receive commands and addresses from memory controller 200, and memory device 100 can access an address-selected region in the memory cell array. That is, memory device 100 can perform operations instructed by commands on the address-selected region. For example, memory device 100 can perform write operations (i.e., programming operations), read operations, and erase operations. During a programming operation, memory device 100 can program data into the address-selected region. During a read operation, memory device 100 can read data from the address-selected region. During an erase operation, memory device 100 can erase data stored in the address-selected region.

[0036] The memory controller 200 can control the overall operation of the storage device 50.

[0037] When power is supplied to storage device 50, memory controller 200 may run firmware (FW). When storage device 100 is a flash memory device, memory controller 200 may run firmware such as flash translation layer (FTL) for controlling communication between the host and storage device 100.

[0038] In one embodiment, the memory controller 200 may receive data and a logical block address (LBA) from a host, and the memory controller 200 may translate the logical block address (LBA) into a physical block address (PBA), the physical block address (PBA) indicating the address of a memory cell included in the memory device 100 and in which data will be stored.

[0039] In response to a request received from the host, the memory controller 200 can control the memory device 100 to perform programming, reading, or erasing operations. During a programming operation, the memory controller 200 can provide the memory device 100 with a write command, a physical block address (PBA), and data. During a read operation, the memory controller 200 can provide the memory device 100 with a read command and a physical block address (PBA). During an erase operation, the memory controller 200 can provide the memory device 100 with an erase command and a physical block address (PBA).

[0040] In one embodiment, regardless of whether a request from the host is received, the memory controller 200 can autonomously generate commands, addresses, and data, and can transmit them to the memory device 100. For example, the memory controller 200 can provide commands, addresses, and data to the memory device 100 to perform background operations, such as programming operations for wear leveling and programming operations for garbage collection.

[0041] In one embodiment, the memory controller 200 can control at least two memory devices 100. In this case, the memory controller 200 can improve operational performance by using an interleaving scheme to control the memory devices 100. The interleaving scheme can be an operational method that causes the operation periods of at least two memory devices 100 to overlap with each other.

[0042] The host can communicate with the storage device 50 using at least one of a variety of communication methods, such as USB, Serial AT Attachment (SATA), Serial Attached SCSI (SAS), High Speed ​​Inter-Chip (HSIC), Small Computer System Interface (SCSI), Peripheral Component Interconnect (PCI), PCIe, Non-Volatile Memory Fast (NVMe), Universal Flash Memory (UFS), Secure Digital (SD), Multimedia Card (MMC), Embedded MMC (eMMC), Dual In-line Memory Module (DIMM), Registered DIMM (RDIMM), and Load-Depleted DIMM (LRDIMM).

[0043] Figure 2 It's a diagram. Figure 1 A diagram illustrating the structure of a memory device.

[0044] refer to Figure 2 The memory device 100 may include a memory cell array 110, peripheral circuitry 120, and control logic 130.

[0045] The memory cell array 110 may include multiple memory blocks BLK1 to BLKz. The multiple memory blocks BLK1 to BLKz may be coupled to the address decoder 121 via row lines RL. The memory blocks BLK1 to BLKz may be coupled to read and write circuitry 123 via bit lines BL1 to BLm. Each memory block in BLK1 to BLKz may include multiple memory cells. In one embodiment, the multiple memory cells may be non-volatile memory cells. Among the multiple memory cells, memory cells coupled to the same word line may be defined as a single physical page. That is, the memory cell array 110 may consist of multiple physical pages. According to one embodiment of this disclosure, each memory block in the multiple memory blocks BLK1 to BLKz included in the memory cell array 110 may include multiple dummy cells. As dummy cells, one or more dummy cells may be coupled in series between a drain select transistor and a memory cell, and between a source select transistor and a memory cell.

[0046] Each memory cell in the memory cell of the memory device 100 can be implemented as a single-level cell (SLC) capable of storing a single data bit, a multi-level cell (MLC) capable of storing two data bits, a three-level cell (TLC) capable of storing three data bits, or a four-level cell (QLC) capable of storing four data bits.

[0047] The peripheral circuit 120 may include an address decoder 121, a voltage generator 122, a read and write circuit 123, a data input / output circuit 124, and a sensing circuit 125.

[0048] The peripheral circuitry 120 can drive the memory cell array 110. For example, the peripheral circuitry 120 can drive the memory cell array 110 to perform programming operations, read operations, and erase operations.

[0049] Address decoder 121 can be coupled to memory cell array 110 via row lines RL. Row lines RL may include drain select lines, word lines, source select lines, and common source lines. According to one embodiment of this disclosure, word lines may include normal word lines and dummy word lines. According to one embodiment of this disclosure, row lines RL may also include pipe select lines.

[0050] Address decoder 121 can operate based on control logic 130. Address decoder 121 can receive address ADDR from control logic 130.

[0051] Address decoder 121 can decode the block address in the received address ADDR. Address decoder 121 can select at least one memory block from BLK1 to BLKz based on the decoded block address. Address decoder 121 can decode the row address in the received address ADDR. Address decoder 121 can select at least one word line from the word lines of the selected memory block based on the decoded row address. Address decoder 121 can apply the operating voltage Vop provided from voltage generator 122 to the selected word line.

[0052] During programming operations, address decoder 121 can apply a programming voltage to the selected word line and a programming pass voltage with a lower level than the programming voltage to the unselected word line. During programming verification operations, address decoder 121 can apply a verification voltage to the selected word line and a verification pass voltage with a higher level than the verification voltage to the unselected word line.

[0053] During a read operation, the address decoder 121 can apply a read voltage to the selected word line and apply a read pass voltage with a higher level than the read voltage to the unselected word line.

[0054] According to one embodiment of this disclosure, the erase operation of the memory device 100 can be performed on a block-by-block basis. During the erase operation, the address ADDR input to the memory device 100 may include a block address. The address decoder 121 can decode the block address and select a single memory block in response to the decoded block address. During the erase operation, the address decoder 121 may apply a ground voltage to a word line coupled to the selected memory block.

[0055] According to embodiments of this disclosure, address decoder 121 can decode the column address in the received address ADDR. The decoded column address can be transmitted to read and write circuitry 123. In one embodiment, address decoder 121 may include components such as row decoder, column decoder, and address buffer.

[0056] Voltage generator 122 can generate multiple operating voltages Vop using the external power supply voltage provided to memory device 100. Voltage generator 122 can operate based on control logic 130.

[0057] In one embodiment, voltage generator 122 can generate an internal power supply voltage by adjusting an external power supply voltage. The internal power supply voltage generated by voltage generator 122 is used as the operating voltage of memory device 100.

[0058] In one embodiment, voltage generator 122 can generate multiple operating voltages Vop by using an external power supply voltage or an internal power supply voltage. Voltage generator 122 can generate various voltages required by memory device 100. For example, voltage generator 122 can generate multiple erase voltages, multiple programming voltages, multiple pass voltages, multiple select read voltages, and multiple unselect read voltages.

[0059] Voltage generator 122 may include multiple pump capacitors for receiving internal power supply voltages to generate multiple operating voltages Vop with different voltage levels, and voltage generator 122 may generate multiple operating voltages Vop by selectively enabling multiple pump capacitors based on control logic 130.

[0060] The generated operating voltage Vop can be provided to the memory cell array 110 by the address decoder 121.

[0061] The read and write circuitry 123 may include first to m-th page buffers PB1 to PBm. The first to m-th page buffers PB1 to PBm may be coupled to the memory cell array 110 via first to m-th bit lines BL1 to BLm, respectively. The first to m-th page buffers PB1 to PBm may operate based on control logic 130.

[0062] The buffers PB1 to PBm, representing pages m, can perform data communication with the data input / output circuit 124. During programming operations, the buffers PB1 to PBm can receive the data to be stored, DATA, through the data input / output circuit 124 and the data line DL.

[0063] During programming operations, when a programming voltage is applied to the selected word line, the first to m-th page buffers PB1 to PBm can transfer the data DATA to be stored, received via the data input / output circuit 124, to the selected memory cell via bit lines BL1 to BLm. The memory cell in the selected page can be programmed based on the received data DATA. Memory cells coupled to bit lines to which a programming enable voltage (e.g., ground voltage) is applied can have an increased threshold voltage. The threshold voltage of memory cells coupled to bit lines to which a programming disable voltage (e.g., power supply voltage) is applied can be maintained. During programming verification operations, the first to m-th page buffers PB1 to PBm read the data DATA stored in the selected memory cell from the selected memory cell via bit lines BL1 to BLm.

[0064] During a read operation, the read and write circuit 123 can read data DATA from the memory cell in the selected page via the bit line BL, and the read and write circuit 123 can store the read data DATA in the first to m-th page buffers PB1 to PBm.

[0065] During the erase operation, the read and write circuitry 123 may allow the bit line BL to float. In one embodiment, the read and write circuitry 123 may include column select circuitry.

[0066] The data input / output circuit 124 can be coupled to the first to m-th page buffers PB1 to PBm via the data line DL. The data input / output circuit 124 can operate in response to the control logic 130.

[0067] The data input / output circuit 124 may include multiple input / output buffers (not shown) for receiving input data DATA. During programming operations, the data input / output circuit 124 may receive data DATA to be stored from an external controller (not shown). During reading operations, the data input / output circuit 124 may output data DATA received from the first to m-th page buffers PB1 to PBm included in the read and write circuit 123 to the external controller.

[0068] During a read or verification operation, the sensing circuit 125 may generate a reference current in response to the enable bit signal VRYBIT generated by the control logic 130, and the sensing circuit 125 may output a pass signal or a failure signal to the control logic 130 by comparing the sensed voltage VPB received from the read and write circuit 123 with the reference voltage generated by the reference current.

[0069] Control logic 130 can be coupled to address decoder 121, voltage generator 122, read and write circuitry 123, data input / output circuitry 124, and sensing circuitry 125. Control logic 130 can control the overall operation of memory device 100. Control logic 130 can operate in response to commands (CMD) transmitted from external devices.

[0070] Control logic 130 can control peripheral circuitry 120 by generating various types of signals in response to command CMD and address ADDR. For example, control logic 130 can generate an operation signal OPSIG, address ADDR, read / write circuit control signals PBSIGNALS, and an enable bit VRYBIT in response to command CMD and address ADDR. Control logic 130 can output the operation signal OPSIG to voltage generator 122, the address ADDR to address decoder 121, the read / write circuit control signals PBSIGNALS to read / write circuitry 123, and the enable bit VRYBIT to sensing circuitry 125. Additionally, control logic 130 can determine whether the verification operation passed or failed in response to a pass signal PASS or a failure signal FAIL output from sensing circuitry 125.

[0071] In one embodiment, the peripheral circuitry 120 can perform memory operations on a memory cell selected from a plurality of memory cells. The memory operation can be a read operation or a program verification operation.

[0072] During memory operation, control logic 130 can control peripheral circuitry 120 such that an operating voltage is applied to selected word lines coupled to selected memory cells. Control logic 130 can also control peripheral circuitry 120 based on whether the operating voltage is lower than or equal to a reference voltage, such that a first pass voltage is applied to unselected word lines adjacent to the selected word lines, referred to as target word lines. Control logic 130 can further control peripheral circuitry 120 such that a second pass voltage, having a lower level than the first pass voltage, is applied to the remaining unselected word lines, excluding the target word lines.

[0073] In one embodiment, control logic 130 may include memory operation table storage device 131 and memory operation controller 132.

[0074] The memory operation table storage device 131 can store information related to the operating voltage used in memory operations and information related to multiple pass voltages. The operating voltage can be a read voltage or a programming verification voltage applied to a selected word line. Multiple pass voltages can be applied to unselected word lines.

[0075] During memory operation, the memory operation controller 132 can control the peripheral circuitry 120 such that an operating voltage is applied to a plurality of word lines coupled to a selected memory cell.

[0076] The memory operation controller 132 can compare the operating voltage with a reference voltage to determine whether the operating voltage is lower than or equal to the reference voltage. The memory operation controller 132 can control the peripheral circuitry 120 such that, when the operating voltage is lower than or equal to the reference voltage, while the operating voltage is applied to the selected word line, a first pass voltage is applied to an unselected word line adjacent to the selected word line, referred to as the target word line. The memory operation controller 132 can also control the peripheral circuitry 120 such that, while the operating voltage is applied to the selected word line, a second pass voltage having a level lower than the first pass voltage is applied to the remaining unselected word lines, excluding the target word line.

[0077] The memory operation controller 132 can control the peripheral circuit 120 such that when the operating voltage is higher than the reference voltage, the same pass voltage is applied to the unselected word line while the operating voltage is applied to the selected word line.

[0078] In one embodiment, the memory operation controller 132 may update the reference voltage based on the degree of preservation degradation of a plurality of memory cells. As the degree of preservation degradation of the plurality of memory cells increases, the memory operation controller 132 may decrease the level of the reference voltage. As the degree of preservation degradation of the plurality of memory cells increases, the memory operation controller 132 may increase the voltage level difference between the first pass voltage and the second pass voltage.

[0079] In one embodiment, the reference voltage may be a programming verification voltage corresponding to the lowest programming state among a plurality of programming states of the selected memory cell. In another embodiment, the reference voltage may be a programming verification voltage corresponding to an intermediate programming state among a plurality of programming states of the selected memory cell.

[0080] Figure 3 It's a diagram. Figure 2 A diagram of a memory cell array.

[0081] refer to Figure 3 The first to the z-th memory blocks BLK1 to BLKz can be jointly coupled to the first to the m-th bit lines BL1 to BLm. Figure 3 For ease of description, the elements included in the first memory block BLK1 of the plurality of memory blocks BLK1 to BLKz are illustrated, while the elements included in each of the remaining memory blocks BLK2 to BLKz are omitted. It should be understood that each of the remaining memory blocks BLK2 to BLKz has the same configuration as the first memory block BLK1.

[0082] The memory block BLK1 may include multiple cell strings CS1_1 to CS1_m (where m is a positive integer). The first to m-th cell strings CS1_1 to CS1_m may be coupled to the first to m-th bit lines BL1 to BLm, respectively. Each cell string in the first to m-th cell strings CS1_1 to CS1_m may include a drain selection transistor DST, multiple memory cells MC1 to MCn (where n is a positive integer) coupled in series with each other, and a source selection transistor SST.

[0083] The gate terminal of the drain-select transistor DST included in each of the first to m-th cell strings CS1_1 to CS1_m can be coupled to the first drain-select line DSL1. The gate terminals of the first to n-th memory cells MC1 to MCn included in each of the first to m-th cell strings CS1_1 to CS1_m can be coupled to the first to n-th word lines WL1 to WLn, respectively. The gate terminal of the source-select transistor SST included in each of the first to m-th cell strings CS1_1 to CS1_m can be coupled to the first source-select line SSL1.

[0084] For ease of description, the structure of each unit string will be described based on the first unit string CS1_1 among multiple unit strings CS1_1 to CS1_m. However, it should be understood that each of the remaining unit strings CS1_2 to CS1_m is configured in the same way as the first unit string CS1_1.

[0085] The drain terminal of the drain select transistor DST included in the first cell string CS1_1 can be coupled to the first bit line BL1. The source terminal of the drain select transistor DST included in the first cell string CS1_1 can be coupled to the drain terminal of the first memory cell MC1 included in the first cell string CS1_1. The first to nth memory cells MC1 to MCn can be coupled in series with each other. The drain terminal of the source select transistor SST included in the first cell string CS1_1 can be coupled to the source terminal of the nth memory cell MCn included in the first cell string CS1_1. The source terminal of the source select transistor SST included in the first cell string CS1_1 can be coupled to the common source line CSL. In one embodiment, the common source line CSL can be commonly coupled to the first to zth memory blocks BLK1 to BLKz.

[0086] The first drain selection line DSL1, the first to nth word lines WL1 to WLn, and the first source selection line SSL1 can be included. Figure 2In the row line RL, the first drain selection line DSL1, the first to nth word lines WL1 to WLn, and the first source selection line SSL1 can be controlled by the address decoder 121. The common source line CSL can be controlled by the control logic 130. The first to mth bit lines BL1 to BLm can be controlled by the read and write circuit 123.

[0087] Figure 4 It's a diagram. Figure 2 A diagram illustrating one embodiment of a memory cell array.

[0088] refer to Figure 4 The memory cell array 110 may include multiple memory blocks BLK1 to BLKz. Each memory block may have a three-dimensional (3D) structure. Each memory block may include multiple memory cells stacked on a substrate. Such memory cells may be arranged along the positive X (+X) direction, the positive Y (+Y) direction, and the positive Z (+Z) direction. Reference will be made below. Figure 5 and Figure 6 Let's describe the structure of each memory block in detail.

[0089] Figure 5 It's a diagram. Figure 4 The circuit diagram of any memory block BLKa among memory blocks BLK1 to BLKz.

[0090] refer to Figure 5 The memory block BLKa may include multiple cell strings CS11 to CS1m and CS21 to CS2m. In one embodiment, each of the cell strings CS11 to CS1m and CS21 to CS2m may be formed in a "U" shape. In the memory block BLKa, m cell strings may be arranged along the row direction (i.e., the positive (+)X direction). Figure 5 In the diagram, two unit strings are illustrated as arranged along the column direction (i.e., the positive (+) Y direction). However, this illustration is for ease of description, and it can be understood that three or more unit strings can be arranged along the column direction.

[0091] In one embodiment, a single memory block may include multiple sub-blocks. A single sub-block may include a string of cells arranged in a "U" shape in a single column.

[0092] Each of the multiple cell strings CS11 to CS1m and CS21 to CS2m may include at least one source selection transistor SST, first to nth memory cells MC1 to MCn, a pipe transistor PT, and at least one drain selection transistor DST.

[0093] The select transistors SST and DST, and the memory cells MC1 to MCn, can have similar structures. In one embodiment, each of the select transistors SST and DST, and the memory cells MC1 to MCn, may include a channel layer, a tunneling insulating layer, a charge storage layer, and a barrier insulating layer. In one embodiment, pillars for providing the channel layer may be provided in each cell string. In another embodiment, pillars for providing at least one of the channel layer, tunneling insulating layer, charge storage layer, and barrier insulating layer may be provided in each cell string.

[0094] The source selection transistor SST of each cell string can be coupled between the common source line CSL and the memory cells MC1 to MCn.

[0095] In one embodiment, source-select transistors of cell strings arranged in the same row can be coupled to source-select lines extending along the row direction, and source-select transistors of cell strings arranged in different rows can be coupled to different source-select lines. Figure 5 In the first row, the source selection transistors of cell strings CS11 to CS1m can be coupled to the first source selection line SSL1. In the second row, the source selection transistors of cell strings CS21 to CS2m can be coupled to the second source selection line SSL2.

[0096] In one embodiment, the source selection transistors of cell strings CS11 to CS1m and CS21 to CS2m can be co-coupled to a single source selection line.

[0097] The first to nth memory cells MC1 to MCn in each cell string can be coupled between the source select transistor SST and the drain select transistor DST.

[0098] The first to nth memory cells MC1 to MCn can be divided into the first to pth memory cells MC1 to MCp and the (p+1)th to nth memory cells MCp+1 to MCn. The first to pth memory cells MC1 to MCp can be arranged sequentially in opposite directions along the positive (+)Z direction and can be series-coupled between the source selection transistor SST and the channel transistor PT. The (p+1)th to nth memory cells MCp+1 to MCn can be arranged sequentially along the +Z direction and can be series-coupled between the channel transistor PT and the drain selection transistor DST. The first to pth memory cells MC1 to MCp and the (p+1)th to nth memory cells MCp+1 to MCn can be coupled to each other via the channel transistor PT. The gates of the first to nth memory cells MC1 to MCn in each cell string can be coupled to the first to nth word lines WL1 to WLn, respectively.

[0099] The gate of the pipe transistor PT in each unit string can be coupled to the pipe line PL.

[0100] The drain select transistor (DST) of each cell string can be coupled between the corresponding bit line and memory cells MCp+1 to MCn. Cell strings in the row direction can be coupled to drain select lines extending along the row direction. The drain select transistors of cell strings CS11 to CS1m in the first row can be coupled to the first drain select line DSL1. The drain select transistors of cell strings CS21 to CS2m in the second row can be coupled to the second drain select line DSL2.

[0101] A string of cells arranged along the column direction can be coupled to a bit line extending along the column direction. Figure 5 In the first column, the cell strings CS11 and CS21 can be coupled to the first bit line BL1. The cell strings CS1m and CS2m in the m-th column can be coupled to the m-th bit line BLm.

[0102] In a cell string arranged along a row direction, memory cells coupled to the same word line can form a single page. For example, in cell strings CS11 to CS1m in the first row, memory cells coupled to the first word line WL1 can form a single page. In cell strings CS21 to CS2m in the second row, memory cells coupled to the first word line WL1 can form additional pages. A cell string arranged in a single row direction can be selected by selecting either the drain select line DSL1 or DSL2. A single page can be selected from the selected cell string by selecting any of the word lines WL1 to WLn.

[0103] In one embodiment, even-numbered bit lines and odd-numbered bit lines can be provided instead of the first to m-th bit lines BL1 to BLm. Furthermore, in the cell strings CS11 to CS1m or CS21 to CS2m arranged along the row direction, even-numbered cell strings can be coupled to the corresponding even-numbered bit lines. In the cell strings CS11 to CS1m or CS21 to CS2m arranged along the row direction, odd-numbered cell strings can be coupled to the corresponding odd-numbered bit lines.

[0104] In one embodiment, one or more memory cells from the first to the nth memory cells MC1 to MCn can be used as dummy memory cells. For example, one or more dummy memory cells can be provided to reduce the electric field between the source selection transistor SST and the memory cells MC1 to MCp. Alternatively, one or more dummy memory cells can be provided to reduce the electric field between the drain selection transistor DST and the memory cells MCp+1 to MCn. As more dummy memory cells are provided, the operational reliability of the memory block BLKa is improved, but the size of the memory block BLKa increases. As fewer memory cells are provided, the size of the memory block BLKa decreases, but the operational reliability of the memory block BLKa may further deteriorate.

[0105] To efficiently control one or more dummy memory cells, each dummy memory cell can have a desired threshold voltage. Programming operations can be performed on all or some of the dummy memory cells before or after an erase operation is performed on the memory block BLKa. When an erase operation is performed after a programming operation has been performed, the threshold voltage of the dummy memory cell can control the voltage applied to the dummy word line coupled to the corresponding dummy memory cell, and therefore, the dummy memory cell can have the desired threshold voltage.

[0106] Figure 6 It's a diagram. Figure 4 A circuit diagram of an example of any memory block BLKb among memory blocks BLK1 to BLKz.

[0107] refer to Figure 6 The memory block BLKb may include multiple cell strings CS11' to CS1m' and CS21' to CS2m'. Each cell string CS11' to CS1m' and CS21' to CS2m' may extend along the positive (+)Z direction. Each cell string CS11' to CS1m' and CS21' to CS2m' may include at least one source selection transistor SST, first to nth memory cells MC1 to MCn, and at least one drain selection transistor DST stacked on a substrate (not shown) below the memory block BLKb.

[0108] In one embodiment, a single memory block may include multiple sub-blocks. A single sub-block may include a string of cells arranged in an "I" shape in a single column.

[0109] The source select transistor SST of each cell string can be coupled between a common source line CSL and memory cells MC1 to MCn. Source select transistors of cell strings arranged in the same row can be coupled to the same source select line. The source select transistors of cell strings CS11' to CS1m' arranged in the first row can be coupled to a first source select line SSL1. The source select transistors of cell strings CS21' to CS2m' arranged in the second row can be coupled to a second source select line SSL2. In one embodiment, the source select transistors of cell strings CS11' to CS1m' and CS21' to CS2m' can be commonly coupled to a single source select line.

[0110] The first to nth memory cells MC1 to MCn in each cell string can be coupled in series between the source select transistor SST and the drain select transistor DST. The gates of the first to nth memory cells MC1 to MCn can be coupled to the first to nth word lines WL1 to WLn, respectively.

[0111] The drain select transistor (DST) of each cell string can be coupled between the corresponding bit line and memory cells MC1 to MCn. The drain select transistors of cell strings arranged along the row direction can be coupled to drain select lines extending along the row direction. The drain select transistors of cell strings CS11' to CS1m' in the first row can be coupled to the first drain select line DSL1. The drain select transistors of cell strings CS21' to CS2m' in the second row can be coupled to the second drain select line DSL2.

[0112] result, Figure 6 The memory block BLKb has the same Figure 5 The memory block BLKa has a similar equivalent circuit, except that the pipe transistor PT is removed from each cell string.

[0113] In one embodiment, even-numbered bit lines and odd-numbered bit lines can be provided instead of the first to m-th bit lines BL1 to BLm. Furthermore, among the cell strings CS11' to CS1m' or CS21' to CS2m' arranged along the row direction, even-numbered cell strings can be coupled to the corresponding even-numbered bit lines. Among the cell strings CS11' to CS1m' or CS21' to CS2m' arranged along the row direction, odd-numbered cell strings can be coupled to the corresponding odd-numbered bit lines.

[0114] In one embodiment, one or more of the first to nth memory cells MC1 to MCn can be used as dummy memory cells. For example, one or more dummy memory cells can be provided to reduce the electric field between the source selection transistor SST and the memory cells MC1 to MCn. Alternatively, one or more dummy memory cells can be provided to reduce the electric field between the drain selection transistor DST and the memory cells MC1 to MCn. As the number of provided dummy memory cells increases, the operational reliability of the memory block BLKb can be improved, while the size of the memory block BLKb may increase. As the number of provided dummy memory cells decreases, the size of the memory block BLKb may decrease, while the operational reliability of the memory block BLKb may further deteriorate.

[0115] To efficiently control one or more dummy memory cells, the corresponding dummy memory cells may require a threshold voltage. Programming operations can be performed on all or some of the dummy memory cells before or after an erase operation on the memory block BLKb. When an erase operation is performed after the programming operation has been performed, the dummy memory cells can receive the required threshold voltage by controlling the voltage to be applied to the dummy word line coupled to the corresponding dummy memory cell.

[0116] Figure 7 This is a diagram illustrating Incremental Step Pulse Programming (ISPP).

[0117] exist Figure 7 For ease of description, it is assumed that the memory cell is a multi-level cell (MLC) that stores 2 bits of data. However, the scope of this disclosure is not limited to this, and the memory cell may be a three-level cell (TLC) that stores 3 bits of data or a four-level cell (QLC) that stores 4 bits of data. The number of data bits stored in each memory cell may be one or more.

[0118] The memory device can perform programming operations by executing multiple programming cycles PL1 to PLn, such that each of the selected memory cells has a threshold voltage corresponding to any of the multiple programming states P1, P2 and P3.

[0119] Each programming cycle in programming cycles PL1 to PLn may include a programming voltage application step (PGM Step) and a programming verification step (Verify Step). The programming voltage application step (PGM Step) applies a programming voltage to a selected word line coupled to the selected memory cell, and the programming verification step (Verify Step) determines whether the memory cell has been programmed by applying a verification voltage.

[0120] For example, when the first programming cycle PL1 is executed, a first programming voltage Vpgm1 can be applied, and then first to third verification voltages V_vfy1 to V_vfy3 can be applied sequentially to verify the programming state of the selected memory cell. Here, a memory cell whose target programming state is the first programming state P1 can be verified using the first verification voltage V_vfy1, a memory cell whose target programming state is the second programming state P2 can be verified using the second verification voltage V_vfy2, and a memory cell whose target programming state is the third programming state P3 can be verified using the third verification voltage V_vfy3.

[0121] Memory cells that have passed verification (i.e., passed verification) via the corresponding verification voltages V_vfy1 to V_vfy3 can be identified as having the target programming state and can then be programmed disabled in the second programming cycle PL2. In other words, a programming disable voltage can be applied to the bit line coupled to the memory cell that has passed verification in the second programming cycle PL2.

[0122] To program memory cells other than those in the programming-disabled memory cell in the second programming cycle PL2, a second programming voltage Vpgm2, which is one unit voltage (step voltage) ΔVpgm higher than the first programming voltage Vpgm1, can be applied to the selected word line. Thereafter, the verification operation can be performed in the same manner as the verification operation in the first programming cycle PL1. In one example, the term "verification passed" can indicate that the memory cell is read as an off-cell by the corresponding verification voltage.

[0123] As described above, when a memory device programs a multilevel cell (MLC) that stores two data bits, the memory device can individually verify the memory cell having the corresponding programming state as the target programming state by using the first to third verification voltages V_vfy1 to V_vfy3.

[0124] During the verification operation, a corresponding verification voltage can be applied to the selected word line, which is the word line coupled to the selected memory cell. Figure 2 The page buffer can determine whether a selected memory cell has been verified based on the current flowing through the bit lines coupled to the selected memory cell or the voltage applied to the bit lines.

[0125] In the case of incremental step pulse programming, the programming verification operation can be performed in each programming cycle, and therefore, the threshold voltage distribution of the memory cell can be formed with greater accuracy. The timing at which the programming disable voltage is applied to the bit line coupled to the memory cell can be determined based on the results of the programming verification operation.

[0126] Figure 8 It is a diagram illustrating multiple programming states categorized according to the reference voltage.

[0127] refer to Figure 8 The memory cell can be a three-level cell that stores three data bits each. However, the number of data bits stored in a memory cell is not limited to the number of data bits stored in a memory cell in this embodiment.

[0128] Each of the multiple memory cells can be programmed into any of the multiple programming states.

[0129] For example, a memory cell can be programmed to any of the first to seventh programming states, PV1 to PV7, based on a threshold voltage (Vth).

[0130] The memory cells can be programmed into multiple programming states, which can be classified into low programming state and high programming state according to the reference voltage.

[0131] For example, the first to third programming states PV1 to PV3, where the threshold voltage distribution is located to the left of the first reference voltage Vref1, can be set to the low programming state Low PV. The fourth to seventh programming states PV4 to PV7, where the threshold voltage distribution is located to the right of the first reference voltage Vref1, can be set to the high programming state High PV.

[0132] In one embodiment, the operating voltage required to read the first to third programming states PV1 to PV3 or to verify the programming state may be lower than or equal to the first reference voltage Vref1. The operating voltage required to read the fourth to seventh programming states PV4 to PV7 or to verify the programming state may be higher than the first reference voltage Vref1.

[0133] In one embodiment, the maximum value of the reference voltage may be a programming verification voltage corresponding to an intermediate programming state among a plurality of programming states. The minimum value of the reference voltage may be a programming verification voltage corresponding to the lowest programming state among a plurality of programming states. The initial value of the reference voltage may be set between the programming verification voltage corresponding to the lowest programming state and the programming verification voltage corresponding to the intermediate programming state.

[0134] The reference voltage can be updated and changed based on the degree of preservation degradation of the memory cell. For example, as the preservation degradation of the memory cell increases, the reference voltage can be changed from a first reference voltage Vref1 to a second reference voltage Vref2.

[0135] In this case, the first programming state PV1, where the threshold voltage distribution is located to the left of the second reference voltage Vref2, can be set to the low programming state Low PV'. The second to seventh programming states PV2 to PV7, where the threshold voltage distribution is located to the right of the second reference voltage Vref2, can be set to the high programming state High PV'.

[0136] In one embodiment, the operating voltage required to read the first programming state PV1 or verify the programming state may be lower than or equal to the second reference voltage Vref2. The operating voltage required to read the second to seventh programming states PV2 to PV7 or verify the programming state may be higher than the second reference voltage Vref2.

[0137] Figure 9 This is a diagram illustrating the distribution of threshold voltages based on the degree of retention degradation of memory cells.

[0138] refer to Figure 9 As time passes after programming multiple memory cells, the retention properties of these memory cells in storing trapped electrons may deteriorate.

[0139] The degradation of memory cell retention characteristics may differ in the High PV state compared to the Low PV state.

[0140] The gain characteristics of memory cells programmed in a low-PV state can dominate, and their threshold voltage distribution may be completely shifted to the right. The loss characteristics of memory cells programmed in a high-PV state can dominate, and their threshold voltage distribution may be completely shifted to the left.

[0141] Due to the preservation degradation of memory cells, the interval between the threshold voltage distributions of memory cells programmed to erase state E and low-programmability state Low PV can be reduced. That is, the read margin can be reduced.

[0142] Figure 10 This is a diagram illustrating the voltages applied to multiple word lines during memory operation according to one embodiment.

[0143] refer to Figure 10 Multiple word lines can include word lines WL1 to WLk from the first to the kth word line (where k is a natural number of 1 or greater). Figure 10In this context, the selected word line can be the nth word line WLn (where n is a natural number of 1 or greater). Among the unselected word lines, the target word lines adjacent to the selected word line can be the (n-1)th word line Wn-1 and the (n+1)th word line Wn+1. Among the unselected word lines, the remaining unselected word lines, excluding the target word lines, can be the first to the (n-2)th word lines WL1 to WLn-2 and the (n+2)th to the kth word lines WLn+2 to WLk.

[0144] Memory operations can be performed on memory cells coupled to multiple word lines, specifically on memory cells coupled to a selected word line. Memory operations can be read operations or program verification operations.

[0145] In one embodiment, different pass voltages can be applied to the target word line and the remaining unselected word lines based on whether the corresponding memory operation corresponds to a low programming state (Low PV) or a high programming state (High PV).

[0146] In memory operations corresponding to the Low PV programming state, the operating voltage Vop can be applied to the selected word line. A first pass voltage Vpass1 can be applied to the target word line. A second pass voltage Vpass2, having a lower level than the first pass voltage Vpass1, can be applied to the remaining unselected word lines.

[0147] In memory operations corresponding to the High PV programming state, the operating voltage Vop can be applied to the selected word line. The same second pass voltage Vpass2 can be applied to all unselected word lines.

[0148] Figure 11 This is a diagram illustrating the effective channel length, which varies with the magnitude of the through voltage applied to the target word line adjacent to the selected word line.

[0149] refer to Figure 11 The operating voltage Vop can be applied to the selected word line WLn. The voltage Vpass can be applied to the target word lines WLn-1 and WLn+1 adjacent to the selected word line.

[0150] When a high through voltage is applied to the target word line, the length of the effective channel can be shorter than when a low through voltage is applied. Since a shorter effective channel length promotes charge movement, a reduction in the threshold voltage of the memory cell is achieved.

[0151] Figure 12 This is a diagram illustrating the difference between margins in adjacent threshold voltage distributions based on the effective channel length.

[0152] refer to Figure 12 Due to preservation degradation, memory cells can have threshold voltage distributions corresponding to multiple states S1 and S2, respectively. The interval between the threshold voltage distribution corresponding to state S1 and the threshold voltage distribution corresponding to state S2 can be a margin1.

[0153] As referenced above Figure 11 As described, when a higher through voltage than that applied to the remaining unselected word lines is applied to a word line adjacent to the selected word line to which the operating voltage is applied, the length of the effective channel can be shortened. When the length of the effective channel is shortened, the effect of reading the memory cell can occur in a state where the threshold voltage distribution of the memory cell is reduced. In other words, when the same operating voltage is applied to the selected word line, memory operation can also be performed using a margin 2 between the threshold voltage distributions corresponding to states S1' and S2', which are different from states S1 and S2. That is, because the interval between the threshold voltage distributions increases, the reduction in the margin attributed to the retention degradation of the memory cell can be mitigated.

[0154] Figure 13A This is a timing diagram illustrating the operation of a memory device according to one embodiment.

[0155] refer to Figure 13A Multiple word lines can include selected word lines and unselected word lines.

[0156] During time period P1, the same second pass voltage Vpass2 can be applied to the selected word line WLn, the target word lines WLn-1 and WLn+1 adjacent to the selected word line, and the remaining unselected word lines (i.e., Other WLs). The reason for applying the same pass voltage to all word lines is to minimize disturbances attributable to voltage level differences between the pass voltages of the respective word lines. In other embodiments, the first pass voltage Vpass1, which will be applied during time period P2, can be applied to the target word line.

[0157] During the second time period P2, memory operations can be performed. The programming state in which the memory operation is performed can be a programming state Low PV in which the programming verification voltage is lower than the reference voltage. In other words, during the memory operation, a first operating voltage Vop1 having a level lower than or equal to the reference voltage can be applied to the selected word line. Simultaneously with the first operating voltage Vop1 applied to the selected word line, a first pass voltage Vpass1 can be applied to the target word line. A second pass voltage Vpass2 having a voltage lower than the first pass voltage Vpass1 can be applied to the remaining unselected word lines.

[0158] During period P3, memory operations can be performed. The programming state in which the memory operation is performed can be a High PV programming state where the programming verification voltage is higher than the reference voltage. In other words, during the memory operation, a second operating voltage Vop2, which has a level higher than the reference voltage, can be applied to the selected word line. While the second operating voltage Vop2 is applied to the selected word line, the same second pass voltage Vpass2 can be applied to the unselected word line.

[0159] Return to reference Figure 9 In the case of Low PV (low programming state), the gain characteristic can dominate, and therefore, as memory cell retention degradation progresses, the threshold voltage distribution of the memory cell can shift to the right. Therefore, as referenced above... Figures 11 to 12 As described, during memory operation, the memory device can apply a pass voltage higher than that applied to the remaining unselected word lines to a target word line adjacent to the selected word line, thereby shortening the length of the effective channel and increasing the margin between threshold voltage distributions, and thus mitigating the reduction in margin attributable to retention degradation.

[0160] In the case of High PV (High Programming Module), loss characteristics dominate, and therefore, as memory cell retention degradation progresses, the threshold voltage distribution can shift completely to the left. Thus, since the High Programming Module can be the opposite of the Low PV (Low Programming Module), the same pass voltage is applied to the target word line adjacent to the selected word line and the remaining unselected word lines, and therefore the reduction in margin due to retention degradation can be mitigated.

[0161] exist Figure 13A In this context, memory operations can be performed sequentially in the direction of increasing operating voltage. Therefore, as a memory operation progresses from time period P2 to time period P3, the operating voltage applied to the selected word line can increase from the first operating voltage Vop1 to the second operating voltage Vop2.

[0162] Figure 13B This is a timing diagram illustrating the operation of a memory device according to one embodiment.

[0163] refer to Figure 13B The time period P1' can be compared with the above references. Figure 13A The time period P1 is the same. Time period P2' can be the same as time period P3. Time period P3' can be the same as time period P2.

[0164] exist Figure 13BIn this context, memory operations can be performed in reverse order, in the direction of decreasing operating voltage. Therefore, as a memory operation progresses from time period P2' to time period P3', the operating voltage applied to the selected word line can decrease from the second operating voltage Vop2 to the first operating voltage Vop1.

[0165] Figure 14 This is a flowchart illustrating the operation of a memory device according to one embodiment.

[0166] refer to Figure 14 In step S1401, the memory device may apply an operating voltage to the selected word line. The operating voltage may be a read voltage or a program verification voltage.

[0167] At step S1403, when the operating voltage is lower than or equal to the reference voltage, the memory device may apply a first pass voltage to the unselected word line adjacent to the selected word line.

[0168] At step S1405, the memory device may apply a second through voltage having a level lower than the first through voltage to the unselected word lines, excluding the word lines adjacent to the selected word lines.

[0169] Figure 15 This is a flowchart illustrating the operation of a memory device according to one embodiment.

[0170] refer to Figure 15 In step S1501, the memory device may apply an operating voltage to the selected word line. The operating voltage may be a read voltage or a program verification voltage.

[0171] At step S1503, the memory device can determine whether the operating voltage is lower than or equal to the reference voltage. When it is determined that the operating voltage is lower than or equal to the reference voltage, the process proceeds to step S1505, and when it is determined that the operating voltage is higher than the reference voltage, the process proceeds to step S1509.

[0172] At step S1505, the memory device may apply a first pass voltage to the unselected word line and the word line adjacent to the selected word line.

[0173] At step S1507, the memory device may apply a second through voltage having a level lower than the first through voltage to the unselected word lines, excluding the word lines adjacent to the selected word lines.

[0174] At step S1509, the memory device may apply a second pass voltage of the same level to an unselected word line among a plurality of word lines.

[0175] According to this disclosure, a memory device and a method of operating the memory device are provided, wherein the read margin between threshold voltage distributions corresponding to the respective programming states is increased in the memory device.

Claims

1. A memory device, comprising: Multiple memory cells are coupled to multiple word lines; Peripheral circuitry is configured to perform memory operations on memory cells selected from the plurality of memory cells; as well as Control logic is configured to control the peripheral circuitry to: The operating voltage is applied to the plurality of word lines, and the selected word lines are coupled to the selected memory cells. Based on whether the operating voltage is lower than or equal to the reference voltage, a first pass voltage is applied to the unselected word line and the target word line adjacent to the selected word line. A second pass voltage is applied to the unselected word lines, excluding the target word line, wherein the second pass voltage has a lower level than the first pass voltage. The memory operation controller is configured to control the peripheral circuitry during memory operation to apply the second pass voltage to all the unselected word lines when the operating voltage is higher than the reference voltage.

2. The memory device of claim 1, wherein the control logic comprises: A memory operation table storage device is configured to store information relating to the operating voltage used in the memory operation and information relating to a plurality of pass voltages; as well as The memory operation controller is configured to control the peripheral circuitry to apply a first pass voltage to the target word line and a second pass voltage to the remaining unselected word lines when the operating voltage is lower than or equal to the reference voltage.

3. The memory device of claim 2, wherein the memory operation controller is configured to update the reference voltage based on the degree of retention degradation of the plurality of memory cells.

4. The memory device of claim 3, wherein as the degree of preservation degradation of the plurality of memory cells increases, the memory operation controller reduces the level of the reference voltage.

5. The memory device of claim 2, wherein as the retention degradation of the plurality of memory cells increases, the memory operation controller increases the voltage level difference between the first pass voltage and the second pass voltage.

6. The memory device of claim 2, wherein the reference voltage is a programming verification voltage corresponding to the lowest programming state among a plurality of programming states of the selected memory cell.

7. The memory device of claim 1, wherein the reference voltage is a programming verification voltage corresponding to an intermediate programming state among a plurality of programming states of the selected memory cell.

8. The memory device of claim 1, wherein the memory operation is a read operation or a program verification operation.

9. A method of operating a memory device, the memory device having a plurality of memory cells coupled to a plurality of word lines, the method comprising: An operating voltage is applied to a selected word line coupled to a memory cell selected from the plurality of memory cells; Determine whether the operating voltage is lower than or equal to the reference voltage; When the operating voltage is lower than or equal to the reference voltage, a first pass voltage is applied to the unselected word lines and the target word line adjacent to the selected word line, and a second pass voltage is applied to the unselected word lines and the remaining unselected word lines excluding the target word line, the second pass voltage having a lower level than the first pass voltage. When the operating voltage is higher than the reference voltage, the second pass voltage is applied to all of the unselected word lines among the plurality of word lines.

10. The method of claim 9, wherein the operating voltage is a read voltage or a programming verification voltage.

11. The method of claim 9, wherein applying the operating voltage to the selected word line comprises: The operating voltage is applied to the selected word line in the direction of increasing operating voltage.

12. The method of claim 9, wherein applying the operating voltage to the selected word line comprises: The operating voltage is applied to the selected word line in the direction of the decrease in operating voltage.

13. The method of claim 9, wherein the reference voltage is a programming verification voltage corresponding to the lowest programming state among a plurality of programming states of the selected memory cell.

14. The method of claim 9, wherein the reference voltage is a programming verification voltage corresponding to an intermediate programming state among a plurality of programming states of the selected memory cell.

15. The method of claim 9, further comprising: The reference voltage is updated based on the degree of preservation degradation of the plurality of memory cells.

16. The method of claim 15, wherein updating the reference voltage comprises: As the degree of preservation degradation of the plurality of memory cells increases, the level of the reference voltage decreases.

17. The method of claim 9, wherein the voltage level difference between the first through voltage and the second through voltage increases as the retention degradation of the plurality of memory cells increases.

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