Non-volatile memory and its read methods compared with NAND flash memory read methods

Abstract

A non-volatile memory includes: M word lines; and a controller. The controller is configured to: receive a read instruction; apply a read voltage to the Nth word line, where N is an integer between 3 and M-3; apply a first through voltage to the (N-1)th word line; apply a second through voltage to the (N-2)th word line; apply a third through voltage to the (N+1)th word line; apply a fourth through voltage to the (N+2)th word line; apply a fifth through voltage to the 1st to the (N-3)th word lines; apply a sixth through voltage to the (N+3)th to the Mth word lines; and sense the current of the memory cell corresponding to the Nth word line, wherein the first through voltage and the second through voltage are greater than the fifth through voltage, and the third through voltage and the fourth through voltage are greater than the sixth through voltage. A method for reading a non-volatile memory and a method for reading NAND flash memory are also provided.

Description

Technical Field

[0001] This disclosure relates to the field of memory technology, and in particular to a non-volatile memory and its reading method, as well as a reading method for NAND flash memory. Background Technology

[0002] NAND flash memory operates on a page-by-page basis during read or erase / write verification. A pass voltage is applied to the unselected word line to make the memory cell connected to the unselected word line conductive. A read voltage is applied to the selected word line. The read voltage is less than the pass voltage. Data is read by judging the voltage of the bit line or the current flowing through the bit line.

[0003] Because all the memory cells in a string of NAND flash memory are connected in series, the memory cells of the selected word line and the memory cells of the adjacent non-selected word lines will be coupled. For example, the read voltage applied to the gate of the selected word line WLN will reduce the voltage coupling of the adjacent non-selected word lines WLN-1 and WLN+1, which will affect the conduction of the memory cells on the non-selected word lines WLN-1 and WLN+1, increase the resistance, reduce the current of the bit line, and the memory cell storing 1 on the selected word line WLN will be read as 0.

[0004] Figure 1 This diagram illustrates the voltage application in an improved read operation in the prior art. A read voltage Vread is applied to the selected word line WLN. A higher pass voltage Vpass10 is applied to the unselected word lines WLN-1 and WLN+1 adjacent to the selected word line WLN. A pass voltage Vpass20 is applied to the other unselected word lines (word lines WL1 to WLN-2, word lines WLN+2 to WLM). The pass voltage Vpass10 is higher than the pass voltage Vpass20. The higher pass voltage Vpass10 ensures that the memory cells of the unselected word lines WLN-1 and WLN+1 are fully turned on, thus not affecting the read operation of the selected word line WLN. However, the higher pass voltage Vpass10 may cause a change in the threshold voltage of the memory cells of the unselected word lines WLN-1 and WLN+1, that is, it may cause stronger read disturbance to the data on the unselected word lines WLN-1 and WLN+1.

[0005] Therefore, it is necessary to propose solutions to the problems of existing technologies. Summary of the Invention

[0006] The purpose of this disclosure is to provide a non-volatile memory and its reading method, as well as a reading method for NAND flash memory, which can solve the reading interference problem caused by applying a higher pass voltage to the gate of the unselected word line in the prior art.

[0007] To address the aforementioned problems, this disclosure provides a non-volatile memory comprising: M word lines, where M is a positive integer; and a controller. The controller is configured to perform: receiving a read instruction; applying a read voltage to the Nth word line, where N is an integer between 3 and M-3; applying a first through voltage to the (N-1)th word line; applying a second through voltage to the (N-2)th word line; applying a third through voltage to the (N+1)th word line; applying a fourth through voltage to the (N+2)th word line; applying a fifth through voltage to the 1st to the (N-3)th word lines; applying a sixth through voltage to the (N+3)th to the Mth word lines; and sensing the current of the memory cell corresponding to the Nth word line, wherein the first through voltage and the second through voltage are greater than the fifth through voltage, and the third through voltage and the fourth through voltage are greater than the sixth through voltage.

[0008] In one embodiment, the first through voltage is equal to the third through voltage, the second through voltage is equal to the fourth through voltage, and the fifth through voltage is equal to the sixth through voltage.

[0009] In one embodiment, the first through voltage, the second through voltage, the third through voltage, and the fourth through voltage are all greater than the fifth through voltage.

[0010] In one embodiment, the first through voltage, the second through voltage, the third through voltage, and the fourth through voltage are all greater than the sixth through voltage.

[0011] In one embodiment, the first through voltage is greater than or equal to the second through voltage, the third through voltage is greater than or equal to the fourth through voltage, and the third through voltage is greater than or equal to the first through voltage.

[0012] To address the aforementioned problems, this disclosure provides a method for reading a non-volatile memory, wherein the non-volatile memory includes M word lines, where M is a positive integer. The method for reading the non-volatile memory includes: receiving a read instruction; applying a read voltage to the Nth word line, where N is an integer between 3 and M-3; applying a first through voltage to the (N-1)th word line; applying a second through voltage to the (N-2)th word line; applying a third through voltage to the (N+1)th word line; applying a fourth through voltage to the (N+2)th word line; applying a fifth through voltage to the 1st to the (N-3)th word lines; applying a sixth through voltage to the (N+3)th to the Mth word lines; and sensing the current of the memory cell corresponding to the Nth word line, wherein the first through voltage and the second through voltage are greater than the fifth through voltage, and the third through voltage and the fourth through voltage are greater than the sixth through voltage.

[0013] In one embodiment, the first through voltage is equal to the third through voltage, the second through voltage is equal to the fourth through voltage, and the fifth through voltage is equal to the sixth through voltage.

[0014] In one embodiment, the first through voltage, the second through voltage, the third through voltage, and the fourth through voltage are all greater than the fifth through voltage.

[0015] In one embodiment, the first through voltage, the second through voltage, the third through voltage, and the fourth through voltage are all greater than the sixth through voltage.

[0016] In one embodiment, the first through voltage is greater than or equal to the second through voltage, the third through voltage is greater than or equal to the fourth through voltage, and the third through voltage is greater than or equal to the first through voltage.

[0017] To address the aforementioned issues, this disclosure provides a method for reading NAND flash memory, comprising: applying a read voltage to a selected word line; and applying a pass voltage to a non-selected word line, wherein the non-selected word line includes a first non-selected word line directly adjacent to the selected word line, a second non-selected word line subsequently adjacent to the selected word line, and a third non-selected word line, wherein the pass voltage applied to the first and second non-selected word lines is greater than the pass voltage applied to the third non-selected word line, and the pass voltage applied to the first non-selected word line at the source end is greater than or applied to the first non-selected word line at the drain end.

[0018] Compared to existing technologies, the non-volatile memory and its reading method disclosed herein, as well as the reading method of NAND flash memory, divide the unselected word lines into at least three groups, and apply different through voltages to each group. By controlling the voltage relationship between the at least three groups of unselected word lines, the reading interference to the data of word lines directly adjacent to the selected word lines is reduced while ensuring the reading accuracy of the selected word lines.

[0019] To make the above-disclosed content clearer and easier to understand, preferred embodiments are described below in detail with reference to the accompanying drawings: Attached Figure Description

[0020] Figure 1 This diagram illustrates the process of reading a string and applying voltage in the prior art.

[0021] Figure 2 This diagram shows a non-volatile memory and a host according to an embodiment of the present disclosure.

[0022] Figure 3 show Figure 2A schematic diagram of a block of a memory array.

[0023] Figure 4 This diagram illustrates a read operation and applied voltage according to an embodiment of the present disclosure.

[0024] Figure 5 This diagram shows a flowchart of a method for reading a non-volatile memory according to an embodiment of this disclosure.

[0025] Figure 6 This diagram shows a flowchart of a method for reading NAND flash memory according to an embodiment of the present disclosure. Detailed Implementation

[0026] The following description of the embodiments is with reference to the accompanying drawings, which illustrate specific embodiments in which this disclosure can be implemented.

[0027] Please see Figure 2 , Figure 2 A schematic diagram showing a non-volatile memory 10 and a host 20 according to an embodiment of the present disclosure is displayed. Figure 3 show Figure 2 A schematic diagram of a block 1020 of the memory array 102.

[0028] The non-volatile memory 10 is electrically coupled to the host 20. The non-volatile memory 10 can perform bidirectional data communication with the host 20. The communication standard between the non-volatile memory 10 and the host 20 is, for example, the Serial Advanced Technology Attachment (SATA) standard, the Parallel Advanced Technology Attachment (PATA) standard, the Universal Serial Bus (USB) standard, the Secure Digital (SD) interface standard, the MultiMediaCard (MMC) interface standard, the Serial Peripheral Interface (SPI) standard, etc.

[0029] The non-volatile memory 10 is, for example, a USB flash drive, a portable hard drive, or a memory card. The host device 20 is a user's device, such as a mobile phone, tablet, laptop, or camera. The host device 20 can also be a microcontroller (MCU), and the non-volatile memory 10 stores code that can run on the host device 20.

[0030] The non-volatile memory 10 includes a memory array 102, a controller 104, an address circuit 106, a write circuit 108, an input / output circuit 110, a sensing circuit 112, a page buffer 114, and a charge pump 116. The non-volatile memory 10 is, for example, NAND flash memory.

[0031] The memory array 102 of the non-volatile memory 10 includes multiple such... Figure 3 Block 1020, as shown, includes M word lines WL1-WLM, P bit lines BL1-BLP, and multiple storage cells SC. M and P are positive integers. The multiple storage cells SC are located at the intersections of the M word lines WL1-WLM and the P bit lines BL1-BLP.

[0032] A memory cell (SC) is, for example, a transistor with a floating gate or charge trapping layer. A memory cell (SC) can be a single-level cell (SLC) storing 1 bit of data, a multi-level cell (MLC) storing 2 bits of data, a three-level cell (TLC) storing 3 bits of data, or a quad-level cell (QLC) storing 4 bits of data. Taking an SLC memory cell as an example, the memory cell (SC) has a programmed state and an unprogrammed state (also called an erased state). A memory cell (SC) in the programmed state has a higher threshold voltage and stores 0 data; a memory cell (SC) in the unprogrammed state has a lower threshold voltage and stores 1 data.

[0033] Memory cells SC are addressed via word lines and bit lines. Each row of memory cells is connected to the same word line; specifically, the control gate of each row of memory cells SC is connected to the same word line. The source and drain of adjacent memory cells SC in each column are connected, forming a memory cell string. The drain of the first memory cell in each string is connected to each bit line BL1-BLP via a first select transistor ST1, and the source of the last memory cell in each string is connected to the common source line CSL via a second select transistor ST2. The side of the memory cell string closest to the first select transistor ST1 is called the source side, and the side of the memory cell string closest to the second select transistor ST2 is called the drain side. Each row of memory cells SC forms a page. The M pages of block 1020 are connected to word lines WL1-WLM, and each page includes P memory cells SC, which are connected to bit lines BL1-BLP. The gate of the first select transistor ST1 is connected to the drain select signal line SGD, and the gate of the second select transistor ST2 is connected to the source select signal line SGS. More specifically, all memory cells SC connected to the same word line together form a page, and all pages connected to word lines WL1-WLM together form a block 1020.

[0034] The controller 104 is used to decode the instructions transmitted by the host 20 through the control bus 118, execute the instructions of the host 20, and / or access the memory array 102. The instructions are used to perform operations on the memory array 102, and the operations include at least read operations, write operations, erase operations, and other operations.

[0035] The address circuit 106 is used to latch the address signal from the input / output circuit 110 and decode the address signal to access the memory array 102. The host 20 transmits the address signal to the input / output circuit 110 via the data bus 120.

[0036] The write circuit 108 is used to perform write operations. The sensing circuit 112 is connected to the bit line BL1-BLP and is used to perform read operations.

[0037] The page buffer 114 is used to store the data of a page that has been read and the data to be written.

[0038] The charge pump 116 is used to provide the word line voltage, bit line voltage, and substrate voltage that need to be applied to each word line WL1-WLM, each bit line BL1-BLP, and during write, read, and erase operations.

[0039] For NAND flash memory, read operations are performed on a page-by-page basis. During a read operation, a read voltage is applied to the selected word line, and a pass voltage is applied to the unselected word lines; the read voltage is less than the pass voltage. See also... Figure 4 , Figure 4 This diagram illustrates a read operation and applied voltage according to an embodiment of the present disclosure.

[0040] To avoid stronger read interference caused by applying higher through voltages to unselected word lines, the controller 104 disclosed herein receives a read command and performs a read operation on the Nth word line WLN. During the read operation, the controller 104 performs the following: applying a read voltage Vread to word line WLN, where N is an integer between 3 and M-3; applying a first through voltage Vpass1 to word line WLN-1 adjacent to word line WLN; applying a second through voltage Vpass2 to word line WLN-2 adjacent to word line WLN; applying a third through voltage Vpass3 to word line WLN+1 adjacent to word line WLN; applying a fourth through voltage Vpass4 to word line WLN+2 next to word line WLN; applying a fifth through voltage Vpass5 to word lines WL1 to WLN-3; applying a sixth through voltage to word line WLN+3 to word line WLM; and sensing the current on bit lines BL1-BLP. The data stored in the memory cell SC corresponding to word line WLN is determined based on the current on bit lines BL1-BLP. Word lines WL1 to WLN-1 are source-side word lines relative to word line WLN, and word lines WLN+1 to WLNM are drain-side word lines relative to word line WLN. For example, if word line WLN is selected and has two adjacent word lines, word line WLN-1 is the source-side adjacent word line, and word line WLN+1 is the drain-side adjacent word line. The first pass voltage Vpass1 and the second pass voltage Vpass2 are greater than the fifth pass voltage Vpass5, and the third pass voltage Vpass3 and the fourth pass voltage Vpass4 are greater than the sixth pass voltage Vpass6.

[0041] In the prior art, a higher pass voltage is applied to the unselected word lines WLN-1 and WLN+1, thereby reducing the impact of the lower read voltage of the selected word line WLN on the conduction of the memory cells of word lines WLN-1 and WLN+1. However, this method will cause stronger read interference to the data of the unselected word lines WLN-1 and WLN+1.

[0042] To solve the above-mentioned technical problems, in this disclosure, the pass voltages Vpass1 and Vpass3 applied to the unselected word lines WLN-1 and WLN+1 adjacent to the selected word line WLN are compared with... Figure 1The pass voltage Vpass10 on the unselected word lines WLN-1 and WLN+1 in the prior art is lower, and the pass voltages Vpass2 and Vpass4 applied on the unselected word lines WLN-2 and WLN+2, which are adjacent to the selected word line WLN, are lower than those applied to the selected word line WLN. Figure 1 In the prior art shown, the pass voltage Vpass20 on the unselected word lines WLN-2 and WLN+2 is higher than the pass voltage Vpass10 on the unselected word lines WLN-1 and WLN+1. Reducing the pass voltage on adjacent unselected word lines WLN-1 and WLN+1 can reduce read interference. Increasing the pass voltage on the next adjacent unselected word lines WLN-2 and WLN+2 can reduce and improve the conduction of the memory cells on adjacent unselected word lines WLN-1 and WLN+1. This reduces read interference and improves the accuracy of read operations. Specifically, the first pass voltage Vpass1 and the second pass voltage Vpass2 are greater than the fifth pass voltage Vpass5, and the third pass voltage Vpass3 and the fourth pass voltage Vpass4 are greater than the sixth pass voltage Vpass6. Applying a higher pass voltage to the adjacent and next adjacent word lines of the selected word line WLN than to other non-selected word lines can reduce the impact of the read voltage applied to the selected word line WLN on the conduction of the memory cells of the adjacent and next adjacent word lines. This achieves the goal of reducing read interference to word lines WLN-1 and WLN+1 while ensuring the read accuracy of the selected word line WLN.

[0043] More specifically, the non-volatile memory 10 disclosed herein not only controls the first pass voltage Vpass1 of the (N-1)th word line WLN-1 and the third pass voltage Vpass3 of the (N+1)th word line WLN+1, but also controls the relationship between the first pass voltage Vpass1 of the (N-1)th word line WLN-1, the second pass voltage Vpass2 of the (N-2)th word line WLN-2, and the fifth pass voltage Vpass5 of the first word line WL1 to the (N-3)th word line WLN-3. The voltage relationship is controlled, and the voltage relationship between the third pass voltage Vpass3 of the (N+1)th word line WLN+1, the fourth pass voltage Vpass4 of the (N+2)th word line WLN+2, and the sixth pass voltage Vpass6 of the (N+3)th word line WLN+3 to the Mth word line WLM is controlled. This achieves the goal of reducing the reading interference to the data of the (N-1)th word line WLN-1 and the (N+1)th word line WLN+1 while ensuring the reading accuracy of the Nth word line WLN.

[0044] In one embodiment, the first through voltage Vpass1 is equal to the third through voltage Vpass3, the second through voltage Vpass2 is equal to the fourth through voltage Vpass4, and the fifth through voltage Vpass5 is equal to the sixth through voltage Vpass6.

[0045] In one embodiment, the first through voltage Vpass1, the second through voltage Vpass2, the third through voltage Vpass3, and the fourth through voltage Vpass4 are all greater than the fifth through voltage Vpass5.

[0046] In one embodiment, the first through voltage Vpass1, the second through voltage Vpass2, the third through voltage Vpass3, and the fourth through voltage Vpass4 are all greater than the sixth through voltage Vpass6.

[0047] In one embodiment, the first through voltage Vpass1 is greater than or equal to the second through voltage Vpass2, the third through voltage Vpass3 is greater than or equal to the fourth through voltage Vpass4, and the third through voltage Vpass3 is greater than or equal to the first through voltage Vpass1. That is, the through voltage of the adjacent unselected word line on the drain side is greater than the through voltage of the adjacent unselected word line on the source side.

[0048] In the above embodiments, the voltage magnitudes of the first pass voltage, the second pass voltage Vpass2, the third pass voltage Vpass3, the fourth pass voltage Vpass4, the fifth pass voltage Vpass5, and the sixth pass voltage Vpass6 are obtained through experiments and have a better technical effect in reducing reading interference on the (N-1)th word line WLN-1 and the (N+1)th word line WLN+1.

[0049] Please see Figure 5 , Figure 5 This diagram shows a flowchart of a method for reading a non-volatile memory according to an embodiment of this disclosure.

[0050] The non-volatile memory includes M word lines, where M is a positive integer, and the method for reading the non-volatile memory includes the following operations.

[0051] During S500 operation, a read command is received.

[0052] In operation S502, a read voltage is applied to the Nth word line, a first pass voltage is applied to the (N-1)th word line, a second pass voltage is applied to the (N-2)th word line, a third pass voltage is applied to the (N+1)th word line, a fourth pass voltage is applied to the (N+2)th word line, a fifth pass voltage is applied to word lines 1 to (N-3)th, and a sixth pass voltage is applied to word lines (N+3) to Mth. The first and second pass voltages are greater than the fifth pass voltage, and the third and fourth pass voltages are greater than the sixth pass voltage. N is an integer between 3 and M-3.

[0053] In one embodiment, the first through voltage is equal to the third through voltage, the second through voltage is equal to the fourth through voltage, and the fifth through voltage is equal to the sixth through voltage.

[0054] In one embodiment, the first through voltage, the second through voltage, the third through voltage, and the fourth through voltage are all greater than the fifth through voltage.

[0055] In one embodiment, the first through voltage, the second through voltage, the third through voltage, and the fourth through voltage are all greater than the sixth through voltage.

[0056] In one embodiment, the first through voltage is greater than or equal to the second through voltage, the third through voltage is greater than or equal to the fourth through voltage, and the third through voltage is greater than or equal to the first through voltage.

[0057] In the above embodiments, the voltage magnitude relationship of the first through voltage, the second through voltage, the third through voltage, the fourth through voltage, the fifth through voltage, and the sixth through voltage is obtained through experiments and has a better technical effect in reducing the reading interference of the (N-1)th word line WLN-1 and the (N+1)th word line WLN+1.

[0058] In operation S504, the current of the memory cell corresponding to the Nth word line is sensed.

[0059] Please refer to Figure 4 and Figure 6 , Figure 6 This diagram shows a flowchart of a method for reading NAND flash memory according to an embodiment of the present disclosure.

[0060] The method for reading the non-volatile memory includes the following operations.

[0061] In operation S600, a read voltage is applied to the selected word line.

[0062] At Figure 4 In this context, the selected character line is the Nth character line.

[0063] In operation S602, a voltage is applied to the unselected word lines. The unselected word lines include a first unselected word line directly adjacent to the selected word line, a second unselected word line next to the selected word line, and a third unselected word line (i.e., other unselected word lines besides the first and second unselected word lines). The voltage applied to the first and second unselected word lines is greater than the voltage applied to the third unselected word line. The first unselected word line includes a source-side first unselected word line and a drain-side first unselected word line. The voltage applied to the source-side first unselected word line is greater than or equal to the voltage applied to the drain-side first unselected word line.

[0064] At Figure 4 In this context, the first unselected character line directly adjacent to the selected character line includes the (N-1)th character line and the (N+1)th character line; the second unselected character line next to the selected character line includes the (N-2)th character line and the (N+2)th character line; and the third unselected character line includes the 1st character line to the (N-3)th character line and the (N+3)th character line to the Mth character line. Figure 4 In this context, the first unselected word line on the source side (i.e., the source select signal line SGS side) is the (N-1)th word line WLN-1, and the first unselected word line on the drain side (i.e., the drain select signal line SGD side) is the (N+1)th word line WLN+1. More specifically, the pass voltage applied to the (N-1)th word line WLN-1 is greater than or equal to the pass voltage applied to the (N+1)th word line WLN+1.

[0065] It should be noted that the non-volatile memory and its reading method disclosed herein, as well as the reading method for NAND flash memory, can be used not only for reading operations, but also for erasure verification and programming verification, etc.

[0066] In the non-volatile memory and its reading method disclosed herein, and the reading method of NAND flash memory, the unselected word lines are divided into at least three groups, and a different through voltage is applied to each group. By controlling the voltage relationship between the at least three groups of unselected word lines, the reading interference to the data of word lines directly adjacent to the selected word lines is reduced while ensuring the reading accuracy of the selected word lines.

[0067] In summary, although the present disclosure has been presented above with reference to preferred embodiments, the above preferred embodiments are not intended to limit the present disclosure. Those skilled in the art can make various modifications and refinements without departing from the spirit and scope of the present disclosure. Therefore, the scope of protection of the present disclosure shall be determined by the scope defined in the claims.

Claims

1. A non-volatile memory, characterized in that, include: M word lines, where M is a positive integer; as well as The controller is used to perform: Receive read command; Apply a read voltage to the Nth word line, where N is an integer between 3 and M-3; Apply the first pass voltage to the (N-1)th word line; Apply a second pass voltage to the (N-2)th word line; Apply a third pass voltage to the (N+1)th word line; Apply a fourth pass voltage to the (N+2)th word line; Apply the fifth pass voltage to word lines 1 through N-3; Apply the sixth pass voltage to word lines N+3 through M; as well as Sensing the current of the memory cell corresponding to the Nth word line. Wherein, the first and second pass voltages are greater than the fifth pass voltage, the third and fourth pass voltages are greater than the sixth pass voltage, and the pass voltage applied to the (N-1)th word line is greater than or equal to the pass voltage applied to the (N+1)th word line; the read voltage is less than the first, second, third, fourth, fifth, and sixth pass voltages.

2. The non-volatile memory according to claim 1, characterized in that, The first through voltage, the second through voltage, the third through voltage, and the fourth through voltage are all greater than the fifth through voltage.

3. The non-volatile memory according to claim 1, characterized in that, The first through voltage, the second through voltage, the third through voltage, and the fourth through voltage are all greater than the sixth through voltage.

4. The non-volatile memory according to claim 1, characterized in that, The first through voltage is greater than or equal to the second through voltage, the third through voltage is greater than or equal to the fourth through voltage, and the third through voltage is greater than or equal to the first through voltage.

5. A method for reading a non-volatile memory, wherein the non-volatile memory comprises M word lines, where M is a positive integer, characterized in that, The method for reading the non-volatile memory includes: Receive read command; Apply a read voltage to the Nth word line, where N is an integer between 3 and M-3; Apply the first pass voltage to the (N-1)th word line; Apply a second pass voltage to the (N-2)th word line; Apply a third pass voltage to the (N+1)th word line; Apply a fourth pass voltage to the (N+2)th word line; Apply the fifth pass voltage to word lines 1 through N-3; Apply a sixth pass voltage to word lines N+3 through M; and Sensing the current of the memory cell corresponding to the Nth word line. Wherein, the first and second pass voltages are greater than the fifth pass voltage, the third and fourth pass voltages are greater than the sixth pass voltage, and the pass voltage applied to the (N-1)th word line is greater than or equal to the pass voltage applied to the (N+1)th word line; the read voltage is less than the first, second, third, fourth, fifth, and sixth pass voltages.

6. The method for reading non-volatile memory according to claim 5, characterized in that, The first through voltage, the second through voltage, the third through voltage, and the fourth through voltage are all greater than the fifth through voltage.

7. The method for reading non-volatile memory according to claim 5, characterized in that, The first through voltage, the second through voltage, the third through voltage, and the fourth through voltage are all greater than the sixth through voltage.

8. The method for reading non-volatile memory according to claim 5, characterized in that, The first through voltage is greater than or equal to the second through voltage, the third through voltage is greater than or equal to the fourth through voltage, and the third through voltage is greater than or equal to the first through voltage.

9. A method for reading NAND flash memory, characterized in that, The method for reading the NAND flash memory includes: Apply read voltage to the selected word line; and Apply voltage to the unselected word line. Wherein, the read voltage is less than the pass voltage; the unselected word line includes a first unselected word line directly adjacent to the selected word line, a second unselected word line next to the selected word line, and a third unselected word line, wherein the pass voltage applied to the first unselected word line and the second unselected word line is greater than the pass voltage applied to the third unselected word line, and the pass voltage applied to the first unselected word line on the source side is greater than or applied to the first unselected word line on the drain side.

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