Memory device and operating method of the memory device

Abstract

The present disclosure relates to a memory device and a method of operating the memory device. A method for operating a memory device for performing a program operation of programming data in selected memory cells among a plurality of memory cells is provided. The method includes applying a program voltage to the selected memory cells, verifying a program state of a memory cell among the selected memory cells programmed to any one of a plurality of program states distinguished based on a plurality of threshold voltages, and verifying an erase state of a memory cell among the selected memory cells programmed to an erase state.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2021-0064410, filed on May 18, 2021, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] This disclosure relates generally to electronic devices, and more specifically to memory devices and methods of operating such memory devices. Background Technology

[0004] A storage device is a device that stores data under the control of a host device, such as a computer or smartphone. Storage devices can include memory devices for storing data and memory controllers for controlling the memory devices. Memory devices are classified as volatile memory devices and non-volatile memory devices.

[0005] Volatile memory devices are memory devices that store data only while power is available and lose the stored data when power is interrupted. Volatile memory devices can include static random access memory (SRAM), dynamic random access memory (DRAM), etc.

[0006] Non-volatile memory devices are memory devices whose data is not lost even when the power supply is interrupted. Non-volatile memory devices can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable ROM (EEROM), flash memory, etc. Summary of the Invention

[0007] According to one aspect of this disclosure, a method is provided for operating a memory device to perform a programming operation that programs data into selected memory cells among a plurality of memory cells. The method may include: applying a programming voltage to the selected memory cells; verifying the programming state of a memory cell among the selected memory cells that is programmed to any one of a plurality of programming states, the plurality of programming states being distinguished based on a plurality of threshold voltages; and verifying the erasure state of a memory cell among the selected memory cells that is programmed to an erase state.

[0008] According to another aspect of this disclosure, a method is provided for operating a memory device to perform a programming operation that programs data into selected memory cells among a plurality of memory cells. The method may include: executing a plurality of programming cycles, the plurality of programming cycles including a programming voltage application operation that applies a programming voltage to the selected memory cells, and a verification operation that verifies at least one of a programming state and an erase state of the selected memory cells; in the verification operation included in at least one programming cycle corresponding to a specific programming state among the plurality of programming cycles, verifying the programming state of a memory cell among the selected memory cells programmed to a specific programming state; and in the verification operation included in at least one programming cycle corresponding to a specific programming state, verifying the erase state of a memory cell among the selected memory cells programmed to an erase state.

[0009] According to another aspect of this disclosure, a memory device may be provided, comprising: a plurality of memory cells; peripheral circuitry configured to execute a plurality of programming cycles, the plurality of programming cycles including the programming voltage application operation of applying a programming voltage to selected memory cells among the plurality of memory cells and the verification operation of verifying the programming state of the selected memory cells; and a programming operation controller configured to control the peripheral circuitry to program data in the selected memory cells according to the plurality of programming cycles, wherein the programming operation controller controls the peripheral circuitry to verify, in the verification operation, the programming state of a memory cell among the selected memory cells programmed to any one of a plurality of programming states, and to verify the erase state of a memory cell among the selected memory cells programmed to an erase state, the plurality of programming states being distinguished based on a plurality of threshold voltages. Attached Figure Description

[0010] Examples of embodiments will now be described below with reference to the accompanying drawings; however, they may be embodied in different forms and should not be construed as being limited to the embodiments set forth herein.

[0011] In the accompanying drawings, dimensions may be exaggerated for clarity. It will be understood that when an element is referred to as being "between" two elements, it can be the only element between those two elements, or there may be one or more intermediate elements. The same reference numerals always refer to the same element.

[0012] Figure 1 This is a diagram illustrating a storage device according to an embodiment of the present disclosure.

[0013] Figure 2 It is a diagram. Figure 1 A diagram of the memory device shown.

[0014] Figure 3It is a diagram. Figure 2 A diagram of one embodiment of the memory cell array shown.

[0015] Figure 4 It is a diagram. Figure 3 The circuit diagram of any one of the memory blocks shown.

[0016] Figure 5 It is a diagram. Figure 3 A circuit diagram of another embodiment of one of the memory blocks shown.

[0017] Figure 6 It is a diagram. Figure 2 A diagram illustrating the programming operations of the memory device.

[0018] Figure 7 This is a diagram illustrating the threshold voltage distribution of a single-stage unit.

[0019] Figure 8 This is a diagram illustrating the threshold voltage distribution of a multi-level unit.

[0020] Figure 9 This is a diagram illustrating the threshold voltage distribution of the three-level unit.

[0021] Figure 10 This is a diagram illustrating an example of the operation of a memory device according to an embodiment of the present disclosure.

[0022] Figure 11 This is a diagram illustrating another example of the operation of a memory device according to an embodiment of the present disclosure.

[0023] Figure 12 This is a diagram illustrating yet another example of the operation of a memory device according to an embodiment of the present disclosure.

[0024] Figure 13 This is a diagram illustrating yet another example of the operation of a memory device according to an embodiment of the present disclosure.

[0025] Figure 14 This is a flowchart illustrating an operation method of a memory device according to an embodiment of the present disclosure.

[0026] Figure 15 This is a flowchart illustrating an operation method of a memory device according to an additional embodiment of the present disclosure.

[0027] Figure 16 This is a flowchart illustrating an operation method of a memory device according to an embodiment of the present disclosure.

[0028] Figure 17 This is a flowchart illustrating an operation method of a memory device according to an embodiment of the present disclosure.

[0029] Figure 18 It is a diagram. Figure 1 The diagram shows the memory controller.

[0030] Figure 19 This is a block diagram illustrating a memory card system according to an embodiment of the present disclosure, wherein a storage device is applied to the memory card system.

[0031] Figure 20 This is a block diagram illustrating a solid-state drive (SSD) system according to an embodiment of the present disclosure, wherein a storage device is applied to the SSD system.

[0032] Figure 21 This is a block diagram illustrating a user system according to an embodiment of the present disclosure, wherein a storage device is applied to the user system. Detailed Implementation

[0033] The specific structural or functional descriptions disclosed herein are merely illustrative and are intended to describe embodiments based on the concepts of this disclosure. Embodiments based on the concepts of this disclosure may be implemented in various forms and should not be construed as limited to the embodiments set forth herein.

[0034] The embodiments provide a memory device capable of preventing read failures caused by memory cells in an erased state, and a method of operating the memory device.

[0035] Figure 1 This is a diagram illustrating a storage device according to an embodiment of the present disclosure.

[0036] refer to Figure 1 Storage device 50 may include memory device 100 and memory controller 200 for controlling the operation of memory device 100. Storage device 50 may be a device for storing data under the control of host 300, such as a mobile phone, smartphone, MP3 player, laptop computer, desktop computer, game console, TV, tablet PC, or in-vehicle infotainment system.

[0037] Depending on the host interface used for communication with host 300, storage device 50 can be manufactured as any of various types of storage devices. For example, storage device 50 can be implemented using any of a wide variety of storage devices, such as solid-state drives (SSDs), multimedia cards (MMCs), embedded MMCs (eMMCs), reduced-size MMCs (RS-MMCs), micro-MMCs (micro-MMCs), secure digital cards (SDs), mini SD cards, micro SD cards, universal serial bus (USB) storage devices, universal flash storage (UFS) devices, compact flash (CF) cards, smart media cards (SMCs), memory sticks, etc.

[0038] Storage device 50 can be manufactured in any of a variety of package types. For example, storage device 50 can be manufactured in any of a variety of package types, such as POP, SIP, SOC, MCP, COB, WFP, and WSP.

[0039] The memory device 100 can store data. The memory device 100 can operate under the control of the memory controller 200. The memory device 100 may include a memory cell array (not shown) that includes a plurality of memory cells for storing data.

[0040] Each memory cell in the memory unit can be configured as any of the following: a single-level cell (SLC) storing one data bit, a multi-level cell (MLC) storing two data bits, a three-level cell (TLC) storing three data bits, and a four-level cell (QLC) storing four data bits.

[0041] A memory cell array (not shown) may include multiple memory blocks. Each memory block may include multiple memory cells. A memory block may include multiple pages. In one embodiment, a page may be a unit for storing data in or retrieving data stored in memory device 100. A memory block may be a unit for erasing data.

[0042] In one embodiment, the memory device 100 may be Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM), Low Power Double Data Rate 4 (LPDDR4) SDRAM, Graphics Double Data Rate (GDDR) SRAM, Low Power DDR (LPDDR), Rambus Dynamic Random Access Memory (RDRAM), NAND flash memory, Vertical NAND flash memory, NOR flash memory, Resistive Random Access Memory (RRAM), Phase Change Random Access Memory (PRAM), Magnetoresistive Random Access Memory (MRAM), Ferroelectric Random Access Memory (FRAM), Spin-Torque Random Access Memory (STT-RAM), etc. In this specification, for ease of description, it is assumed and described that the memory device 100 is a NAND flash memory.

[0043] Memory device 100 can receive commands CMD and addresses ADDR from memory controller 200 and access the region selected by address ADDR in the memory cell array. Memory device 100 can perform operations indicated by command CMD on the region selected by address ADDR. For example, memory device 100 can perform write operations (programming operations), read operations, and erase operations. In a programming operation, memory device 100 can program data into the region selected by address ADDR. In a read operation, memory device 100 can read data from the region selected by address ADDR. In an erase operation, memory device 100 can erase data stored in the region selected by address ADDR.

[0044] At the same time, Figure 1 The illustration shows a storage device 50 including a memory device 100. However, in some embodiments, the storage device 50 may include multiple memory devices.

[0045] The memory controller 200 can control the overall operation of the storage device 50.

[0046] When power is applied to storage device 50, memory controller 200 can execute firmware (FW). When storage device 100 is a flash memory device, FW may include: a host interface layer (HIL) for controlling communication with host 300, a flash translation layer (FTL) for controlling communication between host and storage device 100, and a flash interface layer (FIL) for controlling communication with storage device 100.

[0047] In one embodiment, the memory controller 200 may receive data and a logical block address (LBA) from the host 300 and translate the LBA into a physical block address (PBA), whereby the PBA represents the address of a memory cell included in the memory device 100 in which data is to be stored. In this specification, LBA and "logic address" or "logical address" may be used with the same meaning. In this specification, PBA and "physical address" may be used with the same meaning.

[0048] The memory controller 200 can control the memory device 100 to perform programming operations, read operations, erase operations, etc., in response to requests from the host 300. During programming operations, the memory controller 200 can provide programming commands, PBAs, and data to the memory device 100. During read operations, the memory controller 200 can provide read commands and PBAs to the memory device 100. During erase operations, the memory controller 200 can provide erase commands and PBAs to the memory device 100.

[0049] In one embodiment, the memory controller 200 can be connected to the memory device 100 via a channel. For example, the memory controller 200 can provide commands and addresses to the memory device via the channel to control the memory device 100 to perform programming operations, read operations, erase operations, etc.

[0050] In one embodiment, the memory controller 200 can autonomously generate commands, addresses, and data regardless of any requests from the host 300, and transmit these commands, addresses, and data to the memory device 100. For example, the memory controller 200 can provide commands, addresses, and data to the memory device 100 for performing read and programming operations in conjunction with wear leveling, read recycling, garbage collection, etc.

[0051] In one embodiment, the memory controller 200 can control at least two memory devices 100. The memory controller 200 can control the memory devices according to an interleaving scheme to improve operational performance. The interleaving scheme can be a scheme for overlapping operational control of at least two memory devices 100.

[0052] The host 300 can communicate with the storage device 50 using at least one of various communication methods, such as Universal Serial Bus (USB), Serial AT Accessory (SATA), High Speed ​​Chip Interconnect (HSIC), Small Computer System Interface (SCSI), FireWire, Peripheral Component Interconnect (PCI), PCIe, Non-Volatile Memory Fast (NVMe), Universal Flash Storage (UFS), Secure Digital (SD), Multimedia Card (MMC), Embedded MMC (eMMC), Dual In-line Memory Module (DIMM), Registered DIMM (RDIMM), and Load-Away DIMM (LRDIMM).

[0053] Figure 2 It is a diagram. Figure 1 A diagram of the memory device shown.

[0054] refer to Figure 2 The memory device 100 may include a memory cell array 110, peripheral circuitry 120, and control logic 130. The control logic 130 may be implemented in hardware, software, or a combination of both. For example, the control logic 130 may be control logic circuitry operating according to an algorithm and / or a processor executing control logic code.

[0055] Memory cell array 110 includes multiple memory blocks BLK1 to BLKz. The multiple memory blocks BLK1 to BLKz are connected to row decoder 121 via row lines RL. The multiple memory blocks BLK1 to BLKz are connected to page buffer group 123 via bit lines BL1 to BLm. Each memory block in the multiple memory blocks BLK1 to BLKz includes multiple memory cells. In one embodiment, the multiple memory cells may be non-volatile memory cells. Memory cells connected to the same word line may be defined as a page. Therefore, a memory block may include multiple pages.

[0056] A row line RL may include at least one source select line, multiple word lines, and at least one drain select line.

[0057] Each memory cell in the memory cell array 110 can be configured as: a single-level cell (SLC) storing one data bit, a multi-level cell (MLC) storing two data bits, a three-level cell (TLC) storing three data bits, or a four-level cell (QLC) storing four data bits.

[0058] Under the control of control logic 130, peripheral circuitry 120 can perform programming, reading, or erasing operations on selected regions of memory cell array 110. Peripheral circuitry 120 can drive memory cell array 110. For example, under the control of control logic 130, peripheral circuitry 120 can apply various operating voltages to row lines RL and bit lines BL1 to BLm, or discharge the applied voltages.

[0059] The peripheral circuitry 120 may include a row decoder 121, a voltage generator 122, a page buffer group 123, a column decoder 124, an input / output circuit 125, and a sensing circuit 126.

[0060] The row decoder 121 is connected to the memory cell array 110 via row lines RL. The row lines RL may include at least one source select line, multiple word lines, and at least one drain select line. In one embodiment, the word lines may include normal word lines and dummy word lines. In another embodiment, the row lines RL may also include pipe select lines.

[0061] The line decoder 121 operates under the control of the control logic. The line decoder 121 receives the line address RADD from the control logic 130.

[0062] The row decoder 121 decodes the row address RADD. Based on the decoded address, the row decoder 121 selects at least one memory block from memory blocks BLK1 to BLKz. Furthermore, based on the decoded address, the row decoder 121 can select at least one word line of the selected memory block to apply a voltage generated by the voltage generator 122 to at least one word line WL.

[0063] For example, in a programming operation, the line decoder 121 can apply a programming voltage to the selected word line and a programming pass voltage with a level lower than the programming voltage to the unselected word lines. In a programming verification operation, the line decoder 121 can apply a verification voltage to the selected word line and a verification pass voltage with a level higher than the verification voltage to the unselected word lines.

[0064] During a read operation, the line decoder 121 can apply a read voltage to the selected word line and a read pass voltage at a level higher than the read voltage to the unselected word lines.

[0065] In one embodiment, the erase operation of memory device 100 is performed on a block-by-block basis. During the erase operation, row decoder 121 can select a memory block based on the decoded address. During the erase operation, row decoder 121 can apply a ground voltage to the word line connected to the selected memory block.

[0066] Voltage generator 122 operates under the control of control logic 130. Voltage generator 122 generates multiple voltages using the external power supply voltage supplied to memory device 100. Specifically, the voltage generator can generate various operating voltages Vop for programming, reading, and erasing operations in response to the operation signal OPSIG. For example, voltage generator 122 can generate programming voltage, verification voltage, pass voltage, read voltage, erase voltage, etc., under the control of control logic 130.

[0067] In one embodiment, voltage generator 122 can generate an internal power supply voltage by adjusting an external power supply voltage. The internal power supply voltage generated by voltage generator 122 is used as the operating voltage of memory device 100.

[0068] In one embodiment, voltage generator 122 can generate multiple voltages by using an external power supply voltage or an internal power supply voltage.

[0069] For example, voltage generator 122 may include a plurality of pump capacitors for receiving internal power supply voltages, and generate a plurality of voltages by selectively activating the plurality of pump capacitors under the control of control logic 130.

[0070] The generated voltages can be supplied to the memory cell array 110 via the row decoder 121.

[0071] Page buffer group 123 includes first page buffers PB1 to m-th page buffers PBm. First page buffers PB1 to m-th page buffers PBm are connected to memory cell array 110 via first bit lines BL1 to m-th bit lines BLm, respectively. First bit lines BL1 to m-th bit lines BLm operate under the control of control logic 130. Specifically, first bit lines BL1 to m-th bit lines BLm can operate in response to page buffer control signals PBSIGNALS. For example, first page buffers PB1 to m-th page buffers PBm can temporarily store data received via first bit lines BL1 to m-th bit lines BLm, or sense the voltage or current of bit lines BL1 to BLm during read or verification operations.

[0072] Specifically, during programming, when a programming voltage is applied to the selected word line, the first page buffer PB1 to the m-th page buffer PBm can transmit the data DATA received through the input / output circuit 125 to the selected memory cell via the first bit line BL1 to the m-th bit line BLm. The memory cell of the selected page is programmed according to the transmitted data DATA. Memory cells connected to bit lines to which a programming enable voltage (e.g., ground voltage) is applied can have an increased threshold voltage. The threshold voltage of memory cells connected to bit lines to which a programming disable voltage (e.g., power supply voltage) is applied can be maintained. During programming verification, the first page buffer PB1 to the m-th page buffer PBm read page data from the selected memory cell via the first bit line BL1 to the m-th bit line BLm.

[0073] During the read operation, the first page buffer PB1 to the m-th page buffer PBm read data DATA from the memory cell of the selected page through the first bit line BL1 to the m-th bit line BLm, and output the read data DATA to the input / output circuit 125 under the control of the column decoder 124.

[0074] During the erase operation, the first page buffer PB1 to the m-th page buffer PBm can float the first bit line BL1 to the m-th bit line BLm.

[0075] The column decoder 124 can communicate data between the input / output circuitry 125 and the page buffer group 123 in response to the column address CADD. For example, the column decoder 124 can communicate data with the first page buffer PB1 to the m-th page buffer PBm via the data line DL, or with the input / output circuitry 125 via the column line CL.

[0076] Input / output circuit 125 can transmit data from the reference to control logic 130. Figure 1 The memory controller 200 described receives commands CMD and addresses ADDR, or exchanges data DATA with the column decoder 124.

[0077] In a read or verification operation, the sensing circuit 126 can generate a reference current in response to the enable bit VRYBIT signal, and output a pass signal PASS or a failure signal FAIL by comparing the sensed voltage VPB received from the page buffer group 123 with the reference voltage generated by the reference current.

[0078] Control logic 130 can control peripheral circuit 120 by outputting operation signal OPSIG, row address RADD, page buffer control signal PBSIGNALS, and enable bit VRYBIT in response to command CMD and address ADDR. Furthermore, control logic 130 can determine whether the verification operation has passed or failed in response to pass signal PASS or failure signal FAIL.

[0079] In one embodiment, control logic 130 may include a programmable operation controller 131.

[0080] The programming operation controller 131 can control the peripheral circuitry 120 to perform programming operations. For example, the programming operation controller 131 can control the peripheral circuitry 120 to program data into selected memory cells among a plurality of memory cells according to a plurality of programming cycles. The peripheral circuitry 120 can execute multiple programming cycles. Each of these programming cycles may include a programming voltage application operation and a verification operation. (See reference...) Figure 6 The description includes programming operations involving multiple programming loops, which will be described later. Figure 6 .

[0081] In one embodiment, the programming operation controller 131 can control the peripheral circuitry 120 to apply a programming voltage to the selected memory cell during a programming voltage application operation. Furthermore, the programming operation controller 131 can control the peripheral circuitry 120 to verify the programming state of the selected memory cells that are programmed to any of the programming states during a verification operation. Multiple programming states can be distinguished based on multiple threshold voltages. Therefore, the programming operation controller 131 can detect the programming state of the memory cell by applying a first verification voltage to a selected word line connected to the selected memory cell to distinguish the multiple programming states. The first verification voltage can be a voltage used to verify the programming state.

[0082] In one embodiment, when the threshold voltage of a memory cell programmed to any programming state is lower than a first verification voltage, the programming operation controller 131 can determine that the verification operation for the corresponding programming state has failed. The programming operation controller 131 can then control the peripheral circuitry 120 to execute the next programming cycle.

[0083] In one embodiment, the programming operation controller 131 can control the peripheral circuitry 120 to verify the erase state of selected memory cells programmed to be erased. The programming operation controller 131 can verify the erase state of the memory cells by applying a second verification voltage to the selected word line. The second verification voltage can be lower than the first verification voltage. Furthermore, the second verification voltage can include a negative verification voltage.

[0084] In one embodiment, when the threshold voltage of a memory cell programmed to be in an erase state is higher than the second verification voltage, the programming operation controller 131 can determine that the verification operation for the erase state has failed. Furthermore, when it is determined that the verification operation for the erase state has failed, the programming operation controller 131 can control the peripheral circuitry 120 to program data into memory cells other than the selected memory cell among a plurality of memory cells.

[0085] Therefore, according to embodiments of this disclosure, verifying the erase state of a memory cell programmed to be erased during programming operations can prevent read failures caused by a memory cell in an erased state.

[0086] Meanwhile, verification of the erasure status can be performed according to various embodiments.

[0087] For example, after the verification operation of multiple programming states has passed, the programming operation controller 131 can control the peripheral circuit 120 to verify the erase state of the memory cell programmed to be erased.

[0088] In another example, after verification operations on multiple programming states have passed, the programming operation controller 131 may apply a predetermined minimum programming voltage to the selected memory cell. Furthermore, after the minimum programming voltage is applied to the selected memory cell, the programming operation controller 131 may verify the erase state of the memory cell programmed to be in an erase state. As used herein with respect to parameters such as a predetermined minimum programming voltage, the term "predetermined" means that the value of the parameter is determined before the parameter is used in a process or algorithm. In some embodiments, the value of the parameter is determined before the process or algorithm begins. In other embodiments, the value of the parameter is determined during the process or algorithm, but before the parameter is used in the process or algorithm.

[0089] In another embodiment, during the verification operation of at least one programming cycle corresponding to a specific programming state among multiple programming cycles, the programming operation controller 131 controls the peripheral circuitry 120 to verify the erase state of a selected memory cell programmed into an erase state. During the verification operation of at least one programming cycle corresponding to a programming state, the programming operation controller 131 may control the peripheral circuitry 120 to verify both the programming state of the memory cell programmed into a specific programming state and the erase state of the memory cell programmed into an erase state. In one embodiment, the specific programming state may include a programming state among multiple programming states that has a higher threshold voltage than other programming states.

[0090] Figure 3 It is a diagram. Figure 2 A diagram of one embodiment of the memory cell array shown.

[0091] refer to Figure 3 The memory cell array 110 may include multiple memory blocks BLK1 to BLKz. Each memory block may have a three-dimensional structure. Each memory block may include multiple memory cells stacked on a substrate (not shown). These multiple memory cells may be arranged along the +X, +Y, and +Z directions. Reference will be made below. Figure 4 and Figure 5 Describe the structure of each memory block.

[0092] Figure 4 It is a diagram. Figure 3 The circuit diagram of any one of the memory blocks BLKa from BLK1 to BLKz is shown.

[0093] refer to Figure 4 The memory block BLKa may include multiple memory cell strings CS11 to CS1m and CS21 to CS2m. In one embodiment, each of the multiple memory cell strings CS11 to CS1m and CS21 to CS2m may be formed in a "U" shape. In the memory block BLKa, m memory cell strings are arranged in the row direction (i.e., the +X direction). Figure 4 The illustration shows two strings of memory cells arranged in the column direction (i.e., the +Y direction). However, this is for ease of description, and it will be understood that three strings of memory cells can be arranged in the column direction.

[0094] Each of the multiple memory cell strings CS11 to CS1m and CS21 to CS2m may include at least one source selection transistor SST, a first memory cell MC1 to the nth memory cell MCn, a pipe transistor PT, and at least one drain selection transistor DST.

[0095] The select transistors SST and DST, and the memory cells MC1 to MCn, can have similar structures to each other. In one embodiment, each of the select transistors SST and DST, and the memory cells MC1 to MCn, may include a channel layer, a tunneling insulating layer, a charge storage layer, and a barrier insulating layer. In one embodiment, a pillar for providing the channel layer may be provided in each memory cell string. In another embodiment, a pillar may be provided in each memory cell string for providing at least one of the channel layer, the tunneling insulating layer, the charge storage layer, and the barrier insulating layer.

[0096] The source selection transistor SST of each memory cell string is connected between the common source line CSL and memory cells MC1 to MCp.

[0097] In one embodiment, source select transistors of memory cell strings arranged in the same row are connected to source select lines extending in the row direction, and source select transistors of memory cell strings arranged in different rows are connected to different source select lines. Figure 4 In the first row, the source select transistors of memory cell strings CS11 to CS1m are connected to the first source select line SSL1. The source select transistors of memory cell strings CS21 to CS2m in the second row are connected to the second source select line SSL2.

[0098] In another embodiment, the source select transistors of memory cell strings CS11 to CS1m and CS21 to CS2m can be connected together to a single source select line.

[0099] The first memory cell MC1 to the nth memory cell MCn of each memory cell string are connected between the source selection transistor SST and the drain selection transistor DST.

[0100] The first memory cells MC1 to the nth memory cell MCn can be divided into: the first memory cells MC1 to the pth memory cells MCp, and the (p+1)th memory cells MCp+1 to the nth memory cells MCn. The first memory cells MC1 to the pth memory cells MCp are arranged sequentially in opposite directions in the +Z direction and connected in series between the source selection transistor SST and the channel transistor PT. The (p+1)th memory cells MCp+1 to the nth memory cells MCn are arranged sequentially in the +Z direction and connected in series between the channel transistor PT and the drain selection transistor DST. The first memory cells MC1 to the pth memory cells MCp and the (p+1)th memory cells MCp+1 to the nth memory cells MCn are connected through the channel transistor PT. The gate electrodes of the first memory cells MC1 to the nth memory cells MCn in each memory cell string are respectively connected to the first word line WL1 to the nth word line WLn.

[0101] The gate of the pipe transistor PT in each memory cell string is connected to the pipe line PL.

[0102] The drain select transistor (DST) of each memory cell string is connected between the corresponding bit line and memory cells MCp+1 to MCn. Memory cell strings arranged in the row direction are connected to drain select lines extending in the row direction. The drain select transistors of memory cell strings CS11 to CS1m in the first row are connected to the first drain select line DSL1. The drain select transistors of memory cell strings CS21 to CS2m in the second row are connected to the second drain select line DSL2.

[0103] Memory cells arranged in a column direction are connected in a string to bit lines extending in the column direction. Figure 4 In the diagram, memory cell strings CS11 and CS21 in the first column are connected to the first bit line BL1. Memory cell strings CS1m and CS2m in the m-th column are connected to the m-th bit line BLm.

[0104] Memory cells connected to the same word line in a row-oriented memory cell string constitute a page. For example, memory cells in the memory cell strings CS11 to CS1m in the first row connected to the first word line WL1 constitute one page. Memory cells in the memory cell strings CS21 to CS2m in the second row connected to the first word line WL1 constitute another page. When either drain select line DSL1 or DSL2 is selected, a memory cell string arranged in a row-oriented direction can be selected. When any word line WL1 to WLn is selected, a page can be selected from the selected memory cell string.

[0105] In another embodiment, even-numbered bit lines and odd-numbered bit lines can be provided to replace the first bit line BL1 to the m-th bit line BLm. Furthermore, even-numbered memory cell strings arranged in the row direction CS11 to CS1m or CS21 to CS2m can be connected to the even-numbered bit lines, and odd-numbered memory cell strings arranged in the row direction CS11 to CS1m or CS21 to CS2m can be connected to the odd-numbered bit lines.

[0106] In one embodiment, at least one of the first memory cells MC1 to the nth memory cell MCn can be used as a dummy memory cell. For example, at least one dummy memory cell can be provided to reduce the electric field between the source select transistor SST and the memory cells MC1 to MCp. Alternatively, at least one dummy memory cell can be provided to reduce the electric field between the drain select transistor DST and the memory cells MCp+1 to MCn. When the number of dummy memory cells increases, the operational reliability of the memory block BLKa improves. On the other hand, the size of the memory block BLKa increases. When the number of dummy memory cells decreases, the size of the memory block BLKa decreases. On the other hand, the operational reliability of the memory block BLKa may deteriorate.

[0107] To efficiently control at least one dummy memory cell, the dummy memory cell can have a required threshold voltage. Programming operations can be performed on all or some of the dummy memory cells before or after the erase operation of the memory block BLKa. When an erase operation is performed after a programming operation, the threshold voltage control of the dummy memory cell applies to the voltage of the dummy word line connected to the corresponding dummy memory cell, ensuring that the dummy memory cell has the required threshold voltage.

[0108] Figure 5 It is a diagram. Figure 3 A circuit diagram of another embodiment of memory block BLKb, one of the memory blocks BLK1 to BLKz shown.

[0109] refer to Figure 5 The memory block BLKb may include multiple memory cell strings CS11' to CS1m' and CS21' to CS2m'. Each of the multiple memory cell strings CS11' to CS1m' and CS21' to CS2m' extends along the +Z direction. Each of the multiple memory cell strings CS11' to CS1m' and CS21' to CS2m' includes, stacked on a substrate (not shown) below the memory block BLKb: at least one source selection transistor SST, first memory cells MC1 to nth memory cells MCn, and at least one drain selection transistor DST.

[0110] The source select transistor SST of each memory cell string is connected between the common source line CSL and memory cells MC1 to MCn. Source select transistors of memory cell strings arranged in the same row are connected to the same source select line. The source select transistors of memory cell strings CS11' to CS1m' arranged in the first row are connected to the first source select line SSL1. The source select transistors of memory cell strings CS21' to CS2m' arranged in the second row are connected to the second source select line SSL2. In another embodiment, the source select transistors of memory cell strings CS11' to CS1m' and CS21' to CS2m' may be connected to a common source select line.

[0111] The first memory cell MC1 to the nth memory cell MCn in each memory cell string are connected in series between the source select transistor SST and the drain select transistor DST. The gate electrodes of the first memory cell MC1 to the nth memory cell MCn are respectively connected to the first word line WL1 to the nth word line WLn.

[0112] The drain select transistor (DST) of each memory cell string is connected between the corresponding bit line and memory cells MC1 to MCn. The drain select transistors of memory cell strings arranged in the row direction are connected to drain select lines extending in the row direction. The drain select transistors of memory cell strings CS11' to CS1m' in the first row are connected to the first drain select line DSL1. The drain select transistors of memory cell strings CS21' to CS2m' in the second row are connected to the second drain select line DSL2.

[0113] Therefore, in addition to from Figure 5 Each memory cell string excludes the pipe transistor PT. Figure 5 The memory block BLKb has the same Figure 4 The circuitry is similar to that of the memory block BLKa.

[0114] In another embodiment, even-numbered bit lines and odd-numbered bit lines can be provided to replace the first bit line BL1 to the m-th bit line BLm. Furthermore, memory cell strings with even-numbered addresses among the memory cell strings CS11' to CS1m' or CS21' to CS2m' arranged in the row direction can be connected to the even-numbered bit lines, and memory cell strings with odd-numbered addresses among the memory cell strings CS11' to CS1m' or CS21' to CS2m' arranged in the row direction can be connected to the odd-numbered bit lines.

[0115] In one embodiment, at least one of the first memory cells MC1 to the nth memory cell MCn can be used as a dummy memory cell. For example, at least one dummy memory cell can be provided to reduce the electric field between the source select transistor SST and the memory cells MC1 to MCp. Alternatively, at least one dummy memory cell can be provided to reduce the electric field between the drain select transistor DST and the memory cells MCp+1 to MCn. When the number of dummy memory cells increases, the operational reliability of the memory block BLKb improves. On the other hand, the size of the memory block BLKb increases. When the number of dummy memory cells decreases, the size of the memory block BLKb decreases. On the other hand, the operational reliability of the memory block BLKb may deteriorate.

[0116] To efficiently control at least one dummy memory cell, the dummy memory cell can have a required threshold voltage. Programming operations can be performed on all or some of the dummy memory cells before or after the erase operation of memory block BLKb. When the erase operation is performed after the programming operation, the threshold voltage control of the dummy memory cell applies to the voltage of the dummy word line connected to the corresponding dummy memory cell, ensuring that the dummy memory cell has the required threshold voltage.

[0117] Figure 6 It is a diagram. Figure 2 A diagram illustrating the programming operations of the memory device.

[0118] exist Figure 6 For ease of description, it is assumed that each of the plurality of memory cells is a multi-level cell (MLC) storing 2 bits of data. However, the scope of this disclosure is not limited thereto, and each of the plurality of memory cells may be a three-level cell (TLC) storing 3 bits of data or a four-level cell (QLC) storing 4 bits of data.

[0119] The programming operation of memory device 100 may include multiple programming cycles PL1 to PLn. That is, memory device 100 can program selected memory cells to have a threshold voltage by executing multiple programming cycles PL1 to PLn, the threshold voltage corresponding to any one of multiple programming states P1, P2 and P3.

[0120] Each of the multiple programming cycles PL1 to PLn may include: a programming voltage application operation (PGM Operation) that applies a programming voltage, and a verification operation (Verify Operation) that determines whether a memory cell has been programmed by applying a verification voltage.

[0121] For example, when executing the first programming cycle PL1, after applying the first programming pulse Vpgm1, verification voltages V_vfy1 to V_vfy3 can be applied sequentially to verify the programming states of multiple memory cells. Verification of memory cells with a target programming state of first programming state P1 can be performed using the verification voltage V_vfy1 corresponding to first programming state P1; verification of memory cells with a target programming state of second programming state P2 can be performed using the verification voltage V_vfy2 corresponding to second programming state P2; and verification of memory cells with a target programming state of third programming state P3 can be performed using the verification voltage V_vfy3 corresponding to third programming state P3.

[0122] It can be determined that a memory cell that passes verification by each of the verification voltages V_vfy1 to V_vfy3 has a target programming state. Subsequently, this memory cell can be disabled from programming in the second programming cycle PL2. In the second programming cycle PL2, a second programming pulse Vpgm2, which is a unit voltage ΔVpgm higher than the first programming pulse Vpgm1, is applied to program the memory cells other than those that were disabled from programming. Then, the exact same verification operation as in the first programming cycle PL1 is performed. For example, the term "verification passed" indicates that the memory cell is read as a shutdown cell by the corresponding verification voltage.

[0123] As described above, when the memory device 100 programs the MLC storing 2 bits of data, the memory device 100 can verify the memory cell having a programming state as the target programming state by using verification voltages V_vfy1 to V_vfy3.

[0124] In the verification operation, a verification voltage can be applied to the selected word line, which is connected to the selected memory cell, and the page buffer can determine whether the memory cell has passed verification based on the current or voltage flowing through the bit lines respectively connected to the selected memory cell.

[0125] For example, memory device 100 can store the state of a memory cell based on the voltage of a bit line. The state of a memory cell can correspond to either a successful or failed verification. When the threshold voltage of the memory cell is higher than the verification voltage applied to the selected word line, the memory cell can be read as a disabled cell. A memory cell read as a disabled cell can correspond to a successful verification state. Conversely, when the threshold voltage of the memory cell is lower than the verification voltage applied to the selected word line, the memory cell can be read as an enabled cell. A memory cell read as an enabled cell can correspond to a failed verification state.

[0126] Figure 7 This is a diagram illustrating the threshold voltage distribution of a single-stage unit.

[0127] refer to Figure 7 The horizontal axis represents the threshold voltage of the memory cell, and the vertical axis represents the number of memory cells.

[0128] The memory device 100 can perform programming operations on a word line basis. Multiple memory cells connected to a word line can form a physical page. A physical page can be the unit of programming or reading operations.

[0129] The memory device 100 can program memory cells connected to a selected word line among a plurality of word lines according to the data to be stored.

[0130] Before performing the programming operation, as shown in the diagram above, the selected memory cell, which is a memory cell connected to the selected word line, can have a threshold voltage distribution corresponding to the erase state E.

[0131] When a memory cell stores data corresponding to a bit, the memory cell can be programmed to have a threshold voltage corresponding to either the erase state E or the first programming state P1.

[0132] The erase state E can correspond to the data "1", and the first programming state P1 can correspond to the data "0". However, the data corresponding to the first programming state P1 is merely illustrative. The erase state E can correspond to the data "0", and the first programming state P1 can correspond to the data "1".

[0133] As shown in the diagram below, when the programming operation is completed, the selected memory cell may have a threshold voltage corresponding to either the erase state E or the first programming state P1. The memory device 100 performs a read operation using a first read voltage R1 between the erase state E and the first programming state P1, enabling the reading of data stored in the selected memory cell.

[0134] Figure 8 This is a diagram illustrating the threshold voltage distribution of a multi-level unit.

[0135] refer to Figure 8 The horizontal axis represents the threshold voltage of the memory cell, and the vertical axis represents the number of memory cells.

[0136] Before performing the programming operation, as shown in the diagram above, the selected memory cell, which is a memory cell connected to the selected word line, can have a threshold voltage distribution corresponding to the erase state E.

[0137] When a memory cell stores data corresponding to two bits, the memory cell can be programmed to have a threshold voltage corresponding to any one of the erase state E, the first programming state P1, the second programming state P2, and the third programming state P3. In one embodiment, the third programming state P3 can be the highest programming state.

[0138] The erase state E can correspond to the data "11", the first programming state P1 can correspond to the data "10", the second programming state P2 can correspond to the data "00", and the third programming state P3 can correspond to the data "01". However, the data corresponding to each programming state is merely illustrative and can be changed in various ways.

[0139] As shown in the diagram below, when the programming operation is completed, the selected memory cell may have a threshold voltage corresponding to any one of the erase state E, the first programming state P1, the second programming state P2, and the third programming state P3. The memory device 100 performs a read operation using the first read voltage R1 to the third read voltage R3, enabling the reading of data stored in the selected memory cell.

[0140] The first read voltage R1 can be a read voltage used to distinguish between the erase state E and the first programming state P1, the second read voltage R2 can be a read voltage used to distinguish between the first programming state P1 and the second programming state P2, and the third read voltage R3 can be a read voltage used to distinguish between the second programming state P2 and the third programming state P3.

[0141] Figure 9 This is a diagram illustrating the threshold voltage distribution of the three-level unit.

[0142] refer to Figure 9 The horizontal axis represents the threshold voltage of the memory cell, and the vertical axis represents the number of memory cells.

[0143] Before performing the programming operation, as shown in the diagram above, the selected memory cell, which is a memory cell connected to the selected word line, can have a threshold voltage distribution corresponding to the erase state E.

[0144] When a memory cell stores data corresponding to three bits, the memory cell can be programmed to have a threshold voltage corresponding to any one of the erase state E, the first programming state P1, the second programming state P2, the third programming state P3, the fourth programming state P4, the fifth programming state P5, the sixth programming state P6, and the seventh programming state P7. In one embodiment, programming state P7 can be the highest programming state.

[0145] The erase state E can correspond to the data "111", the first programming state P1 can correspond to the data "110", the second programming state P2 can correspond to the data "101", the third programming state P3 can correspond to the data "100", the fourth programming state P4 can correspond to the data "011", the fifth programming state P5 can correspond to the data "101", the sixth programming state P6 can correspond to the data "001", and the seventh programming state P7 can correspond to the data "000". However, the data corresponding to each programming state is merely illustrative and can be changed in various ways.

[0146] As shown in the diagram below, when the programming operation is completed, the selected memory cell may have a threshold voltage corresponding to any one of the erase state E, the first programming state P1, the second programming state P2, the third programming state P3, the fourth programming state P4, the fifth programming state P5, the sixth programming state P6, and the seventh programming state P7. The memory device 100 performs a read operation using the first read voltage R1 to the seventh read voltage R7, enabling the reading of data stored in the selected memory cell.

[0147] The first read voltage R1 can be a read voltage used to distinguish between the erase state E and the first programming state P1; the second read voltage R2 can be a read voltage used to distinguish between the first programming state P1 and the second programming state P2; the third read voltage R3 can be a read voltage used to distinguish between the second programming state P2 and the third programming state P3; the fourth read voltage R4 can be a read voltage used to distinguish between the third programming state P3 and the fourth programming state P4; the fifth read voltage R5 can be a read voltage used to distinguish between the fourth programming state P4 and the fifth programming state P5; the sixth read voltage R6 can be a read voltage used to distinguish between the fifth programming state P5 and the sixth programming state P6; and the seventh read voltage R7 can be a read voltage used to distinguish between the sixth programming state P6 and the seventh programming state P7.

[0148] Simultaneously, multiple programming cycles may affect the threshold voltage distribution of memory cells programmed into an erase state. Accordingly, the threshold voltage of memory cells programmed into an erase state (such as the distribution indicated by the dashed lines) may change to an abnormal threshold voltage distribution. Even though the memory cells in the slanted area have been programmed into an erase state, during a read operation, these memory cells may be read as memory cells with a first programming state P1. This abnormal threshold voltage distribution may cause error correction failures during read operations. However, typically, programming operations verify the programming state of memory cells programmed into any programming state, but not the erase state of memory cells programmed into an erase state.

[0149] Therefore, according to embodiments of this disclosure, verifying the erase state of a memory cell programmed to be erased during programming operations allows read failures caused by memory cells in an erased state to be prevented or mitigated. Reference will now be made to... Figures 10 to 13 Describes the operation for verifying the erase state of a memory cell that has been programmed to be erased.

[0150] Figure 10 This is a diagram illustrating an example of the operation of a memory device according to an embodiment of the present disclosure.

[0151] exist Figure 10 For ease of description, it is assumed that each of the plurality of memory cells is a three-level cell storing 3 bits of data. However, the scope of this disclosure is not limited thereto; each of the plurality of memory cells may be a multi-level cell storing 2 bits of data or a four-level cell storing 4 bits of data.

[0152] refer to Figure 10 The memory device 100 can execute multiple programming cycles PL1 to PLn. For example, the memory device 100 can apply a programming voltage to selected memory cells and verify the programming state of memory cells programmed to any of the programming states. The memory device 100 can verify the programming state of memory cells by applying verification voltages PV1 to PV7 corresponding to each programming state to selected word lines.

[0153] In one embodiment, after the verification operation of multiple programming states PV1 to PV7 according to multiple programming cycles PL1 to PLn is passed, the memory device 100 can verify the erase state of the memory cell among the selected memory cells that is programmed to erase state E.

[0154] For example, based on the sequential execution of multiple programming cycles PL1 to PLn, the verification operation of the programming state of the memory cell programmed to the seventh programming state P7 can be passed. Subsequently, the memory device 100 can verify the erase state of the memory cell programmed to the erase state. The memory device 100 can verify the erase state of the memory cell programmed to the erase state by applying a verification voltage PV0 corresponding to the erase state to the selected word line. The verification voltage PV0 corresponding to the erase state can be lower than the verification voltages PV1 to PV7 corresponding to each programming state.

[0155] Furthermore, when the threshold voltage of a memory cell programmed to the erase state is lower than the verification voltage PV0 corresponding to the erase state, the memory device 100 can determine that the verification operation for the erase state has passed. The memory cell programmed to the erase state can correspond to a verification passed state. When it is determined that the verification operation for the erase state has passed, the memory device 100 can end the programming operation.

[0156] Alternatively, when the threshold voltage of a memory cell programmed to the erase state is higher than the verification voltage PV0 corresponding to the erase state, the memory device 100 can determine that the verification operation for the erase state has failed. The memory cell programmed to the erase state may correspond to a verification failure state. In one embodiment, when it is determined that the verification operation for the erase state has failed, the memory device 100 can program the data into another memory cell instead of the selected memory cell.

[0157] Figure 11 This is a diagram illustrating another example of the operation of a memory device according to an embodiment of the present disclosure.

[0158] exist Figure 11 For ease of description, it is assumed that each of the plurality of memory cells is a three-level cell storing 3 bits of data. However, the scope of this disclosure is not limited thereto; each of the plurality of memory cells may be a multi-level cell storing 2 bits of data or a four-level cell storing 4 bits of data.

[0159] refer to Figure 11 The memory device 100 can execute multiple programming cycles PL1 to PLn. For example, the memory device 100 can apply a programming voltage to selected memory cells and verify the programming state of memory cells programmed to any of the programming states. The memory device 100 can verify the programming state of memory cells by applying verification voltages PV1 to PV7 corresponding to each programming state to selected word lines.

[0160] In one embodiment, after the verification operation of multiple programming states PV1 to PV7 according to multiple programming cycles PL1 to PLn is passed, the memory device 100 can verify the erase state of the memory cell among the selected memory cells that is programmed to erase state E.

[0161] For example, according to the sequential execution of multiple programming cycles PL1 to PLn, the verification operation of the programming state of the memory cell programmed to the seventh programming state P7 can be passed. Subsequently, the memory device 100 can apply a predetermined minimum programming voltage Vpgm0. The minimum programming voltage Vpgm0 can be the lowest programming voltage that can be applied to the memory cell according to the design of the memory device 100. The minimum programming voltage Vpgm0 can be set during the design process of the memory device 100. For example, the minimum programming voltage Vpgm0 can be lower than the first programming voltage Vpgm1. Therefore, although the minimum programming voltage Vpgm0 is applied to the selected memory cell, the programming state or erase state of the memory cell can be maintained.

[0162] Furthermore, after the minimum programming voltage Vpgm0 is applied to the selected memory cell, the memory device 100 can verify the erase state of the memory cell programmed to be erased. The memory device 100 can verify the erase state of the memory cell programmed to be erased by applying a verification voltage PV0 corresponding to the erase state to the selected word line. The verification voltage PV0 corresponding to the erase state can be lower than the verification voltages PV1 to PV7 corresponding to each programming state. Moreover, the verification voltage PV0 corresponding to the erase state can include a negative verification voltage.

[0163] Furthermore, when the threshold voltage of a memory cell programmed to the erase state is lower than the verification voltage PV0 corresponding to the erase state, the memory device 100 can determine that the verification operation for the erase state has passed. The memory cell programmed to the erase state can correspond to a verification passed state. When it is determined that the verification operation for the erase state has passed, the memory device 100 can end the programming operation.

[0164] Alternatively, when the threshold voltage of a memory cell programmed to the erase state is higher than the verification voltage PV0 corresponding to the erase state, the memory device 100 can determine that the verification operation for the erase state has failed. The memory cell programmed to the erase state may correspond to a verification failure state. In one embodiment, when it is determined that the verification operation for the erase state has failed, the memory device 100 can program the data into another memory cell instead of the selected memory cell.

[0165] Figure 12This is a diagram illustrating yet another example of the operation of a memory device according to an embodiment of the present disclosure. Figure 13 This is a diagram illustrating yet another example of the operation of a memory device according to an embodiment of the present disclosure.

[0166] exist Figure 12 and Figure 13 For ease of description, it is assumed that each of the plurality of memory cells is a three-level cell storing 3 bits of data. However, the scope of this disclosure is not limited thereto; each of the plurality of memory cells may be a multi-level cell storing 2 bits of data or a four-level cell storing 4 bits of data.

[0167] refer to Figure 12 The memory device 100 can execute multiple programming cycles PL1 to PLn. For example, the memory device 100 can apply a programming voltage to selected memory cells and verify the programming state of memory cells programmed to any of the programming states. The memory device 100 can verify the programming state of memory cells by applying verification voltages PV1 to PV7 corresponding to each programming state to selected word lines.

[0168] In one embodiment, in a verification operation included in at least one programming cycle of a plurality of programming cycles PL1 to PLn corresponding to a specific programming state, the memory device 100 can verify the erase state of a memory cell programmed to erase state E.

[0169] This specific programming state can include a programming state that has a higher threshold voltage than other programming states. For example, the specific programming state can be the seventh programming state P7. The PLn-1 programming cycle PLn-1 and the PLn programming cycle PLn can be programming cycles corresponding to the seventh programming state.

[0170] The memory device 100 can verify the erase state of memory cells programmed to the erase state in verification operations included in the PLn-1 programming cycle PLn-1 and the PLn programming cycle PLn. For example, the memory device 100 can verify the programming state of memory cells programmed to the seventh programming state in verification operations included in the PLn-1 programming cycle PLn-1 and the PLn programming cycle PLn. The memory device 100 can verify the programming state of memory cells programmed to the seventh programming state by applying a verification voltage PV7 corresponding to the seventh programming state. Subsequently, the memory device 100 can verify the erase state of memory cells programmed to the erase state in verification operations included in the PLn-1 programming cycle PLn-1 and the PLn programming cycle PLn. The memory device 100 can verify the erase state of memory cells programmed to the erase state by applying a verification voltage PV0 corresponding to the erase state. The verification voltage PV0 corresponding to the erase state can be lower than the verification voltages PV1 to PV7 corresponding to each programming state. Furthermore, the verification voltage PV0 corresponding to the erase state may include a negative verification voltage.

[0171] Furthermore, when the threshold voltage of a memory cell programmed to the erase state is lower than the verification voltage PV0 corresponding to the erase state, the memory device 100 can determine that the verification operation for the erase state has passed. The memory cell programmed to the erase state can correspond to a verification passed state. When it is determined that the verification operation for the erase state has passed, the memory device 100 can end the programming operation.

[0172] Alternatively, when the threshold voltage of a memory cell programmed to the erase state is higher than the verification voltage PV0 corresponding to the erase state, the memory device 100 can determine that the verification operation for the erase state has failed. The memory cell programmed to the erase state may correspond to a verification failure state. In one embodiment, when it is determined that the verification operation for the erase state has failed, the memory device 100 can program the data into another memory cell instead of the selected memory cell.

[0173] At the same time, with Figure 12 Compared to the operations shown, Figure 13 The operation shown can have different sequences of applying the verification voltage.

[0174] refer to Figure 13By applying a verification voltage PV0 corresponding to the erase state in the verification operations included in the PLn-1 programming cycle PLn-1 and the PLn programming cycle PLn, the memory device 100 can verify the erase state of the memory cell programmed to the erase state. Subsequently, by applying a verification voltage PV7 corresponding to the seventh programming state in the verification operations included in the PLn-1 programming cycle PLn-1 and the PLn programming cycle PLn, the memory device 100 can verify the programming state of the memory cell programmed to the seventh programming state.

[0175] Figure 14 This is a flowchart illustrating an operation method of a memory device according to an embodiment of the present disclosure.

[0176] For example, Figure 14 The operation method shown can be performed by Figure 1 The memory device 100 shown is used to perform this action.

[0177] refer to Figure 14 In step S1401, the memory device 100 may apply a programming voltage to a selected memory cell among a plurality of memory cells.

[0178] In step S1403, the memory device 100 can verify the programming state of the selected memory cells that are programmed to any programming state.

[0179] In step S1405, the memory device 100 can verify the erase status of the memory cells among the selected memory cells that are programmed to be erased.

[0180] Figure 15 This is a flowchart illustrating an operation method of a memory device according to an additional embodiment of the present disclosure.

[0181] For example, Figure 15 The operation method shown can be performed by Figure 1 The memory device 100 shown is used to perform this action.

[0182] Figure 15 The operation method shown can be achieved by... Figure 14 The flowchart is a concretization of the operation method shown.

[0183] refer to Figure 15 In step S1501, the memory device 100 may apply a programming voltage to a selected memory cell among a plurality of memory cells.

[0184] In step S1503, the memory device 100 can verify the programming state of the memory cells among the selected memory cells that are programmed to any programming state. For example, the memory device 100 can verify the programming state of the memory cells programmed to any programming state by applying a first verification voltage to the selected word line connected to the selected memory cell.

[0185] In step S1505, the memory device 100 can determine whether the verification operation for multiple programming states has passed. Based on the determination result in step S1505, if the verification operation for multiple programming states fails, the memory device 100 can execute steps S1501 and S1503 again. That is, the memory device 100 can repeatedly perform the programming voltage application operation and the verification operation until the verification operation for multiple programming states passes.

[0186] Based on the determination result in step S1505, when the verification operation of multiple programming states passes, the memory device 100 can execute step S1507. In step S1507, the memory device 100 can verify the erase state of the memory cells among the selected memory cells that are programmed to be in an erase state.

[0187] For example, after a predetermined minimum programming voltage is applied to the selected memory cell, the memory device 100 can verify the erase state of the memory cell programmed to be erased. The memory device 100 can verify the erase state of the memory cell programmed to be erased by applying a second verification voltage to the selected word line. In one embodiment, the second verification voltage is a voltage lower than the first verification voltage and includes a negative verification voltage.

[0188] In step S1509, the memory device 100 can determine whether the verification operation for the erase state has passed. For example, when the threshold voltage of the memory cell programmed to be in the erase state is higher than the second verification voltage, the memory device 100 can determine that the verification operation for the erase state has failed. Alternatively, when the threshold voltage of the memory cell programmed to be in the erase state is lower than the second verification voltage, the memory device 100 can determine that the verification operation for the erase state has passed.

[0189] Based on the determination result in step S1509, when the verification operation of the erase state passes, the programming operation of the selected memory cell can be completed.

[0190] Based on the determination result in step S1509, when it is determined that the verification operation for the erase state has failed, the memory device can execute step S1511. In step S1511, the memory device 100 can program data into memory cells other than the selected memory cell among a plurality of memory cells.

[0191] Figure 16 This is a flowchart illustrating an operation method of a memory device according to an embodiment of the present disclosure.

[0192] For example, Figure 16 The operation method shown can be performed by Figure 1 The memory device 100 shown is used to perform this action.

[0193] refer to Figure 16 In step S1601, the memory device 100 may execute multiple programming cycles. Each programming cycle may include: a programming voltage application operation that applies a programming voltage to a selected memory cell, and a verification operation that determines at least one of the programming state and the erase state of the selected memory cell.

[0194] In step S1603, the memory device 100 may verify the programming state of the memory cell programmed to a specific programming state in a verification operation included in at least one programming cycle corresponding to a specific programming state among a plurality of programming cycles.

[0195] In one embodiment, a specific programming state may include a programming state among a plurality of programming states that has a higher threshold voltage than the other programming states.

[0196] In step S1605, the memory device 100 may verify the erase state of the memory cell programmed to be erased in a verification operation included in at least one programming cycle corresponding to a specific programming state.

[0197] Figure 17 This is a flowchart illustrating an operation method of a memory device according to an embodiment of the present disclosure.

[0198] For example, Figure 17 The operation method shown can be performed by Figure 1 The memory device 100 shown is used to perform this action.

[0199] Figure 17 The operation method shown can be achieved by... Figure 16 The flowchart is a concretization of the operation method shown.

[0200] refer to Figure 17 In step S1701, the memory device 100 may execute multiple programming loops.

[0201] In step S1703, the memory device 100 may determine whether the currently executed programming cycle corresponds to a specific programming state. In one embodiment, a specific programming state may include a programming state among a plurality of programming states that has a higher threshold voltage than other programming states.

[0202] Based on the determination result in step S1703, when the currently executed programming loop is not a programming loop corresponding to a specific programming state, the memory device 100 can execute step S1705.

[0203] In step S1705, the memory device 100 can determine whether the verification operation for multiple programming states has passed. Based on the determination result in step S1705, if the verification operation for multiple programming states fails, the memory device 100 can execute steps S1701 and S1703 again. That is, the memory device 100 can repeatedly perform the programming voltage application operation and the verification operation until the verification operation for multiple programming states passes. Alternatively, based on the determination result in step S1705, if the verification operation for multiple programming states passes, the programming operation for the selected memory cell can end.

[0204] Simultaneously, based on the determination result in step S1703, when the currently executed programming loop corresponds to a specific programming state, the memory device 100 can execute step S1707. In step S1707, the memory device 100 can apply a programming voltage to the selected memory cell.

[0205] In step S1709, the memory device 100 verifies the programming state of the memory cell programmed to the specific programming state in a verification operation included in at least one programming cycle corresponding to the specific programming state. For example, the memory device 100 can verify the programming state of the memory cell programmed to the specific programming state by applying a first verification voltage to a selected word line connected to the selected memory cell.

[0206] Meanwhile, in some embodiments, the order of steps S1707 and S1709 can be changed.

[0207] In step S1711, the memory device 100 may verify the erase state of the memory cell programmed to be erased in a verification operation included in at least one programming cycle corresponding to a specific programming state. For example, the memory device 100 may verify the erase state of the memory cell programmed to be erased by applying a second verification voltage to a selected word line. In one embodiment, the second verification voltage is a voltage lower than the first verification voltage and may include a negative verification voltage.

[0208] In step S1713, the memory device 100 can determine whether the verification operation for the erase state has passed. For example, when the threshold voltage of the memory cell programmed to be in the erase state is higher than the second verification voltage, the memory device 100 can determine that the verification operation for the erase state has failed. Alternatively, when the threshold voltage of the memory cell programmed to be in the erase state is lower than the second verification voltage, the memory device 100 can determine that the verification operation for the erase state has passed.

[0209] Based on the determination result in step S1713, when the verification operation of the erase state passes, the memory device 100 can execute step S1705.

[0210] Based on the determination result in step S1713, when it is determined that the verification operation for the erase state has failed, the memory device 100 may execute step S1715. In step S1715, the memory device 100 may program data into memory cells other than the selected memory cell among a plurality of memory cells.

[0211] Figure 18 It is a diagram. Figure 1 The diagram shows the memory controller.

[0212] refer to Figure 1 and Figure 18 The memory controller 200 may include a processor 210, RAM 220, error correction circuit 230, ROM 240, host interface 250 and flash memory interface 260.

[0213] The processor 210 can control the overall operation of the memory controller 200. The RAM 220 can be used as a buffer memory, high-speed cache memory, working memory, etc. of the memory controller 200.

[0214] Error correction circuit 230 can perform error correction. Error correction circuit 230 can perform error correction code (ECC) encoding based on data to be written to memory device 100 via flash interface 260. ECC-encoded data can be transmitted to memory device 100 via flash interface 260. Error correction circuit 230 can perform ECC decoding on data received from memory device 100 via flash interface 260. For example, error correction circuit 230 is a component of flash interface 260 and can be included within flash interface 260.

[0215] ROM 240 can store various information required for the operation of memory controller 200 in the form of firmware.

[0216] The memory controller 200 can communicate with external devices (e.g., host 300, application processor, etc.) via the host interface 250.

[0217] The memory controller 200 can communicate with the memory device 100 via the flash memory interface 260. The memory controller 200 can transmit commands, addresses, control signals, etc., to the memory device 100 and receive data via the flash memory interface 260. For example, the flash memory interface 260 may include a NAND interface.

[0218] Figure 19 This is a block diagram illustrating a memory card system according to an embodiment of the present disclosure, wherein a storage device is applied to the memory card system.

[0219] refer to Figure 19 The memory card system 2000 includes a memory controller 2100, a memory device 2200, and a connector 2300.

[0220] Memory controller 2100 is connected to memory device 2200. Memory controller 2100 can access memory device 2200. For example, memory controller 2100 can control read, write, erase, and background operations of memory device 2200. Memory controller 2100 provides an interface between memory device 2200 and host. Memory controller 2100 drives firmware for controlling memory device 2200. Memory controller 2100 can be referenced... Figure 1 The memory controller 200 described is implemented exactly the same. The memory device 2200 can be implemented with reference to... Figure 1 The memory device 100 described is implemented in exactly the same way.

[0221] For example, the memory controller 2100 may include components such as random access memory (RAM), processing unit, host interface, memory interface, and ECC circuitry.

[0222] The memory controller 2100 can communicate with external devices via connector 2300. The memory controller 2100 can communicate with external devices (e.g., a host) according to a specific communication protocol. For example, the memory controller 2100 can communicate with external devices via at least one of various communication protocols, such as Universal Serial Bus (USB), Multimedia Card (MMC), Embedded MMC (eMMC), Peripheral Component Interconnect (PCI), PCI Express (PCIe), Advanced Technology Attachment (ATA), Serial ATA (SATA), Parallel ATA (PATA), Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), FireWire, Universal Flash Storage (UFS), Wi-Fi, Bluetooth, and NVMe. For example, connector 2300 can be defined by at least one of the aforementioned communication protocols.

[0223] For example, the memory device 2200 can be implemented using various non-volatile memory devices, such as electrically erasable and programmable ROM (EEPROM), NAND flash memory, NOR flash memory, phase-change RAM (PRAM), resistive RAM (ReRAM), ferroelectric RAM (FRAM), and spin torque transfer magnetic RAM (STT-MRAM).

[0224] The memory controller 2100 and memory device 2200 can be integrated into a single semiconductor device to form a memory card. For example, the memory controller 2100 and memory device 2200 can form memory cards such as: PC cards (Personal Computer Memory Card International Association (PCMCIA)), compact flash (CF) cards, smart media cards (SM and SMC), memory sticks, multimedia cards (MMC, RS-MMC, micro MMC and eMMC), SD cards (SD, mini SD, micro SD and SDHC) and universal flash storage (UFS).

[0225] Figure 20 This is a block diagram illustrating a solid-state drive (SSD) system according to an embodiment of the present disclosure, wherein a storage device is applied to the SSD system.

[0226] refer to Figure 20 The SSD system 3000 includes a host 3100 and an SSD 3200. The SSD 3200 exchanges signals with the host 3100 through a signal connector 3001 and receives power through a power connector 3002. The SSD 3200 includes an SSD controller 3210, multiple flash memory units 3221 to 322n, an auxiliary power supply 3230, and a buffer memory 3240.

[0227] In one embodiment, the SSD controller 3210 can be used as a reference. Figure 1 The memory controller 200 is described.

[0228] SSD controller 3210 can control multiple flash memory devices 3221 to 322n in response to signals received from host 3100. For example, the signal can be based on the interface between host 3100 and SSD 3200. For example, the signal can be defined by at least one interface such as: Universal Serial Bus (USB), Multimedia Card (MMC), Embedded MMC (eMMC), Peripheral Component Interconnect (PCI), PCI Express (PCIe), Advanced Technology Attachment (ATA), Serial ATA (SATA), Parallel ATA (PATA), Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), FireWire, Universal Flash Storage (UFS), Wi-Fi, Bluetooth, and NVMe.

[0229] Auxiliary power supply 3230 is connected to host 3100 via power connector 3002. Auxiliary power supply 3230 can receive power PWR input from host 3100 and use that power PWR for charging. When the power supply from host 3100 is insufficient, auxiliary power supply 3230 can provide power to SSD 3200. For example, auxiliary power supply 3230 can be located inside SSD 3200 or externally to SSD 3200. For example, auxiliary power supply 3230 can be located on the motherboard and provide auxiliary power to SSD 3200.

[0230] Buffer memory 3240 operates as a buffer memory for SSD 3200. For example, buffer memory 3240 may temporarily store data received from host 3100 or data received from multiple flash memories 3221 to 322n, or temporarily store metadata (e.g., mapping tables) of flash memories 3221 to 322n. Buffer memory 3240 may include: volatile memory, such as DRAM, SDRAM, DDR SDRAM, LPDDR SDRAM, and GRAM; or non-volatile memory, such as FRAM, ReRAM, STT-MRAM, and PRAM.

[0231] Figure 21 This is a block diagram illustrating a user system according to an embodiment of the present disclosure, wherein a storage device is applied to the user system.

[0232] refer to Figure 21 The user system 4000 includes an application processor 4100, a memory module 4200, a network module 4300, a storage module 4400, and a user interface 4500.

[0233] Application processor 4100 can drive components, operating system (OS), user programs, etc., included in user system 4000. For example, application processor 4100 may include controllers, interfaces, graphics engines, etc., for controlling components included in user system 4000. Application processor 4100 may be provided as a system-on-a-chip (SoC).

[0234] The memory module 4200 can operate as the main memory, working memory, buffer memory, or cache memory of the user system 4000. The memory module 4200 may include: volatile random access memory, such as DRAM, SDRAM, DDR SDRAM, DDR2 SDRAM, DDR3 SDRAM, LPDDR SDRAM, LPDDR2 SDRAM, and LPDDR3 SDRAM; or non-volatile random access memory, such as PRAM, ReRAM, MRAM, and FRAM. For example, the application processor 4100 and the memory module 4200 can be provided as a single semiconductor package by being packaged in a stacked package (PoP).

[0235] Network module 4300 can communicate with external devices. For example, network module 4300 can support wireless communications such as Code Division Multiple Access (CDMA), Global System for Mobile Communications (GSM), Wideband CDMA (WCDMA), CDMA-2000, Time Division Multiple Access (TDMA), Long Term Evolution (LTE), WiMAX, WLAN, UWB, Bluetooth, and Wi-Fi. For example, network module 4300 can be included in application processor 4100.

[0236] Storage module 4400 can store data. For example, storage module 4400 can store data received from application processor 4100. Alternatively, storage module 4400 can transfer data stored therein to application processor 4100. For example, storage module 4400 can be implemented using a non-volatile semiconductor memory device with a three-dimensional structure, such as phase-change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), NAND flash memory, NOR flash memory, or NAND flash memory. For example, storage module 4400 can be provided as a removable drive, such as a memory card of user system 4000 or an external drive.

[0237] For example, storage module 4400 may include multiple non-volatile memory devices, and these multiple non-volatile memory devices may be used with reference to... Figure 1 The memory device 100 described operates exactly as described. The memory module 4400 can be compared with the reference... Figure 1The storage device 50 described operates exactly the same way.

[0238] User interface 4500 may include interfaces for inputting data or commands to application processor 4100 or outputting data to external devices. For example, user interface 4500 may include user input interfaces such as a keyboard, keypad, buttons, touch panel, touchscreen, touchpad, touchball, camera, microphone, gyroscope sensor, vibration sensor, and piezoelectric element. User interface 4500 may include user output interfaces such as liquid crystal display (LCD), organic light-emitting diode (OLED) display device, active-matrix OLED (AMOLED) display device, LED, speaker, and monitor.

[0239] According to this disclosure, a memory device capable of preventing read failures caused by memory cells in an erased state, and a method of operating the memory device, can be provided.

[0240] While this disclosure has been shown and described with reference to certain examples of its embodiments, those skilled in the art will understand that various changes in form and detail may be made therein without departing from the spirit and scope of this disclosure as defined by the appended claims and their equivalents. Therefore, the scope of this disclosure should not be limited to the above-described examples of the embodiments, but should be determined not only by the appended claims but also by their equivalents.

[0241] In the above embodiments, all steps may be selectively performed, or some steps may be omitted. In each embodiment, the steps are not necessarily performed in the described order and may be rearranged. The embodiments disclosed in this specification and accompanying drawings are merely examples to aid in understanding this disclosure, and this disclosure is not limited thereto. That is, it will be apparent to those skilled in the art that various modifications can be made based on the technical scope of this disclosure.

[0242] Furthermore, examples of embodiments of this disclosure have been described in the accompanying drawings and specification. While specific terminology is used herein, those terms are for the purpose of explaining embodiments of this disclosure only. Therefore, this disclosure is not limited to the embodiments described above, and many variations are possible within the spirit and scope of this disclosure. It will be apparent to those skilled in the art that various modifications can be made beyond the embodiments disclosed herein, building upon the technical scope of this disclosure.

Claims

1. A method for operating a memory device to perform programming operations, the programming operations programming data into a selected memory cell among a plurality of memory cells, the method comprising: A programming voltage is applied to the selected memory cell; Verify the programming state of the selected memory cell that is programmed into any one of a plurality of programming states, the plurality of programming states being distinguished based on a plurality of threshold voltages; After the verification operation of the multiple programming states is successful, the minimum programming voltage is applied to the selected memory cell; as well as After the minimum programming voltage is applied to the selected memory cell, the erase state of the memory cell among the selected memory cells that is programmed to be erased is verified.

2. The method of claim 1, wherein the verification of the erasure state comprises: After the verification operation of the plurality of programming states is passed, the erase state of the memory cell programmed to the erase state is verified.

3. The method according to claim 1, wherein the verification of the programming state includes: The programming state of the memory cell programmed into the selected programming state is verified by applying a first verification voltage to the selected word line connected to the selected memory cell. The verification of the erase state includes verifying the erase state of the memory cell programmed into the erase state by applying a second verification voltage lower than the first verification voltage to the selected word line.

4. The method of claim 3, wherein the second verification voltage includes a negative verification voltage.

5. The method of claim 3, wherein the verification of the erasure state comprises: When the threshold voltage of the memory cell programmed to the erase state is higher than the second verification voltage, it is determined that the verification operation for the erase state has failed.

6. The method according to claim 5, further comprising: When the verification operation for the erase state fails for the selected memory cell among the plurality of memory cells, the data is programmed into other memory cells among the plurality of memory cells besides the selected memory cell.

7. A method for operating a memory device to perform programming operations, the programming operations programming data into a selected memory cell among a plurality of memory cells, the method comprising: Execute multiple programming cycles, the multiple programming cycles including: a programming voltage application operation that applies a programming voltage to the selected memory cell, and a verification operation that verifies at least one of the programming state and the erase state of the selected memory cell; In the verification operation included in at least one programming loop corresponding to a specific programming state among the plurality of programming loops, the programming state of the memory cell among the selected memory cells that is programmed to the specific programming state is verified. After the verification operation for the specific programming state passes, a minimum programming voltage is applied to the selected memory cell; and After the minimum programming voltage is applied to the selected memory cell, the erase state of the memory cell among the selected memory cells that was programmed to be erased is verified in the verification operation included in the at least one programming cycle corresponding to the specific programming state.

8. The method of claim 7, wherein the particular programming state includes a programming state among a plurality of programming states having a higher threshold voltage than the other programming states.

9. The method of claim 7, wherein the verification of the programming state comprises: The programming state of the memory cell programmed to the specific programming state is verified by applying a first verification voltage to the selected word line connected to the selected memory cell. The verification of the erase state includes verifying the erase state of the memory cell programmed into the erase state by applying a second verification voltage lower than the first verification voltage to the selected word line.

10. The method of claim 9, wherein the second verification voltage includes a negative verification voltage.

11. The method of claim 9, wherein the verification of the erasure state comprises: When the threshold voltage of the memory cell programmed to the erase state is higher than the second verification voltage, it is determined that the verification operation for the erase state has failed.

12. The method of claim 11, further comprising: When the verification operation for the erase state fails for the selected memory cell among the plurality of memory cells, the data is programmed into other memory cells among the plurality of memory cells besides the selected memory cell.

13. A memory device, comprising: Multiple memory units; The peripheral circuitry is configured to execute multiple programming cycles, the multiple programming cycles including: a programming voltage application operation that applies a programming voltage to a selected memory cell among the multiple memory cells, and a verification operation that verifies the programming state of the selected memory cell; as well as A programming operation controller is configured to control the peripheral circuitry to program data into the selected memory cell according to the plurality of programming cycles. The programming operation controller controls the peripheral circuitry to verify, during the verification operation, the programming state of a selected memory cell programmed into any one of a plurality of programming states, applies a minimum programming voltage to the selected memory cell after the verification operation of the plurality of programming states passes, and verifies the erase state of a selected memory cell programmed into an erase state, the plurality of programming states being distinguished based on a plurality of threshold voltages.

14. The memory device of claim 13, wherein the programming operation controller controls the peripheral circuitry to verify the erase state of the memory cell programmed to the erase state after a verification operation of the plurality of programming states has passed.

15. The memory device of claim 13, wherein the programming operation controller controls the peripheral circuitry to verify, in a verification operation of at least one programming cycle corresponding to a specific programming state among the plurality of programming cycles, the programming state of the selected memory cells programmed to the specific programming state and the erase state of the selected memory cells programmed to the erase state, and The specific programming state includes the programming state among the plurality of programming states that has a higher threshold voltage than the other programming states.

16. The memory device of claim 13, wherein the programming operation controller controls the peripheral circuitry to apply a first verification voltage to a selected word line connected to the selected memory cell, and to apply a second verification voltage to the selected word line, the first verification voltage being used to verify the programming state of the memory cell programmed to the programming state, and the second verification voltage being used to verify the erasure state of the memory cell programmed to the erasure state. The second verification voltage is lower than the first verification voltage.

17. The memory device of claim 16, wherein the second verification voltage includes a negative verification voltage.

18. The memory device of claim 16, wherein when the threshold voltage of the memory cell programmed to the erase state is higher than the second verification voltage, the programming operation controller determines that the verification operation for the erase state has failed.

19. The memory device of claim 18, wherein when the verification operation for the erase state has failed for the selected memory cell among the plurality of memory cells, the programming operation controller controls the peripheral circuitry to program the data into the other memory cells among the plurality of memory cells besides the selected memory cell.

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