Programming method of memory, memory and storage system

Abstract

The application provides a memory programming method, a memory and a storage system, and relates to the technical field of storage. The method comprises the following steps: in a programming verification process of synchronous programming of at least two memory units, obtaining a programming verification result of the at least two memory units on an mth data state in an nth programming pulse cycle stage; in response to the fact that there is a memory unit with a programming verification failure in the at least two memory units and the verification number reaches a maximum verification number, disabling the memory unit with the programming verification failure, and verifying an (m+1)th data state in the nth programming pulse cycle stage. In the programming verification process, when there is a bad block to be disabled after the maximum verification number is reached, it is not necessary to enter a next programming pulse cycle stage for programming and then perform programming verification, and the programming verification of a subsequent data state is directly performed in the current programming pulse cycle stage, so that the efficiency of the programming verification is improved.

Description

Technical Field

[0001] This application relates to the field of storage technology, and in particular to a programming method for a memory, a memory, and a storage system. Background Technology

[0002] Three-dimensional (3D) memory supports multi-plane programming, meaning that memory cells in different memory blocks can be programmed simultaneously.

[0003] The programming process is implemented through Increment Step Pulse Program (ISPP). In each pulse phase of ISPP, a programming voltage of a certain pulse width is applied for programming, and verification is performed by a verification voltage after the programming voltage is applied.

[0004] However, when there are corrupted bad blocks (GBBs) in multiple storage blocks, the verification process of bad blocks will affect the programming process of normal storage blocks, resulting in low programming efficiency. Summary of the Invention

[0005] This application provides a method for programming a memory, a memory, and a storage system, which can improve programming verification efficiency. The technical solution is as follows:

[0006] On the one hand, a method for programming a memory is provided, the method comprising:

[0007] During the programming verification process of synchronous programming of multiple memory blocks, the programming verification result of the multiple memory blocks for the m-th data state in the nth programming pulse cycle phase is obtained, where n and m are both positive integers;

[0008] In response to the existence of a storage block among the plurality of storage blocks that has failed programming verification, and the verification count for the m-th data state has reached the maximum verification count, the storage block that failed programming verification is disabled, and the (m+1)-th data state is verified in the n-th programming pulse cycle phase.

[0009] In an optional embodiment, the verification of the (m+1)th data state in the nth programming pulse cycle phase includes:

[0010] During the nth programming pulse cycle, the programming threshold voltage corresponding to the (m+1)th data state is obtained;

[0011] Determine the programming pulse voltage corresponding to the memory blocks other than the disabled memory blocks among the plurality of memory blocks;

[0012] The programming pulse voltage is compared with the programming threshold voltage corresponding to the (m+1)th data state;

[0013] The (m+1)th data state is verified based on the comparison between the programming pulse voltage and the programming threshold voltage corresponding to the (m+1)th data state.

[0014] In an optional embodiment, the method further includes:

[0015] In response to the existence of a storage block in the plurality of storage blocks where programming verification has failed, and the number of verifications for the m-th data state has not reached the maximum number of verifications, the m-th data state is verified in the (n+1)th programming pulse cycle phase.

[0016] In an optional embodiment, the method further includes:

[0017] In response to the successful programming verification of the plurality of storage blocks, and since the current programming verification process is not the first verification process in the nth programming pulse cycle phase, the subsequent data states of the current data state are verified in the nth programming pulse cycle phase.

[0018] In an optional embodiment, the method further includes:

[0019] In response to the successful programming verification of the plurality of storage blocks, and since the current programming verification process is the first verification process in the nth programming pulse cycle phase, the m+1th data state is verified in the (n+1)th programming pulse cycle phase.

[0020] In an optional embodiment, the verification of the (m+1)th data state in the (n+1)th programming pulse cycle phase includes:

[0021] Obtain a data state verification threshold, which represents the total number of data states that the plurality of storage blocks need to be programmed to achieve;

[0022] In response to the (m+1)th data state failing to reach the data state verification threshold, the (m+1)th data state is verified during the (n+1)th programming pulse cycle phase.

[0023] In an optional embodiment, the method further includes:

[0024] The programming pulse loop ends when the (m+1)th data state reaches the data state verification threshold.

[0025] In an optional embodiment, the method further includes:

[0026] If, in response to the existence of a memory block among the plurality of memory blocks that has not reached the programming threshold voltage corresponding to the m-th data state, it is determined that there is a memory block among the plurality of memory blocks that has failed programming verification;

[0027] In response to the plurality of memory blocks reaching the programming threshold voltage corresponding to the m-th data state, it is determined that the programming verification of the plurality of memory blocks is successful.

[0028] In an optional embodiment, the method further includes:

[0029] In response to the fact that the memory cell of the target memory block among the plurality of memory blocks does not reach the programming threshold voltage corresponding to the m-th data state after programming, it is determined that the programming verification of the target memory block has failed.

[0030] On the other hand, a memory is provided, the memory comprising: a memory array unit and a peripheral logic unit, the memory array unit comprising a plurality of memory blocks, and the peripheral logic unit comprising a control circuit;

[0031] The control circuit is configured to, during the programming verification process of synchronous programming of multiple memory blocks, obtain the programming verification result of the multiple memory blocks for the m-th data state in the nth programming pulse cycle phase, where n and m are both positive integers;

[0032] The control circuit is further configured to disable the memory block that failed programming verification in response to the presence of a memory block that failed programming verification among the plurality of memory blocks, and to verify the (m+1)th data state in the nth programming pulse cycle phase when the verification count for the mth data state reaches the maximum verification count.

[0033] In an optional embodiment, the control circuit is further configured to: acquire the programming threshold voltage corresponding to the (m+1)th data state during the nth programming pulse cycle phase; determine the programming pulse voltage corresponding to the other memory blocks among the plurality of memory blocks excluding the disabled memory blocks; compare the programming pulse voltage with the programming threshold voltage corresponding to the (m+1)th data state; and verify the (m+1)th data state based on the comparison between the programming pulse voltage and the programming threshold voltage corresponding to the (m+1)th data state.

[0034] In an optional embodiment, the control circuit is further configured to verify the m-th data state in the (n+1)th programming pulse cycle phase in response to the presence of a memory block among the plurality of memory blocks that has failed programming verification and the verification count for the m-th data state has not reached the maximum verification count.

[0035] In an optional embodiment, the control circuit is further configured to verify subsequent data states of the current data state in the nth programming pulse cycle phase in response to the passing of the programming verification of the plurality of memory blocks and the fact that the current programming verification process is not the first verification process in the nth programming pulse cycle phase.

[0036] In an optional embodiment, the control circuit is further configured to verify the (m+1)th data state in the (n+1)th programming pulse cycle stage in response to the passing of the programming verification of the plurality of memory blocks, and the current programming verification process being the first verification process in the nth programming pulse cycle stage.

[0037] In an optional embodiment, the control circuit is further configured to acquire a data state verification threshold, the data state verification threshold being used to represent the total number of data states that the plurality of memory blocks need to be programmed to reach; and to verify the (m+1)th data state in the (n+1)th programming pulse cycle phase in response to the (m+1)th data state not reaching the data state verification threshold.

[0038] In an optional embodiment, the control circuit is further configured to terminate the programming pulse cycle in response to the (m+1)th data state reaching the data state verification threshold.

[0039] In an optional embodiment, the control circuit is further configured to determine that there is a memory block among the plurality of memory blocks that has failed programming verification if there is a memory block among the plurality of memory blocks that has not reached the programming threshold voltage corresponding to the m-th data state; and to determine that the programming verification of the plurality of memory blocks is successful if the plurality of memory blocks reach the programming threshold voltage corresponding to the m-th data state.

[0040] In an optional embodiment, the control circuit is further configured to determine that the programming verification of the target memory block has failed in response to the memory cell of the target memory block among the plurality of memory blocks failing to reach the programming threshold voltage corresponding to the m-th data state after programming.

[0041] On the other hand, a storage system is provided, the storage system comprising:

[0042] One or more memories as described in the above embodiments, and,

[0043] A memory controller coupled to the memory and configured to control the memory.

[0044] On the other hand, a computer-readable storage medium is provided, wherein instructions are stored therein, which, when executed on a control circuit, implement the memory programming method as described in any of the above embodiments.

[0045] The technical solution provided in this application may include the following beneficial effects:

[0046] During the programming verification process, when bad blocks are disabled after the maximum number of verifications, there is no need to enter the next programming pulse cycle stage for programming and then perform programming verification. Instead, subsequent data state programming verification is performed directly in the current programming pulse cycle stage. This improves the efficiency of programming verification, avoids increasing the number of programming pulse cycle stages, reduces programming time, and increases programming speed. Attached Figure Description

[0047] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0048] Figure 1 This is a schematic diagram of the structure of a 3D memory provided in an illustrative embodiment of this application;

[0049] Figure 2 This is a schematic diagram of a step-pulse voltage programming provided in an illustrative embodiment of this application;

[0050] Figure 3 This is a flowchart illustrating a multifaceted programming and verification process provided in an exemplary embodiment of this application;

[0051] Figure 4 This is a schematic diagram of the programming verification process provided in related technologies;

[0052] Figure 5 This is a flowchart of a memory programming method provided in an exemplary embodiment of this application;

[0053] Figure 6 This is a flowchart of a memory programming method provided in another exemplary embodiment of this application;

[0054] Figure 7 This is a flowchart of a memory programming method provided in another exemplary embodiment of this application;

[0055] Figure 8 This is a schematic diagram of the structure of a memory provided in an exemplary embodiment of this application;

[0056] Figure 9 This is a schematic diagram of the structure of a storage system provided in an exemplary embodiment of this application. Detailed Implementation

[0057] The embodiments of this application will now be described in further detail with reference to the accompanying drawings.

[0058] The memory programming method provided in this application embodiment can be applied to memory. This memory can be a 3D memory, such as a 3D NAND flash memory.

[0059] 3D memory is a multi-layered, stacked memory; schematically, this 3D memory is a 3D NAND flash memory. For example... Figure 1 As shown, the 3D memory 100 includes multiple memory strings 110 arranged in a direction parallel to the substrate's bearing surface, and multiple memory cells 120 in each memory string 110 are arranged in a direction perpendicular to the substrate's bearing surface. That is, the multiple memory cells included in the 3D memory are arranged in a three-dimensional array on the substrate, forming a memory array.

[0060] One end of the storage string 110 is connected to the bit line (BL), and the other end is connected to the source line (SL).

[0061] The memory cells in each memory string are also connected to memory cells in other memory strings via word lines (WL). For example, if each memory string can include 64 memory cells, then the 3D memory can include 64 word lines WL<63:0>, and each word line is connected to a portion of memory cells located on the same layer (i.e., having the same height relative to the substrate). It should be noted that 64 memory cells is only a specific example, and the application is not limited to this. In some embodiments, each memory string can include more than 64 memory cells, such as 128, 196, etc. In the 3D memory, the memory cells connected to the same word line are called a memory page, and all memory strings sharing a set of word lines are called a memory block.

[0062] The memory string 110 also includes an upper select transistor connected to the drain of the first memory cell and a lower select transistor connected to the source of the last memory cell. The upper select transistor is also called a top select gate (TSG) or drain select transistor. The lower select transistor is also called a bottom select gate (BSG) or source select transistor.

[0063] The gate of the TSG is connected to the drain select line (DSL), the source of the TSG is connected to the drain of the first memory cell, and the drain of the TSG is connected to the bit line.

[0064] The gate of the BSG is connected to the source select line (SSL), the drain of the BSG is connected to the source of the last memory cell, and the source of the BSG is connected to the source line.

[0065] Depend on Figure 1 It is known that the memory cells in memory string 110 share a set of memory lines (WL) with the memory cells in other memory strings. Assuming each memory string includes m+1 memory cells, the 3D memory can include m+1 WLs: WL0 to WLm, where m is an integer greater than 1. Each WL is connected to each memory cell located on the same layer (i.e., at the same height relative to the substrate's bearing surface). Alternatively, it can be understood that the control gates of each memory cell located on the same layer, and the gate connection lines between each control gate, constitute a WL.

[0066] Based on the amount of data that a storage unit can store, storage units can be classified into single-level cells (SLC), multi-level cells (MLC), tri-level cells (TLC), and quadri-level cells (QLC). Each SLC can store 1 bit of data, each MLC can store 2 bits, each TLC can store 3 bits, and each QLC can store 4 bits. In 3D memory, the data stored in storage units located in the same layer can form k storage pages, where k is the number of bits of data that each storage unit can store.

[0067] In this embodiment, the storage cell in the 3D memory can be a floating-gate field-effect transistor (FET) or a charge-trap FET, or other FET capable of storing data. The TSG and BSG can be ordinary FETs or FETs capable of storing data. The floating-gate FET includes a source, a drain, and two gates. Both gates are conductors, and one is a control gate (CG), while the other is a floating gate (FG), referred to simply as a floating gate. The control gate is used to connect word lines, and the floating gate is used as a data storage cell. The charge-trap FET includes a source, a drain, a control gate, and a charge-trap layer. This charge-trap layer is used as a data storage cell and is made of an insulating material such as silicon nitride. The following description uses a floating-gate FET as an example to illustrate the data writing principle of the storage cell.

[0068] When writing data into a memory cell, a programming voltage is applied to the control gate of the floating-gate field-effect transistor (FET), causing electrons in the FET's channel to tunnel to the floating gate. By controlling the magnitude of this programming voltage, the number of electrons tunneling to the floating gate can be controlled, thereby controlling the threshold voltage Vth of the FET. Generally, the higher the amount of charge stored in the floating gate, the higher the threshold voltage Vth of the FET. It is understandable that different threshold voltages Vth require different voltages applied to the control gate to turn the FET on. Therefore, the magnitude of the threshold voltage Vth of the FET reflects the content of the stored data.

[0069] It should be understood that in 3D memory, the channels of each memory cell in each memory string can be connected sequentially to form a columnar structure perpendicular to the substrate.

[0070] Currently, the main programming method used in memory programming is Increment Step Pulse Program (ISPP). During the programming process, the programming voltage is not applied all at once, but is increased step by step until the voltage meets the programming requirements.

[0071] This is illustrative; please refer to it. Figure 2 It illustrates an ISPP programming diagram provided in an exemplary embodiment of this application, such as Figure 2 As shown, the programming process includes a programming phase and a verification phase. First, in the first pulse phase 210, an initial voltage is applied to the selected word line corresponding to the selected memory cell, which is the programming phase. Then, it is verified whether the initial voltage reaches the required programming voltage, which is the verification phase. If it does not reach the required programming voltage, a voltage step size ΔVpp is added to the initial voltage to obtain a second pulse voltage. This second pulse voltage is then applied to the selected word line corresponding to the selected memory cell in the second pulse phase 220, which is another programming phase of the step-programming process. The verification phase continues to check whether the second pulse voltage reaches the required programming voltage. This process is repeated until the pulse voltage applied to the selected word line reaches the required programming voltage, at which point programming stops.

[0072] When programming the memory, for example, an MLC can be configured to store two data numbers per memory cell represented by four Vth ranges (data states), a TLC can be configured to store three data numbers per memory cell represented by eight Vth ranges (data states), a QLC can be configured to store four data numbers per memory cell represented by sixteen Vth ranges (data states), and so on.

[0073] For example, when the 3D NAND flash memory is MLC flash memory, the storage cells of the 3D NAND flash memory can be programmed into four states corresponding to bit codes 11, 10, 01, and 00 using verification voltages PV1, PV2, and PV3, namely programming states P0 (default is erase state), P1, P2, and P3. In another embodiment, when the 3D NAND flash memory is TLC 3D NAND flash memory, the storage cells of the 3D NAND flash memory can be programmed into eight data states corresponding to bit codes 111, 110, 010, 011, 001, 000, 100, and 101 using verification voltages PV1-PV7 based on the first verification process.

[0074] 3D NAND supports multi-plane programming, where each plane (also known as a block) contains multiple memory cells, and memory cells in different blocks can be programmed simultaneously. For example, in multi-plane programming, memory cell 0 in block 0, memory cell 1 in block 1, and memory cell 2 in block 2 are programmed simultaneously.

[0075] Indicative Figure 3 This is a flowchart illustrating a multifaceted programming and verification process provided in an exemplary embodiment of this application. For example... Figure 3 As shown, the process includes the following steps.

[0076] Step 301: Apply the programming pulse.

[0077] That is, programming pulse voltages are applied to the memory cells in the multiple memory blocks that need to be programmed, thereby programming the memory cells. When the programming pulse voltage is applied, voltage is applied to the word line corresponding to the memory cell.

[0078] Step 302, Programming verification and error bit counting.

[0079] That is, verifying whether the aforementioned programming pulse voltage has reached the programming threshold voltage required for the data state. Here, the error bit count refers to verifying the number of memory blocks in the multi-sided programming that have reached the programming threshold voltage corresponding to the data state, thereby determining whether any memory blocks have not yet reached the currently required data state. In some embodiments, verifying whether the memory cells in the memory block have reached the programming threshold voltage determines whether the memory block has reached the required data state. Optionally, determining the number of memory cells in the memory block that have not reached the programming threshold voltage; when the number of memory cells that have not reached the programming threshold voltage reaches a certain threshold, it is determined that the memory block has not reached the required data state, i.e., the memory block is a bad block.

[0080] Step 303: Determine whether the verified data state has reached the maximum data state.

[0081] When the maximum number of data states is reached, it means that the programming of all data states has been successful; when the maximum number of data states is not reached, it means that some data states have not yet been verified.

[0082] Step 304: When the maximum data state is reached, the programming ends.

[0083] In some embodiments, the voltage threshold is reached by a single pulse voltage or by multiple pulse voltages.

[0084] For example, taking TLC (Transmission Linear Cell) as an example, TLC has 8 data states, of which 1 data state (state 0) is the erase state, and 7 data states (states 1 to 7) are the programming states, which use the ISPP (Intense Pulse Programming) programming method. Based on practical experience, it can be estimated how many programming pulses, or programming verifications, are required to reach state 1. For example, reaching state 1 requires 6 programming verifications; reaching state 2 requires 9 programming verifications. Generally, the higher the data state, the more programming verifications are required. In other words, the preset number of programming verifications is related to the number of bits in the data state; generally, the higher the number of bits in the data state, the greater the preset number of programming verifications required for that data state.

[0085] Optionally, if the maximum data state is not reached, the programming pulse continues to be applied, and the applied pulse voltage is gradually increased according to the pulse voltage application method of the ISPP.

[0086] Figure 4 This is a schematic diagram of the programming verification process provided in related technologies, that is, an expanded explanation of the implementation of step 302 above in related technologies. For example... Figure 4 As shown, in related technologies, the programming verification process includes the following steps.

[0087] Step 401, verify the error bit count.

[0088] That is, in the programming pulse cycle stage, after applying programming pulse voltage to the memory cells in multiple memory blocks, the memory cells are programmed and verified, and the programming verification results of each memory cell in multiple memory blocks are determined.

[0089] Step 402: Determine whether all storage blocks have passed the data state verification.

[0090] That is, it determines whether there are any storage blocks that have failed the current data state verification. In some embodiments, when a storage cell in a storage block fails the data state verification, the storage block fails the data state verification; or, when the number of storage cells in a storage block that have failed the data state verification reaches a certain threshold, the storage block fails the data state verification.

[0091] Step 403: When multiple storage blocks pass data state verification, increment the data state by 1.

[0092] That is, the current data state + 1 is taken as the data state to be verified, and the next programming pulse loop is performed to verify the data state to be verified.

[0093] When all memory blocks have passed data state verification, it means that the current data state programming is complete and the next data state can be verified. Therefore, the next programming pulse cycle begins, and the next data state is programmed and verified.

[0094] Step 404: When there are multiple storage blocks that fail the data state verification, determine whether the number of verification attempts for the current data state has reached the maximum number of attempts.

[0095] Step 405: When the number of verifications for the current data state has not reached the maximum number, proceed to the next programming pulse loop.

[0096] In the next programming pulse cycle, the current data state is verified again.

[0097] Step 406: When the number of verifications for the current data state reaches the maximum, disable the storage block that failed verification.

[0098] Optionally, after disabling the storage block that failed verification, the next programming pulse cycle is performed for the storage block that successfully verified, and the next data state is verified.

[0099] Because memory cells have a limited lifespan or other physical defects that can cause programming failures, when the maximum number of data state verifications is reached and the memory block fails to meet the programming voltage requirements, the memory block is considered damaged and disabled. For memory blocks that have successfully verified their data state, the next programming pulse cycle continues, and the next data state is verified.

[0100] In the programming verification process provided by related technologies, when bad blocks are present, the number of verifications for the same data state will increase due to the impact of bad blocks. During multiple pulse cycles, the programming pulse voltage of other successfully verified memory blocks continues to rise to the subsequent data state, while the programming verification process is still in the data state where bad blocks cannot pass. This results in low programming verification efficiency for normal memory blocks, thus leading to low overall programming efficiency and slow programming speed.

[0101] In illustrative terms, during multi-faceted programming, synchronous programming is performed on memory blocks 0 / 1 / 2 / 3. Memory block 0 is a bad block, and the maximum number of verification loops is 10. Under normal circumstances, the memory cells in memory block 0 can pass data state 3 during the 5th verification. However, when the programming pulse loop reaches the 10th time, the memory cells in memory block 0 have not yet passed data state 3, so memory block 0 is identified as a bad block and disabled. The other memory blocks have passed data state 5 by the 10th time of the programming pulse loop, but data states 4 and 5 have not yet been verified. Therefore, two additional programming pulse loops are needed to pass the verification of data states 4 and 5.

[0102] Figure 5 This is a flowchart of a memory programming method provided in an exemplary embodiment of this application, taking the application of this method in 3D memory as an example. Figure 5 As shown, the method includes:

[0103] Step 501: During the programming verification process of synchronous programming of multiple storage blocks, obtain the programming verification result of the m-th data state of the multiple storage blocks in the nth programming pulse cycle phase, where n and m are both positive integers.

[0104] In some embodiments, synchronous programming of multiple storage blocks is typically implemented as multi-faceted programming, that is, synchronous programming is performed on storage cells in different storage blocks. Optionally, at least two selected storage cells are synchronously programmed, wherein the selected storage cell is the storage cell selected for data writing, and the storage cells other than the selected storage cells are called deselected storage cells.

[0105] Optionally, a programming voltage V is applied to a selected word line. pgm Simultaneously, a conduction voltage V can be applied to both the unselected (unselected) and unselded (unselected) WL. pass The on-state voltage V pass Used to turn on all the deselected memory cells connected to the deselect word line (unsel WL) so that the selected memory cell is connected to sel BL.

[0106] After applying the programming voltage, the programming of selected memory cells in multiple memory blocks is verified, and the programming verification result of each selected memory cell is determined. The programming verification result indicates whether the selected memory cell has reached the programming voltage corresponding to the data state. The programming verification results of multiple memory blocks are obtained based on the programming verification results of each selected memory cell.

[0107] Since at least two selected memory cells are programmed synchronously, in each programming pulse cycle phase, at least two selected memory cells are simultaneously applied programming pulse voltage and simultaneously perform programming verification. That is, at least two selected memory cells perform programming verification for the same data state in the same programming pulse cycle phase. For example, in this embodiment, at least two selected memory cells in multiple memory blocks perform programming verification for the m-th data state in the nth programming pulse cycle phase and obtain the programming verification result.

[0108] The programming verification results of at least two storage units for the m-th data state in the nth programming pulse cycle include any one of the following: 1. Both pass; 2. Neither pass; 3. Partially pass.

[0109] It is understandable that the programming voltage V pgm The voltage is typically high, thus allowing a large voltage difference to be created between the control gate and the channel of the selected memory cell. This enables electrons in the channel to tunnel to the floating gate of the selected memory cell, thereby storing data. Furthermore, by adjusting the programming voltage V... pgm The size of the value can be adjusted to change the number of electrons stored in the floating gate, which in turn can adjust the threshold voltage Vth of the selected memory cell.

[0110] Due to the on-voltage V pass Typically below the programming voltage V pgm Therefore, the voltage difference between the control gate and the channel of the deselected memory cell connected to unsel WL is relatively small, thus preventing electrons in the channel from tunneling to the floating gate. For the deselected memory cells connected to sel WL in the deselected memory string, since the channel of that deselected memory string is floating, the voltage difference between the control gate and the channel of the deselected memory cell connected to sel WL is also relatively small, again preventing electrons in the channel from tunneling to the floating gate. In other words, when programming a selected memory cell, neither the deselected memory cells connected to unsel WL nor those connected to sel WL will be programmed; that is, programming of the deselected memory cells is suppressed.

[0111] Step 502: In response to the existence of a storage block that failed programming verification among multiple storage blocks, and the verification count for the m-th data state reaching the maximum verification count, disable the storage block that failed programming verification, and verify the (m+1)-th data state in the n-th programming pulse cycle phase.

[0112] In some embodiments, the maximum number of verifications for the m-th data state is reached when the m-th data state is verified through the programming pulse cycle phase with the maximum number of verifications, and there is a storage block that still fails the verification of the m-th data state, i.e., the maximum number of verifications for the m-th data state is reached.

[0113] When the number of verifications for the m-th data state reaches the maximum number of verifications, it means that the storage block that failed verification cannot be programmed normally. It may become a bad block due to its lifespan or other physical defects. Therefore, the bad block that failed verification is disabled, and for the other storage blocks that passed verification, the verification of the (m+1)-th data state is performed in the current n-th programming pulse cycle phase.

[0114] In other words, without entering the (n+1)th programming pulse cycle stage to continue increasing and applying the programming voltage, the subsequent data states of the normal memory block can be verified in the current programming pulse cycle stage until the data state that the normal memory block has not yet been programmed to reach is verified, and then the subsequent programming pulse cycle process can continue.

[0115] In some embodiments, in response to the existence of at least two memory blocks that have not reached the programming threshold voltage corresponding to the m-th data state, it is determined that at least two memory blocks have failed programming verification; in response to the existence of at least two memory blocks that have reached the programming threshold voltage corresponding to the m-th data state, it is determined that at least two memory blocks have successfully completed programming verification.

[0116] In some embodiments, in response to the fact that the memory cell of the target memory block among the plurality of memory blocks does not reach the programming threshold voltage corresponding to the m-th data state after programming, it is determined that the programming verification of the target memory block has failed.

[0117] In summary, the method provided in this embodiment, during the programming verification process, when bad blocks are disabled after the maximum number of verifications, does not require entering the next programming pulse cycle stage for programming and then performing programming verification. Instead, it directly performs subsequent data state programming verification in the current programming pulse cycle stage, thereby improving the efficiency of programming verification, avoiding an increase in the number of programming pulse cycle stages, reducing programming time, and increasing programming speed.

[0118] In an optional embodiment, the branches that lead to the programming verification results for at least two storage blocks are also different. Figure 6 This is a flowchart of a programming method provided by another exemplary embodiment of this application, such as... Figure 6 As shown, the method includes:

[0119] Step 601: During the programming verification process of synchronous programming of multiple storage blocks, obtain the programming verification result of the m-th data state of the multiple storage blocks in the nth programming pulse cycle phase, where n and m are both positive integers.

[0120] After applying the programming voltage, the programming of selected memory cells in multiple memory blocks is verified, and the programming verification result of each memory cell is determined. The programming verification result indicates whether the memory cells in the multiple memory blocks have reached the programming voltage corresponding to the data state.

[0121] Step 602: In response to the existence of a storage block that failed programming verification among multiple storage blocks, and the verification count for the m-th data state reaching the maximum verification count, disable the storage block that failed programming verification, and verify the (m+1)-th data state in the n-th programming pulse cycle phase.

[0122] When the number of verifications for the m-th data state reaches the maximum number of verifications, it means that the storage block that failed verification cannot be programmed normally. It may become a bad block due to its lifespan or other physical defects. Therefore, the bad block that failed verification is disabled, and for the other storage blocks that passed verification, the verification of the (m+1)-th data state is performed in the current n-th programming pulse cycle phase.

[0123] The maximum number of verifications is preset and illustrative. For data state 1, the maximum number of verifications is set to 5; for data state 2, the maximum number of verifications is set to 7; and for data state 3, the maximum number of verifications is set to 8.

[0124] Step 603: In response to the existence of a storage block in multiple storage blocks where programming verification has failed, and the number of verifications for the m-th data state has not reached the maximum number of verifications, the m-th data state is verified in the (n+1)th programming pulse cycle phase.

[0125] Since the data state is not necessarily reached directly with a single programming voltage, but may be reached by gradually increasing the programming voltage multiple times, when the number of verifications for the m-th data state does not reach the maximum number of verifications and the memory block programming verification fails, the possible situations include at least one of the following: 1. There is a bad block in the memory block, which cannot reach the m-th data state; 2. The memory cells in multiple memory blocks are gradually increased to the m-th data state by applying programming pulse voltage.

[0126] In order to identify bad blocks from multiple memory blocks and ensure that the bad blocks are not caused by the programming pulse voltage gradually increasing to the m-th data state, the next programming pulse cycle stage is entered when the number of verifications for the m-th data state has not reached the maximum number of verifications. That is, the (n+1)-th programming pulse cycle stage. After the programming pulse voltage is applied in the (n+1)-th programming pulse cycle stage, the verification of the m-th data state continues until the m-th data state is successfully verified, or until the number of verifications for the m-th data state reaches the maximum number of verifications.

[0127] Step 604: In response to multiple memory block programming verifications passing, and the current programming verification process being a non-first verification process in the nth programming pulse cycle phase, the subsequent data states of the current data state are verified in the nth programming pulse cycle phase.

[0128] When multiple memory blocks pass verification in the nth programming pulse cycle, it includes any of the following situations: 1. Multiple memory blocks pass verification directly in the nth programming pulse cycle, that is, in the nth programming pulse cycle, selected memory cells in multiple memory blocks directly pass the verification of the mth data state after the programming pulse voltage is applied. In other words, multiple memory blocks pass the verification of the mth data state in the first verification in the nth programming pulse cycle; 2. Multiple memory blocks fail the verification of the mth data state in the first verification in the nth programming pulse cycle, and after the failing memory block is disabled, the other memory blocks continue to verify the (m+1)th data state and pass the verification of the (m+1)th data state. Then the verification of the (m+1)th data state by the other memory blocks is not the first verification process in the nth programming pulse cycle.

[0129] Because other memory blocks are simultaneously applying programming pulse voltages to bad blocks through multiple programming pulse cycles, and also increasing the programming pulse voltage through multiple programming pulse cycles, that is, when a memory block is identified as a bad block and disabled in the nth programming pulse cycle because it fails the verification of the mth data state, the selected memory cells in other memory blocks may have already reached the (m+k)th data state, where k is a positive integer. Therefore, in the nth programming pulse cycle, when other memory blocks pass the verification of the (m+1)th data state, the verification of the (m+2)th data state can continue until there are memory blocks in other memory blocks that have failed the verification. Then, the subsequent programming pulse cycle stages are executed to increase the programming pulse voltage and perform verification.

[0130] Step 605: In response to the successful programming verification of multiple memory blocks, and the fact that the current programming verification process is the first verification process in the nth programming pulse cycle stage, the (m+1)th data state is verified in the (n+1)th programming pulse cycle stage.

[0131] If multiple memory blocks pass programming verification, and multiple memory blocks pass the verification of the m-th data state directly in the nth programming pulse cycle stage, it means that the multiple memory blocks are programmed normally for the m-th data state. Therefore, the next programming pulse cycle stage, i.e. the (n+1)th programming pulse cycle stage, is entered to verify the next data state, i.e., to verify the (m+1)th data state.

[0132] In some embodiments, before verifying the (m+1)th data state in the (n+1)th programming pulse cycle phase, a data state verification threshold is first obtained. The data state verification threshold is used to represent the total number of data states that the memory cells in multiple memory blocks need to be programmed to reach. For example, if a TLC has a total of 8 data states, of which 1 data state (state 0) is used as the erase state and 7 data states (states 1 to 7) are used as programming states, then at least two memory cells need to be programmed to reach 7 programming states, and state 0 is the default data state.

[0133] If the (m+1)th data state fails to reach the data state verification threshold, the (m+1)th data state is verified during the (n+1)th programming pulse cycle. If the (m+1)th data state reaches the data state verification threshold, it indicates that all data states have been successfully programmed and verified, and the programming pulse cycle ends. In some embodiments, it is determined whether the initial verification level has reached the maximum verification level. When the initial verification level reaches the maximum verification level, it indicates that the (m+1)th data state has reached the data state verification threshold, and the programming pulse cycle ends.

[0134] In summary, the method provided in this embodiment, during the programming verification process, when bad blocks are disabled after the maximum number of verifications, does not require entering the next programming pulse cycle stage for programming and then performing programming verification. Instead, it directly performs subsequent data state programming verification in the current programming pulse cycle stage, thereby improving the efficiency of programming verification, avoiding an increase in the number of programming pulse cycle stages, reducing programming time, and increasing programming speed.

[0135] The method provided in this embodiment, when multiple memory blocks pass programming verification, first determines whether the programming verification process is the first verification process in the nth programming pulse cycle stage. This determines whether the multiple memory blocks directly passed the verification of the mth data state, or whether other memory blocks passed the verification of subsequent data states after disabling bad blocks. Thus, in the nth programming pulse cycle stage, the verification work of other memory blocks on the data states that have not yet been verified is completed, avoiding the time consumption of redundant programming pulse cycle stages and improving programming efficiency.

[0136] Figure 7 This is a flowchart of an overall solution provided by an exemplary embodiment of this application, such as... Figure 7 As shown, the programming method includes the following steps.

[0137] Step 701, verify the error bit count.

[0138] Verify Count check (VFC check) is used to statistically summarize the verification results of each storage block in multi-faceted programming. For example, in multi-faceted programming, four storage blocks (blocks 0 / 1 / 2 / 3) are being programmed synchronously. The VFC check counts the verification results for each of the four storage blocks. For data state 3, the verification result for block 0 is 0, indicating verification passed; the verification result for block 1 is 0, indicating verification passed; the verification result for block 2 is 1, indicating verification failed; and the verification result for block 3 is 0, indicating verification passed. Each storage block includes one or more storage units as selected storage units for synchronous programming. When multiple selected storage units are included, if any selected storage unit fails verification, the storage block verification fails; or, if the number of selected storage units that fail verification reaches a certain threshold, the storage block verification fails.

[0139] Step 702: Determine whether all storage blocks have passed the verification.

[0140] To illustrate, for data state 3, it is determined whether all the memory cells in multiple memory blocks have reached the programming threshold voltage corresponding to data state 3. If they have all reached it, it means that multiple memory blocks have passed the verification. If there are memory cells in a memory block that have not reached data state 3, it means that there is a memory block among the multiple memory blocks that has failed the verification.

[0141] To illustrate, for data state 3, the verification result of block 0 is 0, indicating verification passed; the verification result of block 1 is 0, indicating verification passed; the verification result of block 2 is 1, indicating verification failed; and the verification result of block 3 is 0, indicating verification passed. Since the verification result of block 2 is 1, there are multiple storage blocks that failed verification.

[0142] Step 703: If multiple storage blocks pass the verification, determine whether the verification process is the first verification in the current programming pulse cycle phase.

[0143] When multiple storage blocks pass verification, there are two possible scenarios: Scenario 1: Multiple storage blocks pass verification directly without issue; Scenario 2: In the current programming pulse cycle, multiple storage blocks have had their bad blocks disabled due to reaching the maximum number of verifications, and other storage blocks pass subsequent data-state verifications. In Scenario 1, multiple storage blocks directly pass the first verification of the current programming pulse cycle. In Scenario 2, multiple storage blocks disable bad blocks after the first verification fails in the current programming pulse cycle, and other storage blocks pass subsequent data-state verifications. Therefore, depending on whether the verification process is the first verification of the current programming pulse cycle, it can be determined whether it falls under Scenario 1 or Scenario 2, and different subsequent processing can be applied to Scenario 1 and Scenario 2.

[0144] Step 704: If this verification process is the first verification in the current programming pulse cycle stage, then the current programming pulse cycle stage ends and the next programming pulse cycle stage begins to verify the next data state.

[0145] If the verification process is the first verification in the current programming pulse cycle phase, that is, corresponding to the above possible case 1, indicating that multiple memory blocks have directly passed the first verification in the current programming pulse cycle phase, then the current programming pulse cycle phase ends, the current data state is incremented by one, and the next programming pulse cycle phase is entered to verify the next data state.

[0146] Step 705: If the verification process is not the first verification in the current programming pulse cycle phase, verify the next data state in the current programming pulse cycle phase.

[0147] If the verification process is not the first verification in the current programming pulse cycle phase, that is, corresponding to the above possible case 2, it means that multiple storage blocks were disabled after the first verification in the current programming pulse cycle phase failed, and other storage blocks passed the subsequent data state verification in the subsequent verification. For other storage blocks, when they pass the data state verification once, they may continue to pass the next data state verification. Therefore, the next data state verification continues in the current programming pulse cycle phase.

[0148] In a schematic manner, four memory blocks are programmed and verified synchronously. During the verification of data state 3, block 2 fails the verification of data state 3, and the number of verification attempts reaches the maximum of 7, so block 2 is disabled. Blocks 0 / 1 / 3 may have passed data state 3 on the second verification attempt. In the subsequent 5 programming pulse cycles, blocks 0 / 1 / 3 continue to increase the programming pulse voltage 5 times, remaining in the verification of data state 3. After the 7th verification, block 2 is disabled, while blocks 0 / 1 / 3 continue to verify data state 4 in the current programming pulse cycle. When blocks 0 / 1 / 3 all pass the verification of data state 4, since blocks 0 / 1 / 3 are not the first to be verified in the current programming pulse cycle, they can continue to verify data state 5 in the current programming pulse cycle until a memory block in blocks 0 / 1 / 3 fails the verification of a subsequent data state, or until the data state verified by blocks 0 / 1 / 3 reaches the maximum data state.

[0149] Step 706: If there are multiple storage blocks that have failed verification, determine whether the number of verification attempts has reached the maximum number of verification attempts.

[0150] When multiple memory blocks fail verification, the following situations apply: 1) Multiple memory blocks are in the process of gradually increasing the programming pulse voltage to reach the programming threshold voltage; 2) Multiple memory blocks contain bad blocks and cannot reach the programming threshold voltage.

[0151] To distinguish between Case 1 and Case 2 above, a maximum number of verifications is set for judgment. When the number of verifications for the current data state has not reached the maximum number of verifications, it means that multiple memory blocks are gradually increasing the programming pulse voltage to reach the programming threshold voltage, which corresponds to Case 1 above. When the number of verifications for the current data state has reached the maximum number of verifications, it means that there are bad blocks in multiple memory blocks and the programming threshold voltage cannot be reached, which corresponds to Case 2 above.

[0152] Step 707: If the number of verifications has not reached the maximum number of verifications, end the current programming pulse cycle stage and enter the next programming pulse cycle stage to verify the current data state.

[0153] When multiple storage blocks have not reached the maximum number of verifications for the current data state, which corresponds to situation 1 above, it means that multiple storage blocks are gradually increasing the programming pulse voltage to reach the programming threshold voltage.

[0154] Indicatively, four memory blocks are programmed and verified synchronously. The four memory blocks need to go through two programming pulse cycle stages to reach the programming threshold voltage corresponding to data state 1. In the first programming pulse cycle stage, the four memory blocks failed the programming verification for data state 1, so they continued to enter the second programming pulse cycle stage. In the second programming pulse cycle stage, the programming voltage was increased and applied, and the programming verification for data state 1 continued.

[0155] Step 708: If the number of verification attempts reaches the maximum number of verification attempts, disable the storage blocks that failed verification.

[0156] When multiple storage blocks reach the maximum number of verifications for the current data state, which corresponds to situation 2 above, it indicates that there are bad blocks in multiple storage blocks, and the programming threshold voltage corresponding to the current data state cannot be reached.

[0157] To illustrate, four memory blocks are programmed and verified synchronously. The four memory blocks need to go through two programming pulse cycles to reach the programming threshold voltage corresponding to data state 1. The maximum number of verifications for data state 1 is 3. In the second programming pulse cycle, blocks 0 / 1 / 3 passed the verification for data state 1, while block 2 failed. Therefore, the third programming pulse cycle continues. In the third programming pulse cycle, block 2 still failed the verification for data state 1. Since the maximum number of verifications for data state 1 has been reached, block 2 is disabled.

[0158] In some embodiments, after disabling a failed storage block, programming continues using the remaining storage blocks; or, after disabling a failed storage block, a new storage block is determined from the storage cell array to reprogram the disabled storage block.

[0159] Specifically, after disabling a storage block that has failed verification, the next data state is verified during the current programming pulse cycle phase.

[0160] For other storage blocks that are not disabled in the current programming pulse cycle phase, the subsequent data states of the verified data states continue to be verified until a storage block fails the verification of a subsequent data state, or all data states have been verified.

[0161] Indicatively, during the third programming pulse cycle, block 2 still fails the verification for data state 1. Since the maximum number of verifications for data state 1 has been reached, block 2 is disabled. However, blocks 0 / 1 / 3 pass the verification for data state 1. Therefore, the third programming pulse cycle continues to verify whether blocks 0 / 1 / 3 pass the verification for data state 2. If data state 2 also passes, the third programming pulse cycle continues to verify whether blocks 0 / 1 / 3 pass the verification for data state 3, and so on.

[0162] In summary, the method provided in this embodiment, during the programming verification process, when bad blocks are disabled after the maximum number of verifications, does not require entering the next programming pulse cycle stage for programming and then performing programming verification. Instead, it directly performs subsequent data state programming verification in the current programming pulse cycle stage, thereby improving the efficiency of programming verification, avoiding an increase in the number of programming pulse cycle stages, reducing programming time, and increasing programming speed.

[0163] Figure 8 This is a schematic diagram of the structure of a memory provided in an embodiment of this application. For example... Figure 8 As shown, the memory includes peripheral circuitry 800 and a memory cell array 810;

[0164] The peripheral circuit 800 is used to write data to the memory cell array 810 and to read data from the memory cell array 810.

[0165] The peripheral circuitry 800 includes: a voltage generator 802, a page buffer / sensor amplifier 804, a column decoder / bit line (BL) driver 806, a row decoder / word line (WL) driver 808, a peripheral logic unit 812, a register 814, input / output circuitry 816, and a data bus 818. It should be understood that in some examples, it may also include... Figure 8 Additional peripheral circuitry not shown.

[0166] Page buffer / sensor amplifier 804 can be configured to read data from memory cell array 810 and program (write) data to memory cell array 810 according to control signals from peripheral logic unit 812. In one example, page buffer / sensor amplifier 804 can store a page of programming data (write data) to be programmed into a page of memory cell array 810. In another example, page buffer / sensor amplifier 804 can perform a programming verification operation to ensure that data has been correctly programmed into the memory cell coupled to a selected word line. In yet another example, page buffer / sensor amplifier 804 can also sense a low-power signal from a bit line representing a data bit stored in the memory cell and amplify a small voltage swing to a recognizable logic level during a read operation.

[0167] The column decoder / bit line driver 806 can be configured to be controlled by the peripheral logic unit 812 and to select one or more NAND memory strings by applying a bit line voltage generated from the voltage generator 802.

[0168] The line decoder / word line driver 808 can be configured to be controlled by the peripheral logic unit 812 and to select / deselect blocks of the memory cell array 810 and select / deselect word lines of the blocks. The line decoder / word line driver 808 can also be configured to use word line voltages (V) generated from the voltage generator 802. WL The line decoder / word line driver 808 drives the word lines. In some embodiments, the line decoder / word line driver 808 can also select / deselect and drive the source select gate line and the drain select gate line. Illustratively, the line decoder / word line driver 808 is configured to perform an erase operation on memory cells coupled to one or more selected word lines.

[0169] Voltage generator 802 can be configured to be controlled by peripheral logic unit 812 and generate word line voltages (e.g., read voltage, program voltage, pass voltage, local voltage, verification voltage, etc.), bit line voltages, and source line voltages to be supplied to memory cell array 810.

[0170] The peripheral logic unit 812 can be coupled to each of the peripheral circuits described above and is configured to control the operation of each peripheral circuit. The peripheral logic unit 812 includes the components described above. Figure 8 The control circuit shown is shown.

[0171] Register 814 can be coupled to peripheral logic unit 812 and includes a status register, a command register, and an address register for storing status information, command opcodes (OP codes), and command addresses for controlling the operation of each peripheral circuit. Input / output circuitry 816 can be coupled to peripheral logic unit 812 and acts as a control buffer to buffer control commands received from the host (not shown) and relay them to peripheral logic unit 812, as well as to buffer status information received from peripheral logic unit 812 and relay it to the host. Input / output circuitry 816 can also be coupled to column decoder / bitline driver 806 via data bus 818 and acts as a data input / output interface and data buffer to buffer data and relay it to or from memory cell array 810.

[0172] It should be emphasized that the peripheral circuit 800 is configured to perform the memory programming method provided in the embodiments of this disclosure on a selected memory cell row among a plurality of memory cell rows.

[0173] Figure 9 This is a structural block diagram of a storage system provided in an exemplary embodiment of this application, such as... Figure 9 As shown, the storage system 900 includes: one or more memories 910, and,

[0174] A memory controller 920 is coupled to the memory 910 and configured to control the memory 910.

[0175] The storage system 900 can be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having storage therein.

[0176] Optionally, the storage system 900 may include a host and a storage subsystem, the storage subsystem having one or more memories 910 and a memory controller 920. The host may be a processor of an electronic device (e.g., a central processing unit (CPU)) or a system-on-a-chip (SoC) (e.g., an application processor (AP)). The host may be configured to send data to the memory 910. Alternatively, the host may be configured to receive data from the memory 910.

[0177] According to some implementations, the memory controller 920 is also coupled to a host. The memory controller 920 can manage data stored in the memory 910 and communicate with the host.

[0178] In some implementations, the memory controller 920 is designed to operate in low duty cycle environments, such as secure digital (SD) cards, compact flash (CF) cards, universal serial bus (USB) flash drives, or other media used in electronic devices such as personal calculators, digital cameras, mobile phones, etc.

[0179] In some implementations, the memory controller 920 is designed to operate in a high duty cycle environment solid-state drive (SSD) or embedded multimedia card (eMMC), which serves as data storage for mobile devices such as smartphones, tablets, laptops, etc., as well as enterprise storage arrays.

[0180] The memory controller 920 can be configured to control the operation of the memory 910, such as read, erase, and program operations. The memory controller 920 can also be configured to manage various functions relating to data stored or to be stored in the memory 910, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. In some embodiments, the memory controller 920 is also configured to process error correction codes (ECC) relating to data read from or written to the memory 910.

[0181] The memory controller 920 can also perform any other suitable functions, such as formatting the memory 910. The memory controller 920 can communicate with external devices according to a specific communication protocol.

[0182] The memory controller 920 and one or more memories 910 can be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Memory (UFS) package or an eMMC package). That is, the memory system 900 can be implemented and packaged into different types of end electronic products.

[0183] Schematic illustration: The memory controller 920 and a single memory 910 can be integrated into a memory card. The memory card can include PC cards (PCMCIA, Personal Computer Memory Card International Association), CF cards, Smart Media (SM) cards, memory sticks, multimedia cards (MMC, RS-MMC, MMCmicro), SD cards (SD, miniSD, microSD, SDHC), UFS, etc. The memory card may also include a memory card connector that couples the memory card to the host computer.

[0184] Schematic, the memory controller 920 and multiple memories 910 can be integrated into a solid-state drive (SSD). In some embodiments, the storage capacity and / or operating speed of the SSD is greater than that of the memory card.

[0185] It is understood that the memory controller 920 can perform memory programming methods as provided in any embodiment of this disclosure.

[0186] This application provides a control circuit that includes programmable logic circuitry and / or program instructions. The control circuit can be used to implement the memory programming method provided in the foregoing embodiments of this application.

[0187] Indicative, such as Figure 9 The memory 910 shown includes: a memory array unit and a peripheral logic unit. The memory array unit includes multiple memory blocks, and each memory block includes a memory cell. The peripheral logic unit includes a control circuit.

[0188] The control circuit is configured to, during the programming verification process of synchronous programming of multiple memory blocks, obtain the programming verification result of the multiple memory blocks for the m-th data state in the nth programming pulse cycle phase, where n and m are both positive integers;

[0189] The control circuit is further configured to disable the memory block that failed programming verification in response to the presence of a memory block that failed programming verification among the plurality of memory blocks, and to verify the (m+1)th data state in the nth programming pulse cycle phase when the verification count for the mth data state reaches the maximum verification count.

[0190] In an optional embodiment, the control circuit is further configured to: acquire the programming threshold voltage corresponding to the (m+1)th data state during the nth programming pulse cycle phase; determine the programming pulse voltage corresponding to the other memory blocks among the plurality of memory blocks excluding the disabled memory blocks; compare the programming pulse voltage with the programming threshold voltage corresponding to the (m+1)th data state; and verify the (m+1)th data state based on the comparison between the programming pulse voltage and the programming threshold voltage corresponding to the (m+1)th data state.

[0191] In an optional embodiment, the control circuit is further configured to verify the m-th data state during the (n+1)th programming pulse cycle phase in response to a memory block programming verification failure and the verification count for the m-th data state not reaching the maximum verification count.

[0192] In an optional embodiment, the control circuit is further configured to verify subsequent data states of the current data state in the nth programming pulse cycle phase in response to the passing of the programming verification of the plurality of memory blocks and the fact that the current programming verification process is not the first verification process in the nth programming pulse cycle phase.

[0193] In an optional embodiment, the control circuit is further configured to verify the (m+1)th data state in the (n+1)th programming pulse cycle stage in response to the passing of the programming verification of the plurality of memory blocks, and the current programming verification process being the first verification process in the nth programming pulse cycle stage.

[0194] In an optional embodiment, the control circuit is further configured to acquire a data state verification threshold, the data state verification threshold being used to represent the total number of data states that the plurality of memory blocks need to be programmed to reach; and to verify the (m+1)th data state in the (n+1)th programming pulse cycle phase in response to the (m+1)th data state not reaching the data state verification threshold.

[0195] In an optional embodiment, the control circuit is further configured to terminate the programming pulse cycle in response to the (m+1)th data state reaching the data state verification threshold.

[0196] In an optional embodiment, the control circuit is further configured to determine that there is a memory block among the plurality of memory blocks that has failed programming verification if there is a memory block among the plurality of memory blocks that has not reached the programming threshold voltage corresponding to the m-th data state; and to determine that the programming verification of the plurality of memory blocks is successful if the plurality of memory blocks reach the programming threshold voltage corresponding to the m-th data state.

[0197] In an optional embodiment, the control circuit is further configured to determine that the programming verification of the target memory block has failed in response to the memory cell of the target memory block among the plurality of memory blocks failing to reach the programming threshold voltage corresponding to the m-th data state after programming.

[0198] In summary, the memory provided in this embodiment, during the programming verification process, when bad blocks are disabled after the maximum number of verifications, does not need to enter the next programming pulse cycle stage for programming and then perform programming verification. Instead, it directly performs subsequent data state programming verification in the current programming pulse cycle stage, thereby improving the efficiency of programming verification, avoiding an increase in the number of programming pulse cycle stages, reducing programming time, and increasing programming speed.

[0199] This application provides a computer-readable storage medium storing instructions that, when executed on a control circuit, implement the memory programming method provided in the foregoing embodiments of this application.

[0200] In this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance. The term "at least one" means one or more, and the term "multiple" means two or more, unless otherwise expressly defined.

[0201] In this application, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, the character " / " in this document generally indicates that the preceding and following related objects have an "or" relationship.

[0202] The above description is merely an exemplary embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A method for programming a memory, characterized in that, The method includes: In the programming verification process of synchronous programming of multiple memory blocks, the programming verification result of the m-th data state of the multiple memory blocks in the nth programming pulse cycle stage is obtained, where n and m are both positive integers, and programming pulse voltages are synchronously applied to at least two selected memory cells in the multiple memory blocks. In response to the existence of a storage block among the plurality of storage blocks that has failed programming verification, and the number of verifications for the m-th data state has reached the maximum number of verifications, the storage block that failed programming verification is disabled, and in the n-th programming pulse cycle phase, the storage block that has not been disabled is verified for the (m+1)-th data state, until the data state that the storage block that has not been disabled has not yet been programmed to be reached.

2. The method according to claim 1, characterized in that, The verification of the (m+1)th data state of the non-disabled memory blocks during the nth programming pulse cycle phase includes: During the nth programming pulse cycle, the programming threshold voltage corresponding to the (m+1)th data state is obtained; Determine the programming pulse voltage corresponding to the memory blocks other than the disabled memory blocks among the plurality of memory blocks; The programming pulse voltage is compared with the programming threshold voltage corresponding to the (m+1)th data state; The (m+1)th data state is verified based on the comparison between the programming pulse voltage and the programming threshold voltage corresponding to the (m+1)th data state.

3. The method according to claim 1, characterized in that, The method further includes: In response to the existence of a storage block in the plurality of storage blocks where programming verification has failed, and the number of verifications for the m-th data state has not reached the maximum number of verifications, the m-th data state is verified in the (n+1)th programming pulse cycle phase.

4. The method according to claim 1, characterized in that, The method further includes: In response to the successful programming verification of the plurality of storage blocks, and since the current programming verification process is not the first verification process in the nth programming pulse cycle phase, the subsequent data states of the current data state are verified in the nth programming pulse cycle phase.

5. The method according to claim 1, characterized in that, The method further includes: In response to the successful programming verification of the plurality of storage blocks, and since the current programming verification process is the first verification process in the nth programming pulse cycle phase, the m+1th data state is verified in the (n+1)th programming pulse cycle phase.

6. The method according to claim 5, characterized in that, The verification of the (m+1)th data state in the (n+1)th programming pulse cycle phase includes: Obtain a data state verification threshold, which represents the total number of data states that the plurality of storage blocks need to be programmed to achieve; In response to the (m+1)th data state failing to reach the data state verification threshold, the (m+1)th data state is verified during the (n+1)th programming pulse cycle phase.

7. The method according to claim 6, characterized in that, The method further includes: The programming pulse loop ends when the (m+1)th data state reaches the data state verification threshold.

8. The method according to any one of claims 1 to 7, characterized in that, The method further includes: If, in response to the existence of a memory block among the plurality of memory blocks that has not reached the programming threshold voltage corresponding to the m-th data state, it is determined that there is a memory block among the plurality of memory blocks that has failed programming verification; In response to the plurality of memory blocks reaching the programming threshold voltage corresponding to the m-th data state, it is determined that the programming verification of the plurality of memory blocks is successful.

9. The method according to any one of claims 1 to 7, characterized in that, The method further includes: In response to the fact that the storage cell of the target storage block among the plurality of storage blocks does not reach the programming threshold voltage corresponding to the m-th data state after programming, it is determined that the programming verification of the target storage block has failed.

10. A memory, characterized in that, The memory includes: a memory array unit and a peripheral logic unit. The memory array unit includes multiple memory blocks, and each memory block includes a memory cell. The peripheral logic unit includes a control circuit. The control circuit is configured to, during the programming verification process of synchronous programming of multiple memory blocks, acquire the programming verification result of the multiple memory blocks for the m-th data state in the nth programming pulse cycle phase, where n and m are both positive integers, wherein programming pulse voltages are synchronously applied to at least two selected memory cells in the multiple memory blocks. The control circuit is further configured to, in response to the presence of a memory cell in the plurality of memory blocks that has failed programming verification, and the verification count for the m-th data state reaching the maximum verification count, disable the memory block that failed programming verification, and in the n-th programming pulse cycle phase, verify the (m+1)-th data state of the memory block that was not disabled, until the data state that the memory block that was not disabled has not yet been programmed to reach is verified.

11. The memory according to claim 10, characterized in that, The control circuit is further configured to: acquire the programming threshold voltage corresponding to the (m+1)th data state during the nth programming pulse cycle phase; determine the programming pulse voltage corresponding to the other memory blocks among the plurality of memory blocks excluding the disabled memory blocks; compare the programming pulse voltage with the programming threshold voltage corresponding to the (m+1)th data state; and verify the (m+1)th data state based on the comparison between the programming pulse voltage and the programming threshold voltage corresponding to the (m+1)th data state.

12. The memory according to claim 10, characterized in that, The control circuit is further configured to, in response to the presence of a memory block among the plurality of memory blocks that has failed programming verification, and the verification count for the m-th data state has not reached the maximum verification count, verify the m-th data state during the (n+1)th programming pulse cycle phase.

13. The memory according to claim 10, characterized in that, The control circuit is further configured to verify subsequent data states of the current data state in the nth programming pulse cycle phase in response to the passing of the programming verification of the plurality of memory blocks and the fact that the current programming verification process is not the first verification process in the nth programming pulse cycle phase.

14. The memory according to claim 10, characterized in that, The control circuit is further configured to verify the (m+1)th data state in the (n+1)th programming pulse cycle stage in response to the passing of the programming verification of the plurality of memory blocks, and the current programming verification process being the first verification process in the nth programming pulse cycle stage.

15. The memory according to claim 14, characterized in that, The control circuit is further configured to acquire a data state verification threshold, which represents the total number of data states that the plurality of memory blocks need to be programmed to reach; and to verify the (m+1)th data state in the (n+1)th programming pulse cycle phase in response to the (m+1)th data state not reaching the data state verification threshold.

16. The memory according to claim 15, characterized in that, The control circuit is also configured to terminate the programming pulse cycle in response to the (m+1)th data state reaching the data state verification threshold.

17. The memory according to any one of claims 10 to 16, characterized in that, The control circuit is further configured to determine that there is a memory block among the plurality of memory blocks that has failed programming verification if there is a memory block among the plurality of memory blocks that has not reached the programming threshold voltage corresponding to the m-th data state; and to determine that the programming verification of the plurality of memory blocks is successful if the plurality of memory blocks reach the programming threshold voltage corresponding to the m-th data state.

18. The memory according to any one of claims 10 to 16, characterized in that, The control circuit is further configured to determine that the programming verification of the target memory block has failed in response to the memory cell of the target memory block among the plurality of memory blocks failing to reach the programming threshold voltage corresponding to the m-th data state after programming.

19. A storage system, characterized in that, The storage system includes: One or more memories as described in any one of claims 10 to 18, and, A memory controller coupled to the memory and configured to control the memory.

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