Method for manufacturing a mask structure / through-silicon via, semiconductor structure
By using a mask structure fabrication method that defines TSV regions within the chip's functional areas, the problem of difficult layout of traditional TSV technology on integrated circuit chips is solved, improving product yield and reliability, simplifying the process flow, and reducing costs.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- CHANGXIN MEMORY TECH INC
- Filing Date
- 2021-05-20
- Publication Date
- 2026-07-21
AI Technical Summary
Traditional TSV technology is difficult to deploy on integrated circuit chips, leading to a decrease in product yield or reliability, especially when the chip's functional structure is dense.
During the definition of chip functional areas, a mask structure is prepared to reserve or form TSV regions. Patterns are then transferred on the wafer using a patterned mask layer to avoid product yield reduction or reliability degradation caused by drilling.
It improved product yield and reliability, simplified the fabrication process of through-silicon vias (TSVs), and reduced costs.
Smart Images
Figure CN115376894B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to methods for preparing mask structures / through-silicon vias and semiconductor structures. Background Technology
[0002] With the increasing demand for thinner and lighter electronic products, integrated circuit device packaging technology has been developing towards thinner and smaller designs. Through Silicon Via (TSV) is an interconnect technology that allows 3D chip packaging to follow Moore's Law. Using TSV technology, multiple chips can be stacked, thereby effectively improving system integration and performance, and creating stacked chipset systems with higher density per unit area.
[0003] The design concept of TSV is derived from printed circuit boards. By etching or lasering, holes (vias) are drilled into the chip on the silicon wafer and then filled with conductive materials such as copper, polysilicon, or tungsten, so that two chips are electrically connected through the conductive material filled in the TSV.
[0004] However, traditional TSVs are formed after chip fabrication. If the chip process window contains densely packed circuit functional units, it becomes difficult to further arrange the TSV process window, limiting the types of chips that can be stacked using TSV technology. Furthermore, as integrated circuit chips become increasingly dense and smaller, drilling holes in integrated circuit chips becomes increasingly difficult, easily leading to decreased product yield or reduced reliability. Summary of the Invention
[0005] Based on this, it is necessary to provide a method for fabricating a mask structure / through-silicon via (TSV) and a semiconductor structure to address the problems mentioned above in the background technology. During the process of defining the functional regions of the chip, TSV regions are laid out so as to form or reserve TSV regions during the formation of the chip functional structure. This avoids the problems of limited application of TSV technology due to the dense chip functional structure and reduced product yield or reliability caused by drilling after the chip is manufactured.
[0006] To achieve the above and other related objectives, one aspect of this application provides a method for preparing a mask structure, comprising:
[0007] Provide a mask layer;
[0008] The mask layer is patterned to form a patterned mask layer, wherein the patterned mask layer includes a first opening pattern and a first pattern region that are independent of each other. The first opening pattern is used to define the position and shape of the storage region. A second opening pattern is formed in the first pattern region, and the second opening pattern is used to define the position and shape of the through silicon via.
[0009] In the mask structure fabrication method described in the above embodiments, TSV regions are laid out during the chip functional region definition process, such that the fabricated patterned mask layer includes mutually independent first opening patterns and first patterned regions. The first opening pattern defines the position and shape of the memory region, and a second opening pattern is formed within the first patterned region, defining the position and shape of through-silicon vias (TSVs). This embodiment, by setting independent TSV region patterns in the patterned mask layer corresponding to the chip critical layer—for example, forming a first patterned region defining the position of TSVs during the formation of the first opening pattern defining the position and shape of the memory region—allows for the TSV regions to be reserved or simultaneously formed during the transfer of patterns from the patterned mask layer to the wafer to form the corresponding chip critical layer. This avoids problems such as limited TSV technology application due to dense chip functional structures and decreased product yield or reliability due to drilling after the chip functional structure is fabricated.
[0010] In one embodiment, the mask layer includes a first sub-mask layer; the patterned mask layer includes a first sub-patterned mask layer; patterning the mask layer to form the patterned mask layer includes:
[0011] An independent third opening pattern and a second pattern region are formed on the first sub-mask layer to form the first sub-patterned mask layer. The third opening pattern is used to define the position and shape of the active region. A fourth opening pattern is formed in the second pattern region. The orthographic projection of the fourth opening pattern on the upper surface of the mask layer coincides with the second opening pattern. The orthographic projection of the second pattern region on the upper surface of the mask layer coincides with the first pattern region.
[0012] In the mask structure fabrication method of the above embodiments, during the formation of a first sub-patterned mask layer for transferring the active region pattern, a third opening pattern for defining the position and shape of the active region and a second pattern region for defining the position of the through-silicon via (TSV) are simultaneously formed in the first sub-patterned mask layer. A fourth opening pattern for defining the position and shape of the TSV is formed in the second pattern region. This allows for the reservation or simultaneous formation of a TSV region during the process of transferring the pattern to the wafer using the first sub-patterned mask layer to form the corresponding active region structure. This avoids problems such as a small TSV process window area and reduced product yield or reliability due to drilling after the active region structure of the chip is fabricated.
[0013] In one embodiment, the mask layer further includes a second sub-mask layer located above the first sub-mask layer; the patterned mask layer further includes a second sub-patterned mask layer; and the process of patterning the mask layer to form the patterned mask layer further includes:
[0014] A fifth opening pattern and a third pattern region, which are independent of each other, are formed on the second sub-patterned mask layer to form the second sub-patterned mask layer. The fourth opening pattern is used to define the position and shape of the bit line. A sixth opening pattern is formed in the third pattern region. The orthographic projection of the sixth opening pattern on the upper surface of the mask layer coincides with the second opening pattern. The orthographic projection of the third pattern region on the upper surface of the mask layer coincides with the first pattern region.
[0015] In the mask structure fabrication method of the above embodiments, during the formation of the second sub-patterning mask layer for transferring bit line patterns, a fifth opening pattern for defining the position and shape of bit lines and a third pattern region for defining the position of through-silicon vias (TSVs) are simultaneously formed in the second sub-patterning mask layer. A sixth opening pattern for defining the position and shape of TSVs is formed within the third pattern region. This allows for the reservation or simultaneous formation of TSV regions during the transfer of patterns to the wafer using the second sub-patterning mask layer to form the corresponding bit line structure. This avoids problems such as a small TSV process window area and reduced product yield or reliability due to drilling after the chip bit line structure is fabricated.
[0016] In one embodiment, the first patterned region is a regular polygonal region; the shape of the orthographic projection of the second opening pattern onto the upper surface of the mask layer is at least one of a circle, an ellipse, or a regular polygon. This facilitates alignment between stacked layers using the first patterned region and facilitates the fabrication of through-silicon vias with lower sidewall stress and avoidance of current leakage paths.
[0017] In one embodiment, the second patterned region is a square region; the orthographic projection of the fourth opening pattern onto the upper surface of the mask layer is a regular polygon with twelve or more sides; the center point of the orthographic projection of the fourth opening pattern onto the upper surface of the mask layer coincides with the center point of the second patterned region; wherein each side of the second patterned region is parallel to the side of the adjacent fourth opening pattern. By setting the orthographic projection of the fourth opening pattern onto the upper surface of the mask layer to a regular dodecagon, it is convenient to form rounded-corner through-silicon vias (TSVs) within the regular dodecagon, thereby reducing the sidewall stress and current leakage path of the TSVs; by setting the center point of the orthographic projection of the fourth opening pattern onto the upper surface of the mask layer to coincide with the center point of the second patterned region, and each side of the second patterned region being parallel to the side of the adjacent fourth opening pattern, it is convenient to achieve TSV alignment between stacked layers.
[0018] In one embodiment, the distance between the two parallel sides of the orthographic projection of the fourth opening pattern onto the upper surface of the mask layer is 7.0µm-8.5µm, so as to prepare a through-silicon via with a diameter that meets the preset requirements.
[0019] In one embodiment, the distance between each edge of the second patterned region and the edge of the adjacent and parallel fourth opening pattern is 15.0um-15.3um, so as to ensure that the through silicon via is far away from the dense area of chip functional structure and avoid product yield reduction or reliability reduction caused by TSV.
[0020] In one embodiment, the mask layer further includes a third sub-mask layer located on the side of the second sub-mask layer away from the first sub-mask layer; the patterned mask layer further includes a third sub-patterned mask layer; the patterning of the mask layer to form the patterned mask layer further includes:
[0021] An independent seventh opening pattern and a fourth pattern region are formed on the third sub-patterned mask layer to form the third sub-patterned mask layer. The seventh opening pattern is used to define the position and shape of the capacitor contact trench. An eighth opening pattern is formed in the fourth pattern region. The orthographic projection of the eighth opening pattern on the upper surface of the mask layer coincides with the second opening pattern.
[0022] In the mask structure fabrication method of the above embodiments, during the formation of the third sub-patterned mask layer for transferring the capacitor contact trench pattern, a seventh opening pattern for defining the position and shape of the capacitor contact trench and a fourth pattern region for defining the position of the through-silicon via (TSV) are simultaneously formed in the third sub-patterned mask layer. An eighth opening pattern for defining the position and shape of the TSV is formed in the fourth pattern region. This allows for the reservation or simultaneous formation of a TSV region during the transfer of the pattern to the wafer using the third sub-patterned mask layer to form the corresponding capacitor contact trench. This avoids problems such as a small TSV process window area and reduced product yield or reliability due to drilling after the chip capacitor contact structure is fabricated.
[0023] In one embodiment, the third patterned region is a square region, and the orthographic projection of the third patterned region onto the upper surface of the mask layer coincides with the first patterned region; the shape of the eighth opening pattern is a regular dodecagon; the center point of the orthographic projection of the eighth opening pattern onto the upper surface of the mask layer coincides with the center point of the first patterned region; wherein each side of the fourth patterned region is parallel to the side of the adjacent eighth opening pattern. This embodiment facilitates the alignment of the subsequently formed chip functional layers using a square region; by setting the shape of the eighth opening pattern to a regular dodecagon, the center point of the orthographic projection of the eighth opening pattern onto the upper surface of the mask layer coincides with the center point of the first patterned region, and each side of the fourth patterned region is parallel to the side of the adjacent eighth opening pattern, it facilitates the alignment of silicon vias between stacked layers, and facilitates the formation of rounded-corner silicon vias within the regular dodecagon, thereby reducing the sidewall stress and current leakage path of the silicon vias.
[0024] In one embodiment, the mask layer further includes a fourth sub-mask layer located on the side of the third sub-mask layer away from the second sub-mask layer; the patterned mask layer further includes a fourth sub-patterned mask layer; the patterning of the mask layer to form the patterned mask layer further includes:
[0025] A fifth patterned region is formed on the fourth sub-mask layer to form the fourth sub-patterned mask layer. A ninth opening pattern and a tenth opening pattern are formed in the fifth patterned region. The ninth opening pattern is used to define the position and shape of the first metal wire trench. The orthographic projection of the tenth opening pattern on the upper surface of the mask layer coincides with the second opening pattern. The orthographic projection of the fifth patterned region on the upper surface of the mask layer is located within the first patterned region.
[0026] In the mask structure fabrication method of the above embodiments, during the formation of the fourth sub-patterned mask layer for transferring the first metal line trench pattern, a ninth opening pattern for defining the position and shape of the first metal line trench and a fifth pattern region for defining the position of the through-silicon via (TSV) are simultaneously formed in the fourth sub-patterned mask layer. A tenth opening pattern for defining the position and shape of the TSV is formed in the fifth pattern region. This allows for the reservation or simultaneous formation of a TSV region during the process of transferring the pattern to the wafer using the fourth sub-patterned mask layer to form the corresponding first metal line trench. This avoids problems such as a small TSV process window area and reduced product yield or reliability due to drilling after the first metal line structure of the chip is fabricated.
[0027] In one embodiment, the mask layer further includes a fifth sub-mask layer located on the side of the fourth sub-mask layer away from the third sub-mask layer; the patterned mask layer further includes the fifth sub-patterned mask layer; the patterning of the mask layer to form the patterned mask layer further includes:
[0028] A sixth patterned region is formed on the fifth sub-mask layer to form the fifth sub-patterned mask layer. An eleventh opening pattern and a twelfth opening pattern are formed in the sixth patterned region. The eleventh opening pattern is used to define the position and shape of the second metal wire trench. The orthographic projection of the twelfth opening pattern on the upper surface of the mask layer coincides with the second opening pattern. The orthographic projection of the sixth patterned region on the upper surface of the mask layer is located within the first patterned region and covers the orthographic projection of the fifth patterned region on the upper surface of the mask layer.
[0029] In the mask structure fabrication method of the above embodiments, during the formation of the fifth sub-patterned mask layer for transferring the second metal line trench pattern, an eleventh opening pattern for defining the position and shape of the second metal line trench and a sixth pattern region for defining the position of the through-silicon via (TSV) are simultaneously formed in the fifth sub-patterned mask layer. A twelfth opening pattern for defining the position and shape of the TSV is formed in the sixth pattern region. This allows for the reservation or simultaneous formation of a TSV region during the transfer of the pattern to the wafer using the fifth sub-patterned mask layer to form the corresponding second metal line trench. This avoids problems such as a small TSV process window area and reduced product yield or reliability due to drilling after the second metal line structure of the chip is fabricated.
[0030] In one embodiment, the mask layer further includes a sixth sub-mask layer located on the side of the fifth sub-mask layer away from the fourth sub-mask layer; the patterned mask layer further includes the sixth sub-patterned mask layer; the patterning of the mask layer to form the patterned mask layer further includes:
[0031] A seventh patterned region is formed on the sixth sub-mask layer to form the sixth sub-patterned mask layer. A thirteenth opening pattern and a fourteenth opening pattern are formed in the seventh patterned region. The thirteenth opening pattern is used to define the position and shape of the connecting pad. The orthographic projection of the fourteenth opening pattern on the upper surface of the mask layer covers the second opening pattern. The orthographic projection of the seventh patterned region on the upper surface of the mask layer is located in the first patterned region and covers the orthographic projection of the sixth patterned region on the upper surface of the mask layer.
[0032] In the mask structure fabrication method of the above embodiments, during the formation of the sixth sub-patterned mask layer for transferring the connection pad pattern, a thirteenth opening pattern for defining the position and shape of the connection pad and a seventh pattern region for defining the position of the through-silicon via (TSV) are simultaneously formed in the sixth sub-patterned mask layer. The seventh pattern region contains a fourteenth opening pattern for defining the position and shape of the TSV, thereby forming a connection pad electrically connected to the TSV, which facilitates the electrical connection of two chips through the connection pad and the conductive material filled in the TSV.
[0033] In one embodiment, the orthographic projection of the fourteenth opening pattern onto the upper surface of the mask layer is a regular octagon; the center point of the orthographic projection of the fourteenth opening pattern onto the upper surface of the mask layer coincides with the center point of the second opening pattern.
[0034] Another aspect of this application provides a method for preparing through-silicon vias (TSVs). During the preparation of TSVs, the steps of the mask structure preparation method described in any embodiment of this application are performed to form or reserve TSV regions during the formation of chip functional structures, thereby effectively improving the yield and reliability of the manufactured products.
[0035] Another aspect of this application provides a semiconductor structure in which through-silicon vias (TSVs) are fabricated using any of the through-silicon via fabrication methods described in any of the embodiments of this application. This embodiment simplifies the fabrication process and reduces costs associated with TSVs, while effectively improving the yield and reliability of the manufactured products. Attached Figure Description
[0036] To better describe and illustrate embodiments and / or examples of the applications disclosed herein, reference may be made to one or more accompanying drawings. Additional details or examples used to describe the drawings should not be considered as limiting the scope of any of the disclosed applications, the embodiments and / or examples currently described, or the best mode of conduct of these applications as currently understood.
[0037] Figure 1 This is a top view structural diagram of the storage area and peripheral area of a memory chip;
[0038] Figure 2 The flowchart shown is a method for preparing a mask structure provided in the first embodiment of this application;
[0039] Figure 3 The flowchart shown is a method for preparing a mask structure provided in the second embodiment of this application;
[0040] Figure 4 for Figure 3 A top view of the resulting mask structure;
[0041] Figure 5The flowchart shown is a method for preparing a mask structure provided in the third embodiment of this application;
[0042] Figure 6 for Figure 5 A top view of the resulting mask structure;
[0043] Figure 7 The flowchart shown is a method for preparing a mask structure provided in the fourth embodiment of this application;
[0044] Figure 8 for Figure 7 A top view of the resulting mask structure;
[0045] Figure 9 The flowchart shown is a method for preparing a mask structure provided in the fifth embodiment of this application;
[0046] Figure 10 for Figure 9 A top view of the resulting mask structure;
[0047] Figure 11 The flowchart shown is a method for preparing a mask structure provided in the sixth embodiment of this application;
[0048] Figure 12 for Figure 11 A top view of the resulting mask structure;
[0049] Figure 13 The flowchart shown is a method for preparing a mask structure provided in the seventh embodiment of this application;
[0050] Figure 14 for Figure 13 A top view of the resulting mask structure;
[0051] Explanation of reference numerals in the attached figures:
[0052] 101. Storage area; 102. Peripheral area; 1011. Bit line; 1012. Word line; 104. Active area; 110. Trench isolation structure; 10. First sub-patterning mask layer; 11. Third aperture pattern; 12. Second pattern region; 121. Fourth aperture pattern; 20. Second sub-patterning mask layer; 21. Fifth aperture pattern; 22. Third pattern region; 221. Sixth aperture pattern; 30. Third sub-patterning mask layer; 31. Seventh aperture Pattern; 32, Fourth Pattern Region; 321, Eighth Opening Pattern; 40, Fourth Sub-patterning Mask Layer; 41, Ninth Opening Pattern; 42, Fifth Pattern Region; 421, Tenth Opening Pattern; 50, Fifth Sub-patterning Mask Layer; 51, Eleventh Opening Pattern; 52, Sixth Pattern Region; 521, Twelfth Opening Pattern; 60, Sixth Sub-patterning Mask Layer; 61, Thirteenth Opening Pattern; 62, Seventh Pattern Region; 621, Fourteenth Opening Pattern. Detailed Implementation
[0053] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate preferred embodiments of the application. However, this application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to make the disclosure of this application more thorough and complete.
[0054] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the specification of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.
[0055] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this application, the first element, component, area, layer, or portion discussed below may be referred to as the second element, component, area, layer, or portion.
[0056] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “under” the other element or feature will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.
[0057] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.
[0058] Embodiments of the application are described herein with reference to cross-sectional views that serve as schematic diagrams of preferred embodiments (and intermediate structures). Thus, variations from the illustrated shape can be anticipated due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of the application should not be limited to the specific shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. The regions shown in the figures are substantially schematic, and their shapes are not intended to show the actual shapes of regions of the device and are not intended to limit the scope of the application.
[0059] In the embodiments of this application, the "edge" refers to the edge of the structure projected onto the upper surface of the mask layer.
[0060] Please see Figures 1-14 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of this application. Although the illustrations only show components related to this application and are not drawn according to the actual number, shape and size of the components, the form, quantity and proportion of each component in actual implementation can be arbitrarily changed, and the layout of the components may also be more complex.
[0061] Please see Figure 1For semiconductor memory products, the memory cell array of a semiconductor memory device is generally located within a memory region 101 on a substrate. Peripheral circuitry (not shown) is formed in a peripheral region 102 located around the memory region. This peripheral circuitry is electrically connected to the memory cell array in the memory region 101 via bit lines 1011 and word lines 1012. The memory region 101 can be a high-density region with a relatively high density of active regions 104, defined by the trench isolation structure 110. The peripheral region 102 can be a low-density region with a relatively low density of active regions. As an example, a volatile memory cell array, such as that of dynamic random access memory (DRAM), is formed in the memory region 101. Alternatively, a non-volatile memory cell array, such as that of flash memory, is formed in the memory region 101.
[0062] Traditional TSVs are typically formed within the peripheral region 102 of the chip to avoid affecting the chip's storage performance and reliability. To prevent current leakage paths during conduction of the conductive layer in the TSV, an insulating protective layer needs to be formed around the TSV to prevent electrical contact between the conductive layer in the TSV and the functional structures in the chip. To avoid the technical problems of drilling on the chip and the resulting reduction in product yield and reliability, this application provides a method for fabricating a mask structure / through-silicon via and a semiconductor structure. During the definition of the chip's functional regions, TSV regions are laid out to form or reserve TSV regions during the formation of the chip's functional structures. This avoids the problems of limited TSV technology application due to dense chip functional structures and reduced product yield or reliability caused by drilling after chip fabrication.
[0063] Please see Figure 2 In one embodiment of this application, a method for preparing a mask structure is provided, comprising the following steps:
[0064] Step S1: Provide a mask layer;
[0065] Step S2: Pattern the mask layer to form a patterned mask layer, wherein the patterned mask layer includes a first opening pattern and a first pattern region that are independent of each other. The first opening pattern is used to define the position and shape of the storage region. A second opening pattern is formed in the first pattern region, and the second opening pattern is used to define the position and shape of the through silicon via.
[0066] As an example, please continue reading Figure 1 and Figure 2By laying out TSV regions during the definition of chip functional regions, the fabricated patterned mask layer includes independent first opening patterns and first patterned regions. The first opening pattern defines the position and shape of the memory region 101, and a second opening pattern is formed within the first patterned region, defining the position and shape of the through-silicon via (TSV). This embodiment, by setting independent TSV region patterns in the patterned mask layer corresponding to the chip's critical layer, allows for the reservation or simultaneous formation of TSV regions during the process of transferring patterns from the patterned mask layer to the wafer to form the corresponding chip critical layer. This avoids problems such as limited TSV technology application due to dense chip functional structures and decreased product yield or reliability due to drilling after the chip functional structure is fabricated.
[0067] As an example, the formed patterned mask layer may include a hard mask layer, which can be a single-layer structure or a multi-layer stacked structure, and its material may be silicon oxide. Then, photoresist is coated on the hard mask layer, and after a series of steps such as exposure and development, a patterned photoresist layer is formed. The patterned photoresist layer defines the shape and position of the memory region, the position of the TSV region, and the shape and position of the TSV. The hard mask layer is then etched based on the patterned photoresist layer to form the patterned mask layer, and then the patterned photoresist layer is removed. Of course, in other embodiments of this application, the patterned photoresist layer may be retained during the formation of the patterned mask layer, and then removed after etching the substrate.
[0068] As an example, in one embodiment of this application, the memory area pattern and the TSV area pattern can be exposed and fabricated simultaneously using a photolithography machine, reducing the TSV process flow and device manufacturing costs. This allows for the reservation or simultaneous formation of TSV areas during the process of transferring patterns to the wafer using the patterned mask layer to form the corresponding chip key layers. This avoids problems such as limited TSV technology application due to the dense chip functional structure and reduced product yield or reliability due to drilling after the chip functional structure is fabricated.
[0069] For example, please refer to Figure 3 In one embodiment of this application, the mask layer includes a first sub-mask layer; the patterned mask layer includes a first sub-patterned mask layer, and step S2 may include the following steps:
[0070] Step S21: Form a third opening pattern and a second pattern region that are independent of each other on the first sub-mask layer to form the first sub-patterned mask layer, wherein the third opening pattern is used to define the position and shape of the active region, a fourth opening pattern is formed in the second pattern region, the orthographic projection of the fourth opening pattern on the upper surface of the mask layer coincides with the second opening pattern, and the orthographic projection of the second pattern region on the upper surface of the mask layer coincides with the first pattern region.
[0071] For example, please refer to Figure 4 By simultaneously forming a third opening pattern 11 for defining the position and shape of the active region 104 and a second pattern region 12 for defining the position of the through-silicon via (TSV) in the first sub-patterning mask layer 10 during the formation of the first sub-patterning mask layer 10 for transferring the active region pattern, and a fourth opening pattern 121 for defining the position and shape of the TSV in the second pattern region 12, a TSV region can be reserved or formed simultaneously during the process of transferring the pattern to the wafer using the first sub-patterning mask layer 10 to form the corresponding active region structure. This avoids the problem of reduced product yield or reliability due to the TSV process window area being too small and drilling after the active region structure of the chip is fabricated.
[0072] As an example, in one embodiment of this application, the first patterned region is a regular polygonal region; the shape of the orthographic projection of the second opening pattern onto the upper surface of the mask layer can be at least one of a circle, an ellipse, or a regular polygon. This facilitates alignment between stacked layers using the first patterned region and facilitates the fabrication of through-silicon vias with lower sidewall stress and the ability to avoid current leakage paths.
[0073] As an example, please continue reading Figure 4 In one embodiment of this application, the second patterned region 12 is a square region; the inner boundary of the orthographic projection of the fourth opening pattern 121 onto the upper surface of the mask layer is a regular dodecagon; the center point of the orthographic projection of the fourth opening pattern 121 onto the upper surface of the mask layer coincides with the center point of the second patterned region 12; wherein each side of the second patterned region 12 is parallel to the side of the adjacent fourth opening pattern 121. By setting the orthographic projection of the fourth opening pattern 121 onto the upper surface of the mask layer to a regular dodecagon, it is convenient to form rounded silicon vias within the regular dodecagon, thereby reducing the sidewall stress and current leakage path of the silicon vias; by setting the center point of the orthographic projection of the fourth opening pattern 121 onto the upper surface of the mask layer to coincide with the center point of the first patterned region (not shown), and each side of the second patterned region 12 being parallel to the side of the adjacent fourth opening pattern 121, it is convenient to achieve silicon via alignment between stacked layers.
[0074] As an example, please continue reading Figure 4 In one embodiment of this application, the distance d1 between the two parallel sides of the fourth opening pattern 121 can be set to 7.0um-8.5um. For example, the distance d1 between the two parallel sides of the fourth opening pattern 121 can be set to 7.0um, 7.3um, 7.7um, 8.0um, or 8.5um, etc., to prepare a through-silicon via (TSV) with a diameter that meets the preset requirements. The distance L1 between each side of the second pattern region 12 and the adjacent and parallel side of the fourth opening pattern 121 can be set to 15.0um-15.3um. For example, the distance L1 between each side of the second pattern region 12 and the adjacent and parallel side of the fourth opening pattern 121 can be set to 15.0um, 15.1um, 15.2um, or 15.3um, to ensure that the TSV is far away from the densely populated areas of the chip's functional structure, avoiding problems such as decreased product yield or reduced reliability caused by TSV.
[0075] For example, please refer to Figure 5 In one embodiment of this application, the mask layer further includes a second sub-mask layer located above the first sub-mask layer; the patterned mask layer further includes a second sub-patterned mask layer, and step S2 may further include the following steps:
[0076] Step S22: Form a fifth opening pattern and a third pattern region that are independent of each other on the second sub-mask layer to form the second sub-patterned mask layer, wherein the fourth opening pattern is used to define the position and shape of the bit line, a sixth opening pattern is formed in the third pattern region, the orthographic projection of the sixth opening pattern on the upper surface of the mask layer coincides with the second opening pattern, and the orthographic projection of the third pattern region on the upper surface of the mask layer coincides with the first pattern region.
[0077] For example, please refer to Figure 6 By simultaneously forming a fifth opening pattern 21 for defining the position and shape of the bit line and a third pattern region 22 for defining the position of the through-silicon via (TSV) in the second sub-patterning mask layer 20 during the formation of the second sub-patterning mask layer 20, and forming a sixth opening pattern 221 for defining the position and shape of the TSV in the third pattern region 22, a TSV region can be reserved or formed simultaneously during the process of transferring the pattern to the wafer using the second sub-patterning mask layer 20 to form the corresponding bit line structure. This avoids the problem of reduced product yield or reliability caused by the TSV process window area being too small and drilling after the chip bit line structure is fabricated.
[0078] As an example, please continue reading Figure 6The third patterned region 22 is a square region, and its orthographic projection onto the upper surface of the mask layer coincides with the first patterned region (not shown). The orthographic projection of the sixth opening pattern 221 onto the upper surface of the mask layer is a regular dodecagon. The center point of the orthographic projection of the sixth opening pattern 221 onto the upper surface of the mask layer coincides with the center point of the first patterned region. Each side of the third patterned region 22 is parallel to one side of the adjacent sixth opening pattern 221. The center point of the orthographic projection of the sixth opening pattern 221 onto the upper surface of the mask layer coincides with the center points of both the first and third patterned regions, facilitating the alignment of vias between stacked layers and the formation of rounded-corner vias within the sixth opening pattern 221. The distance L2 between each edge of the third pattern region 22 and the adjacent and parallel edge of the sixth opening pattern 221 can be set to 15.0um-15.3um. For example, the distance L2 between each edge of the third pattern region 22 and the adjacent and parallel edge of the sixth opening pattern 221 can be set to 15.0um, 15.1um, 15.2um or 15.3um to ensure that the through silicon via is far away from the dense area of the chip's functional structure, and to avoid the problem of reduced product yield or reliability caused by TSV.
[0079] For example, please refer to Figure 7 In one embodiment of this application, the mask layer further includes a third sub-mask layer located on the side of the second sub-mask layer away from the first sub-mask layer; the patterned mask layer further includes a third sub-patterned mask layer; step S2 may also include the following steps:
[0080] Step S23: Form a seventh opening pattern and a fourth pattern region that are independent of each other on the third sub-mask layer to form the third sub-patterned mask layer, wherein the seventh opening pattern is used to define the position and shape of the capacitor contact trench, and an eighth opening pattern is formed in the fourth pattern region, and the orthographic projection of the eighth opening pattern on the upper surface of the mask layer coincides with the second opening pattern.
[0081] For example, please refer to Figure 8By simultaneously forming a seventh opening pattern 31 for defining the position and shape of the capacitor contact trench and a fourth pattern region 32 for defining the position of the through-silicon via (TSV) in the third sub-patterning mask layer 30 during the formation of the third sub-patterning mask layer 30, and forming an eighth opening pattern 321 for defining the position and shape of the TSV in the fourth pattern region 32, it is possible to reserve or simultaneously form a TSV region during the process of transferring the pattern to the wafer using the third sub-patterning mask layer 30 to form the corresponding capacitor contact trench. This avoids the problem of reduced product yield or reliability due to the TSV process window area being too small and drilling after the chip capacitor contact structure is fabricated.
[0082] As an example, please continue reading Figure 8 The fourth patterned region 32 can be set as a square region, and the orthographic projection of the fourth patterned region 32 on the upper surface of the mask layer coincides with the first patterned region; the orthographic projection of the eighth opening pattern 321 on the upper surface of the mask layer is a regular dodecagon; the center point of the orthographic projection of the eighth opening pattern 321 on the upper surface of the mask layer coincides with the center point of the first patterned region; wherein, each side of the fourth patterned region 32 is parallel to one side of the adjacent eighth opening pattern 321. By setting the orthographic projection of the eighth opening pattern 321 on the upper surface of the mask layer to a regular dodecagon, the center point of the orthographic projection of the eighth opening pattern 321 on the upper surface of the mask layer coincides with the center point of the first patterned region, and each side of the fourth patterned region 32 is parallel to one side of the adjacent eighth opening pattern 321, it is convenient to achieve alignment of silicon vias between stacked layers, and it is convenient to form rounded silicon vias within the regular dodecagon, so as to reduce the sidewall stress and current leakage path of the silicon vias. The distance L3 between each edge of the fourth pattern region 32 and the adjacent and parallel edge of the eighth opening pattern 321 can be set to 15.0um-15.3um. For example, the distance L3 between each edge of the fourth pattern region 32 and the adjacent and parallel edge of the eighth opening pattern 321 can be set to 15.0um, 15.1um, 15.2um or 15.3um to ensure that the through silicon via is far away from the dense area of the chip's functional structure, and to avoid the problem of reduced product yield or reliability caused by TSV.
[0083] For example, please refer to Figure 9 In one embodiment of this application, the mask layer further includes a fourth sub-mask layer located on the side of the third sub-mask layer away from the second sub-mask layer; the patterned mask layer further includes a fourth sub-patterned mask layer; step S2 may also include the following steps:
[0084] Step S24: A fifth patterned region is formed on the fourth sub-mask layer to form the fourth sub-patterned mask layer. A ninth opening pattern and a tenth opening pattern are formed in the fifth patterned region. The ninth opening pattern is used to define the position and shape of the first metal wire trench. The orthographic projection of the tenth opening pattern on the upper surface of the mask layer coincides with the second opening pattern. The orthographic projection of the fifth patterned region on the upper surface of the mask layer is located within the first patterned region.
[0085] For example, please refer to Figure 10 In one embodiment of this application, during the formation of the fourth sub-patterning mask layer 40 for transferring the first metal line trench pattern, a ninth opening pattern 41 for defining the position and shape of the first metal line trench and a fifth pattern region 42 for defining the position of a through-silicon via (TSV) are simultaneously formed in the fourth sub-patterning mask layer 40. The fifth pattern region 42 contains a tenth opening pattern 421 for defining the position and shape of the TSV. This allows for the reservation or simultaneous formation of a TSV region during the process of transferring the pattern to the wafer using the fourth sub-patterning mask layer 40 to form the corresponding first metal line trench. This avoids problems such as a small TSV process window area and reduced product yield or reliability due to drilling after the first metal line structure of the chip is fabricated.
[0086] As an example, please continue reading Figure 10In one embodiment of this application, the fifth patterned region 42 can be set as a square region with a side length of L0, and the orthographic projection of the fifth patterned region 42 on the upper surface of the mask layer coincides with the first patterned region; the orthographic projection of the tenth opening pattern 421 on the upper surface of the mask layer is a regular dodecagon; the center point of the orthographic projection of the tenth opening pattern 421 on the upper surface of the mask layer coincides with the center point of the first patterned region; wherein, each side of the fifth patterned region 42 is parallel to one side of the adjacent tenth opening pattern 421. By setting the orthographic projection of the tenth opening pattern 421 on the upper surface of the mask layer to a regular dodecagon, the center point of the orthographic projection of the tenth opening pattern 421 on the upper surface of the mask layer to coincide with the center point of the first patterned region, and each side of the fifth patterned region 42 to be parallel to one side of the adjacent tenth opening pattern 421, it is convenient to achieve alignment of silicon vias between stacked layers, and it is convenient to form rounded silicon vias within the regular dodecagon, so as to reduce the sidewall stress and current leakage path of the silicon vias. The distance L5 between each edge of the fifth pattern region 42 and the adjacent and parallel edge of the tenth opening pattern 421 can be set to 15.0um-15.3um. For example, the distance L5 between each edge of the fifth pattern region 42 and the adjacent and parallel edge of the tenth opening pattern 421 can be set to 15.0um, 15.1um, 15.2um, or 15.3um to ensure that the through-silicon vias (TSVs) are far away from densely populated areas of the chip's functional structures, thus avoiding product yield reduction or reliability degradation caused by TSVs. The ninth opening pattern 41 can be arranged in an array, and the orthographic projection of the array formed by the ninth opening pattern 41 onto the upper surface of the mask layer is a square with a side length L4 of 19.8um-20.2um. For example, the side length L4 of the array formed by the ninth opening pattern 41 can be 19.8um, 20.0um, or 20.2um. The side length L0 of the fifth graphic region 42 can be 37.4um-38.0um. For example, the side length L0 of the fifth graphic region 42 can be 37.4um, 37.7um or 38.0um.
[0087] For example, please refer to Figure 11 In one embodiment of this application, the mask layer further includes a fifth sub-mask layer located on the side of the fourth sub-mask layer away from the third sub-mask layer; the patterned mask layer further includes a fifth sub-patterned mask layer; step S2 may also include the following steps:
[0088] Step S25: A sixth patterned region is formed on the fifth sub-mask layer to form the fifth sub-patterned mask layer. An eleventh opening pattern and a twelfth opening pattern are formed in the sixth patterned region. The eleventh opening pattern is used to define the position and shape of the second metal wire trench. The orthographic projection of the twelfth opening pattern on the upper surface of the mask layer coincides with the second opening pattern. The orthographic projection of the sixth patterned region on the upper surface of the mask layer is located within the first patterned region and covers the orthographic projection of the fifth patterned region on the upper surface of the mask layer.
[0089] For example, please refer to Figure 12 In one embodiment of this application, during the formation of the fifth sub-patterning mask layer 50 for transferring the second metal line trench pattern, an eleventh opening pattern 51 for defining the position and shape of the second metal line trench and a sixth pattern region 52 for defining the position of a through-silicon via (TSV) are simultaneously formed in the fifth sub-patterning mask layer 50. The sixth pattern region 52 contains a twelfth opening pattern 521 for defining the position and shape of the TSV. This allows for the reservation or simultaneous formation of a TSV region during the process of transferring the pattern to the wafer using the fifth sub-patterning mask layer 50 to form the corresponding second metal line trench. This avoids problems such as a small TSV process window area and reduced product yield or reliability due to drilling after the second metal line structure of the chip is fabricated.
[0090] As an example, please continue reading Figure 12 In one embodiment of this application, the sixth graphic region 52 can be set as a square region with a side length of L7, and the orthographic projection of the sixth graphic region 52 on the upper surface of the mask layer coincides with the first graphic region; the orthographic projection of the twelfth opening graphic 521 on the upper surface of the mask layer is a regular dodecagon; the center point of the orthographic projection of the twelfth opening graphic 521 on the upper surface of the mask layer coincides with the center point of the first graphic region; wherein each side of the sixth graphic region 52 is parallel to one side of the adjacent twelfth opening graphic 521. The eleventh opening graphic 51 can be set as an array arrangement, and the orthographic projection of the array formed by the eleventh opening graphic 51 on the upper surface of the mask layer is a square with a side length L6 of 24um-26um. For example, the side length L6 of the array formed by the eleventh opening graphic 51 can be 24um, 25um, or 26um. The side length L7 of the sixth graphic region 52 can be 37.4um-38.0um. For example, the side length L7 of the sixth graphic region 52 can be 37.4um, 37.7um or 38.0um.
[0091] For example, please refer to Figure 13In one embodiment of this application, the mask layer further includes a sixth sub-mask layer located on the side of the fifth sub-mask layer away from the fourth sub-mask layer; the patterned mask layer further includes a sixth sub-patterned mask layer; step S2 may also include the following steps:
[0092] Step S26: A seventh patterned region is formed on the sixth sub-mask layer to form the sixth sub-patterned mask layer. A thirteenth opening pattern and a fourteenth opening pattern are formed in the seventh patterned region. The thirteenth opening pattern is used to define the position and shape of the connecting pad. The orthographic projection of the fourteenth opening pattern on the upper surface of the mask layer covers the second opening pattern. The orthographic projection of the seventh patterned region on the upper surface of the mask layer is located in the first patterned region and covers the orthographic projection of the sixth patterned region on the upper surface of the mask layer.
[0093] For example, please refer to Figure 14 In one embodiment of this application, during the formation of the sixth sub-patterned mask layer 60 for transferring the connection pad pattern, a thirteenth opening pattern 61 for defining the position and shape of the connection pad and a seventh patterned region 62 for defining the position of the through-silicon via (TSV) are simultaneously formed in the sixth sub-patterned mask layer 60. The seventh patterned region 62 contains a fourteenth opening pattern 621 for defining the position and shape of the TSV, thereby forming a connection pad electrically connected to the TSV, which facilitates the electrical connection of two chips through the connection pad and the conductive material filled in the TSV.
[0094] As an example, please continue reading Figure 14In one embodiment of this application, the orthographic projection of the fourteenth opening pattern 621 onto the upper surface of the mask layer is a regular octagon; the center point of the orthographic projection of the fourteenth opening pattern 621 onto the upper surface of the mask layer coincides with the center point of the first opening pattern. The seventh pattern region 62 can be set as a square region with a side length of L7, and the orthographic projection of the seventh pattern region 62 onto the upper surface of the mask layer coincides with the first pattern region; the orthographic projection of the fourteenth opening pattern 621 onto the upper surface of the mask layer is a regular dodecagon; the center point of the orthographic projection of the fourteenth opening pattern 621 onto the upper surface of the mask layer coincides with the center point of the first pattern region; wherein each side of the seventh pattern region 62 is parallel to one side of the adjacent fourteenth opening pattern 621. The orthographic projection of the thirteenth opening pattern 61 onto the upper surface of the mask layer can be located within a preset square region, and the side length L8 of the preset square region is 28µm-32µm, for example, the side length L8 of the preset square region can be 28µm, 30µm, or 32µm. The side length L7 of the seventh graphic region 62 can be 37.4um-38.0um. For example, the side length L7 of the seventh graphic region 62 can be 37.4um, 37.7um or 38.0um.
[0095] As an example, in one embodiment of this application, a method for preparing through-silicon vias (TSVs) is provided. During the preparation of the TSVs, the steps of the mask structure preparation method described in any embodiment of this application are performed to form or reserve TSV regions during the formation of the chip functional structure, thereby effectively improving the yield and reliability of the manufactured products.
[0096] As an example, in one embodiment of this application, a semiconductor structure is provided, in which through-silicon vias (TSVs) are fabricated using any of the through-silicon via fabrication methods described in any embodiment of this application. This embodiment simplifies the fabrication process and reduces costs of TSVs, and effectively improves the yield and reliability of the manufactured products.
[0097] Please note that the above embodiments are for illustrative purposes only and do not imply any limitation on this application.
[0098] It should be understood that, unless otherwise expressly stated herein, there is no strict order in which the steps are performed, and these steps may be performed in other orders. Moreover, at least some of the steps may include multiple sub-steps or multiple stages, which are not necessarily completed at the same time, but may be performed at different times, and the execution order of these sub-steps or stages is not necessarily sequential, but may be performed alternately or in turn with other steps or at least some of the sub-steps or stages of other steps.
[0099] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.
[0100] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0101] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.
Claims
1. A method for fabricating a mask structure, characterized in that, include: Provide a mask layer; The mask layer is patterned to form a patterned mask layer, wherein the patterned mask layer includes a first opening pattern and a first pattern region that are independent of each other. The first opening pattern is used to define the position and shape of the storage region. A second opening pattern is formed in the first pattern region, and the second opening pattern is used to define the position and shape of the through silicon via.
2. The method for preparing the mask structure according to claim 1, characterized in that, The mask layer includes a first sub-mask layer; the patterned mask layer includes a first sub-patterned mask layer; patterning the mask layer to form the patterned mask layer includes: An independent third opening pattern and a second pattern region are formed on the first sub-mask layer to form the first sub-patterned mask layer. The third opening pattern is used to define the position and shape of the active region. A fourth opening pattern is formed in the second pattern region. The orthographic projection of the fourth opening pattern on the upper surface of the mask layer coincides with the second opening pattern. The orthographic projection of the second pattern region on the upper surface of the mask layer coincides with the first pattern region.
3. The method for preparing the mask structure according to claim 2, characterized in that, The mask layer further includes a second sub-mask layer located above the first sub-mask layer; the patterned mask layer further includes a second sub-patterned mask layer; the process of patterning the mask layer to form the patterned mask layer further includes: A fifth opening pattern and a third pattern region, which are independent of each other, are formed on the second sub-patterned mask layer to form the second sub-patterned mask layer. The fifth opening pattern is used to define the position and shape of the bit line. A sixth opening pattern is formed in the third pattern region. The orthographic projection of the sixth opening pattern on the upper surface of the mask layer coincides with the second opening pattern. The orthographic projection of the third pattern region on the upper surface of the mask layer coincides with the first pattern region.
4. The method for preparing the mask structure according to claim 2 or 3, characterized in that, The first graphic region is a regular polygon region; The shape of the orthographic projection of the second opening pattern onto the upper surface of the mask layer is at least one of a circle, an ellipse, or a regular polygon.
5. The method for preparing the mask structure according to claim 4, characterized in that, The second graphic region is a square region; The shape of the orthographic projection of the fourth opening pattern onto the upper surface of the mask layer is a regular polygon with twelve or more sides; The center point of the orthographic projection of the fourth opening pattern onto the upper surface of the mask layer coincides with the center point of the second pattern area; Each edge of the second graphic region is parallel to the edge of the adjacent fourth open graphic.
6. The method for preparing the mask structure according to claim 5, characterized in that, The distance between the two parallel sides of the orthographic projection of the fourth opening pattern onto the upper surface of the mask layer is 7.0µm-8.5µm.
7. The method for preparing the mask structure according to claim 6, characterized in that, The distance between each edge of the second graphic region and the edge of the adjacent and parallel fourth open graphic is 15.0um-15.3um.
8. The method for preparing the mask structure according to claim 3, characterized in that, The mask layer further includes a third sub-mask layer located on the side of the second sub-mask layer away from the first sub-mask layer; the patterned mask layer further includes a third sub-patterned mask layer; the process of patterning the mask layer to form the patterned mask layer further includes: An independent seventh opening pattern and a fourth pattern region are formed on the third sub-patterned mask layer to form the third sub-patterned mask layer. The seventh opening pattern is used to define the position and shape of the capacitor contact trench. An eighth opening pattern is formed in the fourth pattern region. The orthographic projection of the eighth opening pattern on the upper surface of the mask layer coincides with the second opening pattern.
9. The method for preparing the mask structure according to claim 8, characterized in that, The third graphic region is a square region, and the orthographic projection of the third graphic region on the upper surface of the mask layer coincides with the first graphic region. The shape of the eighth opening figure is a regular dodecagon; The center point of the orthographic projection of the eighth opening pattern onto the upper surface of the mask layer coincides with the center point of the first pattern area; Each edge of the fourth graphic region is parallel to the edge of the adjacent eighth open graphic.
10. The method for preparing the mask structure according to claim 8, characterized in that, The mask layer further includes a fourth sub-mask layer located on the side of the third sub-mask layer away from the second sub-mask layer; the patterned mask layer further includes a fourth sub-patterned mask layer; the patterning of the mask layer to form the patterned mask layer further includes: A fifth patterned region is formed on the fourth sub-mask layer to form the fourth sub-patterned mask layer. A ninth opening pattern and a tenth opening pattern are formed in the fifth patterned region. The ninth opening pattern is used to define the position and shape of the first metal wire trench. The orthographic projection of the tenth opening pattern on the upper surface of the mask layer coincides with the second opening pattern. The orthographic projection of the fifth patterned region on the upper surface of the mask layer is located within the first patterned region.
11. The method for preparing the mask structure according to claim 10, characterized in that, The mask layer further includes a fifth sub-mask layer located on the side of the fourth sub-mask layer away from the third sub-mask layer; the patterned mask layer further includes a fifth sub-patterned mask layer; the process of patterning the mask layer to form the patterned mask layer further includes: A sixth patterned region is formed on the fifth sub-mask layer to form the fifth sub-patterned mask layer. An eleventh opening pattern and a twelfth opening pattern are formed in the sixth patterned region. The eleventh opening pattern is used to define the position and shape of the second metal wire trench. The orthographic projection of the twelfth opening pattern on the upper surface of the mask layer coincides with the second opening pattern. The orthographic projection of the sixth patterned region on the upper surface of the mask layer is located within the first patterned region and covers the orthographic projection of the fifth patterned region on the upper surface of the mask layer.
12. The method for preparing the mask structure according to claim 11, characterized in that, The mask layer further includes a sixth sub-mask layer located on the side of the fifth sub-mask layer away from the fourth sub-mask layer; the patterned mask layer further includes a sixth sub-patterned mask layer; the patterning of the mask layer to form the patterned mask layer further includes: A seventh patterned region is formed on the sixth sub-mask layer to form the sixth sub-patterned mask layer. A thirteenth opening pattern and a fourteenth opening pattern are formed in the seventh patterned region. The thirteenth opening pattern is used to define the position and shape of the connecting pad. The orthographic projection of the fourteenth opening pattern on the upper surface of the mask layer covers the second opening pattern. The orthographic projection of the seventh patterned region on the upper surface of the mask layer is located in the first patterned region and covers the orthographic projection of the sixth patterned region on the upper surface of the mask layer.
13. The method for preparing the mask structure according to claim 12, characterized in that, The shape of the orthographic projection of the fourteenth opening pattern onto the upper surface of the mask layer is a regular octagon; The center point of the orthographic projection of the fourteenth opening pattern onto the upper surface of the mask layer coincides with the center point of the second opening pattern.
14. A method for preparing a through-silicon via (TSV), characterized in that, The steps of the method described in any one of claims 1-13 are performed during the preparation of through-silicon vias.
15. A semiconductor structure, characterized in that, Through-silicon vias are prepared using the method described in claim 14.