Atomic layer deposition bonding layer for connecting two semiconductor devices

Abstract

Embodiments of the invention relate to atomic layer deposition bonding layers for connecting two semiconductor devices. A method can include forming a first atomic layer deposition (ALD) bonding layer on a surface of a first semiconductor device and forming a second ALD bonding layer on a surface of a second semiconductor device. The method can include bonding the first semiconductor device and the second semiconductor device via the first ALD bonding layer and the second ALD bonding layer. The method can include performing an anneal operation to fuse the first ALD bonding layer and the second ALD bonding layer and forming a single ALD bonding layer that bonds the first semiconductor device and the second semiconductor device.

Description

Technical Field

[0001] This invention relates to an atomic layer deposition bonding layer for connecting two semiconductor devices. Background Technology

[0002] In the semiconductor industry, bonding is a technique used to form stacked semiconductor devices and three-dimensional integrated circuits. Some examples of bonding include wafer-to-wafer bonding, die-to-wafer bonding, and die-to-die bonding. Summary of the Invention

[0003] According to an embodiment of the present invention, a method of manufacturing a semiconductor device includes: forming a first atomic layer deposition (ALD) bonding layer on a surface of a first semiconductor device; forming a second ALD bonding layer on a surface of a second semiconductor device; connecting the first semiconductor device and the second semiconductor device through the first ALD bonding layer and the second ALD bonding layer; and performing an annealing operation to fuse the first ALD bonding layer and the second ALD bonding layer, and forming a single ALD bonding layer bonding the first semiconductor device and the second semiconductor device, wherein the nitrogen concentration at the bonding interface between the first ALD bonding layer and the second ALD bonding layer is less than about 2%.

[0004] According to an embodiment of the present invention, a semiconductor device includes: a first semiconductor device; a second semiconductor device; and an atomic layer deposition (ALD) bonding layer connecting the first semiconductor device and the second semiconductor device, wherein the ALD bonding layer has a thickness ranging from about 20 angstroms to about 400 angstroms, and the ALD bonding layer comprises a ratio of silicon hydroxide to silicon monoxide ranging from about 5% to about 20%.

[0005] According to an embodiment of the present invention, a method of manufacturing a semiconductor device includes: forming a first atomic layer deposition (ALD) bonding layer over a carrier substrate of a first semiconductor device; forming a second ALD bonding layer on a surface of a second semiconductor device; connecting the first semiconductor device and the second semiconductor device through the first ALD bonding layer and the second ALD bonding layer; performing an annealing operation to fuse the first ALD bonding layer and the second ALD bonding layer and form a single ALD bonding layer bonding the first semiconductor device and the second semiconductor device; and removing a silicon layer and a doped layer from the second semiconductor device after performing the annealing operation. Attached Figure Description

[0006] The aspects of this disclosure are best understood from the following detailed description, which is taken in conjunction with the accompanying drawings. It should be noted that, in accordance with industry standard practice, the various components are not drawn to scale. In fact, the dimensions of the various components may be arbitrarily increased or decreased for clarity of explanation.

[0007] Figure 1 This is a diagram of an instance environment in which the systems and / or methods described in this article can be implemented.

[0008] Figure 2A-2H This is one or more example operation diagrams related to the manufacture of the example semiconductor devices described herein.

[0009] Figure 3 yes Figure 1 A diagram of one or more tool and / or device components.

[0010] Figure 4 This is a flowchart illustrating an example of connecting two semiconductor devices using atomic layer deposition (ALD) bonding layers.

[0011] Figures 5A-5E This is one or more example operation diagrams related to the manufacture of the example semiconductor devices described herein.

[0012] Figure 6 This is a flowchart illustrating an example of using an ALD bonding layer to connect two semiconductor devices. Detailed Implementation

[0013] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided object. Specific examples of components and arrangements will be described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first member on or above a second member may include embodiments in which the first and second members are in direct contact, and may also include embodiments in which an additional member may be formed between the first and second members such that the first and second members are not in direct contact. Additionally, reference numerals and / or letters may be repeated in various instances of this disclosure. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0014] Furthermore, for ease of description, spatial relative terms such as “below,” “under,” “down,” “above,” “up,” and similar terms may be used herein to describe the relationship between one element or component and another element or component(s), as illustrated in the figures. In addition to the directions depicted in the figures, spatial relative terms are also intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and thus the spatial relative descriptive terms used herein may also be interpreted.

[0015] Various bonding techniques can be used to bond a first semiconductor device to a second semiconductor device, such as direct bonding, chemically activated bonding, plasma activated bonding, anodic bonding, eutectic bonding, glass frit bonding, adhesive bonding, thermo-compressive bonding, reactive bonding, and / or similar bonding techniques. For example, in some bonding techniques, a thick bonding film can be deposited on either the first or second semiconductor device. The thick bonding film can be a dielectric film of oxide or other dielectric materials and can be deposited using thick film deposition techniques. Planarization techniques (e.g., chemical mechanical polishing (CMP)) can be used to planarize the top surface of the thick bonding film. Plasma (e.g., nitrogen-based plasma or other types of plasma) can be used to pretreat the thick bonding film to promote adhesion between the first and second semiconductor devices. This bonding technique may involve several expensive and time-consuming processing techniques.

[0016] According to some embodiments described herein, a method may include using an ALD bonding layer to connect two semiconductor devices. For example, the method may include forming a first ALD bonding layer on the surface of a first semiconductor device and / or forming a second ALD bonding layer on the surface of a second semiconductor device. The method may include connecting the first semiconductor device and the second semiconductor device through the first ALD bonding layer and / or the second ALD bonding layer, performing an annealing operation to fuse the first ALD bonding layer and the second ALD bonding layer, and forming a single ALD bonding layer that bonds the first semiconductor device and the second semiconductor device.

[0017] In this way, one approach may include using atomic layer deposition (ALD) bonding layers to connect two semiconductor devices. One or more ALD bonding layers can be formed (e.g., on a first semiconductor device and / or a second semiconductor device) as thin bonding layers (e.g., in the range of about 10 angstroms to about 200 angstroms) while maintaining control over the uniformity and roughness of the ALD bonding layer surface, reducing the material cost of the ALD bonding layer. Furthermore, the two semiconductor devices can be bonded using the ALD bonding layer without planarization and pretreatment of the ALD bonding layer prior to bonding, which reduces the cost and complexity of the bonding process and prevents the formation of planarization paste residue on the ALD bonding layer.

[0018] Figure 1 This is a diagram of an instance environment 100 in which the system and / or methods described in this paper can be implemented. For example... Figure 1 As shown, environment 100 may include pre-cleaning tool 102, deposition tool 104, annealing tool 106, photoresist tool 108, etching tool 110, and wafer / bare die transport device 112. The tools and / or devices included in example environment 100 may be contained in semiconductor cleanrooms, semiconductor foundries, semiconductor process and / or manufacturing facilities, etc.

[0019] The pre-cleaning tool 102 includes a pre-cleaning chamber 114 and one or more devices capable of performing a pre-cleaning process on a semiconductor device to remove byproduct layers from the semiconductor device. The one or more devices may include a gas source 116, a plasma source 118, a heat source 120, etc. The gas source 116 may supply various gases, such as ammonia, nitrogen trifluoride, etc., to the pre-cleaning chamber 114. The plasma source 118 may generate plasma that causes a reaction between the gases supplied to the pre-cleaning chamber 114. For example, the plasma source 118 may include an inductively coupled plasma (ICP) source, a transformer-coupled plasma (TCP) source, or other types of plasma sources capable of causing a reaction between ammonia and nitrogen trifluoride to induce the formation of ammonium fluoride gas. As described herein, the heat source 120 is capable of heating the semiconductor device in the pre-cleaning chamber 114 to cause decomposition of one or more layers on the semiconductor device. For example, as described herein, heat source 120 may include a heating lamp, heating coil or other type of heating device to heat the semiconductor device to decompose the ammonium fluoride layer on the semiconductor device into ammonia and hydrogen fluoride gases.

[0020] Deposition tool 104 is a semiconductor processing tool that includes a semiconductor processing chamber and one or more means for depositing various types of materials onto a semiconductor device. For example, deposition tool 104 may include chemical vapor deposition apparatus (e.g., electrostatic spraying apparatus, epitaxial apparatus, and / or other types of chemical vapor deposition apparatus), physical vapor deposition apparatus (e.g., sputtering apparatus, and / or other types of physical vapor deposition apparatus), ion implantation apparatus, and / or similar means. In some embodiments, deposition tool 104 may deposit metal layers onto the source or drain regions of a semiconductor device, deposit contact materials to form contacts of the semiconductor device, and / or the like as described herein.

[0021] Annealing tool 106 is a semiconductor processing tool that includes a semiconductor processing chamber and one or more means for heating a semiconductor device. For example, annealing tool 106 may include a rapid thermal annealing (RTA) tool or other types of annealing tools capable of heating the semiconductor device to induce a reaction between two or more materials or gases, to decompose materials, and / or the like. For example, as described herein, annealing tool 106 can heat the semiconductor device to induce a reaction of a metal layer on an epitaxial region (e.g., a source region or a drain region) and form a metal silicide layer.

[0022] Photoresist tool 108 is a semiconductor processing tool used to remove or supply material to a semiconductor device based on a photoresist layer (e.g., a photoresist mask) applied to the semiconductor device. Photoresist is a photosensitive material used in various processes (e.g., lithography, photogravure, and / or similar processes) to form a patterned coating on the surface of a semiconductor device. Photoresist tool 108 can coat the semiconductor device with a photosensitive organic material and can apply a patterned mask to the semiconductor device to block light, so that only the unmasked areas of the photosensitive organic material are exposed to light. Photoresist tool 108 or other tools (e.g., etching tool 110) can apply a solvent called a developer to the semiconductor device. In the case of a positive photoresist, the photosensitive organic material is photodegraded, the developer dissolves the areas exposed to light, leaving a coating where the mask is placed. In the case of negative photoresist, the photosensitive organic material is photo-enhanced (e.g., polymerized or cross-linked), and the developer only dissolves the unexposed areas, leaving a coating in the areas where no mask is placed.

[0023] Etching tool 110 is a semiconductor processing tool for removing material from the surface of a semiconductor device. In some embodiments, a portion of the semiconductor device is protected from the etchant by an etch-resistant masking material. For example, the masking material may contain a photoresist patterned using photolithography. Etching tool 110 can perform a wet etching process or a dry (e.g., plasma) etching process on the semiconductor device. In a wet etching process, the semiconductor device is immersed in a batch of liquid phase (e.g., wet) etchant and can be agitated for process control. For example, buffered hydrofluoric acid (BHF) can be used to etch silicon dioxide on a silicon substrate. Depending on the parameters of the plasma, the plasma etching process can operate in a variety of modes. For example, the plasma etching process can be operated at pressures ranging from about 0.01 Torr to about 5 Torr. The plasma generates high-energy free radicals that carry a neutral charge and react on the surface of the semiconductor device. Plasma etching can be isotropic (e.g., exhibiting a lateral undercut rate approximately the same as the downward etch rate on a patterned surface) or anisotropic (e.g., exhibiting a lateral undercut rate smaller than the downward etch rate). The source gas for the plasma can contain small molecules rich in chlorine or fluorine. For example, carbon tetrafluoride can be used to etch silicon and chlorine can be used to etch aluminum, while trifluoromethane can be used to etch silicon dioxide and silicon nitride. The plasma may also contain oxygen for oxidizing the photoresist and promoting its removal.

[0024] The wafer / die transport device 112 includes mobile robots, robotic arms, trams or railcars, and / or other types of devices for transporting wafers and / or dies between semiconductor processing tools 102-110 and / or to other locations, such as wafer racks, storage rooms, etc. In some embodiments, the wafer / die transport device 112 may be a programmed device that travels a specific path and / or can operate semi-autonomously or autonomously.

[0025] Figure 1 The number and arrangement of the devices shown are provided as one or more instances. In fact, with... Figure 1 Compared to the apparatus shown, there may be apparatuses with more or fewer devices, different devices, or different configurations. Furthermore, Figure 1 The two or more devices shown can be implemented in a single device, or Figure 1 The single device shown can be implemented as multiple distributed devices. Alternatively or additionally, a group of devices in environment 100 (e.g., one or more devices) can perform one or more functions described as being performed by other groups of devices in environment 100.

[0026] Figure 2A-2HThis is a diagram relating to one or more example operations 200 of manufacturing the example semiconductor devices described herein (e.g., logic devices, memory devices, finFETs, MOSFETs, etc.). Figure 2A As shown, the first semiconductor device 202 may include a first silicon layer 204, an undoped silicate glass (USG) layer 206 on the first silicon layer 204, a first metal contact 208 formed in the USG layer 206, and a passivation layer 209 formed on the USG layer 206 and the first metal contact 208. The first semiconductor device 202 may include a semiconductor wafer, a semiconductor die, and / or the like.

[0027] The first silicon layer 204 may comprise a silicon wafer sliced ​​from a silicon ingot grown into a cylinder. The first silicon layer 204 may have a conductivity value between that of a conductor (e.g., metallic copper) and an insulator (e.g., glass). The first silicon layer 204 may be replaced with other materials, such as germanium, gallium arsenide, silicon germanium, etc.

[0028] USG layer 206 may comprise undoped silicate glass that protects and isolates the components of the first semiconductor device 202. USG layer 206 may comprise a material with a high deposition rate at low temperatures and may possess properties similar to silicon dioxide. USG layer 206 may serve as an insulator and passivation layer in a multi-level interlayer dielectric device (e.g., electrically insulating the first metal contact 208 from other components of the first semiconductor device 202). In some embodiments, the above is combined with... Figure 1 The deposition tool 104 of the described environment 100 can be used to form a USG layer 206 on the top surface of the first silicon layer 204. For example, the deposition tool 104 can perform plasma-enhanced chemical vapor deposition (PECVD), high-density plasma CVD (HDPCVD), subatmospheric pressure CVD (SACVD), etc., to deposit the USG layer 206 on the top surface of the first silicon layer 204.

[0029] The first metal contact 208 may comprise a conductive metal, such as titanium, cobalt, tungsten, aluminum, copper, ruthenium, iridium, etc. In some embodiments, the first metal contact 208 may be formed within an opening formed in the USG layer 206. In some embodiments, the above description is combined with... Figure 1 The deposition tool 104 of the described environment 100 can be used to perform a deposition operation to form a first metal contact 208 in an opening of the USG layer 206. In some embodiments, prior to forming the first metal contact 208 in the opening, the above-described... Figure 1 The etching tool 110 of the described environment 100 can be used to form an opening in the USG layer 206.

[0030] The passivation layer 209 may comprise an oxide material (e.g., a metal oxide) that is inert and does not alter semiconductor properties due to interaction with air or other materials at the passivation layer 209 junction. The passivation layer 209 allows reliable electrical penetration into the conductive layer beneath it and overcomes surface states that prevent electricity from reaching the conductive layer. In some embodiments, the above is combined with… Figure 1 The deposition tool 104 of the described environment 100 can be used to form a passivation layer 209 on the top surface of the USG layer 206 and the first metal contact 208.

[0031] like Figure 2A As further shown, the second semiconductor device 210 may include a second silicon layer 212, a doped layer 214 on the second silicon layer 212, an epitaxial layer 216 formed on the doped layer 214, an intermetallic dielectric (IMD) layer 218 formed on the epitaxial layer 216, a second metal contact 220 formed in the IMD layer 218, and a passivation layer 221 formed on the IMD layer 218 and the second metal contact 220. The second semiconductor device 210 may include a semiconductor wafer, a semiconductor die, and / or the like. In some embodiments, the ratio between the thicknesses of the first semiconductor device 202 and the second semiconductor device 210 may be in the range of approximately 5% to approximately 30%.

[0032] The second silicon layer 212 may comprise a silicon wafer sliced ​​from a silicon ingot grown into a cylinder. The second silicon layer 212 may have a conductivity value between that of a conductor (e.g., metallic copper) and an insulator (e.g., glass). The second silicon layer 212 may be replaced with other materials, such as germanium, gallium arsenide, silicon germanium, etc.

[0033] The doped layer 214 may comprise a material doped with a dopant material (e.g., boron, arsenic, phosphorus, gallium, and / or similar substances) (e.g., silicon, germanium, silicon carbide, silicon-germanium, etc.). Doping is the intentional introduction of impurities into an intrinsically semiconductor material to modulate its electrical, optical, and / or structural properties. In some embodiments, the above is combined with... Figure 1 The deposition tool 104 of the described environment 100 can be used to perform a deposition operation to form an intrinsically semiconductor material on the top surface of the second silicon layer 212. The deposition tool 104 (e.g., an ion implantation tool) can also be used to implant dopant material into the intrinsically semiconductor material and form a doped layer 214.

[0034] Epitaxial layer 216 may comprise silicon-germanium formed by epitaxial growth. In some embodiments, epitaxial layer 216 comprises other materials, such as silicon, silicon carbide, silicon-germanium, gallium arsenide, gallium phosphide, etc. In some embodiments, the above description is combined with... Figure 1The deposition tool 104 of the described environment 100 can be used to perform a deposition operation to form an epitaxial layer 216 on the top surface of the doped layer 214.

[0035] IMD layer 218 may include an intermetallic dielectric material, such as silicon dioxide, a low dielectric constant (e.g., k-value in the range of 3.2 to 2.0) dielectric material, fluorinated quartz glass, silicon, silicon nitride, silicon oxide, etc., to electrically insulate the second metal contact 220 from other components of the second semiconductor device 210. In some embodiments, the above description is combined with... Figure 1 The deposition tool 104 of the described environment 100 can be used to form an IMD layer 218 on the top surface of the epitaxial layer 216. For example, the deposition tool 104 can perform PECVD, HDPCVD, SACVD and / or similar processes to deposit the IMD layer 218 on the top surface of the epitaxial layer 216.

[0036] The second metal contact 220 may comprise a conductive metal, such as titanium, cobalt, tungsten, aluminum, copper, ruthenium, iridium, etc. In some embodiments, the second metal contact 220 may be formed within an opening formed in the IMD layer 218. In some embodiments, the above description is combined with... Figure 1 The deposition tool 104 of the described environment 100 can be used to perform a deposition operation to form a second metal contact 220 in an opening of the IMD layer 218. In some embodiments, prior to forming the second metal contact 220 in the opening, the above-described... Figure 1 The etching tool 110 of the described environment 100 can be used to form openings in the IMD layer 218.

[0037] Passivation layer 221 may comprise an oxide material (e.g., a metal oxide) that is inert and does not alter semiconductor properties due to interaction with air or other materials in contact with passivation layer 221. Passivation layer 221 allows electricity to reliably penetrate into the conductive layer beneath it and overcomes surface states that prevent electricity from reaching the conductive layer. In some embodiments, the above is combined with... Figure 1 The deposition tool 104 of the described environment 100 can be used to form a passivation layer 221 on the top surface of the IMD layer 218 and the second metal contact 220.

[0038] like Figure 2BAs shown, via reference numeral 222, an atomic layer deposition (ALD) operation can be performed to form a first ALD bonding layer 224 on the top surface of the first semiconductor device 202 and a second ALD bonding layer 226 on the top surface of the second semiconductor device 210. For example, the first ALD bonding layer 224 can be formed on the top surfaces of the USG layer 206 and the first metal contact 208, and the second ALD bonding layer 226 can be formed on the top surfaces of the IMD layer 218 and the second metal contact 220. In some embodiments, the first ALD bonding layer 224 and the second ALD bonding layer 226 each have a thickness that allows for control over the surface uniformity and roughness of the surfaces of the first ALD bonding layer 224 and the second ALD bonding layer 226, which reduces the material cost of the first ALD bonding layer 224 and the second ALD bonding layer 226. For example, the first ALD bonding layer 224 and the second ALD bonding layer 226 can each have a thickness ranging from approximately 10 angstroms to approximately 200 angstroms, which is much thinner than the thickness of current bonding layers. As another example, the first ALD bonding layer 224 and / or the second ALD bonding layer 226 may each have a thickness ranging from about 20 angstroms to about 50 angstroms. Each of the first ALD bonding layer 224 and the second ALD bonding layer 226 may contain a dielectric material, such as silicon, silicon nitride, silicon oxide, silicon dioxide, organosilicon glass, spin-coated organic polymer dielectric, and / or the like.

[0039] In some implementations, the above text is combined with Figure 1 The deposition tool 104 of the described environment 100 can be used to form a first ALD bonding layer 224 on the top surface of the first semiconductor device 202 and a second ALD bonding layer 226 on the top surface of the second semiconductor device 210. For example, the deposition tool 104 can perform an atomic layer deposition operation to form the first ALD bonding layer 224 on the top surface of the first semiconductor device 202 and the second ALD bonding layer 226 on the top surface of the second semiconductor device 210. In some embodiments, the atomic layer deposition operation can be performed under specific process conditions to form the first ALD bonding layer 224 on the top surface of the first semiconductor device 202 and the second ALD bonding layer 226 on the top surface of the second semiconductor device 210. For example, the atomic layer deposition operation can include a deposition operation to deposit each of the first ALD bonding layer 224 and the second ALD bonding layer 226 having a thickness such that control over the surface uniformity and roughness of the first ALD bonding layer 224 and the second ALD bonding layer 226 is maintained. In this way, atomic layer deposition can reduce the material cost of the first ALD bonding layer 224 and the second ALD bonding layer 226.

[0040] After the formation of the first ALD bonding layer 224 and the second ALD bonding layer 226, CMP and plasma treatment operations are not performed on the first ALD bonding layer 224 and the second ALD bonding layer 226. CMP and plasma treatment increase the surface roughness of the first ALD bonding layer 224 and the second ALD bonding layer 226, which reduces the direct bonding performance between the first ALD bonding layer 224 and the second ALD bonding layer 226. For example, after CMP, the average root mean square surface roughness (Rq) of the first ALD bonding layer 224 and the second ALD bonding layer 226 can be about 1 angstrom, while after ALD deposition without CMP and plasma treatment, the Rq of the first ALD bonding layer 224 and the second ALD bonding layer 226 can be in the range of about equal to or greater than 0.75 angstroms for a layer thickness of about 25 angstroms, and can be in the range of less than 1 angstrom for a layer thickness of about 100 angstroms.

[0041] like Figure 2C As shown, and via reference numeral 228, the first semiconductor device 202 and the second semiconductor device 210 can be connected via the first ALD bonding layer 224 and the second ALD bonding layer 226. For example, one of the first semiconductor device 202 or the second semiconductor device 210 can be rotated 180 degrees so that the first ALD bonding layer 224 faces the second ALD bonding layer 226. Figure 2C A second semiconductor device 210 rotated 180 degrees is shown; however, the first semiconductor device 202 can be rotated 180 degrees instead of rotating the second semiconductor device 210. Once the first ALD bonding layer 224 faces the second ALD bonding layer 226, the first ALD bonding layer 224 can be bonded to the second ALD bonding layer 226, which connects the first semiconductor device 202 and the second semiconductor device 210. Therefore, as Figure 2C As shown in the example orientation, the second ALD bonding layer 226 can be located on the top surface of the first ALD bonding layer 224. A second metal contact 220 and an IMD layer 218 can be located on the second ALD bonding layer 226, and an epitaxial layer 216 can be located on the IMD layer 218. A doped layer 214 can be located on the epitaxial layer 216, and a second silicon layer 212 can be located on the doped layer 214. The first ALD bonding layer 224 and the second ALD bonding layer 226 can be connected on the first ALD bonding layer 224 and the second ALD bonding layer 226 after their formation without CMP operation and plasma processing operation.

[0042] In some embodiments, each of the first ALD bonding layer 224 and the second ALD bonding layer 226 contains silicon hydroxide and silicon monoxide in a ratio ranging from about 5% to about 20%, allowing the first semiconductor device 202 and the second semiconductor device 210 to be directly bonded. The bonding strength of each of the first ALD bonding layer 224 and the second ALD bonding layer 226 can be greater than 2 joules per square meter, allowing the first semiconductor device 202 and the second semiconductor device 210 to be directly bonded. For example, the bonding strength of each of the first ALD bonding layer 224 and the second ALD bonding layer 226 can be about greater than 2.5 joules per square meter. In some embodiments, the first semiconductor device 202 and the second semiconductor device 210 are connected via the first ALD bonding layer 224 and the second ALD bonding layer 226 without pretreatment. The bonding strength of the first ALD bonding layer 224 and the second ALD bonding layer 226 eliminates the need for expensive and time-consuming plasma pretreatment used in current bonding processes.

[0043] In some embodiments, the uniformity of each of the first ALD bonding layer 224 and the second ALD bonding layer 226 is in the range of about 1% to about 2%, allowing the first semiconductor device 202 and the second semiconductor device 210 to be directly bonded. In some embodiments, the nitrogen concentration between the surfaces of the first ALD bonding layer 224 and the second ALD bonding layer 226 is less than 2% (e.g., at the bonding interface between the first ALD layer 224 and the second ALD layer 226), allowing the first semiconductor device 202 and the second semiconductor device 210 to be directly bonded. The uniformity and nitrogen concentration associated with the first ALD bonding layer 224 and the second ALD bonding layer 226 eliminate the need for the expensive and time-consuming chemical mechanical polishing planarization used in current bonding processes.

[0044] In some embodiments, the first ALD bonding layer 224 or the second ALD bonding layer 226 may be omitted, and a single ALD bonding layer may be located on the top surface of the first semiconductor device 202 or on the top surface of the second semiconductor device 210. In such embodiments, the first semiconductor device 202 and the second semiconductor device 210 may be connected together via a single ALD bonding layer. The single ALD bonding layer may include the characteristics described above regarding the first ALD bonding layer 224 and / or the second ALD bonding layer 226.

[0045] like Figure 2DAs shown, and via reference numeral 230, an annealing operation can be performed to fuse the first ALD bonding layer 224 and the second ALD bonding layer 226 to form a single ALD bonding layer 232. Since the single ALD bonding layer 232 is formed by fusing the first ALD bonding layer 224 and the second ALD bonding layer 226 together, the single ALD bonding layer 232 may include the characteristics described above for the first ALD bonding layer 224 and / or the second ALD bonding layer 226. In some embodiments, the single ALD bonding layer 232 contains a silicon hydroxide to silicon monoxide ratio in the range of approximately 5% to approximately 20%, such that the first ALD bonding layer 224 and the second ALD bonding layer 226 are directly bonded to form the single ALD bonding layer 232.

[0046] In some implementations, the above text is combined with Figure 1 The annealing tool 106 of the described environment 100 can be used to perform an annealing operation to fuse the first ALD bonding layer 224 and the second ALD bonding layer 226 (e.g., by covalent bonding of the first ALD bonding layer 224 and the second ALD bonding layer 226) and form a single ALD bonding layer 232. In some embodiments, the annealing operation can be performed under specific process conditions to fuse the first ALD bonding layer 224 and the second ALD bonding layer 226 and form a single ALD bonding layer 232. For example, the annealing operation can be performed at a temperature ranging from approximately 150 degrees Celsius to approximately 400 degrees Celsius and at a time period ranging from approximately 30 minutes to approximately 3 hours to fuse the first ALD bonding layer 224 and the second ALD bonding layer 226 and form a single ALD bonding layer 232.

[0047] like Figure 2E As shown, and via reference numeral 234, an etching operation can be performed to remove the second silicon layer 212 and the doped layer 214 from the epitaxial layer 216. In some embodiments, a first etching operation is performed to remove the second silicon layer 212 from the doped layer 214, and a second etching operation is performed to remove the doped layer 214 from the epitaxial layer 216. In some embodiments, the above is combined with... Figure 1 The etching tool 110 of the described environment 100 can be used to perform a first etching operation to remove the second silicon layer 212 from the doped layer 214 and a second etching operation to remove the doped layer 214 from the epitaxial layer 216. In some embodiments, a single etching operation is performed to remove both the second silicon layer 212 and the doped layer 214 from the epitaxial layer 216.

[0048] like Figure 2FAs shown, and via reference numeral 236, a passivation layer 238 can be formed on the epitaxial layer 216. For example, the passivation layer 238 can be deposited on the top surface of the epitaxial layer 216. The passivation layer 238 can comprise an oxide material (e.g., a metal oxide) that is inert and does not alter semiconductor properties due to interaction with air or other materials in contact with the passivation layer 238. The passivation layer 238 allows electricity to reliably penetrate into the conductive layer beneath it and overcomes surface states that prevent electricity from reaching the conductive layer. In some embodiments, the above is combined with... Figure 1 The deposition tool 104 of the described environment 100 can be used to form a passivation layer 238 on the top surface of the epitaxial layer 216.

[0049] like Figure 2G As shown, referring to reference numeral 240, a metal via 242 can be formed, passing through the passivation layer 238, epitaxial layer 216, IMD layer 218, and a single ALD bonding layer 232, to connect the first metal contact 208 and the second metal contact 220. For example, one or more etching operations can be performed to form an opening through the passivation layer 238, epitaxial layer 216, IMD layer 218, second metal contact 220, and single ALD bonding layer 232. Then, one or more deposition operations can be performed to provide the metal via 242 in the opening formed through the passivation layer 238, epitaxial layer 216, IMD layer 218, second metal contact 220, and single ALD bonding layer 232. The metal via 242 can contain a conductive metal, such as titanium, cobalt, tungsten, aluminum, copper, ruthenium, iridium, etc. In some embodiments, the above is combined with... Figure 1 The deposition tool 104 and etching tool 110 of the described environment 100 can be used to form a metal via 242 through a passivation layer 238, an epitaxial layer 216, an IMD layer 218 and a single ALD bonding layer 232 to connect a first metal contact 208 and a second metal contact 220.

[0050] In some embodiments, a metal via 242 may be formed for each first metal contact 208 and each second metal contact 220; a single metal via 242 may be formed to connect to two or more first metal contacts 208 and / or two or more second metal contacts 220; and / or similar.

[0051] like Figure 2H As shown, and via reference numeral 244, a third metal contact 246 can be formed on the metal via 242. The third metal contact 246 may comprise a conductive metal, such as titanium, cobalt, tungsten, aluminum, copper, ruthenium, iridium, etc. In some embodiments, the above-described... Figure 1The deposition tool 104 of the described environment 100 can be used to form a third metal contact 246 on the metal via 242. The final setup may include stacked semiconductor devices (e.g., first semiconductor device 202 and second semiconductor device 210), three-dimensional integrated circuits, etc. In some embodiments, the third metal contact 246 may be formed on each metal via 242; a single third metal contact 246 may be formed on two or more metal vias 242; and / or similar.

[0052] As described above, Figure 2A-2H Provided only as one or more instances. Other instances may be related to... Figure 2A-2H The descriptions are different.

[0053] Figure 3 This is a diagram of an example component of device 300. Device 300 may correspond to a pre-cleaning tool 102, a deposition tool 104, an annealing tool 106, a photoresist tool 108, an etching tool 110, and / or a wafer / die transport device 112. In some embodiments, the pre-cleaning tool 102, deposition tool 104, annealing tool 106, photoresist tool 108, etching tool 110, and / or wafer / die transport device 112 may comprise one or more devices 300 and / or one or more components of device 300. Figure 3 As shown, device 300 may include bus 310, processor 320, memory 330, storage component 340, input component 350, output component 360 and communication component 370.

[0054] Bus 310 includes components that enable communication between the components of device 300. Processor 320 is implemented in hardware, firmware, or a combination of hardware and software. Processor 320 includes a central processing unit (CPU), graphics processing unit (GPU), accelerated processing unit (APU), microprocessor, controller, microcontroller, digital signal processor (DSP), field-programmable gate array (FPGA), application-specific integrated circuit (ASIC), and / or other types of processing components. In some embodiments, processor 320 includes one or more processors that can be programmed to perform functions. Memory 330 includes random access memory (RAM), read-only memory (ROM), and / or other types of memory (e.g., flash memory, magnetic memory, and / or optical memory) that stores information and / or instructions for use by processor 320.

[0055] Storage component 340 stores information and / or software related to the operation and use of device 300. For example, storage component 340 may include hard disks (e.g., magnetic disks, optical disks, magneto-optical disks, and / or solid-state disks), optical disks (CDs), digital versatile optical disks (DVDs), floppy disks, cartridges, magnetic tapes, and / or other types of non-transitory computer-readable media, and corresponding drives.

[0056] Input component 350 includes components that enable device 300 to receive information, such as via user input (e.g., touchscreen, keyboard, keypad, mouse, button, switch, and / or microphone). Alternatively or additionally, input component 350 may be used for sensors that sense information (e.g., GPS components, accelerometers, gyroscopes, and / or actuators). Output component 360 includes components that provide output information from device 300 (e.g., display, speaker, and / or one or more light-emitting diodes (LEDs)).

[0057] Communication component 370 includes transceiver-like components (e.g., a transceiver and / or separate receiver and transmitter) enabling device 300 to communicate with other devices, such as via wired connections, wireless connections, and / or a combination of both. Communication component 370 allows device 300 to receive information from and / or provide information to another device. For example, communication component 370 may include an Ethernet interface, an optical interface, a coaxial interface, an infrared interface, an RF interface, a Universal Serial Bus (USB) interface, a wireless local area network (WLAN) interface, a cellular network (CNN) interface, and / or the like.

[0058] Device 300 can execute one or more processing programs described herein. Device 300 can execute processing programs by executing software instructions stored in a non-transitory computer-readable medium, such as memory 330 and / or storage component 340, according to processor 320. Computer-readable medium is defined herein as a non-transitory memory device. Memory includes memory space within a single physical storage device or memory space distributed across multiple physical storage devices.

[0059] Software instructions are read from another computer-readable medium or from another device via communication component 370 into memory 330 and / or storage component 340. When executed, the software instructions stored in memory 330 and / or storage component 340 can cause processor 320 to execute one or more processing programs described herein. Additionally, or alternatively, wired circuitry may be used in place of or in combination with the software instructions to execute one or more processing programs described herein. Therefore, the embodiments described herein are not limited to any particular combination of hardware circuitry and software.

[0060] Figure 3The number and settings of the components shown are provided as an example. In fact, with... Figure 3 Compared to the illustrated device, device 300 may include additional components, fewer components, different components, or components with different configurations. Additionally or alternatively, a group of components of device 300 (e.g., one or more components) may perform one or more functions described as being performed by other groups of components of device 300.

[0061] Figure 4 This is a flowchart of an instance processing procedure 400 for connecting two semiconductor devices using an ALD bonding layer. In some embodiments, Figure 4 One or more processing blocks may be provided by a device (e.g., Figure 1 (One or more of the tools described herein) are executed. In some implementations, Figure 4 One or more overprocessing boxes can be processed by... Figure 1 The one or more tools described herein are separate or contain Figure 1 Other means or a set of means of the one or more tools described herein are used to perform the action. Alternatively or alternatively, Figure 4 One or more processing blocks may be executed by one or more components of the device 300, such as processor 320, memory 330, storage component 340, input component 350, output component 360 and / or communication component 370, etc.

[0062] like Figure 4 As shown, the processing procedure 400 may include forming a first atomic layer deposition (ALD) bonding layer (processing block 410) on the surface of the first semiconductor device. For example, the device may form a first ALD bonding layer 224 on the surface of the first semiconductor device 202, as described above.

[0063] like Figure 4 As further shown, the processing procedure 400 may include forming a second ALD bonding layer (processing block 420) on the surface of the second semiconductor device. For example, the device may form a second ALD bonding layer 226 on the surface of the second semiconductor device 210, as described above.

[0064] like Figure 4 As further shown, the processing procedure 400 may include connecting a first semiconductor device and a second semiconductor device via a first ALD bonding layer and a second ALD bonding layer (processing block 430). For example, the devices may connect the first semiconductor device 202 and the second semiconductor device 210 via a first ALD bonding layer 224 and a second ALD bonding layer 226, as described above.

[0065] like Figure 4As further shown, the processing procedure 400 may include performing an annealing operation to fuse the first ALD bonding layer and the second ALD bonding layer and form a single ALD bonding layer bonding the first semiconductor device and the second semiconductor device (processing block 440). For example, the device may perform an annealing operation to fuse the first ALD bonding layer 224 and the second ALD bonding layer 226 and form a single ALD bonding layer 232 bonding the first semiconductor device 202 and the second semiconductor device 210, as described above.

[0066] Processor 400 may include additional implementations, such as any single implementation of one or more other processors described below and / or in combination with those described elsewhere herein, or any combination of implementations.

[0067] In a first embodiment, each of the first ALD bonding layer 224 and the second ALD bonding layer 226 has a thickness ranging from approximately 10 angstroms to approximately 200 angstroms. In a second embodiment, either alone or in combination with the first embodiment, connecting the first semiconductor device 202 and the second semiconductor device 210 via the first ALD bonding layer 224 and the second ALD bonding layer 226 includes connecting the first semiconductor device 202 and the second semiconductor device 210 via the first ALD bonding layer 224 and the second ALD bonding layer 226 without planarizing the first ALD bonding layer 224 or the second ALD bonding layer 226.

[0068] In the third embodiment, either alone or in combination with one or more of the first and second embodiments, the bonding strength of each of the first ALD bonding layer 224 and the second ALD bonding layer 226 is greater than 2 joules per square meter, such that the first semiconductor device 202 and the second semiconductor device 210 are directly bonded. In the fourth embodiment, either alone or in combination with one or more of the first to third embodiments, connecting the first semiconductor device 202 and the second semiconductor device 210 via the first ALD bonding layer 224 and the second ALD bonding layer 226 includes connecting the first semiconductor device 202 and the second semiconductor device 210 via the first ALD bonding layer 224 and the second ALD bonding layer 226 without pre-processing the first ALD bonding layer 224 and the second ALD bonding layer 226.

[0069] In the fifth embodiment, annealing is performed alone or in combination with one or more of the first to fourth embodiments to fuse the first ALD bonding layer 224 and the second ALD bonding layer 226 and form a single ALD bonding layer 232. The annealing operation is performed at a temperature ranging from about 150 degrees Celsius to about 400 degrees Celsius and for a time period ranging from about 30 minutes to about 3 hours to fuse the first ALD bonding layer 224 and the second ALD bonding layer 226 and form a single ALD bonding layer 232.

[0070] In a sixth embodiment, either alone or in combination with one or more of the first to fifth embodiments, the uniformity of each of the first ALD bonding layer 224 and the second ALD bonding layer 226 is in the range of about 1% to about 2%, such that the first semiconductor device 202 and the second semiconductor device 210 are directly bonded. In a seventh embodiment, either alone or in combination with one or more of the first to sixth embodiments, each of the first ALD bonding layer 224 and the second ALD bonding layer 226 comprises a dielectric material.

[0071] In the eighth embodiment, each of the first ALD bonding layer 224 and the second ALD bonding layer 226 may comprise a dielectric material, such as one or more of silicon, silicon nitride, silicon oxide, silicon dioxide, organosilicon glass, spin-coated organic polymer dielectric, either alone or in combination with one or more of the first to eighth embodiments. In the ninth embodiment, the first semiconductor device 202 comprises one of a first semiconductor wafer or a first semiconductor die, either alone or in combination with one or more of the first to eighth embodiments, and the second semiconductor device 210 comprises one of a second semiconductor wafer or a second semiconductor die.

[0072] In the tenth embodiment, each of the first ALD bonding layer 224 and the second ALD bonding layer 226, alone or in combination with one or more of the first to ninth embodiments, contains a silicon hydroxide to silicon monoxide ratio ranging from approximately 5% to approximately 20%. In the eleventh embodiment, alone or in combination with one or more of the first to tenth embodiments, the nitrogen concentration between the surface of the first ALD bonding layer 224 and the surface of the second ALD layer 226 is less than 2%. In the twelfth embodiment, alone or in combination with one or more of the first to eleventh embodiments, a single ALD bonding layer 232 contains a silicon hydroxide to silicon monoxide ratio ranging from approximately 5% to approximately 20%.

[0073] although Figure 4 An instance block of the processor 400 is shown, but in some implementations, it is different from... Figure 4Compared to those depicted, processor 400 may contain additional boxes, fewer boxes, different boxes, or boxes arranged differently. Alternatively, two or more boxes of processor 400 may execute in parallel.

[0074] Figures 5A-5E This is a diagram of one or more instance operations 500 associated with manufacturing the example semiconductor device described herein. In particular, one or more instance operations 500 can be performed to bond the second semiconductor device 210 to a carrier substrate, such as a silicon carrier wafer, so that one or more additional operations (e.g., one or more back-side operations) can be performed on the second semiconductor device 210 while the second semiconductor device 210 is supported by the carrier substrate.

[0075] like Figure 5A As shown, the first semiconductor device 202 may include a first silicon layer 204. The first silicon layer 204 may be a carrier substrate, such as a silicon carrier wafer. Figure 5A As further shown, the second semiconductor device 210 may include a second silicon layer 212, a doped layer 214 located on the second silicon layer 212, an epitaxial layer 216 formed on the doped layer 214, an IMD layer 218 formed on the epitaxial layer 216, and a second metal contact 220 formed in the IMD layer 218. In some embodiments, a passivation layer 221 may also be formed on the IMD layer 218 and the second metal contact 220.

[0076] like Figure 5BAs shown, and via reference numeral 502, an ALD operation can be performed to form a first ALD bonding layer 224 on the top surface of the first semiconductor device 202 and a second ALD bonding layer 226 on the top surface of the second semiconductor device 210. For example, the first ALD bonding layer 224 can be formed on the top surface of the first silicon layer 204 (e.g., a carrier substrate), and the second ALD bonding layer 226 can be formed on the top surfaces of the IMD layer 218 and the second metal contact 220. In some embodiments, the first ALD bonding layer 224 and the second ALD bonding layer 226 each have a thickness that allows for control over the surface uniformity and roughness of the surfaces of the first ALD bonding layer 224 and the second ALD bonding layer 226, thereby reducing the material cost of the first ALD bonding layer 224 and the second ALD bonding layer 226. For example, each of the first ALD bonding layer 224 and the second ALD bonding layer 226 can contain a thickness ranging from approximately 10 angstroms to approximately 200 angstroms, which is much thinner than the thickness of current bonding layers. In another example, the first ALD bonding layer 224 and / or the second ALD bonding layer 226 may each have a thickness ranging from about 20 angstroms to about 50 angstroms. Each of the first ALD bonding layer 224 and the second ALD bonding layer 226 may contain a dielectric material, such as silicon, silicon nitride, silicon oxide, silicon dioxide, organosilicon glass, spin-coated organic polymer dielectric, and / or the like.

[0077] In some implementations, the above text is combined with Figure 1 The deposition tool 104 of the described environment 100 can be used to form a first ALD bonding layer 224 on the top surface of the first semiconductor device 202 and a second ALD bonding layer 226 on the top surface of the second semiconductor device 210. For example, the deposition tool 104 can perform an atomic layer deposition operation to form the first ALD bonding layer 224 on the top surface of the first semiconductor device 202 and the second ALD bonding layer 226 on the top surface of the second semiconductor device 210. In some embodiments, the atomic layer deposition operation can be performed under specific process conditions to form the first ALD bonding layer 224 on the top surface of the first semiconductor device 202 and the second ALD bonding layer 226 on the top surface of the second semiconductor device 210. For example, the atomic layer deposition operation can include a deposition operation that deposits each of the first ALD bonding layer 224 and the second ALD bonding layer 226 having a thickness capable of maintaining control over the surface uniformity and roughness of the surfaces of the first ALD bonding layer 224 and the second ALD bonding layer 226. In this way, atomic layer deposition can reduce the material cost of the first ALD bonding layer 224 and the second ALD bonding layer 226.

[0078] like Figure 5CAs shown, and via reference numeral 504, the first semiconductor device 202 and the second semiconductor device 210 can be connected via the first ALD bonding layer 224 and the second ALD bonding layer 226. For example, one of the first semiconductor device 202 or the second semiconductor device 210 can be rotated 180 degrees so that the first ALD bonding layer 224 faces the second ALD bonding layer 226. Figure 5C A second semiconductor device 210 rotated 180 degrees is shown; however, the first semiconductor device 202 can be rotated 180 degrees instead of rotating the second semiconductor device 210. Once the first ALD bonding layer 224 faces the second ALD bonding layer 226, the first ALD bonding layer 224 can be bonded to the second ALD bonding layer 226, which can connect the first semiconductor device 202 and the second semiconductor device 210. Therefore, as Figure 5C As shown in the example orientation, the second ALD bonding layer 226 can be located on the top surface of the first ALD bonding layer 224. A second metal contact 220 and an IMD layer 218 can be located on the second ALD bonding layer 226, and an epitaxial layer 216 can be located on the IMD layer 218. A doped layer 214 can be located on the epitaxial layer 216, and a second silicon layer 212 can be located on the doped layer 214. The first ALD bonding layer 224 and the second ALD bonding layer 226 can be connected on the first ALD bonding layer 224 and the second ALD bonding layer 226 after their formation without CMP operation and plasma processing operation.

[0079] In some embodiments, each of the first ALD bonding layer 224 and the second ALD bonding layer 226 comprises a silicon hydroxide to silicon monoxide ratio ranging from about 5% to about 20%, such that the first semiconductor device 202 and the second semiconductor device 210 are directly bonded. The bonding strength of each of the first ALD bonding layer 224 and the second ALD bonding layer 226 can be greater than 2 joules per square meter, such that the first semiconductor device 202 and the second semiconductor device 210 are directly bonded. For example, the bonding strength of each of the first ALD bonding layer 224 and the second ALD bonding layer 226 can be about greater than 2.5 joules per square meter. In some embodiments, the first semiconductor device 202 and the second semiconductor device 210 are connected via the first ALD bonding layer 224 and the second ALD bonding layer 226 without pretreatment. The bonding strength of the first ALD bonding layer 224 and the second ALD bonding layer 226 eliminates the need for the expensive and time-consuming plasma pretreatment used in current bonding processes.

[0080] In some embodiments, the uniformity of each of the first ALD bonding layer 224 and the second ALD bonding layer 226 is in the range of about 1% to about 2%, allowing the first semiconductor device 202 and the second semiconductor device 210 to be directly bonded. In some embodiments, the nitrogen concentration between the surfaces of the first ALD bonding layer 224 and the second ALD bonding layer 226 is less than 2% (e.g., at the bonding interface between the first ALD layer 224 and the second ALD layer 226), allowing the first semiconductor device 202 and the second semiconductor device 210 to be directly bonded. The uniformity and nitrogen concentration associated with the first ALD bonding layer 224 and the second ALD bonding layer 226 eliminate the need for the expensive and time-consuming chemical mechanical polishing planarization used in current bonding processes.

[0081] In some embodiments, the first ALD bonding layer 224 or the second ALD bonding layer 226 may be omitted, and a single ALD bonding layer may be provided on the top surface of the first semiconductor device 202 or the top surface of the second semiconductor device 210. In such embodiments, the first semiconductor device 202 and the second semiconductor device 210 may be connected together via a single ALD bonding layer. The single ALD bonding layer may include the characteristics described above regarding the first ALD bonding layer 224 and / or the second ALD bonding layer 226.

[0082] After the formation of the first ALD bonding layer 224 and the second ALD bonding layer 226, CMP and plasma treatment operations are not performed on the first ALD bonding layer 224 and the second ALD bonding layer 226. CMP and plasma treatment can increase the surface roughness of the first ALD bonding layer 224 and the second ALD bonding layer 226, which will reduce the direct bonding performance between the first ALD bonding layer 224 and the second ALD bonding layer 226. For example, after CMP, the average root mean square surface roughness (Rq) of the first ALD bonding layer 224 and the second ALD bonding layer 226 can be about 1 angstrom, while after ALD deposition without CMP and plasma treatment, the Rq of the first ALD bonding layer 224 and the second ALD bonding layer 226 can be in the range of about equal to or greater than 0.75 angstroms for a layer thickness of about 25 angstroms, and can be in the range of less than 1 angstrom for a layer thickness of about 100 angstroms.

[0083] like Figure 5DAs shown, and via reference numeral 506, an annealing operation can be performed to fuse the first ALD bonding layer 224 and the second ALD bonding layer 226 to form a single ALD bonding layer 232. Since the single ALD bonding layer 232 is formed by fusing the first ALD bonding layer 224 and the second ALD bonding layer 226 together, the single ALD bonding layer 232 may include the characteristics described above for the first ALD bonding layer 224 and / or the second ALD bonding layer 226. In some embodiments, the single ALD bonding layer 232 comprises a ratio of approximately 5% to approximately 20% silicon hydroxide and silicon monoxide, such that the first ALD bonding layer 224 and the second ALD bonding layer 226 are directly bonded to form the single ALD bonding layer 232.

[0084] In some implementations, the above text is combined with Figure 1 The annealing tool 106 of the described environment 100 can utilize an annealing operation to fuse the first ALD bonding layer 224 and the second ALD bonding layer 226 (e.g., through covalent bonding of the first ALD bonding layer 224 and the second ALD bonding layer 226) and form a single ALD bonding layer 232. In some embodiments, the annealing operation can be performed under specific process conditions to fuse the first ALD bonding layer 224 and the second ALD bonding layer 226 and form a single ALD bonding layer 232. For example, the annealing operation can be performed at a temperature ranging from approximately 150 degrees Celsius to approximately 400 degrees Celsius and at a time period ranging from approximately 30 minutes to approximately 3 hours to fuse the first ALD bonding layer 224 and the second ALD bonding layer 226 and form a single ALD bonding layer 232.

[0085] like Figure 5E As shown, and via reference numeral 508, an etching operation can be performed to remove the second silicon layer 212 and the doped layer 214 from the epitaxial layer 216. In some embodiments, a first etching operation is performed to remove the second silicon layer 212 from the doped layer 214, and a second etching operation is performed to remove the doped layer 214 from the epitaxial layer 216. In some embodiments, the above is combined with... Figure 1 The etching tool 110 of the described environment 100 can be used to perform a first etching operation to remove the second silicon layer 212 from the doped layer 214 and a second etching operation to remove the doped layer 214 from the epitaxial layer 216. In some embodiments, a single etching operation is performed to remove both the second silicon layer 212 and the doped layer 214 from the epitaxial layer 216.

[0086] In this way, the annealing operation described above in conjunction with reference numeral 506 can be performed to bond the second semiconductor device 210 to a carrier substrate, such as a silicon carrier wafer (e.g., the first silicon layer 204), so that one or more additional operations (e.g., one or more back-side operations) can be performed on the second semiconductor device 210 while the second semiconductor device 210 is supported by the carrier substrate.

[0087] As described above, Figures 5A-5E Provided only as one or more instances. Other instances may be related to... Figures 5A-5E The descriptions are different.

[0088] Figure 6 This is a flowchart of an instance processing procedure 600 for connecting two semiconductor devices using an ALD bonding layer. In some embodiments, Figure 6 One or more processing blocks may be provided by a device (e.g., Figure 1 (One or more of the tools described herein) are executed. In some implementations, Figure 6 One or more overprocessing boxes can be processed by... Figure 1 The one or more tools described herein are separate or contain Figure 1 Other means or a set of means of the one or more tools described herein are used to perform the action. Alternatively or alternatively, Figure 6 One or more processing blocks may be executed by one or more components of the device 300, such as processor 320, memory 330, storage component 340, input component 350, output component 360 and / or communication component 370, etc.

[0089] like Figure 6 As shown, the processing procedure 600 may include forming a first ALD bonding layer over a carrier substrate of the first semiconductor device (processing block 610). For example, the device may form a first ALD bonding layer 224 over a carrier substrate of the first semiconductor device 202. The carrier substrate includes a first silicon layer 204, such as a silicon carrier wafer, as described above.

[0090] like Figure 6 As further shown, the processing procedure 600 may include forming a second ALD bonding layer (process block 620) on the surface of the second semiconductor device. For example, the device may form a second ALD bonding layer 226 on the surface of the second semiconductor device 210, as described above.

[0091] like Figure 6As further shown, the process 600 may include connecting a first semiconductor device and a second semiconductor device via a first ALD bonding layer and a second ALD bonding layer (process block 630). For example, the devices may connect the first semiconductor device 202 and the second semiconductor device 210 via the first ALD bonding layer 224 and the second ALD bonding layer 226, as described above.

[0092] like Figure 6 As further shown, the processing procedure 600 may include performing an annealing operation to fuse the first ALD bonding layer and the second ALD bonding layer, and forming a single ALD bonding layer that bonds the first semiconductor device and the second semiconductor device (processing block 640). For example, the device may perform an annealing operation to fuse the first ALD bonding layer 224 and the second ALD bonding layer 226, and form a single ALD bonding layer 232 to bond the first semiconductor device 202 and the second semiconductor device 210, as described above.

[0093] like Figure 6 As further shown, the processing procedure 600 may include removing the silicon layer and doped layer from the second semiconductor device after performing an annealing operation (processing block 650). For example, after performing an annealing operation, the device may remove the second silicon layer 212 and doped layer 214 from the second semiconductor device 210, as described above.

[0094] Processor 600 may include additional implementations, such as any single implementation of one or more other processors described below and / or in combination with those described elsewhere herein, or any combination of implementations. Although Figure 6 An instance block of processor 600 is shown, but in some implementations, it is different from... Figure 6 Compared to those described herein, processor 600 may contain additional boxes, fewer boxes, different boxes, or boxes arranged differently. Alternatively, two or more boxes of processor 600 may execute in parallel.

[0095] In this manner, a method may include using ALD bonding layers 224 and 226 to connect a first semiconductor device 202 and a second semiconductor device 210. ALD bonding layers 224 and 226 can be formed as thin bonding layers (e.g., thinner than thick bonding layers) while maintaining control over the surface uniformity and roughness of the surfaces of ALD bonding layers 224 and 226, which reduces the material cost of ALD bonding layers 224 and 226. Furthermore, the first semiconductor device 202 can be bonded to the second semiconductor device 210 using ALD bonding layers 224 and 226 without planarization and pretreatment of ALD bonding layers 224 and 226 prior to bonding, which reduces the cost and complexity of the bonding process and prevents the formation of planarization paste residue on ALD bonding layers 224 and 226.

[0096] As described in more detail above, some embodiments described herein provide a method for manufacturing an apparatus. The method may include: forming a first atomic layer deposition (ALD) bonding layer on a surface of a first semiconductor device; and forming a second ALD bonding layer on a surface of a second semiconductor device. The method may include: connecting the first semiconductor device and the second semiconductor device via the first ALD bonding layer and the second ALD bonding layer; performing an annealing operation to fuse the first ALD bonding layer and the second ALD bonding layer; and forming a single ALD bonding layer that bonds the first semiconductor device and the second semiconductor device. The nitrogen concentration at the bonding interface between the first ALD bonding layer and the second ALD bonding layer is less than about 2%.

[0097] As described in more detail above, some embodiments described herein provide an apparatus. The apparatus may include a first semiconductor device, a second semiconductor device, and an atomic layer deposition (ALD) bonding layer connecting the first and second semiconductor devices. The ALD bonding layer may have a thickness ranging from about 10 angstroms to about 200 angstroms, and the ALD bonding layer contains a ratio of silicon hydroxide to silicon monoxide ranging from about 5% to about 20%.

[0098] As described in more detail above, some embodiments described herein provide a method for manufacturing a device. The method may include forming a first atomic layer deposition (ALD) bonding layer on the surface of a first semiconductor device and forming a second ALD bonding layer on the surface of a second semiconductor device. The method may include: bonding the first semiconductor device and the second semiconductor device via the first ALD bonding layer and the second ALD bonding layer; and performing an annealing operation to fuse the first ALD bonding layer and the second ALD bonding layer, forming a single ALD bonding layer with a thickness in the range of approximately 20 angstroms to approximately 400 angstroms.

[0099] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand aspects of this disclosure. Those skilled in the art will understand that this disclosure can be readily used as a basis for designing or modifying other programs and structures to implement the same purposes as those incorporated herein and / or to achieve the same advantages as those incorporated herein. Those skilled in the art will also recognize that these equivalent constructions should not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made to this document without departing from the spirit and scope of this disclosure.

[0100] Symbol Explanation

[0101] 100: Instance Environment

[0102] 102: Pre-cleaning tools

[0103] 104: Sedimentation Tools

[0104] 106: Annealing tools

[0105] 108: Photoresist Tools

[0106] 110: Etching tools

[0107] 112: Wafer / Die Transport Equipment

[0108] 114: Pre-cleaning chamber

[0109] 116: Gas Source

[0110] 118: Plasma Source

[0111] 120: Heat source

[0112] 200: Instance Operation

[0113] 202: First Semiconductor Device

[0114] 204: First silicon layer

[0115] 206: USG layer

[0116] 208: First metal contact

[0117] 209: Passivation layer

[0118] 210: Second semiconductor device

[0119] 212: Second silicon layer

[0120] 214: Doped layer

[0121] 216: Epitaxial layer

[0122] 218: IMD layer

[0123] 220: Second metal contact

[0124] 221: Passivation layer

[0125] 222: Reference number

[0126] 224: First ALD bonding layer

[0127] 226: Second ALD bonding layer

[0128] 228: Reference number

[0129] 230: Reference number

[0130] 232: Single ALD bonding layer

[0131] 234: Reference number

[0132] 236: Reference number

[0133] 238: Passivation layer

[0134] 240: Reference number

[0135] 242: Metal through hole

[0136] 244: Reference number

[0137] 246: Third metal contact

[0138] 300: Device

[0139] 310: Bus

[0140] 320: Processor

[0141] 330: Memory

[0142] 340: Storage Components

[0143] 350: Input component

[0144] 360: Output Component

[0145] 370: Communication Components

[0146] 400: Handling Procedure

[0147] 410: Step Frame

[0148] 420: Step Box

[0149] 430: Step Box

[0150] 440: Step Box

[0151] 500: Instance Operation

[0152] 502: Reference number

[0153] 504: Reference number

[0154] 506: Reference number

[0155] 508: Reference number

[0156] 600: Handling Procedure

[0157] 610: Step Box

[0158] 620: Step Box

[0159] 630: Step Box

[0160] 640: Step Box

[0161] 650: Step box.

Claims

1. A method for manufacturing a semiconductor device, the method comprising: Formation of the first atomic layer deposition bonding layer; A second atomic layer deposition bonding layer is formed, wherein the first atomic layer deposition bonding layer is formed only on the surface of the first passivation layer of the first semiconductor device, the first passivation layer being composed entirely of an oxide material, and the second atomic layer deposition bonding layer is formed only on the surface of the second passivation layer of the second semiconductor device, the second passivation layer being composed entirely of the oxide material; The first semiconductor device and the second semiconductor device are connected through the first atomic layer deposition bonding layer and the second atomic layer deposition bonding layer; An annealing operation is performed to fuse the first atomic layer deposition bonding layer and the second atomic layer deposition bonding layer, and to form a single atomic layer deposition bonding layer that bonds the first semiconductor device to the second semiconductor device. Wherein, the nitrogen concentration at the interface between the first atomic layer deposition bonding layer and the second atomic layer deposition bonding layer is less than 2%; The first atomic layer deposition bonding layer and the second atomic layer deposition bonding layer contain at least one of silicon hydroxide and silicon monoxide in a certain ratio, said ratio being in the range of 5% to 20%; and A first metal via is formed, completely penetrating a first portion of the single-atom-layer deposition bonding layer of the first semiconductor device and connecting to a first metal contact in the second semiconductor device; and a second metal via is formed, completely penetrating a second portion of the single-atom-layer deposition bonding layer of the first semiconductor device and connecting to a second metal contact in the second semiconductor device, wherein the first metal via and the second metal via are formed completely through the first semiconductor device. Wherein, the first portion of the single atomic layer deposition bonding layer and the second portion of the single atomic layer deposition bonding layer are spaced apart from each other, and the first metal contact in the second semiconductor device and the second metal contact in the second semiconductor device are spaced apart from each other.

2. The method of claim 1, wherein the first atomic layer deposition bonding layer and the second atomic layer deposition bonding layer each have a thickness ranging from 10 angstroms to 200 angstroms.

3. The method of claim 1, wherein connecting the first semiconductor device and the second semiconductor device via the first atomic layer deposition bonding layer and the second atomic layer deposition bonding layer comprises: The first semiconductor device and the second semiconductor device are connected through the first atomic layer deposition bonding layer and the second atomic layer deposition bonding layer without planarizing the first atomic layer deposition bonding layer or the second atomic layer deposition bonding layer.

4. The method of claim 1, wherein the bonding strength of the first atomic layer deposition bonding layer or the second atomic layer deposition bonding layer is greater than 2 joules per square meter, such that the first semiconductor device and the second semiconductor device are directly bonded.

5. The method of claim 1, wherein connecting the first semiconductor device and the second semiconductor device via the first atomic layer deposition bonding layer and the second atomic layer deposition bonding layer comprises: The first semiconductor device and the second semiconductor device are connected through the first atomic layer deposition bonding layer and the second atomic layer deposition bonding layer without preprocessing the first atomic layer deposition bonding layer and the second atomic layer deposition bonding layer.

6. The method of claim 1, wherein performing an annealing operation to fuse the first atomic layer deposition bonding layer and the second atomic layer deposition bonding layer to form the single atomic layer deposition bonding layer comprises: The annealing operation is performed at a temperature ranging from 150 degrees Celsius to 400 degrees Celsius and for a time period ranging from 30 minutes to 3 hours, fusing the first atomic layer deposition bonding layer and the second atomic layer deposition bonding layer to form the single atomic layer deposition bonding layer.

7. The method of claim 1, wherein the uniformity of the first atomic layer deposition bonding layer or the second atomic layer deposition bonding layer is in the range of 1% to 2%, such that the first semiconductor device and the second semiconductor device are directly bonded.

8. A semiconductor device comprising: First semiconductor device; Second semiconductor device; A first atomic layer is deposited as a bonding layer, which exists only on the surface of a first passivation layer of the first semiconductor device. This first passivation layer is composed entirely of an oxide material. A second atomic layer is deposited as a bonding layer, which is only on the surface of the second passivation layer of the second semiconductor device, the second passivation layer being entirely composed of the oxide material. The first atomic layer deposition bonding layer and the second atomic layer deposition bonding layer constitute a single atomic layer deposition bonding layer to connect the first semiconductor device and the second semiconductor device. The first atomic layer deposition bonding layer and the second atomic layer deposition bonding layer each have a certain thickness, the thickness ranging from 20 angstroms to 400 angstroms, and The first atomic layer deposition bonding layer and the second atomic layer deposition bonding layer each contain a ratio of silicon hydroxide to silicon monoxide, said ratio being in the range of 5% to 20%; and A first metal via, completely penetrating a first portion of the single-atom-layer deposited bonding layer of the first semiconductor device, and connecting to a first metal contact in the second semiconductor device, and A second metal via completely penetrates the second portion of the single-atom-layer deposited bonding layer of the first semiconductor device and connects to a second metal contact in the second semiconductor device. The first metal via and the second metal via completely pass through the first semiconductor device, and in, The first portion of the single atomic layer deposition bonding layer and the second portion of the single atomic layer deposition bonding layer are spaced apart from each other, and the first metal contact in the second semiconductor device and the second metal contact in the second semiconductor device are spaced apart from each other.

9. The semiconductor device of claim 8, wherein the uniformity of the atomic layer deposition bonding layer is in the range of 1% to 2%, such that the first semiconductor device and the second semiconductor device are directly bonded.

10. The semiconductor device of claim 8, wherein the atomic layer deposition bonding layer comprises a dielectric material.

11. The semiconductor device of claim 8, wherein the atomic layer deposition bonding layer comprises one or more of the following: silicon, Silicon nitride, silicon dioxide Silicon dioxide, Organic silicate glass, or Spin-coated organic polymer dielectric.

12. The semiconductor device of claim 8, wherein the first semiconductor device comprises one of a first semiconductor wafer or a first semiconductor die, and the second semiconductor device comprises one of a second semiconductor wafer or a second semiconductor die.

13. The semiconductor device of claim 8, wherein the ratio of the thickness of the first semiconductor device to the thickness of the second semiconductor device is in the range of 5% to 30%.

14. The semiconductor device of claim 8, wherein the bonding strength of the atomic layer deposition bonding layer is greater than 2 joules per square meter, such that the first semiconductor device and the second semiconductor device are directly bonded.

15. A method of manufacturing a semiconductor device, the method comprising: Formation of the first atomic layer deposition bonding layer; A second atomic layer deposition bonding layer is formed, wherein the first atomic layer deposition bonding layer is formed only on the surface of the first passivation layer of the first semiconductor device, and the second atomic layer deposition bonding layer is formed only on the surface of the second passivation layer of the second semiconductor device, wherein at least one of the first atomic layer deposition bonding layer and the second atomic layer deposition bonding layer comprises a certain ratio of silicon hydroxide and silicon monoxide, the ratio being in the range of 5% to 20%. The first semiconductor device and the second semiconductor device are connected through the first atomic layer deposition bonding layer and the second atomic layer deposition bonding layer; An annealing operation is performed to fuse the first atomic layer deposition bonding layer and the second atomic layer deposition bonding layer, and to form a single atomic layer deposition bonding layer that bonds the first semiconductor device and the second semiconductor device; as well as A first metal via is formed, completely penetrating a first portion of the single-atom-layer deposition bonding layer and connecting to a first metal contact in the second semiconductor device; and a second metal via is formed, completely penetrating a second portion of the single-atom-layer deposition bonding layer and connecting to a second metal contact in the second semiconductor device, wherein the first metal via and the second metal via are formed completely through the first semiconductor device. Wherein, the first portion of the single atomic layer deposition bonding layer and the second portion of the single atomic layer deposition bonding layer are spaced apart from each other, and the first metal contact in the second semiconductor device and the second metal contact in the second semiconductor device are spaced apart from each other.

16. The method of claim 15, wherein the second semiconductor device is one of a second semiconductor wafer or a second semiconductor die.

17. The method of claim 15, wherein the nitrogen concentration between the surface of the first atomic layer deposition bonding layer and the surface of the second atomic layer deposition bonding layer is less than 2%.

18. The method of claim 15, wherein the first atomic layer deposition bonding layer and the second atomic layer deposition bonding layer each have a thickness ranging from 20 angstroms to 400 angstroms.

19. The method of claim 15, wherein connecting the first semiconductor device and the second semiconductor device via the first atomic layer deposition bonding layer and the second atomic layer deposition bonding layer comprises: The first semiconductor device and the second semiconductor device are bonded via the first atomic layer deposition bonding layer and the second atomic layer deposition bonding layer without preprocessing the first atomic layer deposition bonding layer and the second atomic layer deposition bonding layer.

20. The method of claim 15, wherein connecting the first semiconductor device and the second semiconductor device via the first atomic layer deposition bonding layer and the second atomic layer deposition bonding layer comprises: The first semiconductor device and the second semiconductor device are bonded via the first atomic layer deposition bonding layer and the second atomic layer deposition bonding layer without planarizing the first atomic layer deposition bonding layer and the second atomic layer deposition bonding layer.

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