Semiconductor structure and method of forming the same

Abstract

A semiconductor structure and a method of forming the same are disclosed. The method of forming the semiconductor structure includes providing a first die having a conductive pillar; providing a heat spreading structure having a post disposed around the first die; and planarizing the post of the heat spreading structure and the conductive pillar of the first die such that an end of the post is flush with an end of the conductive pillar.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more specifically, to a semiconductor structure and a method for forming the same. Background Technology

[0002] The current development of FOSiP (Fan-Out System in Package) integrated packaging technology is trending towards Z-direction integration. The most common integration method is to use stacked packaging integration (e.g., IPD integrated on the active surface of AP die). In the integrated structure, the upper and lower layer circuits are used as one of the signal paths through the Z-direction conductive structure.

[0003] However, the distance between the upper and lower layer circuits in the Z direction affects the ease of fabrication of the conductive structure. If the aforementioned distance is too large, then... Figure 1 As shown, the conductive structure 12 is relatively tall. When the conductive structure 12 is formed by electroplating and filling vias, its aspect ratio must be considered to avoid uneven electroplating or voids 14. If the conductive structure 12 is a copper conductive pillar, the aspect ratio of the copper conductive pillar is limited to 1:10, which may cause void abnormalities in the process, thus leading to the risk of open circuit.

[0004] The current approach to solving the above problems is to use SMT (Surface Mount Technology) conductive pillars instead of conductive structures formed by electroplating and filling. However, the SMT conductive pillar method needs to consider the process complexity of multiple SMT conductive pillars, as well as the impact of the molding process on the conductive pillars, which may affect the mask alignment of subsequent bumping. Summary of the Invention

[0005] To address the above problems, this invention proposes a semiconductor structure and its formation method, which can fabricate conductive pillars with a high aspect ratio while achieving high process yield.

[0006] The technical solution of this invention is implemented as follows:

[0007] According to one aspect of the present invention, a method for forming a semiconductor structure is provided, comprising: providing a first die having conductive pillars; providing a heat dissipation structure having pillars disposed around the first die; and planarizing the pillars of the heat dissipation structure and the conductive pillars of the first die such that one end of the pillars is flush with one end of the conductive pillar.

[0008] In some embodiments, prior to providing the heat dissipation structure, the method further includes stacking a second die on top of a first die, wherein conductive posts of the first die are disposed around the second die.

[0009] In some embodiments, the second die is attached to the active surface of the first die. In some embodiments, the second die is an interposer.

[0010] In some embodiments, after planarization, a first redistribution layer (RDL) is formed above one end of the pillar and one end of the conductive pillar.

[0011] In some embodiments, the method of forming a semiconductor structure further includes providing a passive element adjacent to a first die, wherein the passive element is connected to the first die via pillars surrounding the passive element.

[0012] In some embodiments, the method of forming a semiconductor structure further includes: providing a passive element adjacent to a first die, wherein the passive element has pillars, and the passive element is connected to the first die via the pillars on the passive element and a first redistribution layer. The pillars on the passive element are shorter than the pillars surrounding the passive element.

[0013] In some embodiments, the method of forming a semiconductor structure further includes forming a second redistribution layer at the other end of the pillar.

[0014] In some embodiments, the heat dissipation structure further includes a cover connected above the column and located above the first die, wherein planarization includes removing the cover.

[0015] In some embodiments, after providing the heat dissipation structure, the method further includes: forming a dielectric material that surrounds the heat dissipation structure and encapsulates the pillar and the first die.

[0016] According to another aspect of the present invention, a semiconductor structure is provided, comprising: a first die; a second die stacked on the first die; and a pillar located around the first die and the second die; wherein the first die, the second die, and the pillar are covered by the same dielectric material.

[0017] In some embodiments, the semiconductor structure further includes a passive element disposed adjacent to the first die, wherein the passive element has a pillar that is shorter than the pillars surrounding the passive element.

[0018] In some embodiments, the passive element is connected to the first die via a post on the passive element.

[0019] In some embodiments, the semiconductor structure further includes a passive element disposed adjacent to the first die, wherein a pillar is disposed around the passive element, and the passive element is connected to the first die via the pillar.

[0020] In some embodiments, the second die is attached to the active surface of the first die.

[0021] In some embodiments, the second die is an interlayer.

[0022] In some embodiments, the semiconductor structure further includes a first redistribution layer located at one end of the pillar and one end of the conductive pillar.

[0023] In some embodiments, the semiconductor structure further includes a second redistribution layer located at the other end of the pillar.

[0024] In some embodiments, the first die has a conductive post that is flush with the end of the post that is furthest from the first die.

[0025] In some embodiments, conductive posts are arranged around the second die. Attached Figure Description

[0026] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0027] Figure 1 This is a schematic diagram of a current semiconductor packaging structure.

[0028] Figures 2A to 2H This is a schematic diagram of the various stages of a method for forming a semiconductor structure according to an embodiment of the present invention.

[0029] Figure 3 This is a schematic diagram of a semiconductor structure according to another embodiment of the present invention.

[0030] Figure 4 This is a flowchart of a method for forming a semiconductor structure according to an embodiment of the present invention.

[0031] Figure 5 This is a schematic diagram of a semiconductor structure according to another embodiment of the present invention.

[0032] Figure 6 This is a schematic diagram of a semiconductor structure according to another embodiment of the present invention. Detailed Implementation

[0033] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention are within the scope of protection of the present invention.

[0034] Embodiments of the present invention provide a method for forming a semiconductor structure. Figures 2A to 2HThis is a schematic diagram of various stages of a method for forming a semiconductor structure according to an embodiment of the present invention. First, in Figure 2A The carrier 202 and the release layer 204 on the carrier 202 are provided. A first die 210 is provided on the carrier 202. The first die 210 has conductive pillars 212 on a surface 215 away from the carrier 202, which may be referred to as the active surface of the first die 210.

[0035] exist Figure 2B In this configuration, a second die 220 is stacked on top of a first die 210. Conductive posts 212 of the first die 210 are disposed around the second die 220. The second die 220 is attached to the active surface (surface 215) of the first die 210. In some embodiments, the second die 220 may be an interposer.

[0036] Then, in Figure 2C The device includes a heat dissipation structure 230 having pillars 234 disposed around a first die 210. The top surface of the pillars 234 is higher than the top surface of the conductive pillars 212 of the first die 210 and higher than the top surface of the second die 220. The heat dissipation structure 230 also includes a cover 232 connected above the pillars 234 and extending above the first die 210.

[0037] exist Figure 2D In this process, a dielectric material 240 is formed, which surrounds the heat dissipation structure 230 and encapsulates the first die 210 and the pillar 234 of the heat dissipation structure 230. The dielectric material 240 can expose the top surface of the cover 232 of the heat dissipation structure 230. Figure 2E In the middle, Figure 2D The structure is inverted, and the carrier 202 is removed by releasing layer 204.

[0038] Then remove carrier 202 Figure 2D The structure inverted, such as Figure 2F As shown, a planarization process 244 is performed, which can remove the cover 232 of the heat dissipation structure 230 to expose one end 239 of the pillar 234 of the heat dissipation structure 230 and one end 219 of the conductive pillar 212 of the first die 210, and make one end 239 of the pillar 234 flush with one end 219 of the conductive pillar 212.

[0039] exist Figure 2G In this configuration, a first redistribution layer (RDL) 252 is formed above one end 239 of the pillar 234 and one end 219 of the conductive pillar 212. Solder balls 291 are formed on the first redistribution layer 252.

[0040] exist Figure 2HIn this process, a dicing process is performed to form a single structure, which is then inverted and connected to a main board 295 via solder balls 291, thereby obtaining a semiconductor structure 200. The semiconductor structure 200 includes a first die 210 and a second die 220 stacked on the first die 210. Pillars 234 are located around the first die 210 and the second die 220. The first die 210, the second die 220, and the pillars 234 are covered by the same dielectric material 240.

[0041] In some embodiments, Figure 2H After the steps shown, as Figure 3 As shown, a second wiring layer 254 can also be formed on the other end 238 of the column 234 opposite to one end 239 and on the first die 210. The first wiring layer 252 and the second wiring layer 254 are located at the two ends of the column 234, respectively.

[0042] Figure 4 This is a flowchart of a method for forming a semiconductor structure according to an embodiment of the present invention. The method for forming a semiconductor structure includes the following steps. Step S402, providing a first die having conductive pillars. This step 402 corresponds to... Figure 2A The stage shown. Step S404, providing a heat dissipation structure, the heat dissipation structure having pillars disposed around the first die. This step 404 corresponds to Figure 2C The stage shown. Step S406, planarize the pillar of the heat dissipation structure and the conductive pillar of the first die, so that one end of the pillar is flush with one end of the conductive pillar. This step 406 corresponds to Figure 2F The stage shown.

[0043] The technical solution of the present invention forms a conductive structure with a high aspect ratio by forming a heat dissipation structure and planarizing the heat dissipation structure. Compared with the existing process for forming conductive structures, it can achieve a higher process yield.

[0044] Figure 5 This is a schematic diagram of a semiconductor structure according to another embodiment of the present invention. The semiconductor structure also includes a passive element 260 disposed adjacent to the first die 210. In the process of forming the semiconductor structure, the passive element 260 may be formed simultaneously with the first die 210 on the carrier 202 (e.g., ...). Figure 2A Thus, the surface 261 of the passive element 260 is flush with the surface 211 of the first die 210, which is away from the second die 220. A pillar 234 is located on another surface of the passive element 260 opposite to the surface 261. The pillar 234 connected to the passive element 260 is shorter than the pillars 234 surrounding the passive element 260.

[0045] When a post 234 is provided at the passive component 260, the passive component 260 is electrically connected to the first die 210 through the post 234 connected to the passive component 260, the conductive post 212 passing through the first rewiring layer 252 and the first die 210. The conductive path from the passive component 260 to the first die 210 is as follows: Figure 5 Line 52 is shown in the diagram.

[0046] Figure 6 This is a schematic diagram of a semiconductor structure according to another embodiment of the present invention. When there are no pillars 234 on the surface of the passive element 260, the passive element 260 is connected to the first die 210 through the pillars 234 surrounding the passive element 260. In this case, the conductive path of the passive element 260 electrically connected to the first die 210 is as follows: Figure 6 As shown in line 62, the passive component 260 is electrically connected to the first die 210 through the second rewiring layer 25, the pillar 234, the first rewiring layer 252, and the conductive pillar 212 of the first die 210.

[0047] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A method for forming a semiconductor structure, characterized in that, include: Provide a first die with conductive pillars; A passive element is formed around the first die, wherein the surface of the passive element is flush with the surface of the first die away from the conductive post; The second die is stacked on top of the first die, wherein the conductive posts of the first die are disposed around the second die; A heat dissipation structure is provided, the heat dissipation structure having pillars disposed around the first die and the passive element; A cylindrical structure that simultaneously covers the first die, the second die, and the heat dissipation structure with dielectric material; The column of the heat dissipation structure and the conductive column of the first die are flattened so that one end of the column is flush with one end of the conductive column; A first redistribution layer is formed on one end of the column of the heat dissipation structure; A second wiring layer is formed at the other end of the column of the heat dissipation structure. The passive component is electrically connected to the first die through the first rewiring layer, the pillar of the heat dissipation structure, the second rewiring layer, and the conductive pillar.

2. The method for forming a semiconductor structure according to claim 1, characterized in that, Before providing the heat dissipation structure, wherein: The second die is the interlayer.

3. A semiconductor structure, characterized in that, include: A first die, wherein the first die has conductive posts; The second die is stacked on top of the first die; The column of the heat dissipation structure is located around the first die and the second die; A passive element is disposed adjacent to the first die, wherein the column of the heat dissipation structure is disposed around the passive element; The first wiring layer is located at one end of the pillar of the heat dissipation structure and one end of the conductive pillar; The second wiring layer is located at the other end of the column of the heat dissipation structure; The first die, the second die, and the column of the heat dissipation structure are all covered with the same dielectric material. The passive component is electrically connected to the first die through the first rewiring layer, the pillar of the heat dissipation structure, the second rewiring layer, and the conductive pillar.

4. The semiconductor structure according to claim 3, characterized in that: The second die is the interlayer.

5. The semiconductor structure according to claim 3, characterized in that, The second die is attached to the active surface of the first die.

6. The semiconductor structure according to claim 3, characterized in that, The conductive post is flush with the end of the heat dissipation structure that is furthest from the first die.

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