Method for manufacturing a three-dimensional system-on-chip and three-dimensional system-on-chip

Abstract

A method for fabricating a three-dimensional system on chip includes providing a memory wafer structure having a first redistribution layer; disposing a first conductive structure, a core die structure having a second conductive structure, and an input / output die structure on the first redistribution layer, the input / output die structure disposed on a periphery of the core die structure; forming a dielectric layer covering the core die structure, the input / output die structure, and the first conductive structure; removing portions of the dielectric layer and thinning the core die structure and the plurality of input / output die structures to expose the first and second conductive structures; forming a third redistribution layer on the dielectric layer and electrically connected to the first and second conductive structures; forming a plurality of solder balls on the third redistribution layer; and singulating. A three-dimensional system on chip is also provided.

Description

Technical Field

[0001] This invention relates to a method for manufacturing a semiconductor structure, and more particularly to a method for manufacturing a three-dimensional (3D) system-on-chip (SoC) and the 3D SoC itself. Background Technology

[0002] With the booming development of the electronics industry, electronic products are gradually moving towards multifunctional and high-performance research and development. Semiconductor technology has been widely used in the manufacture of chipsets such as memory and central processing units. In order to achieve high integration and high speed, the size of semiconductor integrated circuits continues to shrink. Currently, a variety of different materials and technologies have been developed to meet the above-mentioned requirements for integration and speed.

[0003] Generally, multiple devices / components (e.g., transistors, diodes, etc.) can be designed and embedded in an integrated circuit (IC) chip. This chip is then placed in a package (e.g., a plastic housing) or used as a bare die on a printed circuit board (PCB) of an electronic device. Beyond the miniaturization of traditional technology nodes at the transistor level, there is an increasing use of three-dimensional (3D) IC chip stacking to continue using current semiconductor manufacturing technologies to create three-dimensional system-on-a-chip (3D SoC) devices and provide solutions to meet the performance, power, and bandwidth requirements of various electronic devices. A 3D SoC device can include several logic, memory, analog, or other chips at different technology nodes. How to stack logic, memory, analog, and other chips to form a 3D system-on-a-chip has become a pressing research focus in this field. Summary of the Invention

[0004] This invention provides a method for manufacturing a 3D SoC and a 3D SoC that enables the 3D SoC to meet high integration and speed requirements, while having better electrical characteristics and efficiency.

[0005] The manufacturing method of a three-dimensional system single chip provided by the present invention includes: providing a memory wafer structure, including a wafer, a first active layer, and a first redistribution layer, wherein the first active layer is formed on the wafer, and the first redistribution layer is formed on the first active layer; disposing a plurality of first conductive structures, a core die structure, and a plurality of input / output die structures on the first redistribution layer, wherein the input / output die structures are disposed around the core die structure, wherein each core die structure and each input / output die structure includes a semiconductor substrate, a stop layer structure, a second active layer, a plurality of second conductive structures, and a second redistribution layer, wherein the semiconductor substrate has opposing active surfaces and back surfaces, the stop layer structure is formed within the semiconductor substrate, and the semiconductor substrate is divided into a first substrate portion and a second substrate portion, wherein the first substrate portion is located between the stop layer structure and the active surface, and the second substrate portion is located between the stop layer structure and the back surface, and the second... An active layer is formed on the active surface; a second conductive structure is formed on a first portion of the substrate to connect the second active layer and the stop layer structure; a second redistribution layer is formed on the second active layer; the second redistribution layer of each core die structure and the second redistribution layer of each input / output die structure are bonded to the first redistribution layer; a back-side grinding process is performed to grind from the back side of the semiconductor substrate to remove a portion of the second portion of the substrate; a dielectric filling process is performed to form a dielectric layer covering the core die structure, the input / output die structure, and the first conductive structure; a thinning process is performed to remove a portion of the dielectric layer, the remaining second portion of the substrate, and a portion of the stop layer structure to expose the first conductive structure and the second conductive structure; a third redistribution layer is formed on the dielectric layer, and the third redistribution layer is electrically connected to the exposed first conductive structure and the second conductive structure; a plurality of solder balls are formed on the third redistribution layer; and dicing is performed.

[0006] The method for manufacturing a three-dimensional system-on-a-chip (SoC) provided by this invention includes: providing a plurality of memory dies, each memory die including a die substrate, a first active layer, and a first redistribution layer, the first active layer being formed on the die substrate and the first redistribution layer being formed on the first active layer; providing an SoC wafer structure, divided into an independent core die region and a plurality of input / output die regions, the input / output die regions being disposed around the core die region, the SoC wafer structure including a semiconductor wafer, a stop layer structure, a second active layer, a plurality of conductive structures, and a second redistribution layer, the semiconductor wafer having opposing active surfaces and back surfaces, the stop layer structure being formed within the semiconductor wafer, dividing the semiconductor wafer into a first wafer portion and a second wafer portion, wherein the first wafer portion is located between the stop layer structure and the active surface, and the second wafer portion... Located between the stop layer structure and the back side, a second active layer is formed on the active side, a conductive structure is formed on the first portion of the wafer to connect the second active layer and the stop layer structure, and a second redistribution layer is formed on the second active layer; the first redistribution layer of each memory die is bonded to the second redistribution layer of the core die region of the SoC wafer structure; a dielectric filling process is performed to form a dielectric layer covering the memory die; a back-side grinding process is performed to grind from the back side of the semiconductor wafer to remove a portion of the second portion of the wafer; a thinning process is performed to remove the remaining second portion of the wafer and a portion of the stop layer structure to expose the conductive structure; a third redistribution layer is formed on the remaining portion of the stop layer structure, and the third redistribution layer is electrically connected to the exposed conductive structure; multiple solder balls are formed on the third redistribution layer; and dicing is performed.

[0007] The manufacturing method of a three-dimensional system-on-a-chip provided by the present invention includes: providing a memory wafer structure, including a wafer, a first active layer, and a first redistribution layer, wherein the first active layer is formed on the wafer, and the first redistribution layer is formed on the first active layer; providing a SoC wafer structure, divided into an independent core die region and multiple input / output die regions, wherein the input / output die regions are disposed around the core die region, the SoC wafer structure includes a semiconductor wafer, a stop layer structure, a second active layer, multiple conductive structures, and a second redistribution layer, wherein the semiconductor wafer has opposing active surfaces and back surfaces, the stop layer structure is formed within the semiconductor wafer, and the semiconductor wafer is divided into a first wafer portion and a second wafer portion, wherein the first wafer portion is located within the stop layer structure and the second redistribution layer. Between the active surfaces, the second portion of the wafer is located between the stop layer structure and the back surface. A second active layer is formed on the active surface, and a conductive structure is formed on the first portion of the wafer to connect the second active layer and the stop layer structure. A second redistribution layer is formed on the second active layer. The first redistribution layer of the memory wafer structure is bonded to the second redistribution layer of the SoC wafer structure. A back-side grinding process is performed to grind the back of the semiconductor wafer to remove a portion of the second portion of the wafer. A thinning process is performed to remove the remaining second portion of the wafer and a portion of the stop layer structure to expose the conductive structure. A third redistribution layer is formed on the first portion of the wafer, and the third redistribution layer is electrically connected to the exposed conductive structure. Solder balls are formed on the third redistribution layer. And the wafer is diced.

[0008] In one embodiment of the present invention, the above-mentioned stop layer structure includes a first stop layer and a second stop layer stacked on top of each other. The material of the first stop layer is different from the material of the second stop layer. The second stop layer is located between the first stop layer and the second active layer. In the thinning process, the step of removing part of the stop layer structure includes first removing the first stop layer and then removing part of the second stop layer.

[0009] In one embodiment of the present invention, the first stop layer is a silicon nitride layer and the second stop layer is a silicon dioxide layer.

[0010] In one embodiment of the present invention, the steps for forming the silicon nitride layer and the silicon dioxide layer include performing a nitrogen ion implantation process at a first depth of the semiconductor substrate (semiconductor wafer), performing an oxygen ion implantation process at a second depth of the semiconductor substrate (semiconductor wafer), wherein the second depth is less than the first depth, and then performing a high-temperature processing process, so that the region where the nitrogen ion implantation is performed forms a silicon nitride layer and the region where the oxygen ion implantation is performed forms a silicon dioxide layer.

[0011] In one embodiment of the present invention, the method for removing the silicon nitride layer and silicon dioxide layer is selected from chemical mechanical polishing and plasma dry etching, wherein the selection ratio of silicon nitride to silicon dioxide is between 10 and 20, and the selection ratio of silicon dioxide to silicon is about 5.

[0012] In one embodiment of the present invention, the above-mentioned thinning process includes: a first removal step, removing a portion of the dielectric layer and the remaining second portion of the substrate (second wafer portion); and a second removal step, removing a portion of the stop layer structure to expose the second conductive structure (conductive structure).

[0013] In one embodiment of the present invention, the first removal step is selected from one of chemical mechanical polishing, wet etching and plasma dry etching, and the second removal step is selected from one of chemical mechanical polishing and plasma dry etching.

[0014] In one embodiment of the present invention, the second overlay layer is bonded to the first overlay layer using a hybrid bonding technique.

[0015] The three-dimensional system single chip provided by this invention includes a memory chip structure, multiple first conductive structures, a core die, multiple input / output dies, a dielectric layer, a third redistribution layer, and multiple solder balls. The memory chip structure includes a semiconductor substrate, a first active layer, and a first redistribution layer. The first active layer is formed on the semiconductor substrate, and the first redistribution layer is formed on the first active layer. The first conductive structures, the core die, and the input / output dies are disposed on the first redistribution layer, wherein the input / output dies are disposed around the core die. The core die and the input / output dies include a substrate, a stop layer structure, a second active layer, multiple second conductive structures, and a second redistribution layer. The second active layer and the stop layer structure are respectively disposed on opposite sides of the substrate. The second conductive structures are formed on the substrate. Each second conductive structure... One end of the structure is connected to the second active layer, and the other end of each second conductive structure penetrates and is exposed in the stop layer structure. A second redistribution layer is formed on the second active layer. The second redistribution layer in the core die region and the second redistribution layer in the input / output die region are bonded to the first redistribution layer. A dielectric layer is filled between the core die, the input / output die, and the first conductive structure, and exposes one end of the stop layer structure and the first conductive structure. A third redistribution layer is formed on the dielectric layer, and the third redistribution layer is electrically connected to the exposed first conductive structure and the exposed second conductive structure. Solder balls are formed on the third redistribution layer.

[0016] The three-dimensional system-on-a-chip provided by this invention includes multiple memory dies, a dielectric layer, a SoC chip, a third redistribution layer, and solder balls. Each memory die includes a die substrate, a first active layer, and a first redistribution layer. The first active layer is formed on the die substrate, and the first redistribution layer is formed on the first active layer. The dielectric layer covers the memory die and exposes the first redistribution layer of each memory die. The SoC chip is divided into an independent core die and multiple input / output dies. The input / output dies are disposed around the core die. The SoC chip includes a substrate, a stop layer structure, a second active layer, multiple conductive structures, and a second redistribution layer. The second active layer and the stop layer structure are respectively disposed on opposite sides of the substrate. The conductive structures are formed on the substrate. One end of each conductive structure is connected to the second active layer, and the other end of each conductive structure penetrates and is exposed in the stop layer structure. The second redistribution layer is formed on the second active layer, and the first redistribution layer of each memory die is bonded to the second redistribution layer of the core die. The third redistribution layer is formed on the stop layer structure and is electrically connected to the exposed conductive structures. Solder balls are formed on the third redistribution layer.

[0017] The three-dimensional system-on-a-chip provided by this invention includes a memory chip structure, a SoC chip, a third redistribution layer, and solder balls. The memory chip structure includes a semiconductor substrate, a first active layer, and a first redistribution layer. The first active layer is formed on the semiconductor substrate, and the first redistribution layer is formed on the first active layer. The SoC chip is divided into an independent core die and multiple input / output dies, with the input / output dies disposed around the core die. The SoC chip includes a substrate, a stop layer structure, a second active layer, multiple conductive structures, and a second redistribution layer. The second active layer and the stop layer structure are respectively disposed on opposite sides of the substrate. The conductive structures are formed on the substrate, with one end of each conductive structure connected to the second active layer and the other end of each conductive structure penetrating and exposed in the stop layer structure. The second redistribution layer is formed on the second active layer, and the first redistribution layer of each memory die is bonded to the second redistribution layer of the core die. The third redistribution layer is formed on the stop layer structure and is electrically connected to the exposed conductive structures. Solder balls are formed on the third redistribution layer.

[0018] In this invention's three-dimensional system-on-a-chip (SoC), a memory chip can be bonded to a core die and multiple input / output dies covered by a dielectric layer, or a SoC chip can be bonded to multiple memory dies covered by a dielectric layer, or the memory chip and the SoC chip can be bonded to each other. The core die, input / output dies, or SoC chip can all be made very thin due to the stop layer structure, thus significantly reducing the overall thickness of the three-dimensional SoC, meeting high integration and speed requirements, and providing better electrical characteristics and efficiency.

[0019] The above description is merely an overview of the technical solution of the present invention. In order to better understand the technical means of the present invention and to implement it in accordance with the contents of the specification, and to make the above and other objects, features and advantages of the present invention more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0020] Figures 1A to 1I The diagram shown is a cross-sectional schematic of the manufacturing method of a three-dimensional system single chip according to the first embodiment of the present invention.

[0021] Figure 2 This is a cross-sectional structural diagram of a single chip in a three-dimensional system according to the first embodiment of the present invention.

[0022] Figure 3 This is a bottom view of a single chip in a three-dimensional system according to an embodiment of the present invention.

[0023] Figures 4A to 4H The diagram shown is a cross-sectional schematic of the manufacturing method of a three-dimensional system single chip according to the second embodiment of the present invention.

[0024] Figure 5 This is a cross-sectional structural diagram of a three-dimensional system single chip according to the second embodiment of the present invention.

[0025] Figure 6 This is a bottom view schematic diagram of a three-dimensional system single chip according to the second embodiment of the present invention.

[0026] Figures 7A to 7E This is a cross-sectional schematic diagram of the manufacturing method of a three-dimensional system single chip according to the third embodiment of the present invention.

[0027] Figure 8 This is a cross-sectional structural diagram of a three-dimensional system single chip according to the third embodiment of the present invention. Detailed Implementation

[0028] Figures 1A to 1I The diagram shown is a cross-sectional schematic of the manufacturing method of a three-dimensional system single chip according to the first embodiment of the present invention. Figure 1A As shown, a memory wafer structure 10 is provided, including a wafer 12, a first active layer 14, and a first redistribution layer 16. The first active layer 14 is formed on the wafer 12, and the first redistribution layer 16 is formed on the first active layer 14. In one embodiment, the wafer 12 is, for example, a silicon wafer, an epitaxial silicon wafer, a silicon-germanium wafer, or a silicon carbide wafer; basic memory elements such as transistors are formed on the first active layer 14; and metal wiring, metal pillars (VIAs), and microbumps are formed on the first redistribution layer 16.

[0029] like Figure 1B As shown, multiple first conductive structures 18 are disposed on the first redistribution layer 16, and the first conductive structure 18 is, for example, a conductive pillar; Figure 1C As shown, a core die structure 20 and multiple input / output die structures 22 are disposed on the first redistribution layer 16. The input / output die structures 22 are disposed around the core die structure 20, and a first conductive structure 18 is disposed between the input / output die structures 22 and the core die structure 20. The structure and configuration of each core die structure 20 and each input / output die structure 22 are generally the same. The main difference between them lies in the different electrical component configurations within the active layer of the core die structure 20 and the input / output die structures 22. Therefore, the corresponding or identical structures in the core die structure 20 and the input / output die structures 22 are marked with the same component symbols below.

[0030] Please continue reading. Figure 1C As shown, the core die structure 20 and the input / output die structure 22 include a semiconductor substrate 24, a stop layer structure 26, a second active layer 28, a plurality of second conductive structures 30, and a second redistribution layer 32. The semiconductor substrate 24 has an active surface 241 and a back surface 242. The stop layer structure 26 is formed within the semiconductor substrate 24, dividing the semiconductor substrate 24 into a first substrate portion 243 and a second substrate portion 244. The semiconductor substrate 24 between the stop layer structure 26 and the active surface 241 is referred to as the first substrate portion 243, and the semiconductor substrate 24 between the stop layer structure 26 and the back surface 242 is referred to as the second substrate portion 244. Therefore, the first substrate portion 243 is located between the stop layer structure 26 and the active surface 241, and the second substrate portion 244 is located between the stop layer structure 26 and the back surface 242. The second active layer 28 is formed on the active surface 241. In one embodiment, electrical components such as metal-oxide-semiconductor (MOS) are formed on the second active layer 28. Multiple second conductive structures 30 are formed on the first portion 243 of the substrate to connect the second active layer 28 and the stop layer structure 26. In one embodiment, the second conductive structure 30 is, for example, a conductive pillar. A second redistribution layer 32 is formed on the second active layer 28, and the second redistribution layer 32 has, for example, metal wiring, metal pillars (VIA), and microbumps. Figure 1C As shown, in one embodiment, the second redistribution layer 32 of the core die structure 20 and the second redistribution layer 32 of the input / output die structure 22 are bonded to the first redistribution layer 16 using a hybrid bonding technique.

[0031] In one embodiment, the stop layer structure 26 includes a first stop layer 261 and a second stop layer 262 stacked on top of each other. The material of the first stop layer 261 is different from the material of the second stop layer 262. The second stop layer 262 is located between the first stop layer 261 and the second active layer 28. The first stop layer 261 is, for example, a silicon nitride (Si3N4) layer, and the second stop layer 262 is, for example, a silicon dioxide (SiO2) layer. The fabrication of the stop layer structure 26 includes an ion implantation process and a high-temperature processing process. The ion implantation process includes performing a nitrogen ion implantation process at a first depth D1 of the semiconductor substrate 24 from the active surface 241, and then performing an oxygen ion implantation process at a second depth D2 of the semiconductor substrate 24 from the active surface 241. The second depth D2 of the oxygen ion implantation region is smaller than the first depth D1 of the nitrogen ion implantation region, that is, the oxygen ion implantation region is closer to the active surface 241. Afterwards, a high-temperature process is performed to form a silicon nitride layer (i.e., the first stop layer 261) in the nitrogen ion implantation region and a silicon dioxide layer (i.e., the second stop layer 262) in the oxygen ion implantation region. The second stop layer 262 is closer to the active surface 241, and the first stop layer 261 is closer to the back surface 242.

[0032] like Figure 1D As shown, a back-side grinding process is performed, grinding is performed on the back side 242 of the semiconductor substrate 24 to remove a portion of the second portion 244 of the substrate, as... Figure 1D As shown, the second portion 244' of the substrate has an extremely thin residual thickness.

[0033] like Figure 1E As shown, a dielectric filling process is performed to form a dielectric layer 34 covering the core die structure 20, the input / output die structure 22, and the first conductive structure 18. Next, a thinning process is performed to remove a portion of the dielectric layer 34, the remaining second portion 244' of the substrate, and a portion of the stop layer structure 26 to expose the first conductive structure 18 and the second conductive structure 30. In one embodiment, the thinning process includes a first removal step and a second removal step. The first removal step is used to remove the remaining second portion 244' of the substrate and a portion of the dielectric layer 34, such as... Figure 1F As shown, to expose the stop layer structure 26, for example, to expose the first stop layer 261, the first removal step is, for example, a process selected from chemical mechanical polishing, wet etching and plasma dry etching. In one embodiment, the material of the second portion 244' of the substrate is silicon, and the material of the first stop layer 261 is silicon nitride. When the first removal step is a chemical mechanical polishing process, the silicon to silicon nitride ratio is, for example, 20, that is, Si / Si3N4 is 20.

[0034] Continuing with the above explanation, the second removal step is used to remove a portion of the stop layer structure 26, that is, to sequentially remove the first stop layer 261 and a portion of the second stop layer 262, as follows: Figure 1G As shown, to expose the first conductive structure 18 and the second conductive structure 30, the second removal step is, for example, a process selected from chemical mechanical polishing and plasma dry etching. In one embodiment, the first stop layer 261 is, for example, a silicon nitride (Si3N4) layer, and the second stop layer 262 is, for example, a silicon dioxide (SiO2) layer. In the second removal step, the silicon nitride layer (first stop layer 261) is first removed by a chemical mechanical polishing process to expose the silicon dioxide layer (second stop layer 262), wherein the selectivity ratio of silicon nitride to silicon dioxide is, for example, between 10 and 20, that is, Si3N4 / SiO2 is between 10 and 20; then, a portion of the silicon dioxide layer (second stop layer 262) is removed by another chemical mechanical polishing process to leave an extremely thin silicon dioxide layer (second stop layer 262') and expose the first conductive structure 18 and the second conductive structure 30, wherein the selectivity ratio of silicon dioxide to silicon is approximately 5, that is, SiO2 / Si is 5. This results in a core grain structure 20 (indicated in...) Figure 1E ) and input / output grain structure 22 (labeled in Figure 1E Both are thinned, and the thinned core grain structure 20 and input / output grain structure 22 are referred to as core grain 20A and input / output grain 22A, respectively.

[0035] Specifically, the core die 20A and the input / output die 22A include a substrate (i.e., the first portion 243 of the substrate), a residual second stop layer 262' of the stop layer structure 26, a second active layer 28, a second conductive structure 30, and a second redistribution layer 32. The second active layer 28 and the second stop layer 262' are respectively disposed on opposite sides of the substrate (i.e., the first portion 243 of the substrate). The second conductive structure 30 is formed on the substrate (i.e., the first portion 243 of the substrate). One end of the second conductive structure 30 is connected to the second active layer 28, and the other end of the second conductive structure 30 penetrates and is exposed in the second stop layer 262'. The second redistribution layer 32 is formed on the second active layer 28.

[0036] like Figure 1H As shown, a third wiring layer 36 is formed on the dielectric layer 34 and a partially remaining, extremely thin second stop layer 262'. The third wiring layer 36 is electrically connected to the exposed first conductive structure 18 and second conductive structure 30. The third wiring layer 36 has good adhesion to the second stop layer 262', therefore the third wiring layer 36 is not easily peeled off. Figure 1IAs shown, a plurality of solder balls 38 are formed on the third wiring layer 36. In one embodiment, the solder balls 38 are electrically connected to, for example, the first conductive structure 18 and the second conductive structure 30 via the third wiring layer 36. Afterwards, after performing chip probing (CP) to test the electrical function, the chip is die-sawed to complete the three-dimensional system-on-a-chip.

[0037] Figure 2 This is a cross-sectional structural diagram of a single chip in a three-dimensional system according to the first embodiment of the present invention. Figure 2 The diagram further illustrates the placement of a 3D system chip 40 on a circuit board 42 or a flexible circuit board, with electrical connections to the circuit board 42 or the flexible circuit board via solder balls 38. Figure 2 As shown, the three-dimensional system single chip 40 includes a memory chip structure 10A, multiple first conductive structures 18, a core die 20A, multiple input / output dies 22A, a dielectric layer 34, a third redistribution layer 36, and multiple solder balls 38. The memory chip structure 10A is the aforementioned memory wafer structure 10 (labeled as...). Figure 1A In one embodiment, the memory chip structure 10A, after being cut into individual chips, includes a semiconductor substrate 44, a first active layer 14, and a first redistribution layer 16. The first active layer 14 is formed on the semiconductor substrate 44, and the first redistribution layer 16 is formed on the first active layer 14. A first conductive structure 18, a core die 20A, and an input / output die 22A are disposed on the first redistribution layer 16, wherein the input / output die 22A is disposed around the core die 20A, and the first conductive structure 18 is located between the input / output die 22A and the core die 20A. The structures of the core die 20A and the input / output die 22A have been described above and will not be repeated here. The second rewiring layer 32 of the core die structure 20A and the input / output die 22A is bonded to the first rewiring layer 16; the dielectric layer 34 fills the space between the core die 20A, the input / output die 22A, and the first conductive structure 18, and exposes the residual second stop layer 262' of the stop layer structure 26 and one end of the second conductive structure 30; the third rewiring layer 36 is formed on the dielectric layer 34 and the residual second stop layer 262', and the third rewiring layer 36 is electrically connected to the exposed first conductive structure 18 and the exposed second conductive structure 30; a plurality of solder balls 38 are formed on the third rewiring layer 36.

[0038] Figure 3 This is a bottom view of a three-dimensional system single chip according to an embodiment of the present invention, that is, viewed from the solder ball side, as shown. Figure 3 As shown, multiple solder balls 38 are arranged on the third wiring layer 36. Figure 3The positions of the core die 20A and the input / output die 22A are indicated by dashed lines, with the input / output die 22A located around the core die 20A. In one embodiment, the plurality of solder balls 38 may include signal solder balls 381 and power / ground solder balls 382, ​​wherein some of the power / ground solder balls 382 can provide power or ground to the core die 20A and the input / output die 22A, and some of the power / ground solder balls 382 can also provide power or ground to the memory chip structure 10A via the third wiring layer 36 and the first conductive structure 18, and some of the signal solder balls 381 can serve as the signal transmission medium for the input / output die 22A, wherein the signals of the input / output die 22A may, for example, originate from the core die 20A and / or the circuit board 42, and the core die 20A and the memory chip structure 10A have, for example, a three-level cache (L3 cache) access mechanism.

[0039] Figures 4A to 4H The diagram shown is a cross-sectional schematic of a manufacturing method for a three-dimensional system single chip according to a second embodiment of the present invention. Figure 4A As shown, a SoC wafer structure 50 is provided, divided into an independent core die region 501 and multiple input / output die regions 502. The input / output die regions 502 are disposed around the core die region 501. The SoC wafer structure 50 includes a semiconductor wafer 52, a stop layer structure 54, a second active layer 56, multiple conductive structures 58, and a second redistribution layer 60. The semiconductor wafer 52 has an opposing active surface 521 and a back surface 522. The stop layer structure 54 is formed within the semiconductor wafer 52, dividing the semiconductor wafer 52 into a first wafer portion 523 and a second wafer portion 524. The first wafer portion 523 is located between the stop layer structure 54 and the active surface 521, and the second wafer portion 524 is located between the stop layer structure 54 and the back surface 522. In one embodiment, the stop layer structure 54 includes a first stop layer 541 and a second stop layer 542 stacked on top of each other. The material of the first stop layer 541 is different from the material of the second stop layer 542. The second stop layer 542 is located between the first stop layer 541 and the active surface 521. The first stop layer 541 is, for example, a silicon nitride (Si3N4) layer, and the second stop layer 542 is, for example, a silicon dioxide (SiO2) layer. The manufacturing process of the stop layer structure 54 is the same as or similar to that of the stop layer structure 26 disclosed in the first embodiment, and will not be described again here.

[0040] Continuing from the above description, the second active layer 56 is formed on the active surface 521 of the semiconductor wafer 52; the conductive structure 58 is formed on the first portion 523 of the wafer to connect the second active layer 56 and the stop layer structure 54. In one embodiment, the conductive structure 58 is, for example, a conductive pillar; and the second redistribution layer 60 is formed on the second active layer 56. For example, metal wiring, metal pillars (VIA), and microbumps are formed on the second redistribution layer 60.

[0041] like Figure 4B As shown, multiple memory chips 62 are provided. Figure 4B Only three memory chips 62 are shown, but the representation is not limited to these. Each memory chip 62 includes a chip substrate 64, a first active layer 66, and a first redistribution layer 68. The first active layer 66 is formed on the chip substrate 64, and basic memory elements such as transistors are formed on the first active layer 66. The first redistribution layer 68 is formed on the first active layer 66, and metal wiring, metal pillars (VIAs), and microbumps are formed on the first redistribution layer 68, for example. Figure 4B As shown, multiple memory dies 62 are inverted, and the first overlay layer 68 of each memory die 62 is bonded to the second overlay layer 60 of the core die region 501 of the SoC wafer structure 50. In one embodiment, the first overlay layer 68 is bonded to the second overlay layer 60 using a hybrid bonding technique.

[0042] like Figure 4C As shown, a dielectric filling process is performed to form a dielectric layer 70 covering the memory die 62. In one embodiment, the dielectric layer 70 is disposed on the SoC wafer structure 50 and filled between multiple memory dies 62, and the top surface of the dielectric layer 70 is flush with the die substrate 64 of the memory die 62.

[0043] Next, a back-side grinding process is performed, grinding is performed on the back side 522 of the semiconductor wafer 52 to remove a portion of the second part 524 of the wafer, such as... Figure 4D As shown, a very thin second portion 524' of the wafer remains. A thinning process is then performed to remove the remaining second portion 524' and part of the stop layer structure 54 to expose the conductive structure 58. In one embodiment, the thinning process includes a first removal step and a second removal step, the first removal step being used to remove the remaining second portion 524' of the wafer, as shown... Figure 4E As shown, the stop layer structure 54 is exposed, for example, the first stop layer 541 is exposed; the second removal step is used to remove a portion of the stop layer structure 54, that is, to sequentially remove the first stop layer 541 and a portion of the second stop layer 542, as shown. Figure 4F As shown, the conductive structure 58 is exposed with a very thin second stop layer 542' remaining. The processes and methods selectable for the first and second removal steps have been disclosed in the first embodiment and will not be repeated here. The thinning process exposes the SoC wafer structure 50 (labeled as shown in the diagram). Figure 4A The wafer is thinned to form a thinned SoC wafer structure 50'.

[0044] like Figure 4GAs shown, a third wiring layer 72 is formed on the partially remaining and extremely thin second stop layer 542'. The third wiring layer 72 is electrically connected to the exposed conductive structure 58. The third wiring layer 72 has good adhesion to the second stop layer 542', therefore the third wiring layer 72 is not easily peeled off from the thinned SoC wafer structure 50'. Figure 4H As shown, a plurality of solder balls 74 are formed on the third wiring layer 72. In one embodiment, the solder balls 74 are electrically connected to, for example, a conductive structure 58 via the third wiring layer 72. Afterwards, after wafer probing to perform electrical functional testing, the wafers are cut to complete the three-dimensional system-on-a-chip.

[0045] Figure 5 This is a cross-sectional structural diagram of a three-dimensional system single chip according to the second embodiment of the present invention. Figure 5 The diagram further illustrates the placement of a 3D system chip 80 on a circuit board 42 or a flexible circuit board, with electrical connections to the circuit board 42 or the flexible circuit board via solder balls 74. Figure 5 As shown, the three-dimensional system-on-a-chip 80 includes multiple memory dies 62, a dielectric layer 70, a SoC chip 50A, a third redistribution layer 72, and multiple solder balls 74. The structure of each memory die 62 has been revealed in... Figure 4B The details will not be repeated here; the dielectric layer 70 fills the spaces between the memory chips 62; the SoC chip 50A is the aforementioned thinned SoC wafer structure 50' (marked in...). Figure 4F After being cut into individual chips, the SoC chip 50A is divided into an independent core die 501A and multiple input / output dies 502A. The input / output dies 502A are disposed around the core die 501A. The SoC chip 50A includes a substrate 52A (i.e., the first part of the wafer 523 after being cut into individual chips), a residual second stop layer 542' of the stop layer structure 54, a second active layer 56, multiple conductive structures 58, and a second redistribution layer 60. The second active layer 56 and the residual second stop layer 542' are respectively disposed on opposite sides of the substrate 52A. The conductive structures 58 are formed on the substrate 52A. One end of each conductive structure 58 is connected to the second active layer 56, and the other end of each conductive structure 58 penetrates and is exposed in the residual second stop layer 542'. A first wiring layer 68 of multiple memory dies 62 covered by dielectric layer 70 is bonded to a second wiring layer 60 of core die 502A; a third wiring layer 72 is formed on the residual second stop layer 542' and is electrically connected to the exposed conductive structure 58; a plurality of solder balls 74 are formed on the third wiring layer 72.

[0046] Figure 6 This is a bottom view of the three-dimensional system single chip of the second embodiment of the present invention, that is, viewed from the side of solder ball 74, as shown. Figure 6As shown, multiple solder balls 74 are arranged on the third wiring layer 72. Figure 6 The positions of the core die 501A and the input / output die 502A are marked by long dashed lines, with the input / output die 502A located around the core die 501A; Figure 6 The location of the memory chip 62 is marked with dotted lines, as shown in the figure. The memory chip 62 mainly corresponds to the core chip 501A. Although six memory chips 62 are shown in the figure, it is not limited to this.

[0047] Continuing with the above description, in one embodiment, the plurality of solder balls 74 may include signal solder balls 741 and power / ground solder balls 742, wherein the power / ground solder balls 742 may provide power or ground to the core die 501A, input / output die 502A and memory die 62; and some of the signal solder balls 741 may serve as signal transmission and transmission mediums for the input / output die 502A, wherein the signals of the input / output die 502A may, for example, come from the core die 501A and / or the circuit board 42, and the core die 501A and the memory die 62 have, for example, a three-level cache (L3 cache) access mechanism.

[0048] Figures 7A to 7E This is a cross-sectional schematic diagram of the manufacturing method of a three-dimensional system single chip according to the third embodiment of the present invention, as shown below. Figure 7A As shown, a memory wafer structure 10 and a SoC wafer structure 50 are provided. The memory wafer structure 10 includes a wafer 12, a first active layer 14, and a first redistribution layer 16. The first active layer 14 is formed on the wafer 12, and the first redistribution layer 16 is formed on the first active layer 14. Further features of the memory wafer structure 10 have been disclosed in the first embodiment and will not be repeated here. The SoC wafer structure 50 is divided into an independent core die region 501 and a plurality of input / output die regions 502. The input / output die regions 502 are disposed around the core die region 501. The SoC wafer structure 50 includes a semiconductor wafer 52, a stop layer structure 54, a second active layer 56, a plurality of conductive structures 58, and a second redistribution layer 60. The structure and configuration of the SoC wafer structure 50 have been disclosed in the second embodiment and will not be repeated here.

[0049] like Figure 7B As shown, the first redistribution layer 16 of the memory wafer structure 10 is bonded to the second redistribution layer 60 of the SoC wafer structure 50; then, the SoC wafer structure 50 is sequentially subjected to a back-side grinding process and a thinning process, as shown. Figure 7C As shown, one end of the conductive structure 58 is exposed and an extremely thin second stop layer 542' remains. The back-side grinding process and thinning process have been disclosed in the second embodiment and will not be repeated here.

[0050] like Figure 7DAs shown, a third wiring layer 72 is formed on the partially remaining and extremely thin second stop layer 542', and the third wiring layer 72 is electrically connected to the exposed conductive structure 58; then, as Figure 7E As shown, a plurality of solder balls 74 are formed on the third wiring layer 72. In one embodiment, the solder balls 74 are electrically connected to, for example, a conductive structure 58 via the third wiring layer 72. Afterwards, after wafer probing to perform electrical functional testing, the wafers are cut to complete the three-dimensional system-on-a-chip.

[0051] Figure 8 This is a cross-sectional structural diagram of a three-dimensional system single chip according to the third embodiment of the present invention. Figure 8 The diagram further illustrates the placement of a 3D system chip 90 on a circuit board 42 or a flexible circuit board, with electrical connections to the circuit board 42 or the flexible circuit board via solder balls 74. Figure 8 As shown, the three-dimensional system-on-a-chip 90 includes a memory chip structure 10A, a SoC chip 50A, a third wiring layer 72, and multiple solder balls 74. The memory chip structure 10A is a memory wafer structure 10 (labeled as...). Figure 7A After being cut into individual components, the SoC chip 50A is a thinner SoC wafer structure 50' (marked as...). Figure 7C The memory chip structure 10A is formed after being cut into individual components. The first rewiring layer 16 of the memory chip structure 10A and the second rewiring layer 60 of the SoC chip 50A are bonded together face-to-face. In one embodiment, the first rewiring layer 16 is bonded to the second rewiring layer 60 using a hybrid bonding technique. A third rewiring layer 72 is formed on the residual second stop layer 542' and is electrically connected to the exposed conductive structure 58; a plurality of solder balls 74 are formed on the third rewiring layer 72.

[0052] According to the above, in one embodiment of the present invention, a three-dimensional system-on-a-chip includes a memory chip, a core die covered by a dielectric layer, and a plurality of input / output dies, wherein the input / output dies are located around the core die, and the memory chip is bonded to the core die; in one embodiment of the present invention, a three-dimensional system-on-a-chip includes a SoC chip and a plurality of memory dies covered by a dielectric layer, the SoC chip includes an independent core die and a plurality of input / output dies located around the core die, and the core die is bonded to the plurality of memory dies; in one embodiment of the present invention, a three-dimensional system-on-a-chip includes a memory chip and an SoC chip, the SoC chip includes an independent core die and a plurality of input / output dies located around the core die, and the core die is bonded to the memory chip. In the three-dimensional system-on-a-chip embodiment of the present invention, whether it is the core die, input / output die, or SoC chip, the thickness can be reduced to a very thin thickness by setting the stop layer structure therein. For example, the overall thickness of the core die, input / output die, or SoC chip is no more than 12 micrometers. This greatly reduces the overall thickness of the three-dimensional system-on-a-chip, which can meet the requirements of high integration and speed, and has better electrical characteristics and efficiency.

[0053] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications or alterations to the methods and techniques disclosed above without departing from the scope of the present invention to create equivalent embodiments. Any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of the present invention without departing from the scope of the present invention shall still fall within the scope of the present invention.

Claims

1. A method for manufacturing a three-dimensional system single chip, characterized in that, include: A plurality of memory dies are provided, each of the memory dies including a die substrate, a first active layer and a first redistribution layer, wherein the first active layer is formed on the die substrate and the first redistribution layer is formed on the first active layer; A SoC wafer structure is provided, divided into at least one independent core die region and multiple input / output die regions. The input / output die regions are disposed around the at least one core die region. The SoC wafer structure includes a semiconductor wafer, a stop layer structure, a second active layer, multiple conductive structures, and a second redistribution layer. The semiconductor wafer has opposing active surfaces and back surfaces. The stop layer structure is formed within the semiconductor wafer, dividing the semiconductor wafer into a first wafer portion and a second wafer portion. The first wafer portion is located between the stop layer structure and the active surface, and the second wafer portion is located between the stop layer structure and the back surface. The second active layer is formed on the active surface. The conductive structures are formed on the first wafer portion to connect the second active layer and the stop layer structure. The second redistribution layer is formed on the second active layer. The first redistribution layer of each memory die is bonded to the second redistribution layer of at least one core die region of the SoC wafer structure; A dielectric filling process is performed to form a dielectric layer covering the memory die; A back-side grinding process is performed to grind from the back side of the semiconductor wafer to remove a portion of the second part of the wafer; A thinning process is performed to remove the remaining second portion of the wafer and a portion of the stop layer structure to expose the conductive structure; A third wiring layer is formed on the remaining portion of the stop layer structure, and the third wiring layer is electrically connected to the exposed conductive structure; Multiple solder balls are formed on the third wiring layer; as well as Cut the order.

2. The method for manufacturing a three-dimensional system single chip as described in claim 1, characterized in that, The stop layer structure includes a first stop layer and a second stop layer stacked on top of each other. The material of the first stop layer is different from the material of the second stop layer. The second stop layer is located between the first stop layer and the second active layer. In the thinning process, the step of removing a portion of the stop layer structure includes first removing the first stop layer and then removing a portion of the second stop layer.

3. The method for manufacturing a three-dimensional system single chip as described in claim 2, characterized in that, The first stop layer is a silicon nitride layer, and the second stop layer is a silicon dioxide layer.

4. The method for manufacturing a three-dimensional system single chip as described in claim 3, characterized in that, The steps for forming the silicon nitride layer and the silicon dioxide layer include performing a nitrogen ion implantation process at a first depth of the semiconductor wafer, followed by an oxygen ion implantation process at a second depth of the semiconductor wafer, wherein the second depth is smaller than the first depth, and then performing a high-temperature processing process, so that the region where the nitrogen ion was implanted forms the silicon nitride layer and the region where the oxygen ion was implanted forms the silicon dioxide layer.

5. The method for manufacturing a three-dimensional system single chip as described in claim 3, characterized in that, The method for removing the silicon nitride layer and the silicon dioxide layer is selected from one of chemical mechanical polishing and plasma dry etching, wherein the selection ratio of silicon nitride to silicon dioxide is between 10 and 20, and the selection ratio of silicon dioxide to silicon is 5.

6. The method for manufacturing a three-dimensional system single chip as described in claim 1, characterized in that, The thinning process includes: The first removal step involves removing the remaining second portion of the wafer; and The second removal step involves removing a portion of the stop layer structure to expose the conductive structure.

7. The method for manufacturing a three-dimensional system single chip as described in claim 6, characterized in that, The first removal step is selected from one of chemical mechanical polishing, wet etching and plasma dry etching, and the second removal step is selected from one of chemical mechanical polishing and plasma dry etching.

8. The method for manufacturing a three-dimensional system single chip as described in claim 1, characterized in that, The second redistribution layer is bonded to the first redistribution layer using a hybrid bonding technique.

9. A method for manufacturing a three-dimensional system single chip, characterized in that, include: A memory wafer structure is provided, including a wafer, a first active layer and a first redistribution layer, wherein the first active layer is formed on the wafer and the first redistribution layer is formed on the first active layer; A SoC wafer structure is provided, divided into at least one independent core die region and multiple input / output die regions. The input / output die regions are disposed around the at least one core die region. The SoC wafer structure includes a semiconductor wafer, a stop layer structure, a second active layer, multiple conductive structures, and a second redistribution layer. The semiconductor wafer has opposing active surfaces and back surfaces. The stop layer structure is formed within the semiconductor wafer, dividing the semiconductor wafer into a first wafer portion and a second wafer portion. The first wafer portion is located between the stop layer structure and the active surface, and the second wafer portion is located between the stop layer structure and the back surface. The second active layer is formed on the active surface. The conductive structures are formed on the first wafer portion to connect the second active layer and the stop layer structure. The second redistribution layer is formed on the second active layer. The first redistribution layer of the memory wafer structure is bonded to the second redistribution layer of the SoC wafer structure; A back-side grinding process is performed to grind from the back side of the semiconductor wafer to remove a portion of the second part of the wafer; A thinning process is performed to remove the remaining second portion of the wafer and a portion of the stop layer structure to expose the conductive structure; A third wiring layer is formed on the first portion of the wafer, and the third wiring layer is electrically connected to the exposed conductive structure. Multiple solder balls are formed on the third wiring layer; as well as Cut the order.

10. The method for manufacturing a three-dimensional system single chip as described in claim 9, characterized in that, The stop layer structure includes a first stop layer and a second stop layer stacked on top of each other. The material of the first stop layer is different from the material of the second stop layer. The second stop layer is located between the first stop layer and the second active layer. In the thinning process, the step of removing a portion of the stop layer structure includes first removing the first stop layer and then removing a portion of the second stop layer.

11. The method for manufacturing a three-dimensional system single chip as described in claim 10, characterized in that, The first stop layer is a silicon nitride layer, and the second stop layer is a silicon dioxide layer.

12. The method for manufacturing a three-dimensional system single chip as described in claim 11, characterized in that, The steps for forming the silicon nitride layer and the silicon dioxide layer include performing a nitrogen ion implantation process at a first depth of the semiconductor wafer, followed by an oxygen ion implantation process at a second depth of the semiconductor wafer, wherein the second depth is smaller than the first depth, and then performing a high-temperature processing process, so that the region where the nitrogen ion was implanted forms the silicon nitride layer and the region where the oxygen ion was implanted forms the silicon dioxide layer.

13. The method for manufacturing a three-dimensional system single chip as described in claim 11, characterized in that, The method for removing the silicon nitride layer and the silicon dioxide layer is selected from one of chemical mechanical polishing and plasma dry etching, wherein the selection ratio of silicon nitride to silicon dioxide is between 10 and 20, and the selection ratio of silicon dioxide to silicon is 5.

14. The method for manufacturing a three-dimensional system single chip as described in claim 9, characterized in that, The thinning process includes: The first removal step involves removing the remaining second portion of the wafer; and The second removal step involves removing a portion of the stop layer structure to expose the conductive structure.

15. The method for manufacturing a three-dimensional system single chip as described in claim 14, characterized in that, The first removal step is selected from one of chemical mechanical polishing, wet etching and plasma dry etching, and the second removal step is selected from one of chemical mechanical polishing and plasma dry etching.

16. The method for manufacturing a three-dimensional system single chip as described in claim 9, characterized in that, The second redistribution layer is bonded to the first redistribution layer using a hybrid bonding technique.

Images