Chip packaging structure and method for manufacturing the same

Abstract

The application provides a chip packaging structure preparation method and a chip packaging structure, and relates to the technical field of semiconductors.The chip packaging structure preparation method comprises the following steps: providing a substrate with a dielectric layer; forming a TSV structure in the substrate, wherein one end of the TSV structure close to the dielectric layer extends to the dielectric layer; and forming a heat dissipation piece in the dielectric layer, wherein the heat dissipation piece surrounds the TSV structure in the dielectric layer, and the surface of the heat dissipation piece close to the TSV structure is arranged in close contact with the TSV structure.The application forms a heat dissipation piece in the dielectric layer, and the heat dissipation piece surrounds the TSV structure in the dielectric layer, so that the heat generated by the TSV structure is diffused to the outside of the chip through the heat dissipation piece, the temperature of the chip is reduced, the damage of the temperature to the chip is reduced, and the performance of the chip is improved.In addition, the temperature of the chip is reduced through the heat dissipation piece, and the deformation between the TSV structure and the substrate or between the TSV structure and the dielectric layer is prevented, so that the yield of the chip is improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a method for preparing a chip packaging structure and the chip packaging structure thereof. Background Technology

[0002] With the continuous development of integrated circuit design and manufacturing capabilities, electronic products are trending towards miniaturization and high integration, giving rise to multilayer chip packaging technology. Multilayer chip packaging, also known as 3D packaging technology, refers to packaging technology that vertically stacks two or more chips within the same package. For example, in Dynamic Random Access Memory (DRAM), multiple chips are vertically stacked and interconnected using 3D packaging technology to increase the DRAM's storage capacity.

[0003] In 3D packaging technology, it is usually necessary to create corresponding through-holes on each chip, fill the through-holes with conductive material to form a TSV structure, and use the TSV structure to achieve vertical conduction between stacked chips.

[0004] However, the TSV structure generates a lot of heat when the chip is working, which affects the performance of the TSV structure and thus reduces the performance of the chip. Summary of the Invention

[0005] In view of the above problems, embodiments of the present invention provide a method for preparing a chip packaging structure and a chip packaging structure, which transfers the heat generated by the TSV structure to the outside of the chip through a heat sink, thereby improving the performance of the TSV structure and the chip.

[0006] To achieve the above objectives, the embodiments of the present invention provide the following technical solutions:

[0007] A first aspect of this invention provides a method for fabricating a chip packaging structure, comprising the following steps:

[0008] A substrate is provided, on which a dielectric layer is disposed;

[0009] A TSV structure is formed within the substrate, with one end of the TSV structure near the dielectric layer extending into the dielectric layer;

[0010] A heat sink is formed within the dielectric layer, the heat sink surrounds the TSV structure located within the dielectric layer, and the heat sink is disposed close to the surface of the TSV structure and in contact with the TSV structure.

[0011] The method for fabricating a chip packaging structure as described above, wherein the step of forming a heat sink within the dielectric layer includes:

[0012] A first through-hole is formed within the dielectric layer, the first through-hole surrounding the TSV structure located within the dielectric layer and exposing the surface of the TSV structure;

[0013] A first metal layer is formed in the first through hole, the first metal layer fills the first through hole, and the first metal layer constitutes a first heat dissipation component.

[0014] A second heat sink is formed within the dielectric layer, the second heat sink is disposed around the first heat sink, and a heat dissipation gap extending circumferentially within the second heat sink is formed therein.

[0015] The method for fabricating a chip package structure as described above, wherein the step of forming a second heat sink within the dielectric layer includes:

[0016] Step a: Form a second through hole in the dielectric layer, wherein the second through hole is located on the side of the first heat sink away from the TSV structure;

[0017] Step b: A second metal layer is formed on the sidewall and bottom wall of the second through hole, the second metal layer forming the intermediate hole;

[0018] Step c: An insulating layer for sealing the intermediate hole is formed inside the intermediate hole, and a heat dissipation gap is formed between the insulating layer and the bottom wall of the intermediate hole. The second metal layer, the heat dissipation gap and the insulating layer constitute a second heat dissipation component.

[0019] Repeat steps a, b, and c at least once until multiple second heat sinks are formed.

[0020] In the chip packaging structure fabrication method described above, the bottom walls of the heat dissipation gaps of the plurality of second heat sinks are distributed in a stepped manner.

[0021] The method for fabricating a chip packaging structure as described above, wherein the step of forming a TSV structure within the substrate includes:

[0022] A first accommodating hole is formed within the dielectric layer, penetrating the dielectric layer;

[0023] The substrate exposed within the first receiving hole is removed to form a second receiving hole within the substrate, the first receiving hole and the second receiving hole constituting a receiving hole;

[0024] The TSV structure is formed within the accommodating hole.

[0025] The method for fabricating a chip package structure as described above, wherein the step of forming a first via in the dielectric layer includes:

[0026] A first photoresist layer is formed on the dielectric layer, and a first annular opening is formed in the first photoresist layer. The projection of the first annular opening in the dielectric layer surrounds the TSV structure.

[0027] The dielectric layer exposed within the first annular opening is removed to form a first through-hole within the dielectric layer, the first through-hole exposing the surface of the TSV structure.

[0028] The method for fabricating a chip package structure as described above, wherein the step of forming a second via within the dielectric layer includes:

[0029] A second photoresist layer is formed within the dielectric layer, and a second annular opening is provided within the second photoresist layer. The projection of the second annular opening on the dielectric layer surrounds the first heat sink.

[0030] Remove the dielectric layer exposed within the second annular opening to form a second through-hole within the dielectric layer.

[0031] In the chip packaging structure fabrication method described above, the first metal layer and the second metal layer are made of the same material, and the material of the first metal layer and the second metal layer includes one of copper, aluminum, gold and tantalum.

[0032] A second aspect of this invention provides a chip packaging structure, comprising:

[0033] A substrate on which a dielectric layer is disposed;

[0034] A TSV structure is disposed within the substrate, and one end of the TSV structure opposite to the substrate extends to the dielectric layer.

[0035] A heat sink is disposed within the dielectric layer and surrounds the TSV structure located within the dielectric layer, wherein the surface of the heat sink near the TSV structure is fitted to the TSV structure.

[0036] In the chip packaging structure described above, the heat sink includes a first heat sink and a second heat sink;

[0037] The first heat sink surrounds the TSV structure located within the dielectric layer, and the surface of the first heat sink near the TSV structure is fitted to the TSV structure located within the dielectric layer.

[0038] The second heat sink is disposed around the first heat sink, and the surface of the second heat sink near the first heat sink is fitted to the first heat sink. A heat dissipation gap extending circumferentially along the second heat sink is formed inside the second heat sink.

[0039] In the chip packaging structure described above, the cross-sectional shape of the TSV structure is circular, with the cross-section taken in a direction parallel to the substrate.

[0040] There are multiple second heat sinks, which are stacked sequentially along an axis perpendicular to the TSV structure.

[0041] As described above, the heat dissipation gaps in adjacent second heat sinks have a height difference.

[0042] In the chip packaging structure described above, the height of the heat dissipation gap gradually decreases from the end closest to the TSV structure to the end furthest from the TSV structure along the axial direction perpendicular to the TSV structure.

[0043] In the chip packaging structure described above, the height difference between adjacent heat dissipation gaps is between 0.2 and 0.5 μm.

[0044] In the chip packaging structure described above, the height of the heat dissipation gap is between 0.3 and 1 μm along a direction perpendicular to the substrate.

[0045] In the chip packaging structure preparation method and chip packaging structure provided in the embodiments of the present invention, a heat dissipation component is formed in the dielectric layer, which surrounds the TSV structure located in the dielectric layer. In this way, the heat generated by the TSV structure is diffused to the outside of the chip through the heat dissipation component, thereby reducing the temperature of the chip, reducing temperature damage to the chip, and improving the chip performance. In addition, reducing the temperature of the chip by the heat dissipation component can also prevent deformation between the TSV structure and the substrate or between the TSV structure and the dielectric layer, thereby improving the chip yield.

[0046] In addition to the technical problems solved by the embodiments of the present invention, the technical features constituting the technical solutions, and the beneficial effects brought about by the technical features of these technical solutions described above, other technical problems that can be solved by the chip packaging structure preparation method and the chip packaging structure provided by the embodiments of the present invention, other technical features included in the technical solutions, and the beneficial effects brought about by these technical features will be further explained in detail in the specific embodiments. Attached Figure Description

[0047] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0048] Figure 1This is a schematic diagram of a chip packaging structure provided in related technologies;

[0049] Figure 2 A process flow diagram of the method for fabricating a chip packaging structure provided in an embodiment of the present invention;

[0050] Figure 3 This is a schematic diagram of the structure forming the substrate and dielectric layer in the chip packaging structure fabrication method provided in the embodiments of the present invention;

[0051] Figure 4 This is a schematic diagram of the structure forming the first accommodating hole and the second accommodating hole in the chip packaging structure fabrication method provided in the embodiments of the present invention;

[0052] Figure 5 This is a schematic diagram of the TSV structure formed in the chip packaging structure fabrication method provided in the embodiments of the present invention;

[0053] Figure 6 A schematic diagram of the structure for forming the first photoresist layer in the chip packaging structure fabrication method provided in the embodiment of the present invention;

[0054] Figure 7 This is a schematic diagram of the structure for forming the first through hole in the chip packaging structure fabrication method provided in the embodiments of the present invention;

[0055] Figure 8 A schematic diagram of the structure forming the first heat sink in the chip packaging structure fabrication method provided in the embodiment of the present invention;

[0056] Figure 9 A schematic diagram of the formation of the second photoresist layer in the chip packaging structure fabrication method provided in the embodiment of the present invention;

[0057] Figure 10 This is a schematic diagram of the structure for forming the first second through hole in the chip packaging structure fabrication method provided in the embodiments of the present invention;

[0058] Figure 11 A schematic diagram of the structure for forming the first second metal layer in the chip packaging structure fabrication method provided in the embodiment of the present invention;

[0059] Figure 12 A schematic diagram of the structure forming the first second heat sink in the chip packaging structure fabrication method provided in the embodiment of the present invention;

[0060] Figure 13 This is a schematic diagram of the structure for forming the second through-hole in the chip packaging structure fabrication method provided in the embodiments of the present invention;

[0061] Figure 14This is a schematic diagram of the structure for forming the second metal layer in the chip packaging structure fabrication method provided in this embodiment of the invention;

[0062] Figure 15 A schematic diagram of the structure for forming the second heat sink in the chip packaging structure fabrication method provided in the embodiment of the present invention;

[0063] Figure 16 This is a schematic diagram of the structure for forming the third second through hole in the chip packaging structure fabrication method provided in the embodiments of the present invention;

[0064] Figure 17 A schematic diagram of the structure for forming the third second metal layer in the chip packaging structure fabrication method provided in the embodiments of the present invention;

[0065] Figure 18 This is a schematic diagram of the structure for forming the third second heat sink in the preparation method provided in the embodiment of the present invention.

[0066] Figure label:

[0067] 10: Substrate; 11: Second receiving hole;

[0068] 20: Dielectric layer; 21: First via;

[0069] 22: Second through hole; 23: Middle hole;

[0070] 24: First receiving hole; 30: TSV structure;

[0071] 40: Heat sink; 41: First heat sink;

[0072] 42: Second heat sink; 421: Heat dissipation gap;

[0073] 422: Second metal layer; 423: Insulating layer;

[0074] 50: First photoresist layer; 51: First annular opening;

[0075] 60: Second photoresist layer; 61: Second annular opening;

[0076] 70: Interconnection structure. Detailed Implementation

[0077] like Figure 1As shown, a chip package structure typically includes a substrate 10 and a dielectric layer 20 disposed on the substrate 10. The dielectric layer 20 has a TSV structure 30. One end of the TSV structure 30 extends into the substrate 10, and the bottom surface of the TSV structure 30 is flush with the bottom surface of the substrate 10 for electrical connection with the active area of ​​the substrate 10. The other end of the TSV structure 30 is used for electrical connection with the interconnect structure 70 disposed in the dielectric layer 20 to realize the electrical connection between the interconnect structure and the active area. In addition, when multiple chips are stacked together, the TSV structure is also used to realize vertical conduction between adjacent chips. During chip operation, the TSV structure generates a large amount of heat. Normally, this heat is mainly diffused to the outside of the chip through the substrate. However, the substrate has poor thermal conductivity, causing a large amount of heat to accumulate inside the chip. The heat accumulated inside the chip affects the conductivity of the TSV structure, thereby reducing the chip's performance. In addition, the TSV structure may also expand or contract due to thermal stress, causing strain between the TSV structure and the substrate, or between the TSV structure and the dielectric layer. This deformation can damage the chip and reduce its yield.

[0078] To address the aforementioned technical problems, embodiments of the present invention provide a method for fabricating a chip packaging structure and a chip packaging structure. By forming a heat sink within a dielectric layer, the heat sink surrounds and is attached to the TSV structure located within the dielectric layer. In this way, the heat generated by the TSV structure is diffused to the outside of the chip through the heat sink, reducing the chip temperature and thus reducing temperature-related damage to the chip, thereby improving chip performance. In addition, reducing the chip temperature through the heat sink can also prevent deformation between the TSV structure and the substrate, or between the TSV structure and the dielectric layer, thereby improving chip yield.

[0079] To make the above-mentioned objectives, features, and advantages of the embodiments of the present invention more apparent and understandable, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are merely some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0080] Figure 2 A process flow diagram of the method for fabricating a chip packaging structure provided in an embodiment of the present invention;

[0081] Figures 3 to 18 The diagram below illustrates the various stages of the chip packaging structure fabrication process. Figures 2-18 The fabrication methods and structures of chip packaging are described in detail.

[0082] like Figure 2As shown in the figure, the chip packaging structure fabrication method also provided in this embodiment of the invention includes the following steps:

[0083] Step S100: Provide a substrate on which a dielectric layer is disposed.

[0084] For example, such as Figure 3 As shown, a substrate 10 can be provided first, and then a dielectric layer 20 of a certain thickness can be deposited on the substrate 10 by physical vapor deposition or chemical vapor deposition. The substrate 10 serves as a support component for the chip, supporting other components disposed thereon. The substrate 10 can be made of semiconductor material, which can be one or more of silicon, germanium, silicon-germanium compounds, and silicon-carbon compounds.

[0085] The dielectric layer 20 can be used to form interconnect structures or gate structures of transistors. The material of the dielectric layer 20 may include silicon nitride or silicon oxide.

[0086] Step S200: A TSV structure is formed in the substrate, with one end of the TSV structure near the dielectric layer extending into the dielectric layer.

[0087] For example, such as Figure 4 As shown, a first accommodating hole 24 penetrating the dielectric layer 20 can be formed first in the dielectric layer 20. That is, an etching solution or etching gas can be used to remove part of the dielectric layer 20 to form the first accommodating hole 24 in the dielectric layer 20.

[0088] After the first accommodating hole 24 is formed, an etching solution or etching gas is used to remove the substrate 10 exposed in the first accommodating hole 24, so as to form a second accommodating hole 11 in the substrate 10. The second accommodating hole 11 and the first accommodating hole 24 constitute an accommodating hole.

[0089] After that, as Figure 5 As shown, conductive metal is then filled into the accommodating holes using physical vapor deposition or chemical vapor deposition processes. The conductive metal fills the accommodating holes completely to form a TSV structure 30.

[0090] It should be noted that the top surface of the TSV structure can be flush with the top surface of the dielectric layer or extend into the dielectric layer. When the top surface of the TSV structure is flush with the top surface of the dielectric layer, a silicon oxide layer can be formed on the dielectric layer to facilitate the formation of interconnect structures within the silicon oxide layer. For example, the interconnect structure may include a metal layer M1 formed within the silicon oxide layer. When the TSV structure extends into the interior of the dielectric layer, during the fabrication of the TSV structure, vias can be formed on the substrate first, and then a portion of the dielectric layer located within the vias can be etched to form etched holes communicating with the vias. After that, the TSV structure is formed within the vias and etched holes, and finally, a metal layer M1 is formed within the dielectric layer.

[0091] Step S300: A heat sink is formed within the dielectric layer. The heat sink surrounds the TSV structure located within the dielectric layer, and the surface of the heat sink near the TSV structure is attached to the TSV structure.

[0092] In this embodiment, the surface of the heat sink 40 near the TSV structure 30 is fitted to the TSV structure 30, so that the heat generated by the TSV structure can be conducted to the heat sink 40 in a timely manner, preventing heat from accumulating on the chip.

[0093] The heat sink 40 can be a solid ring surrounding the TSV structure 30 located within the dielectric layer 20, or a hollow ring surrounding the TSV structure 30 located within the dielectric layer 20, or a combination of a solid ring and a hollow ring.

[0094] For example, such as Figure 6 As shown, a first photoresist layer 50 is formed on the dielectric layer 20. That is, the first photoresist layer 50 can be formed on the dielectric layer 20 by coating process, and then a first annular opening 51 is formed on the first photoresist layer 50 by exposure, development or etching process. The projection of the first annular opening 51 in the dielectric layer 20 surrounds the TSV structure 30.

[0095] like Figure 7 As shown, an etching solution or etching gas is used to remove the dielectric layer 20 exposed in the first annular opening 51 to form a first through hole 21 in the dielectric layer. The first through hole 21 exposes the surface of the TSV structure 30 located in the dielectric layer 20. In other words, the surface of the TSV structure 30 constitutes the inner wall of the first through hole 21.

[0096] like Figure 8 As shown, a first metal layer is formed in the first through hole 21, which fills the first through hole 21 and constitutes the first heat sink 41.

[0097] In this embodiment, a solid thermally conductive metal can be deposited in the first through-hole using a chemical vapor deposition process to form a first metal layer. Alternatively, a liquid thermally conductive metal can be filled into the first through-hole using a spin-coating process, and the liquid thermally conductive metal can solidify to form the first metal layer. The thermally conductive metal may include one of copper, aluminum, gold, and tantalum.

[0098] like Figures 9 to 18 As shown, a second heat sink 42 is formed in the dielectric layer 20. The second heat sink 42 is arranged around the first heat sink 41, and a heat dissipation gap 421 extending circumferentially in the second heat sink 42 is formed therein. That is, the second heat sink 42 is a hollow ring structure.

[0099] The TSV structure generates a large amount of heat during operation. This heat is first rapidly transferred to the first heat sink, and then from the first heat sink to the second heat sink. When the heat is transferred to the second heat sink, its larger surface area accelerates the heat diffusion, preventing heat accumulation within the chip and improving chip performance and yield. On the other hand, the low dielectric constant of the heat dissipation gap within the second heat sink reduces the parasitic capacitance formed between the TSV structure and other components in the substrate, further improving chip performance. Therefore, this embodiment, by designing the heat sink as a combination of a solid ring and a hollow ring, not only improves the heat dissipation capacity of the heat sink but also reduces the parasitic capacitance formed between the TSV structure and other components.

[0100] The process of forming the second heat sink may include the following steps:

[0101] Step a: A second through hole 22 is formed in the dielectric layer 20. The second through hole 22 is located on the side of the first heat sink 41 away from the TSV structure 30.

[0102] For example, such as Figure 9 As shown, a second photoresist layer 60 can be formed on the dielectric layer 20. That is, the second photoresist layer 60 can be formed on the dielectric layer 20 by coating process, and then a second annular opening 61 can be formed on the second photoresist layer 60 by exposure, development or etching process. The projection of the second annular opening 61 in the dielectric layer 20 surrounds the first heat sink 41.

[0103] like Figure 10 As shown, the dielectric layer 20 exposed within the second annular opening 61 is removed to form a second through-hole 22 within the dielectric layer 20.

[0104] In this embodiment, along the axis perpendicular to the TSV structure 30, the width of the second through hole 22 is between 0.05 and 0.5 μm, for example, it can be 0.1 μm, 0.2 μm, 0.3 μm, and 0.4 μm. If the width of the second through hole 22 is less than 0.05 μm, it will increase the difficulty of fabricating the second through hole and the difficulty of forming a heat dissipation gap within the second heat sink, thus reducing the heat dissipation effect of the second heat sink. If the width of the second through hole 22 is greater than 0.5 μm, it will increase the amount of the second metal layer used, thereby increasing the manufacturing cost of the second heat sink.

[0105] Therefore, by limiting the width of the second through hole, this embodiment aims to both ensure the heat dissipation effect of the second heat sink and reduce its manufacturing cost.

[0106] Step b, as follows Figure 11As shown, a second metal layer 422 can be formed on the sidewall and bottom wall of the second through hole 22 by a deposition process, and the second metal layer 422 surrounds the intermediate hole 23.

[0107] For example, a thermally conductive metal can be formed on the sidewalls and bottomwalls of the second via 22 using a chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD) process. This thermally conductive metal extends beyond the second via 22 and covers the top surface of the dielectric layer 20, the first heat sink 41, and the TSV structure 30. Then, an etching gas or etching solution is used to remove the thermally conductive metal on the top surface of the dielectric layer 20, the first heat sink 41, and the TSV structure 30, leaving the conductive metal inside the second via. The retained thermally conductive metal forms the second metal layer 422, wherein the material of the thermally conductive metal includes one of copper, aluminum, gold, and tantalum.

[0108] It should be noted that, in this embodiment, the thickness of the second metal layer can be equal or unequal everywhere, for example, as shown below. Figure 11 As shown, the thickness of the second metal layer 422 on the bottom wall of the second via 22 is greater than the thickness of the second metal layer 422 on the side wall of the second via 22. This can increase the thermal conductivity of the second metal layer 422 on the bottom wall of the second via 22, and better transfer the heat in the substrate to the outside of the chip, so as to ensure the performance and yield of the chip.

[0109] Step c: As Figure 12 As shown, an insulating layer 423 for sealing the intermediate hole 23 is formed inside the intermediate hole 23. A heat dissipation gap 421 is provided between the insulating layer 423 and the bottom wall of the intermediate hole 23. The second metal layer 422, the heat dissipation gap 421 and the insulating layer 423 constitute a second heat dissipation element 42.

[0110] For example, an insulating layer 423 can be deposited into the intermediate hole 23 by chemical vapor deposition. By adjusting the process parameters of the chemical vapor deposition process, the insulating layer 423 is preferentially deposited on the top of the intermediate hole 23 and the intermediate hole 23 is sealed, so that a heat dissipation gap 421 is formed between the insulating layer 423 and the second metal layer 422. In other words, the second heat sink forms a hollow ring structure. The material of the insulating layer 423 may include silicon oxide, etc.

[0111] In this embodiment, by setting a heat dissipation gap, on the one hand, the specific surface area of ​​the second heat sink can be increased, enhancing the heat dissipation capacity of the second heat sink, thereby preventing heat from accumulating inside the chip and improving the chip's performance and yield; on the other hand, since the heat dissipation gap has a low dielectric constant, the capacitance value of the parasitic capacitance formed between the TSV structure and other components in the substrate can be reduced, thus improving the chip's performance.

[0112] The number of the second heat sink 42 can be one or more, and this embodiment does not make a specific limitation on this.

[0113] When there is only one second heat sink 42, steps a to c above can be used to prepare the second heat sink. When there are multiple second heat sinks 42, steps a to c above can be repeated multiple times until multiple second heat sinks are formed. In order to facilitate a detailed explanation of the formation process of the second heat sink, in this embodiment, the second heat sink is divided into the first second heat sink, the second second heat sink, ... and the nth second heat sink along the axis perpendicular to the TSV structure, that is, from the center of the TSV structure to the outer wall.

[0114] It should be noted that when there is only one second heat sink, only one second through hole is formed, which is used to expose the surface of the first heat sink; when there are multiple second heat sinks, except for the second through hole adjacent to the first heat sink, the remaining second through holes are used to expose the surface of one of the second heat sinks. That is, the second second through hole is used to expose the surface of the first second heat sink, the third second through hole is used to expose the surface of the second second heat sink, and so on, with the nth second through hole being used to expose the (n-1)th second heat sink.

[0115] For example, there are three second heat sinks 42, and the steps for forming the second and third heat sinks are as follows:

[0116] like Figure 13 As shown, a second second through hole 22 is formed in the dielectric layer 20, and the second second through hole 22 surrounds the first second heat sink 42.

[0117] like Figure 14 As shown, after the second second through hole 22 is formed, an atomic layer deposition process can be used to form a second second metal layer 422 on the sidewall and bottom wall of the second second through hole 22, and the second second metal layer 422 surrounds the second intermediate hole 23.

[0118] like Figure 15 As shown, after the second metal layer is formed, a second insulating layer 423 can be formed in the second intermediate hole 23 by chemical vapor deposition. The second insulating layer 423 and the bottom wall of the intermediate hole have a second heat dissipation gap 421. The second metal layer 422, the second heat dissipation gap 421 and the second insulating layer 423 constitute the second heat dissipation component 42.

[0119] It should be noted that in this embodiment, the steps of forming the second second through hole, forming the second second metal layer, and forming the second insulating layer are the same as the steps of forming the first second through hole, the first first metal layer, and the first insulating layer in the above embodiment, and will not be described in detail here.

[0120] After the second heat sink is formed, steps a, b, and c above are repeated to form the third heat sink on the substrate, as follows: Figure 16 , Figure 17 and Figure 18 As shown.

[0121] In this embodiment, three second heat sinks are sequentially mounted on the TSV structure and stacked sequentially along the axis perpendicular to the TSV structure. By setting up three second heat sinks, the heat dissipation capacity of the heat sinks can be increased, thereby reducing the chip temperature and improving the chip performance and yield.

[0122] When forming the second and third heat sinks, the heat dissipation gap of the second heat sink and the heat dissipation gap inside the third heat sink can be equal to or unequal to the heat dissipation gap of the first heat sink. For example, the process of depositing the second metal layer can be controlled separately, so that the thickness of the second metal layer on the bottom wall of the middle hole in adjacent second heat sinks is different, thereby making the heat dissipation gap in adjacent second heat sinks have a height difference. In this way, the type of second heat sink corresponding to different components can be set according to the different types of components located in different positions in the substrate, which generate different amounts of heat, thus improving the heat dissipation effect of the heat sink.

[0123] For example, such as Figure 18 As shown, along the axial direction perpendicular to the TSV structure 30, the height of the heat dissipation gap 421 gradually decreases from the end near the TSV structure 30 to the end away from the TSV structure 30, making the adjacent heat dissipation gaps 421 appear as a step. Since the heat dissipation performance of the second heat sink mainly depends on the thickness and content of the second metal layer, when heat is transferred along the axial direction perpendicular to the TSV structure 30, the thickness of the second metal layer becomes larger and larger. Correspondingly, the heat dissipation capacity of the second heat sink becomes higher and higher. This is conducive to the diffusion of heat along the axial direction perpendicular to the TSV structure 30 and along the direction perpendicular to the substrate, avoiding the accumulation of heat in the substrate, improving the service life of components located in the substrate, and thus improving the performance and yield of the chip.

[0124] To facilitate the limitation of the thickness of the second metal layer on the bottom wall of the second heat sink, this embodiment uses the thickness of the first metal layer as the standard for measurement. For example, the thickness of the second metal layer on the bottom wall in the first second heat sink can be controlled to be 10% to 30% of the thickness of the first metal layer, the thickness of the second metal layer on the bottom wall in the second second heat sink can be 40% to 50% of the thickness of the first metal layer, and the thickness of the second metal layer on the bottom wall in the third second heat sink can be 60% to 70% of the thickness of the first metal layer.

[0125] This invention also provides a chip packaging structure, which is obtained by the preparation method described in the above embodiments. Here, a chip usually refers to a semiconductor element containing an integrated circuit. For example, the semiconductor is made into a wafer through processes such as crystal pulling and slicing. The wafer is then formed into a circuit structure through semiconductor manufacturing processes. After that, the wafer with the circuit structure is further processed through processes such as cutting and packaging to form a chip packaging structure.

[0126] like Figure 18 As shown, the chip packaging structure may include a substrate 10, a TSV structure 30, and a heat sink 40. The substrate 10 serves as a support component for the chip, supporting the TSV structure 30 and the heat sink 40 disposed thereon.

[0127] A dielectric layer 20 is formed on the substrate 10. Interconnect structures or gate structures of transistors can be formed in the dielectric layer 20. The material of the dielectric layer 20 may include silicon oxide, etc.

[0128] The substrate 10 also has a TSV structure 30. One end of the TSV structure 30 away from the substrate 10 extends into the dielectric layer 20. The end of the TSV structure 30 away from the substrate 10 can be flush with the top surface of the dielectric layer or located inside the dielectric layer. For ease of description of the TSV structure, the following will take the example of the top surface of the TSV structure being flush with the top surface of the dielectric layer for detailed description.

[0129] To facilitate the fabrication of the TSV structure 30, the cross-section of the TSV structure 30 is circular, with the cross-section parallel to the substrate 10.

[0130] The heat sink 40 is disposed within the dielectric layer 20 and surrounds the TSV structure 30 located within the dielectric layer 20.

[0131] In this embodiment, the heat sink can be a metal ring. Compared with insulating materials, metal has higher thermal conductivity. In this embodiment, by placing the heat sink on the TSV structure located in the dielectric layer, the heat generated by the TSV structure can be transferred to the outside of the chip package structure, avoiding heat accumulation inside the chip and improving the chip performance and yield.

[0132] It should be noted that in this embodiment, the heat sink can be spaced apart from the TSV structure or attached to it. For example, the surface of the heat sink 40 close to the TSV structure 30 is attached to the TSV structure 30. In this way, the heat generated by the TSV structure can be quickly transferred to the outside of the chip through the heat sink, avoiding heat accumulation inside the chip and improving the chip's performance and yield.

[0133] As a possible implementation of the heat dissipation component, the heat dissipation component 40 may include a first heat dissipation component 41 and a second heat dissipation component 42.

[0134] The first heat sink 41 surrounds the TSV structure 30 located within the dielectric layer 20, and the surface of the first heat sink 41 near the TSV structure 30 is fitted to the TSV structure 30 located within the dielectric layer 20.

[0135] The second heat sink 42 is arranged around the first heat sink 41. The surface of the second heat sink 42 close to the first heat sink 41 is fitted to the first heat sink 41, and a heat dissipation gap 421 extending circumferentially is formed in the second heat sink 42. That is, the second heat sink is a hollow ring structure. When the TSV structure is working, it will generate a lot of heat. This heat will first be quickly transferred to the first heat sink, and then transferred to the second heat sink through the first heat sink. When the heat is transferred to the second heat sink, the second heat sink has a large specific surface area, which will accelerate the heat diffusion rate and prevent heat from accumulating in the chip, thereby improving the chip's performance and yield. On the other hand, since the heat dissipation gap in the second heat sink has a low dielectric constant, it can reduce the capacitance value of the parasitic capacitance formed between the TSV structure and other components in the substrate, thereby improving the chip's performance. Therefore, this embodiment, by designing the heat sink as a combination of a solid ring and a hollow ring, can improve the chip's heat dissipation capacity and reduce the parasitic capacitance formed between the TSV structure and other components.

[0136] Furthermore, along the direction perpendicular to the substrate 10, the height of the heat dissipation gap 421 is between 0.3 and 1 μm, for example, it can be 0.4 μm, 0.5 μm, 0.6 μm, 0.7 μm, 0.8 μm and 0.9 μm.

[0137] If the height of the heat dissipation gap 421 is too large, it will reduce the heat dissipation capacity of the second heat sink. If the height of the heat dissipation gap 421 is too small, it will increase the dielectric constant of the second heat sink, thereby increasing the capacitance value of the parasitic capacitance between the TSV structure and other components in the substrate. Therefore, this embodiment limits the height of the heat dissipation gap in order to both enhance the heat dissipation capacity of the second heat sink and reduce the capacitance value of the parasitic capacitance between the TSV structure and other components in the substrate.

[0138] It should be noted that the number of second heat sinks 42 can be one or more. When there are multiple second heat sinks 42, they are stacked sequentially along the axis perpendicular to the TSV structure 30, i.e., in order to... Figure 18 Taking the orientation shown as an example, the first second heat sink is fitted onto the TSV structure located within the dielectric layer, the second second heat sink is fitted onto the first second heat sink, and so on, with the nth second heat sink fitted onto the (n-1)th second heat sink.

[0139] This embodiment improves the thermal conductivity of the heat sink by using multiple second heat sinks, thereby preventing heat from accumulating inside the chip and improving chip performance and yield.

[0140] In some embodiments, the heat dissipation gaps 421 in adjacent second heat sinks 42 have a height difference, that is, the heights of adjacent heat dissipation gaps 421 are different, that is, the bottom walls of the heat dissipation gaps 421 of the multiple heat sinks 42 are distributed in a stepped manner, in other words, the vertical distances of the bottom walls of adjacent heat dissipation gaps 421 from the substrate are different.

[0141] For example, along the axial direction perpendicular to the TSV structure 30, the height of the heat dissipation gap 421 gradually decreases from the end near the TSV structure 30 to the end away from the TSV structure 30, making the adjacent heat dissipation gaps appear stepped. Since the heat dissipation performance of the second heat sink mainly depends on the thickness and content of the second metal layer, as heat is transferred along the axial direction perpendicular to the TSV structure 30, the thickness of the second metal layer becomes larger and larger. Correspondingly, the heat dissipation capacity of the second heat sink becomes higher and higher. This is conducive to the dissipation of heat along the axial direction perpendicular to the TSV structure 30 and along the direction perpendicular to the substrate, avoiding the accumulation of heat in the substrate, improving the service life of components located in the substrate, and thus improving the performance and yield of the chip.

[0142] Furthermore, the height difference between adjacent heat dissipation gaps 421 is between 0.2 and 0.5 μm, for example, 0.3 μm and 0.4 μm, to prevent the height difference between adjacent heat dissipation gaps from being too large or too small, thus ensuring the thermal conductivity of the heat dissipation component, thereby preventing heat from accumulating inside the chip and improving the chip's performance and yield.

[0143] The various embodiments or implementation methods described in this specification are presented in a progressive manner. Each embodiment focuses on the differences from other embodiments, and the same or similar parts between the embodiments can be referred to each other.

[0144] In the description of this specification, references to terms such as "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with an embodiment or example that are included in at least one embodiment or example of the present invention.

[0145] In this specification, the illustrative expressions of the terms used do not necessarily refer to the same implementation or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more implementations or examples.

[0146] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for fabricating a chip packaging structure, characterized in that, Includes the following steps: A substrate is provided, on which a dielectric layer is disposed; A TSV structure is formed within the substrate, with one end of the TSV structure near the dielectric layer extending into the dielectric layer; A heat sink is formed within the dielectric layer, the heat sink surrounds the TSV structure located within the dielectric layer, and the surface of the heat sink near the TSV structure is fitted to the TSV structure. The step of forming a heat sink within the dielectric layer includes: A first through-hole is formed within the dielectric layer, the first through-hole surrounding the TSV structure located within the dielectric layer and exposing the surface of the TSV structure; A first metal layer is formed in the first through hole, the first metal layer fills the first through hole, and the first metal layer constitutes a first heat dissipation component. A second heat sink is formed within the dielectric layer, the second heat sink is disposed around the first heat sink, and a heat dissipation gap extending circumferentially within the second heat sink is formed therein. The step of forming the second heat sink within the dielectric layer includes: Step a: Form a second through hole in the dielectric layer, the second through hole being located on the side of the first heat sink away from the TSV structure; Step b: A second metal layer is formed on the sidewall and bottom wall of the second through hole, the second metal layer forming the intermediate hole; Step c: An insulating layer for sealing the intermediate hole is formed inside the intermediate hole, and a heat dissipation gap is formed between the insulating layer and the bottom wall of the intermediate hole. The second metal layer, the heat dissipation gap and the insulating layer constitute a second heat dissipation component. Repeat steps a, b, and c at least once until multiple second heat sinks are formed.

2. The method for fabricating the chip packaging structure according to claim 1, characterized in that, The bottom walls of the heat dissipation gaps of the plurality of second heat sinks are distributed in a stepped manner.

3. The method for fabricating the chip packaging structure according to claim 1 or 2, characterized in that, The step of forming the TSV structure within the substrate includes: A first accommodating hole is formed within the dielectric layer, penetrating the dielectric layer; The substrate exposed within the first receiving hole is removed to form a second receiving hole within the substrate, the first receiving hole and the second receiving hole constituting a receiving hole; The TSV structure is formed within the accommodating hole.

4. The method for fabricating the chip packaging structure according to claim 1 or 2, characterized in that, The step of forming the first through-hole within the dielectric layer includes: A first photoresist layer is formed on the dielectric layer, and a first annular opening is formed in the first photoresist layer. The projection of the first annular opening in the dielectric layer surrounds the TSV structure. The dielectric layer exposed within the first annular opening is removed to form a first through-hole within the dielectric layer, the first through-hole exposing the surface of the TSV structure.

5. The method for fabricating a chip packaging structure according to claim 4, characterized in that, The step of forming a second via within the dielectric layer includes: A second photoresist layer is formed on the dielectric layer, and a second annular opening is provided in the second photoresist layer. The projection of the second annular opening on the dielectric layer surrounds the first heat sink. Remove the dielectric layer exposed within the second annular opening to form a second through-hole within the dielectric layer.

6. The method for fabricating a chip packaging structure according to claim 5, characterized in that, The first metal layer and the second metal layer are made of the same material, and the material of both the first metal layer and the second metal layer includes one of copper, aluminum, gold and tantalum.

7. A chip packaging structure, characterized in that, The chip packaging structure, manufactured by the preparation method according to any one of claims 1-6, comprises: A substrate on which a dielectric layer is disposed; A TSV structure is disposed within the substrate, and one end of the TSV structure opposite to the substrate extends to the dielectric layer. A heat sink is disposed within the dielectric layer and surrounds the TSV structure located within the dielectric layer, and the surface of the heat sink near the TSV structure is fitted to the TSV structure.

8. The chip packaging structure according to claim 7, characterized in that, The heat dissipation component includes a first heat dissipation component and a second heat dissipation component; The first heat sink surrounds the TSV structure located within the dielectric layer, and the surface of the first heat sink near the TSV structure is fitted to the TSV structure located within the dielectric layer. The second heat sink is disposed around the first heat sink, and the surface of the second heat sink near the first heat sink is fitted to the first heat sink. A heat dissipation gap extending circumferentially along the second heat sink is formed inside the second heat sink.

9. The chip packaging structure according to claim 8, characterized in that, With a cross-section parallel to the substrate, the cross-sectional shape of the TSV structure is circular; There are multiple second heat sinks, which are stacked sequentially along an axis perpendicular to the TSV structure.

10. The chip packaging structure according to claim 9, characterized in that, The heat dissipation gaps in adjacent second heat sinks have a height difference.

11. The chip packaging structure according to claim 10, characterized in that, Along the axis perpendicular to the TSV structure, the height of the heat dissipation gap gradually decreases from the end closer to the TSV structure to the end away from the TSV structure.

12. The chip packaging structure according to claim 10 or 11, characterized in that, The height difference between adjacent heat dissipation gaps is between 0.2 and 0.5 μm.

13. The chip packaging structure according to claim 12, characterized in that, Along a direction perpendicular to the substrate, the height of the heat dissipation gap is between 0.3 and 1 μm.

Images