A bump structure and chip packaging structure and method

Abstract

This disclosure provides a bump structure, chip packaging structure, and method. This disclosure relates to the field of semiconductor technology. The bump structure is applied in a chip stacking structure and includes: a plurality of first bumps and a plurality of second bumps; the first bumps are disposed on the central region of a first stacked layer, and the second bumps are disposed on the peripheral region of the first stacked layer; the size of the first bumps is smaller than the size of the second bumps; a plurality of first pads and a plurality of second pads, the first pads are disposed on the central region of a second stacked layer, and the second pads are disposed on the peripheral region of the first stacked layer; the size of the first pads is smaller than the size of the second pads; the positions of the first bumps are adapted to the positions of the first pads; the positions of the second bumps and the second pads are adapted to each other. This allows for consistent soldering of the first bumps in the central region of the chip and the second bumps in the peripheral region.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a bump structure and chip packaging structure and method. Background Technology

[0002] In related technologies, when manufacturing three-dimensional stacked products, such as high-bandwidth memory (HBM), using three-dimensional stacking (3DS) technology, thermocompression bonding (TCB) is typically used to weld bumps to achieve chip stacking. During the manufacturing process, because the bumps and bond heads on the chip are directly connected by through-silicon vias (TSVs) for heat conduction, the thermal resistance of the bumps at the center of the chip differs from that of the outer bumps. This results in a significant temperature difference between the two bump regions, with the temperature (Tc) of the bump at the center of the chip being higher than that of the outer bumps (Te). Therefore, this can have a certain impact on product reliability. Summary of the Invention

[0003] The following is an overview of the subject matter described in detail in this disclosure. This overview is not intended to limit the scope of the claims.

[0004] This disclosure provides a bump structure and a chip packaging structure and method.

[0005] A first aspect of this disclosure provides a bump structure applied in a chip stacking structure, the bump structure comprising:

[0006] Multiple first bumps and multiple second bumps; the first bumps are disposed in the central region of the first stacked layer, and the second bumps are disposed in the peripheral region of the first stacked layer; the size of the first bumps is smaller than the size of the second bumps;

[0007] Multiple first pads and multiple second pads are provided, wherein the first pads are disposed in the central region of the second stacked layer, and the second pads are disposed in the peripheral region of the first stacked layer; the size of the first pads is smaller than the size of the second pads.

[0008] The position of the first bump is adapted to the position of the first pad; the position of the second bump is adapted to the position of the second pad.

[0009] In some embodiments of this disclosure, the second pad is an annular pad, and the inner diameter of the annular pad is less than or equal to the diameter of the second bump.

[0010] In some embodiments of this disclosure, the shape of the first pad and the shape of the first bump are both cylindrical structures.

[0011] In some embodiments of this disclosure, the thermal resistance of the first bump is greater than that of the second bump.

[0012] A second aspect of this disclosure provides a chip packaging structure, characterized in that the chip packaging structure includes a chip stacking structure, the chip stacking structure comprising:

[0013] A first stacked layer and a second stacked layer are combined using a bump structure as described in an exemplary embodiment of this disclosure.

[0014] In some embodiments of this disclosure, the first stacked layer includes a first chip; the second stacked layer includes a second chip.

[0015] In some embodiments of this disclosure, the first bump corresponds to the first conductive via of the first chip.

[0016] In some embodiments of this disclosure, the first bump of the second chip corresponds to the second conductive via of the second chip.

[0017] In some embodiments of this disclosure, the chip stacking structure further includes: a substrate disposed at the bottom of the chip stacking structure, the central region of a first surface of the substrate including a plurality of first pads, and the peripheral region of the first surface of the substrate including a plurality of second pads, wherein the first pads of the substrate are connected to a third conductive via of the substrate.

[0018] In some embodiments of this disclosure, the central region of the first surface of the first chip includes a plurality of first bumps, and the peripheral region of the first surface of the first chip includes a plurality of second bumps; the central region of the second surface of the first chip includes a plurality of first pads, and the peripheral region of the second surface of the chip includes a plurality of second pads; the first pads of the first chip correspond to the first conductive vias of the first chip.

[0019] In some embodiments of this disclosure, the chip packaging structure further includes an m-th layer stacking structure disposed on the second stacking structure, where m is a positive integer greater than or equal to 3;

[0020] The central region of the first surface of the m-th layer stacked structure includes a plurality of first bumps, and the peripheral region of the first surface of the m-th layer stacked structure includes a plurality of second bumps; the central region of the second surface of the m-th layer stacked structure includes a plurality of first pads, and the peripheral region of the second surface of the m-th layer stacked structure includes a plurality of second pads.

[0021] Wherein, the first bump of the m-th layer stacked structure corresponds to the n-th conductive via of the m-th layer stacked structure, the first pad of the m-th layer stacked structure corresponds to the n-th conductive via of the m-th layer stacked structure, n is a positive integer greater than or equal to 4, and n = m + 1.

[0022] A third aspect of this disclosure provides a chip packaging method, the packaging method comprising:

[0023] A chip stack structure is formed, the chip stack structure including a first stack layer and a second stack layer, the first stack layer and the second stack layer being combined by the bump structure described in the exemplary embodiments of this disclosure.

[0024] In some embodiments of this disclosure, forming the chip stack structure includes:

[0025] A substrate is provided, wherein the central region of the first surface of the substrate includes a plurality of first pads, and the peripheral region of the first surface of the substrate includes a plurality of second pads;

[0026] A first chip is provided, wherein the central region of the first surface of the first chip includes a plurality of first bumps, and the peripheral region of the first surface of the first chip includes a plurality of second bumps; the first bumps correspond to the first conductive vias of the first chip.

[0027] Align a plurality of first bumps on a first surface of the first chip with a plurality of first pads on a first surface of the substrate; align a plurality of second bumps on a first surface of the first chip with a plurality of second pads on a first surface of the substrate;

[0028] The first bump on the first surface of the first chip is bonded to the first pad on the first surface of the substrate, and the second bump on the first surface of the first chip is bonded to the second pad on the first surface of the substrate, thereby forming a stack of the first chip and the substrate.

[0029] In some embodiments of this disclosure, the central region of the second side of the first chip includes a plurality of first pads, and the peripheral region of the second side of the chip includes a plurality of second pads; the first pads correspond to the first conductive vias of the first chip; the first side and the second side of the first chip are two opposing sides along the thickness direction of the first chip; the formation of the chip stack structure further includes:

[0030] A second chip is provided, wherein the central region of the first surface of the second chip includes a plurality of first bumps, and the peripheral region of the first surface of the second chip includes a plurality of second bumps; the first bumps correspond to the second conductive vias of the second chip.

[0031] Align the plurality of first bumps on the first surface of the second chip with the plurality of first pads on the second surface of the first chip; align the plurality of second bumps on the first surface of the second chip with the plurality of second pads on the second surface of the first chip;

[0032] The first bump on the first surface of the second chip is bonded to the first pad on the second surface of the first chip, and the second bump on the first surface of the second chip is bonded to the second pad on the second surface of the first chip, thereby forming a stack of the second chip and the first chip.

[0033] In some embodiments of this disclosure, a plurality of first pads on a first surface of the substrate are connected to a third conductive via on the substrate.

[0034] The bump structure provided in this disclosure optimizes the positions of the bumps (including first and second bumps) and pads (including first and second pads) and optimizes their dimensions. Based on the optimized bumps and pads, this bump structure effectively reduces the thermal resistance of the bumps in the peripheral region, thereby reducing the temperature difference between the central and peripheral regions during soldering. Furthermore, based on the improved bump structure in the chip stacking structure disclosed in this disclosure, when using the bump structure provided in this embodiment for thermocompression bonding, it is not necessary to increase the temperature of the bonding head in the thermocompression bonding process, while ensuring consistent soldering of the first bump in the chip's central region and the second bump in the peripheral region.

[0035] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood. Attached Figure Description

[0036] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the present disclosure and, together with the description, serve to explain the principles of these embodiments. In these drawings, similar reference numerals are used to denote similar elements. The drawings described below are some embodiments of the present disclosure, but not all embodiments. Other drawings will be readily available to those skilled in the art based on these drawings without inventive effort.

[0037] Figure 1 This diagram illustrates a chip stack structure formed by welding and bonding bumps using a thermal compression bonding (TCB) process.

[0038] Figure 2 This is a schematic diagram of a bump structure shown in an exemplary embodiment;

[0039] Figure 3 This is a schematic diagram showing the distribution of a first bump and a second bump on a first stacked layer according to an exemplary embodiment;

[0040] Figure 4 This is a schematic diagram illustrating the distribution of the first and second pads on a second stacked layer according to an exemplary embodiment;

[0041] Figure 5 This is a schematic diagram of a chip stacking structure according to an exemplary embodiment;

[0042] Figure 6 This is a schematic diagram of a chip stacking structure according to an exemplary embodiment;

[0043] Figure 7 This is a schematic diagram illustrating the process of stacking a first chip and a substrate according to an exemplary embodiment;

[0044] Figure 8 This is a schematic diagram illustrating the stacking of a first chip and a second chip according to an exemplary embodiment.

[0045] Figure label:

[0046] 001. Chip; 002. Bump; 0021. Bump in the central area; 0022. Bump in the peripheral area; 003. Through-silicon via; 004. Substrate; 005. Pad; 006. Bonding head;

[0047] 101. First chip; 101A. First side of the first chip; 101B. Second side of the first chip; 102. Second chip; 102A. First side of the second chip; 102B. Second side of the second chip; 103. Substrate; 103A. First side of the substrate; 103B. Second side of the substrate;

[0048] 201, First bump; 202, Second bump; 203, First pad; 204, Second pad;

[0049] 301, First conductive via; 302, Second conductive via; 303, Third conductive via;

[0050] 401, pin;

[0051] 501. Bonding head. Detailed Implementation

[0052] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions in the disclosed embodiments will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the embodiments of this disclosure without creative effort are within the scope of protection of this disclosure. It should be noted that, unless otherwise specified, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other.

[0053] In related technologies, such as Figure 1 As shown, Figure 1 This paper illustrates a chip stack structure formed by welding bumps using a thermal compression bonding (TCB) process. When welding the corresponding stacked layers in the chip stack structure using TCB, since the bumps 002 on chip 001 correspond to the pads 005 on substrate 004, the bumps 002 and pads 005 can be quickly aligned during the welding process, and the chip 001 is stacked on substrate 004 through welding. To ensure that all bumps 002 on chip 001 can be soldered (reaching the solder melting point) onto pad 005, the temperature of the bonding head 006 in the thermo-press bonding process is increased. At this time, the corresponding bonding head 006 is connected to the bumps 0021 in the central region of chip 001 through the silicon via 003 in the central region of chip 001 for heat conduction. As a result, during the actual soldering process, the temperature Tc of the bumps 0021 in the central region of chip 001 is more than 10°C higher than the temperature Te of the bumps 0022 in the peripheral region of chip 001. Even if the soldering is successful, there will be a large difference in the soldering shape between the bumps 0021 in the central region and the bumps 0022 in the peripheral region of the chip stacking structure, which may affect the reliability of the product.

[0054] Based on this, embodiments of this disclosure provide a bump structure that connects adjacent stacked layers. By rationally arranging the bumps and pads of this bump structure and optimizing the dimensions of the bumps and pads, the thermal resistance of the bumps located in the peripheral region can be effectively reduced, thereby reducing the temperature difference between the central and peripheral regions. This ensures consistent bonding between the bumps in the central and peripheral regions of the chip without increasing the temperature of the bonding head in the thermoforming bonding process. Therefore, bonding adjacent stacked layers in a chip stack structure using this bump structure can improve the reliability of the chip stack structure.

[0055] An exemplary embodiment of this disclosure provides a bump structure that can be applied to a chip stacking structure for connecting corresponding stacked layers. For example... Figure 2 As shown, Figure 2 This is a schematic diagram illustrating a bump structure in an exemplary embodiment. The bump structure includes:

[0056] Multiple first bumps 201 and multiple second bumps 202; the first bumps 201 are disposed in the central region of the first stacked layer, and the second bumps 202 are disposed in the peripheral region of the first stacked layer; the size of the first bumps 201 is smaller than the size of the second bumps 202;

[0057] Multiple first pads 203 and multiple second pads 204 are provided, with the first pads 203 disposed in the central region of the second stacked layer and the second pads 204 disposed in the peripheral region of the first stacked layer; the size of the first pads 203 is smaller than the size of the second pads 204.

[0058] The position of the first bump 201 is adapted to the position of the first pad 203; the positions of the second bump 202 and the second pad 204 are adapted to each other.

[0059] In this exemplary embodiment, to ensure that the size of the first bump 201 is smaller than the size of the second bump 202, the size of the first bump 201 in the central region of the first stacked layer can remain unchanged in the optimized bump structure. Since a thermocompression bonding process is required for welding bonding, the size of the second bump 202 located in the peripheral region of the first stacked layer can be increased, provided that the various processes (including the thermocompression bonding process) for stacking the first and second stacked layers meet the allowable conditions. This effectively adjusts the heat conduction-related parameters of the second bump 202, improving the heat conduction performance of the bump in the peripheral region. For example, the heat conduction-related parameters may include thermal resistance. Increasing the size of the second bump 202 can reduce the thermal resistance of the second bump 202, thereby reducing the temperature difference between the central region and the peripheral region. This way, the temperature of the bonding head in the thermocompression bonding process can be increased without increasing it, and the welding condition of the bumps in the central region and the bumps in the peripheral region can be guaranteed to be consistent.

[0060] For example, Figure 2The first stacked layer in the bump structure shown is illustrated using the first chip 101 as an example, and the second stacked layer is illustrated using the substrate 103 as an example. The first bump 201 and the second bump 202 can be made of the same material. For example, the first bump 201 includes: a first bottom metal layer disposed on one surface of the first chip 101, a first metal pad disposed on the first bottom metal layer, and solder disposed on the first metal pad. The solder on the first metal pad has the same dimensions as the first metal pad. The first bump 201 is bonded to the first pad 203 by heating the solder. The second bump 202 includes: a second bottom metal layer disposed on one surface of the first chip 101, a second metal pad disposed on the second bottom metal layer, and solder disposed on the second metal pad. The solder on the second metal pad has the same dimensions as the second metal pad. The second bump 202 is bonded to the second pad 204 by heating the solder. The first chip 101 and the substrate 103 will be described in detail later.

[0061] It should be noted that, in the description of bump size in this exemplary embodiment, the size referred to can be understood as the cross-sectional area of ​​the first bump 201 and the second bump 202 taken along a plane parallel to the first stack layer, that is, the cross-sectional area of ​​the first bump 201 is smaller than the cross-sectional area of ​​the second bump 202; similarly, in the description of pad size in this exemplary embodiment, the size referred to can be understood as the cross-sectional area of ​​the first pad 203 being smaller than the cross-sectional area of ​​the second pad 204 along a plane parallel to the second stack layer.

[0062] In this exemplary embodiment, the bump structure optimizes the size of the first bump 201 in the central region and the second bump 202 in the peripheral region of the first stacked layer. The size of the first pad 203 in the central region and the second pad 204 in the peripheral region of the second stacked layer is also improved. The first pad 203 corresponds to the first bump 201, and the second pad 204 corresponds to the second bump 202. When stacking different stacked layers of the chip stacking structure, thermocompression bonding can also be used. There is no need to worry about the large difference in the welding shape between the central region and the peripheral region of the corresponding stacked layer during the thermocompression bonding process. This can effectively ensure the reliability of the product prepared based on this bump structure.

[0063] The bump structure shown in this exemplary embodiment is designed with bumps of two sizes on the first stacked layer, such as... Figure 3 As shown, Figure 3This is a schematic diagram illustrating the distribution of a first bump and a second bump on a first stacked layer according to an exemplary embodiment. A first bump 201 with a first preset size is designed in the central region of the first stacked layer, and a second bump 202 with a second preset size is designed in the peripheral region of the first stacked layer. It is understood that the number, size, and distribution of the first bump 201 and the second bump 202 on the first stacked layer can be determined based on the core region and the peripheral region of the first stacked layer.

[0064] The bump structure shown in this exemplary embodiment is designed with pads of two sizes on the first stack layer, such as... Figure 4 As shown, Figure 4 This is a schematic diagram illustrating the distribution of first and second pads on a second stacked layer according to an exemplary embodiment. A first pad 203 with a third preset size is designed in the central region of the second stacked layer, and a second pad 204 with a fourth preset size is designed in the peripheral region of the second stacked layer. It is understood that the number, size, and distribution position of the first and second pads 203 and 204 on the second stacked layer can be configured according to the number and size of the bumps on the first stacked layer.

[0065] In this exemplary embodiment, the bumps on the first stack layer can be designed with three or more sizes. For example, when three sizes of bumps are provided on the first stack layer, three sizes of pads can be provided on the second stack layer that is soldered to the first stack layer to cooperate with them. In this case, the bumps of the three different sizes can be arranged sequentially from the center region to the outer region of the first stack layer in an order of increasing size; that is, the bumps closer to the center region are smaller, and the bumps closer to the outer region are larger.

[0066] Similar to setting three sizes of bumps on the first stack layer, when arranging pads of three different sizes, in order to cooperate with the bumps on the first stack layer, the pads can also be arranged sequentially from the center area of ​​the second stack layer to the outer area in order of increasing pad size. That is, the pad size is smaller closer to the center area and larger closer to the outer area.

[0067] In the bump structures shown in the above exemplary embodiments, the bumps are designed on the first stack layer and the pads are designed on the second stack layer. However, in some other alternative exemplary embodiments, if the structure or material of the pads and bumps are different, the first bump 201 and the second bump 202 can be set separately, and correspondingly, the first pad 203 and the second pad 204 can be set separately, that is, a portion of the bumps and a portion of the pads are set on the first stack layer at the same time, and another portion of the bumps and another portion of the pads are set on the second stack layer at the same time, and then solder bonding is performed. When a portion of the bumps and a portion of the pads are set on the first stack layer at the same time, for example, a plurality of third bumps and a plurality of third pads are designed on the first stack layer, and a plurality of fourth bumps and a plurality of fourth pads are designed on the second stack layer.

[0068] In some exemplary embodiments, in order to ensure uniform heat transfer inside the chip stack structure when the hot-press bonding process is used to weld the bonding stack layers, for example, in the optimized bump structure, the size of the first bump 201 in the central region of the first stack layer can be kept unchanged. Under the condition that the requirements for welding the bump structure using the hot-press bonding process can be met, the size of the second bump in the peripheral region can be appropriately increased, thereby effectively reducing the thermal resistance of the second bump in the peripheral region and achieving the purpose of reducing the temperature difference between the central region and the peripheral region.

[0069] Based on the design dimensions of the first bump 201 and the second bump 202, although it is possible to ensure that the welding of the first bump 201 in the central region and the second bump 202 in the peripheral region is consistent without increasing the bonding head temperature in the hot-press bonding process, considering that the second bump 202 with a larger size generally has a higher welding height in the single-step electroplating process, that is, when the first bump 201 is welded to the first pad 203 and the second bump 202 is welded to the second pad 204 respectively, the height of the second bump 202 in the peripheral region of the first stacked layer will be higher than the height of the first bump 201 in the central region, and the height of the second pad 204 in the peripheral region of the second stacked layer will also be higher than the height of the first pad 203 in the central region. In other words, the height of the second bump 202 and the second pad 204 in the peripheral region form a height difference with the height of the first bump 201 and the first pad 203 in the central region. To ensure successful solder bonding between the first bump 201 and the first pad 203, and between the second bump 202 and the second pad 204, during the solder bonding process, design modifications can be made to the second stack layer to be soldered to the first stack layer to match the height difference. In this exemplary embodiment, the second pad 204 can be designed as an annular pad, where the inner diameter of the annular pad is less than or equal to the diameter of the second bump 202, so that the second bump 202 and the second pad 204 have a certain contact area after alignment, facilitating the soldering operation during bonding. Figure 4 As shown, Figure 4 This is a schematic diagram illustrating the distribution of the first and second pads on a second stacked layer according to an exemplary embodiment. In practical applications, when designing the second pad 204, the inner diameter of the annular pad is designed to be smaller than the diameter of the second bump 202, and the outer diameter of the annular pad is greater than or equal to the diameter of the second bump 202. This facilitates alignment between the second bump 202 and the second pad 204, ensures a certain contact area after alignment, and also addresses the height difference issue caused by the welding bonding operation to some extent. During the welding bonding process, while overcoming the height difference, the size of the second pad 204 can be increased to further reduce thermal resistance and improve thermal conductivity. Furthermore, designing the second pad 204 as an annular pad reduces the contact area with the second bump 202, further reducing the heat required to melt the second bump 202. This more effectively reduces the temperature difference between the central and peripheral regions, ensuring consistent welding conditions between the bumps in the central and peripheral regions.

[0070] It is understandable that the shape of the inner ring of the annular second pad 204 can be adapted to the shape of the second bump 202. When the second bump 202 is cylindrical, the cross-section of the inner ring of the second pad 204 can be an annular shape that can fit the second bump 202; the shape of the inner ring of the annular second pad 204 can also not be completely adapted to the shape of the second bump 202. For example, the cross-section of the inner ring of the second pad 204 can be square, which can also solve the height difference problem when welding and bonding with the cylindrical second bump 202 to a certain extent.

[0071] In some exemplary embodiments, the shape of the first pad 203 is adapted to the shape of the first bump 201, and the positions of the first pad 203 and the first bump 201 correspond one-to-one. For example, both the first pad 203 and the first bump 201 can be cylindrical, providing a good contact surface after mating, reducing welding difficulty and ensuring welding quality during processing. Alternatively, the shapes of the first bump 201 and the first pad 203 can also be other structures such as square prisms or triangular prisms.

[0072] In some exemplary embodiments, considering the dimensions of the first bump 201 and the second bump 202, it is necessary to save materials while ensuring the welding effect. In this exemplary embodiment, the dimensions of the first bump 201 and the second bump 202 can be optimized based on the thermal conductivity parameters of the central region and the peripheral region, respectively, during the stacking process. During the welding bonding process, the bonding head 501 communicates with the first bump 201 through a through-silicon via (TSV) located in the central region of the chip for heat conduction. However, the peripheral region of the chip does not have TSVs, so the bonding head 501 can only communicate with the second bump 202 through the chip itself for heat conduction, resulting in different thermal conductivity performance. This characteristic can be considered when designing the dimensions of the first bump 201 and the second bump 202. The design can be based on the thermal conductivity parameters of different regions. For bumps with good thermal conductivity, the size can be designed to be appropriately smaller, while for bumps with poor thermal conductivity, the size can be designed to be appropriately larger.

[0073] In this exemplary embodiment, the thermal conductivity-related parameters can be any parameters that describe the thermal conductivity performance of the chip, such as thermal resistance. A low thermal resistance allows for a smaller bump size, appropriately reducing heat conduction; a high thermal resistance allows for a larger bump size, increasing heat conduction. For example, the ratio of the size of the second bump 202 to the size of the first bump 201 can be designed to be positively correlated with the ratio of the thermal resistance of the peripheral region to the thermal resistance of the central region during stacking. For example, the ratio of the size of the second bump 202 to the size of the first bump 201 is 1.1:1 to 2:1. Since the thermal resistance is high and the thermal conductivity is poor in the peripheral region of the chip, the size of the second bump 202 can be increased to reduce its thermal resistance. This allows the second bump 202 to melt under very low heat, matching the fusibility of the first bump 201 located in the central region of the chip, ensuring consistent bump welding between the central and peripheral regions.

[0074] In this exemplary embodiment, the bump structure increases the size of the second bump 202 located in the outer region of the first stacked layer and coordinates the design with the second pad 204 in the second stacked layer to which it is welded. This effectively reduces the thermal resistance of the second bump 202 located in the outer region, thereby reducing the temperature difference between the central region and the outer region of the stacked layer. This eliminates the need to increase the temperature of the bonding head in the hot-press bonding process, while ensuring that the welding of the first bump 201 in the central region and the second bump 202 in the outer region of the first stacked layer is consistent.

[0075] An exemplary embodiment of this disclosure provides a chip packaging structure, which includes a chip stacking structure. The chip stacking structure includes a first stacking layer and a second stacking layer, which are combined by a bump structure described in the above exemplary embodiment of this disclosure.

[0076] In some exemplary embodiments, the first stacked layer includes a first chip 101; the second stacked layer includes a second chip 102. Considering the need to ensure conductivity between different stacked layers after stacking, this can be achieved by connecting a first bump 201 on the chip to a conductive via on the chip, and simultaneously soldering the first bump 201 to the pads of other stacked layers. In this exemplary embodiment, the first bump 201 corresponds to the first conductive via 301 of the first chip 101.

[0077] In some exemplary embodiments, the stacking of the first chip 101 and the second chip 102 can be achieved using the aforementioned bump structure. Similarly, the connection between the first chip 101 and the substrate 103 can also be achieved using the aforementioned bump structure. When the chip stacking structure includes the substrate 103, the substrate 103 is disposed at the bottom of the chip stacking structure, and the substrate is provided with a plurality of first pads 203 and a plurality of second pads 204. The first pads 203 of the substrate 103 are connected to the third conductive vias 303 of the substrate 103.

[0078] like Figure 5 As shown, Figure 5 This is a schematic diagram illustrating a chip stacking structure according to an exemplary embodiment. Figure 5 The diagram illustrates, exemplarily, a structure in which a first chip 101 and a substrate 103 are stacked and bonded. To achieve bonding between the substrate 103 and the first chip 101, a plurality of first pads 203 are provided in the central region of the first surface 103A of the substrate, and a plurality of second pads 204 are provided in the peripheral region of the first surface 103A of the substrate. Correspondingly, a plurality of first bumps 201 are provided in the central region of the first surface 101A of the first chip, and a plurality of second bumps 202 are provided in the peripheral region of the first surface 101A of the first chip, wherein the first bumps 201 correspond to the first conductive vias 301 of the first chip 101. Based on the bump structure provided in this exemplary embodiment, when aligning the plurality of first bumps 201 on the first surface 101A of the first chip with the plurality of first pads 203 on the first surface 103A of the substrate, the plurality of second bumps 202 on the first surface 101A of the first chip are simultaneously aligned with the plurality of second pads 204 on the first surface 103A of the substrate. During soldering, heating the bonding head 501 melts the solder on the first bump 201 on the first surface 101A of the first chip, thereby bonding the first bump 201 to the first pad 203 on the first surface 103A of the substrate. Simultaneously, the solder on the second bump 202 on the first surface 101A of the first chip melts, thereby bonding the second bump 202 to the second pad 204 on the first surface 103A of the substrate, thus forming a stack of the first chip 101 and the substrate 103. This soldering process does not require additional increases in soldering temperature to achieve soldering bonding of all bumps to pads; that is, the temperature difference between the central and peripheral regions of the first chip 101 is small during soldering, improving yield while meeting processing requirements. Stacking based on the bump structure provided in this exemplary embodiment ensures the reliability of the formed chip stack structure.

[0079] like Figure 5As shown, considering that the chip stack structure prepared based on the bump structure of this exemplary embodiment can also be connected to other circuits, for example, corresponding pins 401 can also be provided on the second surface 103B of the substrate, and other circuits can be connected by using the pins 401 on the second surface 103B of the substrate.

[0080] In some exemplary embodiments, when the second stacked structure includes a second chip 102, the first bump 201 of the second chip 102 corresponds to the second conductive via 302 of the second chip 102.

[0081] like Figure 6 As shown, Figure 6 This is a schematic diagram illustrating a chip stacking structure according to an exemplary embodiment. Figure 6 The diagram illustrates, by way of example, a structural schematic of a second chip, a first chip, and a substrate stacked and bonded together. The chip stacking structure shown in this exemplary embodiment comprises two layers of chips, namely, a first chip 101 and a second chip sequentially disposed on top of a substrate, forming a chip stacking structure.

[0082] When stacking layers one by one, in one soldering bonding method, the current stacked layer is soldered to the stacked layer below it using a bonding head 501. After completion, the bonding head 501 is removed, and then another stacked layer is stacked on top of the current stacked layer, thereby achieving layer-by-layer soldering bonding of multiple stacked layers. In another soldering bonding method, a soldering bonding operation is performed using the bonding head 501, namely: aligning the first bump 201 of each stacked layer with the first pad 203, and aligning the second bump 202 with the second pad 204, and then placing the bonding head 501 on the topmost stacked layer. By heating the bonding head 501, the stacked layers are simultaneously soldered and bonded.

[0083] First, similar to adopting Figure 5The substrate 103 and the first chip 101 are stacked together. A plurality of first pads 203 are provided in the central region of the first surface 103A of the substrate, and a plurality of second pads 204 are provided in the peripheral region of the first surface 103A of the substrate. Correspondingly, a plurality of first bumps 201 are provided in the central region of the first surface 101A of the first chip, and a plurality of second bumps 202 are provided in the peripheral region of the first surface 101A of the first chip. The first bumps 201 correspond to the first conductive vias 301 of the first chip 101. Based on the bump structure provided in this exemplary embodiment, when aligning the plurality of first bumps 201 on the first surface 101A of the first chip with the plurality of first pads 203 on the first surface 103A of the substrate, the plurality of second bumps 202 on the first surface 101A of the first chip are simultaneously aligned with the plurality of second pads 204 on the first surface 103A of the substrate. When stacking the various layers one by one, heating the bonding head 501 on the current stack layer melts the solder on the first bump 201 on the first surface 101A of the first chip, thereby bonding the first bump 201 to the first pad 203 on the first surface 103A of the substrate. Simultaneously, the solder on the second bump 202 on the first surface 101A of the first chip melts, thereby bonding the second bump 202 to the second pad 204 on the first surface 103A of the substrate, thus forming a stack of the first chip 101 and the substrate 103. This bonding operation is repeated sequentially to achieve layer-by-layer stacking.

[0084] If synchronous soldering bonding is performed via bonding head 501, the soldering bonding of the first chip 101 to the substrate 103 is not performed first. Multiple first bumps 201 are provided in the central region of the first surface 102A of the second chip, and multiple second bumps 202 are provided in the peripheral region of the first surface 102A of the second chip. The first bumps 201 correspond to the second conductive vias 302 of the second chip 102. After the stacking of the first chip 101 and the substrate 103 is completed, the first pads 203 in the central region of the second surface 101B of the first chip can engage with the first bumps 201 in the central region of the first surface 102A of the second chip, and simultaneously, the second pads 204 in the peripheral region of the second surface 101B of the first chip can engage with the second bumps 202 in the peripheral region of the first surface 102A of the second chip, thereby completing the stacking of the second chip 102 on the first chip 101. When stacking the second chip 102 onto the first chip 101, the plurality of first bumps 201 on the first side 102A of the second chip are aligned with the plurality of first pads 203 on the second side 101B of the first chip, and the plurality of second bumps 202 on the first side 102A of the second chip are aligned with the plurality of second pads 204 on the second side 101B of the first chip; then, the bonding head 501 is heated to simultaneously solder the second chip 102, the first chip 101 and the substrate 103. At this time, the solder on the first bumps 201 on the first surface 101A of the first chip and the first surface 102A of the second chip is melted simultaneously, so that the first bumps 201 between the corresponding bonding layers are bonded to the first pads 203. Simultaneously, the solder on the second bumps 202 on the first surface 101A of the first chip and the first surface 102A of the second chip is melted, so that the second bumps 202 between the corresponding bonding layers are bonded to the second pads 204, thereby forming a stack of the second chip 102, the first chip 101, and the substrate 103. This process can be repeated to achieve synchronous stacking of multiple layers of chips and substrates. This welding and bonding process also ensures that the temperature difference between the central and peripheral areas of the first chip 101 and the second chip 102 is not too large, improving the yield while meeting processing requirements.

[0085] The chip packaging structure adopts the above-mentioned bump structure, in which the size of the second bump 202 located in the outer region of the first stacked layer is increased, and the second pad 204 in the second stacked layer to which it is soldered is designed in a coordinated manner. This effectively reduces the thermal resistance of the second bump 202 located in the outer region, thereby reducing the temperature difference between the central region and the outer region of the stacked layer of the bump structure. This way, the temperature of the bonding head 501 in the hot-press bonding process does not need to be increased, and the soldering of the first bump 201 in the central region of the first stacked layer and the second bump 202 in the outer region can be kept consistent.

[0086] In some exemplary embodiments, the chip stacking structure may have multiple (more than two) stacking structures to achieve more layers of stacking. Exemplarily, the chip stacking structure further includes an m-th layer stacking structure disposed on the second stacking structure, where m is a positive integer greater than or equal to 3. The central region of the first surface of the m-th layer stacking structure includes multiple first bumps 201, and the peripheral region of the first surface of the m-th layer stacking structure includes multiple second bumps 202; the central region of the second surface of the m-th layer stacking structure includes multiple first pads 203, and the peripheral region of the second surface of the m-th layer stacking structure includes multiple second pads 204. The first bumps 201 of the m-th layer stacking structure correspond to the n-th conductive via of the m-th layer stacking structure, and the first pads 203 of the m-th layer stacking structure correspond to the n-th conductive via of the m-th layer stacking structure, where n is a positive integer greater than or equal to 4, and n = m + 1.

[0087] An exemplary embodiment of this disclosure provides a chip packaging method, the packaging method including: forming a chip stack structure, the chip stack structure including a first stack layer and a second stack layer, the first stack layer and the second stack layer being combined by a bump structure provided in the above exemplary embodiment of this disclosure.

[0088] In some exemplary embodiments, such as Figure 7 As shown, Figure 7 This is a schematic diagram illustrating the process of stacking a first chip and a substrate according to an exemplary embodiment, forming a chip stack structure including:

[0089] Step S701: Provide a substrate 103. The central region of the first surface 103A of the substrate includes a plurality of first pads, and the peripheral region of the first surface 103A of the substrate includes a plurality of second pads 204.

[0090] Step S702: A first chip is provided. The central region of the first surface 101A of the first chip includes a plurality of first bumps 201, and the peripheral region of the first surface 101A of the first chip includes a plurality of second bumps 202. The first bumps 201 correspond to the first conductive vias 301 of the first chip 101.

[0091] Step S703: Align the plurality of first bumps 201 on the first surface 101A of the first chip with the plurality of first pads 203 on the first surface 103A of the substrate; align the plurality of second bumps 202 on the first surface of the first chip with the plurality of second pads 204 on the first surface 103A of the substrate.

[0092] In step S704, the first bump 201 on the first surface 101A of the first chip is bonded to the first pad 203 on the first surface 103A of the substrate, and the second bump 202 on the first surface 101A of the first chip is bonded to the second pad 204 on the first surface 103A of the substrate, thereby forming a stack of the first chip 101 and the substrate 103.

[0093] like Figure 5 As shown, a plurality of first pads 203 are provided in the central region of the first surface 103A of the substrate, and a plurality of second pads 204 are provided in the peripheral region of the first surface 103A of the substrate; a plurality of pins 401 are provided in the second surface 103B of the substrate, which can be connected to peripheral circuits; a plurality of first bumps 201 are provided in the central region of the first surface 101A of the first chip, and a plurality of second bumps 202 are provided in the peripheral region of the first surface 101A of the first chip; wherein, by heating the bonding head 501 on the first chip 101, the solder on the first bumps 201 is melted, so that the first bumps 201 are bonded to the first pads 203, and at the same time the solder on the second bumps 202 is melted, so that the second bumps 202 are bonded to the second pads 204, thereby enabling the stacking of the first chip 101 and the substrate 103.

[0094] In this exemplary embodiment, the bump structure provided in the above exemplary embodiment is applied. When packaging the chip package structure, by employing the above-described bump structure, which increases the size of the second bump 202 located in the peripheral region of the first chip 101 and coordinates the design with the second pad 204 of the substrate 103 to which it is soldered, the thermal resistance of the second bump 202 in the peripheral region is effectively reduced. This achieves the purpose of reducing the temperature difference between the central region and the peripheral region of the stacked layer of the bump structure. This eliminates the need to increase the temperature of the bonding head 501 in the thermoforming process, while ensuring that the soldering of the first chip 101 and the substrate 103 is consistent between the first bump 201 in the central region and the second bump 202 in the peripheral region.

[0095] In some exemplary embodiments, a plurality of first pads 203 on the first surface 103A of the substrate are connected to third conductive vias 303 on the substrate 103.

[0096] In some exemplary embodiments, such as Figure 8 As shown, Figure 8This is a schematic diagram illustrating the stacking of a first chip and a second chip according to an exemplary embodiment. The central region of the second surface 101B of the first chip includes a plurality of first pads 203, and the peripheral region of the second surface 101B of the first chip includes a plurality of second pads 204; the first pads 203 correspond to the first conductive vias 301 of the first chip 101; the first surface 101A and the second surface of the first chip are two opposing surfaces along the thickness direction of the first chip 101. Figure 8 As shown, forming the chip stack structure also includes:

[0097] Step S801: A second chip 102 is provided. The central region of the first surface 102A of the second chip includes a plurality of first bumps 201, and the peripheral region of the first surface 102A of the second chip includes a plurality of second bumps 202. The first bumps 201 correspond to the second conductive vias 302 of the second chip 102.

[0098] Step S802: Align the plurality of first bumps 201 on the first surface 102A of the second chip with the plurality of first pads 203 on the second surface 101B of the first chip; align the plurality of second bumps 202 on the first surface 102A of the second chip with the plurality of second pads 204 on the second surface 101B of the first chip.

[0099] In step S803, the first bump 201 on the first surface 102A of the second chip is bonded to the first pad 203 on the second surface 101B of the first chip, and the second bump 202 on the first surface 102A of the second chip is bonded to the second pad 204 on the second surface 101B of the first chip, to form a stack of the second chip 102 and the first chip 101.

[0100] like Figure 6 As shown, a plurality of first pads 203 are provided in the central region of the first surface 103A of the substrate, and a plurality of second pads 204 are provided in the peripheral region of the first surface 103A of the substrate; a plurality of pins 401 are provided in the second surface 103B of the substrate, which can be connected to peripheral circuits. A plurality of first bumps 201 are provided in the central region of the first surface 101A of the first chip, and a plurality of second bumps 202 are provided in the peripheral region of the first surface 101A of the first chip; a plurality of first pads 203 are provided in the central region of the second surface 101B of the first chip, and a plurality of second pads 204 are provided in the peripheral region of the second surface 101B of the first chip.

[0101] When stacking layers one by one, in one soldering bonding method, the current stacked layer is soldered to the stacked layer below it using a bonding head 501 on the current stacked layer. After completion, the bonding head 501 is removed, and then another stacked layer is stacked on top of the current stacked layer, thus achieving layer-by-layer soldering bonding. In another soldering bonding method, synchronous soldering bonding is performed using the bonding head 501. Specifically, the first bump 201 of each stacked layer is aligned with the first pad 203, and the second bump 202 is aligned with the second pad 204. Then, the bonding head 501 is placed on the topmost stacked layer, and the stacked layers are synchronously soldered by heating the bonding head 501.

[0102] When stacking the various layers one by one, a bonding head 501 is first set on the second surface 101B of the first chip and heated to melt the solder on the first bump 201 of the first chip 101, so that the first bump 201 is bonded to the first pad 203 of the substrate 103. At the same time, the solder on the second bump 202 of the first chip 101 is melted to bond the second bump 202 to the second pad 204 of the substrate 103, thereby realizing the stacking of the first chip 101 and the substrate 103. The bonding head 501 on the second surface 101B of the first chip is then removed. The bonding head 501 aligns the second chip 102 with the first chip 101. Then, the bonding head 501 is placed on the second surface 102B of the second chip and heated to melt the solder on the first bump 201 of the second chip 102, so that the first bump 201 is bonded to the first pad 203 of the first chip 101. At the same time, the solder on the second bump 202 of the second chip 102 is melted to bond the second bump 202 to the second pad 204 of the first chip 101, thereby completing the stacking of the second chip 102 on the first chip 101.

[0103] In this exemplary embodiment, the bump structure provided in the above exemplary embodiment is applied. When packaging the chip package structure, by employing the above-described bump structure, which increases the size of the second bump 202 located in the peripheral region of the first chip 101 and coordinates the design with the second pad 204 of the second chip 102 to be soldered thereto, the thermal resistance of the second bump 202 in the peripheral region is effectively reduced. This achieves the purpose of reducing the temperature difference between the central region and the peripheral region of the stacked layer of the bump structure. This eliminates the need to increase the temperature of the bonding head in the thermoforming process, while ensuring that the soldering of the first chip 101 and the second chip 102 ensures that the soldering of the first bump 201 in the central region and the second bump 202 in the peripheral region is consistent.

[0104] The various embodiments or implementation methods described in this specification are presented in a progressive manner. Each embodiment focuses on the differences from other embodiments, and the same or similar parts between the embodiments can be referred to each other.

[0105] In the description of this specification, references to the terms "embodiment," "exemplary embodiment," "some implementation," "illustrated implementation," "example," etc., refer to specific features, structures, materials, or characteristics described in connection with an implementation or example that are included in at least one implementation or example of this disclosure.

[0106] In this specification, the illustrative expressions of the terms used do not necessarily refer to the same implementation or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more implementations or examples.

[0107] In the description of this disclosure, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this disclosure.

[0108] It is understood that the terms "first," "second," etc., as used in this disclosure may be used to describe various structures, but these structures are not limited by these terms. These terms are only used to distinguish one structure from another.

[0109] In one or more accompanying drawings, the same elements are represented by similar reference numerals. For clarity, many parts in the drawings are not drawn to scale. Furthermore, certain well-known parts may not be shown. For simplicity, a structure obtained after several steps may be depicted in a single drawing. Many specific details of this disclosure, such as the structure, materials, dimensions, processing methods, and techniques of the devices, are described below to provide a clearer understanding of the disclosure. However, as those skilled in the art will understand, this disclosure may be implemented without adhering to these specific details.

[0110] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this disclosure, and are not intended to limit them. Although this disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this disclosure.

Claims

1. A bump structure, characterized in that, Applied in a chip stacking structure, the chip stacking structure includes: a first stacking layer and a second stacking layer, and the bump structure includes: Multiple first bumps and multiple second bumps; the first bumps are disposed in the central region of the first stacked layer, and the second bumps are disposed in the peripheral region of the first stacked layer; the first stacked layer includes a first chip; the first bumps are connected to a first conductive via of the first chip; Multiple first pads and multiple second pads are provided, wherein the first pads are disposed in the central region of the second stacked layer, and the second pads are disposed in the peripheral region of the second stacked layer; the positions of the first bumps are adapted to the positions of the first pads; the positions of the second bumps are adapted to the positions of the second pads. The size of the first bump is smaller than that of the second bump, and the size of the first pad is smaller than that of the second pad. This effectively reduces the thermal resistance of the second bump located in the peripheral region, thereby reducing the temperature difference between the central region and the peripheral region.

2. The bump structure according to claim 1, characterized in that, The second pad is an annular pad, and the inner diameter of the annular pad is less than or equal to the diameter of the second bump.

3. The bump structure according to claim 1, characterized in that, Both the first pad and the first bump are cylindrical structures.

4. The bump structure according to any one of claims 1-3, characterized in that, The thermal resistance of the first bump is greater than that of the second bump.

5. A chip packaging structure, characterized in that, The chip packaging structure includes a chip stacking structure, which includes: A first stacked layer and a second stacked layer, wherein the first stacked layer and the second stacked layer are combined by a bump structure as described in any one of claims 1-4.

6. The chip packaging structure according to claim 5, characterized in that, The second stacked layer includes a second chip.

7. The chip packaging structure according to claim 6, characterized in that, The first bump of the second chip corresponds to the second conductive via of the second chip.

8. The chip packaging structure according to claim 5, characterized in that, The chip stacking structure further includes: a substrate, the substrate being disposed at the bottom of the chip stacking structure, the central region of the first side of the substrate including a plurality of first pads, the peripheral region of the first side of the substrate including a plurality of second pads, wherein the first pads of the substrate are connected to a third conductive via of the substrate.

9. The chip packaging structure according to claim 5, characterized in that, The central region of the first surface of the first chip includes a plurality of first bumps, and the peripheral region of the first surface of the first chip includes a plurality of second bumps; the central region of the second surface of the first chip includes a plurality of first pads, and the peripheral region of the second surface of the chip includes a plurality of second pads; the first pads of the first chip correspond to the first conductive vias of the first chip.

10. The chip packaging structure according to claim 5, characterized in that, The chip stacking structure also includes an m-th stacking structure disposed on the second stacking layer, where m is a positive integer greater than or equal to 3; The central region of the first surface of the m-th layer stacked structure includes a plurality of first bumps, and the peripheral region of the first surface of the m-th layer stacked structure includes a plurality of second bumps; the central region of the second surface of the m-th layer stacked structure includes a plurality of first pads, and the peripheral region of the second surface of the m-th layer stacked structure includes a plurality of second pads. Wherein, the first bump of the m-th layer stacked structure corresponds to the n-th conductive via of the m-th layer stacked structure, the first pad of the m-th layer stacked structure corresponds to the n-th conductive via of the m-th layer stacked structure, n is a positive integer greater than or equal to 4, and n = m + 1.

11. A chip packaging method, characterized in that, The encapsulation method includes: A chip stack structure is formed, the chip stack structure including a first stack layer and a second stack layer, the first stack layer and the second stack layer being combined by a bump structure as described in any one of claims 1-4.

12. The chip packaging method according to claim 11, characterized in that, The formation of the chip stack structure includes: A substrate is provided, wherein the central region of the first surface of the substrate includes a plurality of first pads, and the peripheral region of the first surface of the substrate includes a plurality of second pads; A first chip is provided, wherein the central region of the first surface of the first chip includes a plurality of first bumps, and the peripheral region of the first surface of the first chip includes a plurality of second bumps; the first bumps correspond to the first conductive vias of the first chip. Align a plurality of first bumps on a first surface of the first chip with a plurality of first pads on a first surface of the substrate; align a plurality of second bumps on a first surface of the first chip with a plurality of second pads on a first surface of the substrate; The first bump on the first surface of the first chip is bonded to the first pad on the first surface of the substrate, and the second bump on the first surface of the first chip is bonded to the second pad on the first surface of the substrate, thereby forming a stack of the first chip and the substrate.

13. The chip packaging method according to claim 12, characterized in that, The central region of the second side of the first chip includes a plurality of first pads, and the peripheral region of the second side of the chip includes a plurality of second pads; the first pads correspond to the first conductive vias of the first chip; The first and second surfaces of the first chip are two opposite surfaces along the thickness direction of the first chip; The formation of the chip stack structure also includes: A second chip is provided, wherein the central region of the first surface of the second chip includes a plurality of first bumps, and the peripheral region of the first surface of the second chip includes a plurality of second bumps; the first bumps correspond to the second conductive vias of the second chip. Align the plurality of first bumps on the first surface of the second chip with the plurality of first pads on the second surface of the first chip; align the plurality of second bumps on the first surface of the second chip with the plurality of second pads on the second surface of the first chip; The first bump on the first surface of the second chip is bonded to the first pad on the second surface of the first chip, and the second bump on the first surface of the second chip is bonded to the second pad on the second surface of the first chip, thereby forming a stack of the second chip and the first chip.

14. The chip packaging method according to claim 12, characterized in that, The plurality of first pads on the first surface of the substrate are connected to the third conductive via on the substrate.

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