Semiconductor device

Abstract

The semiconductor device of this embodiment includes a first insulating layer. A first bonding pad is exposed on the surface of the first insulating layer. A second insulating layer is bonded to the first insulating layer. A second bonding pad is exposed on the surface of the second insulating layer and bonded to the first bonding pad. When viewed from a first top view in a direction substantially perpendicular to the surface of the first insulating layer, a first conductive material and a first insulating material with an etch rate lower than that of the first conductive material are present inside the first bonding pad. The first insulating material is disposed in an island-like pattern inside the first conductive material.

Description

[0001] [Citation of relevant applications]

[0002] This application asserts priority based on the priority of a prior Japanese patent application No. 2021-086411 filed on May 21, 2021, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This embodiment relates to a semiconductor device. Background Technology

[0004] In recent years, techniques have been developed to electrically bond multiple semiconductor chips together by attaching them to each other. On the other hand, in polishing methods such as CMP (Chemical Mechanical Polishing), disc-shaped deformation (depression) sometimes occurs due to differences in the materials being polished. If the bonding pads on the joint surface are depressed due to disc-shaped deformation, then when multiple semiconductor chips are attached together, the contact resistance between the bonding pads may increase, or open circuit defects may occur between the bonding pads. Summary of the Invention

[0005] One embodiment provides a semiconductor device capable of suppressing the rise of contact resistance between bonded semiconductor chips or suppressing open circuit defects.

[0006] The semiconductor device of this embodiment includes a first insulating layer. A first bonding pad is exposed on the surface of the first insulating layer. A second insulating layer is bonded to the first insulating layer. A second bonding pad is exposed on the surface of the second insulating layer and bonded to the first bonding pad. When viewed from a first top view in a direction substantially perpendicular to the surface of the first insulating layer, inside the first bonding pad, there is a first conductive material and a first insulating material with an etch rate lower than that of the first conductive material. The first insulating material is disposed in an island-like pattern inside the first conductive material.

[0007] According to the above configuration, a semiconductor device can be provided that can suppress the rise of contact resistance between bonded semiconductor chips or suppress open circuit defects. Attached Figure Description

[0008] Figure 1 This is a cross-sectional view showing a configuration example of the semiconductor package according to the first embodiment.

[0009] Figure 2 This is a cross-sectional view showing a configuration example of a portion of the semiconductor package according to the first embodiment.

[0010] Figure 3A This is a top view showing an example of the solder pad configuration.

[0011] Figure 3BThis is a top view showing an example of the solder pad configuration.

[0012] Figure 3C This is a top view showing an example of the configuration of a wiring layer.

[0013] Figure 4 This is a cross-sectional view showing an example of the composition of the mating surface.

[0014] Figure 5 This is a cross-sectional view illustrating an example of a method for manufacturing the solder pad according to the first embodiment.

[0015] Figure 6 It means to connect to Figure 5 A cross-sectional view of an example of a method for manufacturing solder pads.

[0016] Figure 7 It means to connect to Figure 6 A cross-sectional view of an example of a method for manufacturing solder pads.

[0017] Figure 8 It means to connect to Figure 7 A cross-sectional view of an example of a method for manufacturing solder pads.

[0018] Figure 9 It means to connect to Figure 8 A cross-sectional view of an example of a method for manufacturing solder pads.

[0019] Figure 10 It means to connect to Figure 9 A cross-sectional view of an example of a method for manufacturing solder pads.

[0020] Figure 11 It means to connect to Figure 10 A cross-sectional view of an example of a method for manufacturing solder pads.

[0021] Figure 12 This is a cross-sectional view illustrating an example of the formation process of the through-electrode region of a circuit chip.

[0022] Figure 13 It means to connect to Figure 12 A cross-sectional view of an example of a method for manufacturing solder pads.

[0023] Figure 14 It means to connect to Figure 13 A cross-sectional view of an example of a method for manufacturing solder pads.

[0024] Figure 15 It means to connect to Figure 14 A cross-sectional view of an example of a method for manufacturing solder pads.

[0025] Figure 16 It means to connect to Figure 15A cross-sectional view of an example of a method for manufacturing solder pads.

[0026] Figure 17 It means to connect to Figure 16 A cross-sectional view of an example of a method for manufacturing solder pads.

[0027] Figure 18A This is a cross-sectional view illustrating another example of a method for manufacturing solder pads.

[0028] Figure 18B It means to connect to Figure 18A A cross-sectional view of the subsequent method for manufacturing solder pads.

[0029] Figure 18C It means to connect to Figure 18B A cross-sectional view of the subsequent method for manufacturing solder pads.

[0030] Figure 18D It means to connect to Figure 18C A cross-sectional view of the subsequent method for manufacturing solder pads.

[0031] Figure 19A This is a cross-sectional view illustrating yet another example of a method for manufacturing solder pads.

[0032] Figure 19B It means to connect to Figure 19A A cross-sectional view of the subsequent method for manufacturing solder pads.

[0033] Figure 19C It means to connect to Figure 19B A cross-sectional view of the subsequent method for manufacturing solder pads.

[0034] Figure 19D It means to connect to Figure 19C A cross-sectional view of the subsequent method for manufacturing solder pads.

[0035] Figure 19E It means to connect to Figure 19D A cross-sectional view of the subsequent method for manufacturing solder pads.

[0036] Figure 19F It means to connect to Figure 19E A cross-sectional view of the subsequent method for manufacturing solder pads.

[0037] Figure 19G It means to connect to Figure 19F A cross-sectional view of the subsequent method for manufacturing solder pads.

[0038] Figure 20A This is a cross-sectional view showing another example of the formation process of the through-electrode region of a circuit chip.

[0039] Figure 20B It means to connect to Figure 20AA cross-sectional view of another example of the process for forming the region of the through electrode.

[0040] Figure 20C It means to connect to Figure 20B A cross-sectional view of another example of the process for forming the region of the through electrode.

[0041] Figure 20D It means to connect to Figure 20C A cross-sectional view of another example of the process for forming the region of the through electrode.

[0042] Figure 20E It means to connect to Figure 20D A cross-sectional view of another example of the process for forming the region of the through electrode.

[0043] Figure 20F It means to connect to Figure 20E A cross-sectional view of another example of the process for forming the region of the through electrode.

[0044] Figure 21 This is a top view showing an example of the pad configuration in the second embodiment.

[0045] Figure 22 This is a cross-sectional view showing an example of the configuration of the area of ​​the mating surface in the second embodiment.

[0046] Figure 23 This is a top view showing an example of the pad configuration in the third embodiment.

[0047] Figure 24 This is a top view showing an example of the pad configuration in the fourth embodiment.

[0048] Figure 25 This is a cross-sectional view showing an example of the configuration of the area of ​​the mating surface in the fifth embodiment. Detailed Implementation

[0049] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. These embodiments do not limit the present invention. In the following embodiments, the vertical direction of the semiconductor chip may sometimes differ from the vertical direction based on gravitational acceleration. The accompanying drawings are schematic or conceptual diagrams, and the proportions of the parts may not be the same as those of the actual object. In the specification and drawings, elements identical to those described above with reference to the accompanying drawings are labeled with the same symbols, and detailed descriptions are appropriately omitted.

[0050] (First Embodiment) Figure 1 This is a cross-sectional view showing a configuration example of the semiconductor package 1 according to the first embodiment. The semiconductor package 1 of this embodiment is an example of a semiconductor memory package. However, this embodiment can also be applied to other semiconductor devices.

[0051] The semiconductor package 1 includes a wiring substrate 10, metal bumps 20, solder balls 70, a controller chip 30, a memory chip stack 40 containing multiple memory chips, electrodes 50 disposed through each memory chip, and a sealing resin 60.

[0052] The wiring substrate 10 includes an insulator 11, a wiring layer 12, and a solder resist layer 13. The insulator 11 is, for example, made of an insulating material such as glass epoxy resin. The wiring layer 12 is a conductor disposed on the surface and back of the insulator 11. The wiring layer 12 is, for example, made of a low-resistance metal material such as copper. The solder resist layer 13 is disposed on the wiring layer 12.

[0053] Metal bumps 20 are disposed on the surface side of the wiring substrate 10 and electrically connected to a portion of the wiring layer 12. Solder balls 70 are disposed on the back side of the wiring substrate 10 and electrically connected to a portion of the wiring layer 12.

[0054] The controller chip 30 is disposed above the surface of the wiring substrate 10. The controller chip 30 is configured to control multiple memory chips.

[0055] The memory chip stack 40 is stacked on top of the controller chip 30. Multiple memory chips are, for example, semiconductor chips equipped with NAND (Not And) type memory cells. The memory chips and the controller chip 30 are electrically connected via electrodes 50. Electrodes 50 transmit power, ground voltage, control signals, or data. Electrodes 50 are made of conductive materials such as tungsten, nickel, copper, gold, aluminum, or polysilicon.

[0056] Sealing resin 60 is disposed on the surface of wiring substrate 10 and seals the controller chip 30 and memory chip stack 40.

[0057] Figure 2 This is a cross-sectional view showing a configuration example of a portion of the semiconductor package 1 according to the first embodiment. Figure 2 The image shows the cross-section of the two stacked memory chips 40_1 and 40_2. Memory chip 40_1 and memory chip 40_2 are bonded in the bonding surface B_chip.

[0058] Memory chip 40_1 includes an array chip CH_A1 containing a memory cell array MCA1, and a circuit chip CH_C1 containing a CMOS (Complementary Metal Oxide Semiconductor) circuit CMOS1. Memory chip 40_2 includes an array chip CH_A2 containing a memory cell array MCA2, and a circuit chip CH_C2 containing a CMOS circuit CMOS2.

[0059] In memory chip 40_1, either the memory cell array MCA1 or CMOS1 can be set as the first semiconductor circuit, and the other can be set as the second semiconductor circuit.

[0060] In the memory chip 40_2, either the memory cell array MCA2 or CMOS2 can be set as the first semiconductor circuit, and the other can be set as the second semiconductor circuit.

[0061] Alternatively, with the bonding surface B_chip in between, the memory cell array MCA1 and CMOS1 included in memory chip 40_1 can be set as the first semiconductor circuit, and the memory cell array MCA2 and CMOS2 included in memory chip 40_2 can be set as the second semiconductor circuit.

[0062] (Memory chip 40_1) The array chip CH_A1 includes a memory cell array MCA1 covered by an interlayer insulating film ILD1_1. The memory cell array MCA1 has multiple word lines WL1 stacked and insulated from each other in the Z direction, and multiple pillars CL1 extending through the stacked word lines WL1 in the stacking direction (Z direction). Memory cells MC1 are disposed at the intersections of word lines WL1 and pillars CL1. One end of the multiple pillars CL1 is commonly connected to a source line SL1. The other end of the multiple pillars CL1 is connected to any one of the bit lines BL1 extending in the Y direction.

[0063] The memory cell array MCA1 is located in the array region R_Arr. Word lines WL1 extend in the X direction to the stepped region R_Trr, forming a stepped shape within R_Trr. Contact plugs CC1 connect to the stepped surfaces of each word line WL1. Contact plugs CC1 are electrically connected via wiring layer W1_1 to the pads P1_1a located in the array region R_Arr and the word lines WL1, respectively. Pads P1_1a are exposed from the surface of the interlayer insulating film ILD1_1 and are electrode pads located on the bonding surface B_mc1 of the array chip CH_A1. Wiring layer W1_1 electrically connects the memory cell array MCA1 and pads P1_1a via contact plugs CC1.

[0064] A peripheral region R_Pri is provided around the array region R_Arr and the stepped region R_Trr. The peripheral region R_Pri can be located in various positions, including not only the periphery of the memory chip but also the center of the memory chip. In the peripheral region R_Pri, a contact plug Cpri1 is provided such that it penetrates the interlayer insulating film ILD1_1 of the array chip CH_A1 in the Z direction. One end of the contact plug Cpri1 is electrically connected via wiring layer W1_1 to the pad P1_1a of the bonding surface B_mc1 in the peripheral region R_Pri. The other end of the contact plug Cpri1 is electrically connected to the pad P1_1b of the array chip CH_A1 on the opposite side of the bonding surface B_mc1.

[0065] The circuit chip CH_C1 is located below the array chip CH_A1 (in the -Z direction) and contains a CMOS circuit CMOS1 covered by an interlayer insulating film ILD1_2. The CMOS circuit CMOS1 is located on the semiconductor layer SUB1 and includes a P-type MOSFET (Metal Oxide Semiconductor Field Effect Transistor) and an N-type MOSFET. The CMOS circuit CMOS1 may also include other semiconductor elements (e.g., resistors, capacitors). The CMOS circuit CMOS1 is covered by the interlayer insulating film ILD1_2. A multilayer wiring layer W1_2 is disposed on the interlayer insulating film ILD1_2. The multilayer wiring layer W1 electrically connects the CMOS circuit CMOS1 to the bonding pad P1_2a. The bonding pad P1_2a is exposed from the surface of the interlayer insulating film ILD1_2 and is an electrode pad on the bonding surface B_mc1 of the circuit chip CH_C1. The pad P1_2a can also be set in any of the array region R_Arr, the step region R_Trr, and the surrounding region R_Pri.

[0066] A through electrode TSV1 is disposed in the peripheral region R_Pri of the circuit chip CH_C1. The through electrode TSV1 is part of electrode 50. The through electrode TSV1 penetrates the semiconductor layer SUB1 in the Z direction and is electrically connected between pads P1_2a and P1_2b. Pad P1_2b is an electrode pad disposed at the end of the through electrode TSV1 on the opposite side of the bonding surface B_mc1.

[0067] The array chip CH_A1 and the circuit chip CH_C1 are bonded together at the bonding surface B_mc1. In the bonding surface B_mc1, interlayer insulating films ILD1_1 and ILD1_2 are bonded, and solder pads P1_1a and P1_2a are bonded. Thus, the CMOS circuit CMOS1 of the circuit chip CH_C1 is electrically connected to the memory cell array MCA1 via multilayer wiring layers W1_2, solder pads P1_2a and P1_1a, and contact plug CC1. As a result, the CMOS circuit CMOS1 can control the memory cell array MCA1. Additionally, the through electrode TSV1 is electrically connected to the contact plug Cpri1 via solder pads P1_2a and P1_1a, and wiring layer W1_1. The through electrode TSV1 is provided, for example, to allow the common transfer of power or ground potential between the chips.

[0068] (Memory chip 40_2) The array chip CH_A2 includes a memory cell array MCA2 covered by an interlayer insulating film ILD2_1. The memory cell array MCA2 has multiple word lines WL2 stacked and insulated from each other in the Z direction, and multiple pillars CL2 extending through the stacked word lines WL2 in the stacking direction (Z direction). Memory cells MC2 are disposed at the intersections of word lines WL2 and pillars CL2. One end of the multiple pillars CL2 is commonly connected to a source line SL2. The other end of the multiple pillars CL2 is connected to any one of the bit lines BL2 extending in the Y direction.

[0069] The memory cell array MCA2 is located in the array region R_Arr. Word lines WL2 extend in the X direction to the stepped region R_Trr, forming a stepped shape within R_Trr. Contact plugs CC2 are connected to the stepped surfaces of each word line WL2. Contact plugs CC2 are electrically connected via wiring layer W2_1 between the pads P2_1a located in the array region R_Arr and the word lines WL2. Pads P2_1a are electrode pads exposed on the surface of the interlayer insulating film ILD2_1 and located on the bonding surface B_mc2 of the array chip CH_A2. Wiring layer W2_1 electrically connects the memory cell array MCA2 and pads P2_1a via contact plugs CC2.

[0070] A peripheral region R_Pri is provided around the array region R_Arr and the stepped region R_Trr. In the peripheral region R_Pri, a contact plug Cpri2 is provided such that it penetrates the interlayer insulating film ILD2_1 of the array chip CH_A2 in the Z direction. One end of the contact plug Cpri2 is electrically connected via wiring layer W2_1 to the pad P2_1a of the bonding surface B_mc2 in the peripheral region R_Pri. The other end of the contact plug Cpri2 is electrically connected to the pad P2_1b on the opposite side of the bonding surface B_mc2 of the array chip CH_A2.

[0071] The circuit chip CH_C2 is located below the array chip CH_A2 (in the -Z direction) and contains a CMOS circuit CMOS2 covered by an interlayer insulating film ILD2_2. The CMOS circuit CMOS2 is located on the semiconductor layer SUB2 and includes P-type MOSFETs and N-type MOSFETs. The CMOS circuit CMOS2 may also include other semiconductor elements (e.g., resistors, capacitors). The CMOS circuit CMOS2 is covered by the interlayer insulating film ILD2_2. A multilayer wiring layer W2_2 is disposed on the interlayer insulating film ILD2_2. The multilayer wiring layer W2_2 electrically connects the CMOS circuit CMOS2 to the bonding pad P2_2a. The bonding pad P2_2a is an electrode pad exposed on the surface of the interlayer insulating film ILD2_2 and disposed on the bonding surface B_mc2 of the circuit chip CH_C2. The bonding pad P2_2a may also be disposed in any of the following regions: the array region R_Arr, the stepped region R_Trr, and the peripheral region R_Pri.

[0072] A through electrode TSV2 is disposed in the peripheral region R_Pri of the circuit chip CH_C2. The through electrode TSV2 penetrates the semiconductor layer SUB2 in the Z direction and is electrically connected between pads P2_2a and P2_2b. Pad P2_2b is an electrode pad disposed at the end of the through electrode TSV2 on the opposite side of the bonding surface B_mc2.

[0073] The array chip CH_A2 and the circuit chip CH_C2 are bonded together at the bonding surface B_mc2. In the bonding surface B_mc2, interlayer insulating films ILD2_1 and ILD2_2 are bonded, and solder pads P2_1a and P2_2a are bonded. Thus, the CMOS circuit CMOS2 of the circuit chip CH_C2 is electrically connected to the memory cell array MCA2 via multilayer wiring layer W2_2, solder pads P2_2a and P2_1a, and contact plug CC2. As a result, the CMOS circuit CMOS2 can control the memory cell array MCA2. Additionally, the through electrode TSV2 is electrically connected to the contact plug Cpri2 via solder pads P2_2a and P2_1a, and wiring layer W2_1. The through electrode TSV2 is also provided, for example, to allow for the common transfer of power or ground potential between the chips.

[0074] (Jointing between memory chips 40_1 and 40_2) Memory chips 40_1 and 40_2 are joined at the bonding surface B_chip. In the bonding surface B_chip, solder pads P1_1b and P2_1b are joined. Memory chips 40_1 and 40_2 are electrically connected via the mutually joined solder pads P1_1b and P2_1b. Thus, through electrodes TSV1 and TSV2 and contact plugs Cpri1 and Cpri2 are electrically connected, enabling, for example, the common transmission of power or ground potential among the stacked memory chips 40_1 and 40_2.

[0075] (The composition of solder pads P1_1a, etc.) Figure 3A This is a top view showing an example of the configuration of solder pad P1_1a. Figure 3A In the first top view (view from the Z direction) taken approximately perpendicular to the surface (bonding surface B_mc1) of the interlayer insulating film ILD1_1 relative to the array chip CH_A1, the solder pad P1_1a is exposed from the surface of the interlayer insulating film ILD1_1. In this top view, the solder pad P1_1a is surrounded by the interlayer insulating film ILD1_1, and for example, the solder pad P1_1a has a generally octagonal shape. The planar shape of the solder pad P1_1a can also be a polygon other than an octagon, approximately circular, or approximately elliptical.

[0076] On the inner side of the solder pad P1_1a, a barrier metal film 101_1a, a conductive material 102_1a, and an insulating material 103_1a are disposed. On the outer side of the solder pad P1_1a, an interlayer insulating film ILD1_1 is disposed.

[0077] The barrier metal film 101_1a is disposed on the outer edge of the pad P1_1a and is disposed between the interlayer insulating film ILD1_1 or the insulating material 103_1a and the conductive material 102_1a. The barrier metal film 101_1a is made of conductive materials such as titanium film and titanium nitride film laminate.

[0078] Conductive material 102_1a is disposed inside the pad P1_1a surrounded by barrier metal film 101_1a. Conductive material 102_1a may be, for example, copper, tungsten, or other conductive materials. Insulating material 103_1a is disposed in an island shape inside conductive material 102_1a, and is surrounded by conductive material 102_1a.

[0079] In the top view, multiple insulating materials 103_1a extend in the Y direction on the surface of the conductive material 102_1a and have an elongated shape. Additionally, in the top view, the multiple insulating materials 103_1a are arranged in a stripe-like or line-and-gap pattern in the X direction orthogonal to the Y direction on the surface of the conductive material 102_1a. In other words, the multiple insulating materials 103_1a are configured as slits or short strips extending approximately parallel to each other. In the top view, the multiple insulating materials 103_1a are disposed inside the pad P1_1a and do not reach the barrier metal film 101_1a and the interlayer insulating film ILD1_1. Furthermore, the insulating materials 103_1a may also be connected to the interlayer insulating film ILD1_1 below the pad P1_1a. The insulating materials 103_1a can be made of the same material as the interlayer insulating film ILD1_1 (e.g., silicon oxide film).

[0080] Furthermore, in the top view, the area of ​​the insulating material 103_1a of the solder pad P1_1a is smaller than the area of ​​the conductive material 102_1a. By making the area of ​​the conductive material 102_1a relatively large, and thus increasing the contact area with the conductive material 102_2a of the solder pad P1_2a of the circuit chip CH_C1, the contact resistance between the solder pad P1_1a and the solder pad P1_2a can be kept low.

[0081] Here, the insulating material 103_1a is formed from a material with a lower etching rate in the CMP process than the material of the conductive material 102_1a (e.g., a metal material such as copper or tungsten). This material can be an oxide film such as silicon oxide, a nitride film such as silicon nitride, a carbide film such as silicon carbide, or composites thereof. For example, the insulating material 103_1a can also be formed from a physically harder material that is more difficult to grind than the material of the conductive material 102_1a. Alternatively, the insulating material 103_1a can be formed from a material that is more difficult to chemically etch using an abrasive (slurry) than the material of the conductive material 102_1a. Therefore, in the CMP process, the insulating material 103_1a acts as a support inside the conductive material 102_1a, mitigating the thinning of the film thickness in the central part of the conductive material 102_1a and preventing depressions (disc-shaped deformation).

[0082] The width Wp1_1a of the solder pad P1_1a in the X or Y direction is, for example, about 1 μm. The width W103_1a of the insulating material 103_1a is, for example, about tens of nm.

[0083] The wiring layer W1_1, indicated by the dashed line, is disposed below the solder pad P1_1a. The wiring layer W1_1 is electrically connected to the solder pad P1_1a via through-hole contacts V1_1. In this embodiment, nine through-hole contacts V1_1 are disposed between the solder pad P1_1a and the wiring layer W1_1. However, the number of through-hole contacts V1_1 is not limited to nine and can be arbitrary. Furthermore, Figure 3C This is a top view showing an example of the configuration of wiring layer W1_1. In this top view, wiring layer W1_1 is formed in a cross shape within a roughly square frame below the solder pad P1_1a. Nine through-hole contacts V1_1 are provided on wiring layer W1_1. Alternatively, wiring layer W1_1 may not be cross-shaped, but rather a three-dimensional shape.

[0084] Figure 3B This is a cross-sectional view showing an example of the configuration of solder pad P1_1a. Figure 3B Indicates along Figure 3A The cross-section of the BB line. The solder pad P1_1a is embedded within the interlayer insulating film ILD1_1 and exposed on the surface of the interlayer insulating film ILD1_1. The conductive material 102_1a is electrically connected to the wiring layer W1_1 disposed beneath the conductive material 102_1a via the through-hole contact V1_1. The insulating material 103_1a can be part of the interlayer insulating film ILD1_1 or the same material. Furthermore, the height of the conductive material 102_1a is, for example, approximately 1 μm.

[0085] Thus, according to this embodiment, the solder pad P1_1a includes an insulating material 103_1a, which, when viewed from a direction substantially perpendicular to the bonding surface B_mc1, is arranged in an island-like manner inside the conductive material 102_1a. The insulating material 103_1a is formed of a material with a lower etching rate than the conductive material 102_1a. Therefore, in the CMP process of polishing the interlayer insulating film ILD1_1 and the conductive material 102_1a, the insulating material 103_1a acts as a pillar within the conductive material 102_1a, mitigating the disc-shaped deformation of the conductive material 102_1a.

[0086] Without the insulating material 103_1a, the conductive material 102_1a is ground over a relatively wide area. In this case, the inner side of the conductive material 102_1a is significantly recessed in a disc-shaped deformation.

[0087] In contrast, according to this embodiment, the insulating material 103_1a divides the conductive material 102_1a into relatively small areas, thus forming a support within the conductive material 102_1a. This suppresses disc-shaped deformation on the inner side of the conductive material 102_1a.

[0088] The insulating material 103_1a is preferably disposed approximately evenly within the conductive material 102_1a. This helps to suppress large-scale localized disc-shaped deformation of the conductive material 102_1a.

[0089] Figure 3A and Figure 3B The solder pad P1_1a has been described, but solder pads P1_2a, P2_1a, P2_2a, P1_2b, and P2_1b can also be constructed in the same way. Therefore, similarly, for solder pads P1_2a, P2_1a, P2_2a, P1_2b, and P2_1b other than solder pad P1_1a, disc-shaped deformation is suppressed during the CMP process. Furthermore, the construction of solder pads P1_2a, P2_1a, P2_2a, P1_2b, and P2_1b can be referenced from [the previous description]. Figure 3A and Figure 3B Therefore, detailed explanations are omitted as they are easy to understand.

[0090] Figure 4 This is a cross-sectional view showing a configuration example of the bonding surface B_mc1. The pad P1_1a on the array chip CH_A1 side and the pad P1_2a on the circuit chip CH_C1 side are bonded at the bonding surface B_mc1.

[0091] Both solder pads P1_1a and P1_2a have Figure 3A and Figure 3B The structure shown. Therefore, with Figure 3A Similarly, when viewed from a direction approximately perpendicular to the surface of the interlayer insulating film ILD1_2, the pad P1_2a shown has a barrier metal film 101_2a, a conductive material 102_2a, and an insulating material 103_2a disposed on the inner side of the pad P1_2a.

[0092] Furthermore, in the following description of solder pad P1_2a, Figure 3A and Figure 3B The solder pad P1_1a, interlayer insulating film ILD1_1, barrier metal film 101_1a, conductive material 102_1a, and insulating material 103_1a are respectively renamed solder pad P1_2a, interlayer insulating film ILD1_2, barrier metal film 101_2a, conductive material 102_2a, and insulating material 103_2a. An interlayer insulating film ILD1_2 is disposed on the outer side of the solder pad P1_2a.

[0093] The barrier metal film 101_2a is disposed on the outer edge of the pad P1_2a and between the interlayer insulating film ILD1_2 or the insulating material 103_2a and the conductive material 102_2a. The barrier metal film 101_2a is made of conductive materials such as titanium film and titanium nitride film laminate.

[0094] Conductive material 102_2a is disposed inside the pad P1_2a surrounded by barrier metal film 101_2a. Conductive material 102_2a may be, for example, copper, tungsten, or other conductive materials. Insulating material 103_2a is disposed in an island shape inside conductive material 102_2a, and is surrounded by conductive material 102_2a.

[0095] In the top view, multiple insulating materials 103_2a extend in the Y direction on the surface of the conductive material 102_2a and have elongated shapes. Additionally, in the top view, the multiple insulating materials 103_2a are arranged in a stripe-like or line-and-gap pattern in the X direction orthogonal to the Y direction on the surface of the conductive material 102_2a. In other words, the multiple insulating materials 103_2a are configured as slits or short strips extending in a generally parallel manner. In the top view, the multiple insulating materials 103_2a are disposed inside the pad P1_2a and do not reach the barrier metal film 101_2a and the interlayer insulating film ILD1_2. Furthermore, the insulating material 103_2a can be made of the same material as the interlayer insulating film ILD1_2 (e.g., silicon oxide film).

[0096] Here, the insulating material 103_2a is formed of a material (e.g., a silicon oxide film) with a lower etching rate than the material of the conductive material 102_2a (e.g., a metallic material such as copper or tungsten). For example, the insulating material 103_2a may also be formed of a physically harder material that is more difficult to grind than the material of the conductive material 102_2a. Alternatively, the insulating material 103_2a may also be formed of a material that is more difficult to chemically etch using an abrasive (slurry) than the material of the conductive material 102_2a. Therefore, in the CMP process, the insulating material 103_2a acts as a support on the inside of the conductive material 102_2a, mitigating the disc-shaped deformation of the conductive material 102_2a.

[0097] The width Wp1_2a of the solder pad P1_2a in the X or Y direction is, for example, about 1 μm. The width W103_2a of the insulating material 103_2a is, for example, about tens of nm.

[0098] The solder pad P1_2a is embedded within the interlayer insulating film ILD1_2 and exposed on the surface of the interlayer insulating film ILD1_2. The conductive material 102_2a is electrically connected to the wiring layer W1_2 disposed beneath the conductive material 102_2a. The insulating material 103_2a can be part of the interlayer insulating film ILD1_2 or the same material. Furthermore, the height of the conductive material 102_2a is, for example, approximately 1 μm.

[0099] Thus, solder pads P1_1a and P1_2a have substantially the same configuration. Solder pads P1_1a and P1_2a are bonded at their bonding surfaces B_mc1 in a manner where the extending directions of insulating material 103_1a and insulating material 103_2a are substantially the same (e.g., the Y direction). Therefore, when bonding array chip CH_A1 to circuit chip CH_C1, as... Figure 4 As shown, conductive materials 102_1a and 102_2a are bonded at the bonding surface B_mc1 in a substantially opposing manner. At this time, the solder pads P1_1a and P1_2a hardly undergo disc-shaped deformation, and the conductive materials 102_1a and 102_2a hardly show any indentation at the bonding surface B_mc1. That is, the conductive materials 102_1a and 102_2a are disposed on substantially the same surface in the bonding surface B_mc1. Therefore, although insulating materials 103_1a and 103_2a are disposed on the inner sides of each of the conductive materials 102_1a and 102_2a, the conductive materials 102_1a and 102_2a can be bonded at the bonding surface B_mc1 with sufficiently low resistance.

[0100] If insulating materials 103_1a and 103_2a are not provided, although the area of ​​conductive materials 102_1a and 102_2a in the bonding surface B_mc1 will be correspondingly wider, the conductive materials 102_1a and 102_2a are prone to poor bonding due to disc-shaped deformation during the CMP process. Therefore, there is a concern that the contact resistance between conductive materials 102_1a and 102_2a will increase.

[0101] In contrast, according to this embodiment, since insulating materials 103_1a and 103_2a are provided, the area of ​​conductive materials 102_1a and 102_2a in the bonding surface B_mc1 is correspondingly smaller. However, the disc-shaped deformation of conductive materials 102_1a and 102_2a is suppressed, and conductive materials 102_1a and 102_2a hardly sink in the bonding surface B_mc1. Therefore, the contact resistance between conductive materials 102_1a and conductive materials 102_2a is low and stable.

[0102] Next, the manufacturing method of the solder pads P1_1a and P1_2a in the first embodiment will be described.

[0103] Figures 5 to 11 This is a cross-sectional view illustrating an example of the manufacturing method of the solder pad P1_1a according to the first embodiment. Furthermore, the manufacturing method of the solder pad P1_2a is the same as that of the solder pad P1_1a, so its detailed description is omitted.

[0104] First, a memory cell array MCA1 and an interlayer insulating film ILD1_1 are formed on the substrate (e.g., a silicon substrate) of the array chip CH_A1. Next, a wiring layer W1_1 is formed on the interlayer insulating film ILD1_1 of the array chip CH_A1. Then, an insulating film is deposited on the wiring layer W1_1 and the interlayer insulating film ILD1_1. The insulating film can be made of the same material as the interlayer insulating film ILD1_1 (e.g., a silicon oxide film). Therefore, the insulating film on the wiring layer W1_1 is also referred to as the interlayer insulating film ILD1_1. Thus, a... Figure 5 The structure shown.

[0105] Next, photolithography and etching techniques are used to process the interlayer insulating film ILD1_1 on the wiring layer W1_1. Thus, as... Figure 6 As shown, the interlayer insulating film ILD1_1 on the wiring layer W1_1 is processed into a pattern of through-hole contacts V1_1.

[0106] Next, as Figure 7 As shown, a barrier metal film 201_1a and a conductive material 202_1a are deposited on the interlayer insulating film ILD1_1 and the wiring layer W1_1. The barrier metal film 201_1a may be, for example, a laminated film of titanium film and titanium nitride film. The conductive material 202_1a may be, for example, a conductive material such as copper or tungsten.

[0107] Next, the barrier metal film 201_1a and the conductive material 202_1a were polished using the CMP method until the interlayer insulating film ILD1_1 was exposed. Thus, as... Figure 8 As shown, a through-hole contact V1_1 is formed, comprising a barrier metal film 201_1a and a conductive material 202_1a.

[0108] Next, an insulating film is deposited on the via contact V1_1. The insulating film can be made of the same material as the interlayer insulating film ILD1_1 (e.g., silicon oxide). Therefore, the insulating film on the via contact V_1 is also referred to as the interlayer insulating film ILD1_1. Next, photolithography and etching techniques are used, such as... Figure 9 As shown, the interlayer insulating film IL_1 on the through-hole contact V1_1 is processed into the pattern of the solder pad P1_1a. Here, a first recess Con_1 can also be formed on the solder pad P1_1a, a first insulating layer can be formed around it, and a first insulating material can be formed on the inner side of the first recess.

[0109] Next, as Figure 10As shown, a barrier metal film 101_1a and a conductive material 102_1a are deposited on the interlayer insulating film ILD1_1 and the through-hole contact V1_1. The barrier metal film 101_1a is, for example, a laminated film of titanium film and titanium nitride film. The conductive material 102_1a is, for example, a conductive material such as copper or tungsten.

[0110] Next, the barrier metal film 101_1a and the conductive material 102_1a are polished using the CMP method until the interlayer insulating film ILD1_1 is exposed. Thus, as... Figure 11 As shown, a bonding pad P1_1a is formed, comprising a barrier metal film 101_1a and a conductive material 102_1a. Furthermore, the interlayer insulating film ILD1_1 exposed during the CMP process becomes the insulating material 103_1a.

[0111] Here, as Figure 3A As shown, the insulating material 103_1a is arranged in an island shape (e.g., stripe shape or line and gap shape) inside the conductive material 102_1a. During the CMP process of the barrier metal film 101_1a and the conductive material 102_1a, the insulating material 103_1a functions as a support within the conductive material 102_1a. Therefore, dish-shaped deformation (depression) of the conductive material 102_1a in the solder pad P1_1a is suppressed.

[0112] The manufacturing method of pad P1_1a for array chip CH_A1 has been described above. Although pad P1_2a for circuit chip CH_C1 is connected to CMOS circuit CMOS1, it is formed in the same manner as pad P1_1a. Therefore, the disc-shaped deformation (depression) of the conductive material 102_2a in pad P1_2a is also suppressed.

[0113] The disc-shaped deformation of pad P1_1a of array chip CH_A1 and pad P1_2a of circuit chip CH_C1 is suppressed. Therefore, when bonding array chip CH_A1 and circuit chip CH_C1, as Figure 4 As shown, solder pads P1_1a and P1_2a are fully bonded with almost no gap. As a result, the increase in contact resistance between the solder pads of array chip CH_A1 and circuit chip CH_C1 can be suppressed, thus suppressing open circuit defects.

[0114] The above describes the connection between array chip CH_A1 and circuit chip CH_C1, but this embodiment can also be applied to the connection between memory chips 40_1 and 40_2.

[0115] (The connection between memory chips 40_1 and 40_2) such as Figure 2As shown, memory chip 40_1 and memory chip 40_2 are bonded together at the bonding surface B_chip. Memory chips 40_1 and 40_2 have the same configuration.

[0116] In the bonding surface B_chip, the pad P1_2b of memory chip 40_1 is electrically connected to the pad P2_1b of memory chip 40_2. Pad P1_2b is electrically connected via a redistribution layer (not shown) to the through electrode TSV1 of the circuit chip CH_C1 in memory chip 40_1. Pad P2_1b is electrically connected to the contact plug Cpri2 of the array chip CH_A2 in memory chip 40_2.

[0117] Here, pads P1_2b and P2_1b can respectively have the same characteristics as... Figure 3A and Figure 3B The solder pad P1_1a shown has the same configuration. Therefore, solder pad P1_2b is identical to solder pad P1_1a. Figure 4 The pads P1_1a and P1_2a shown are bonded in the same way. Therefore, the effects of this embodiment can also be obtained in the bonding between memory chips 40_1 and 40_2.

[0118] Figures 12-17 This is a cross-sectional view showing an example of the formation process of the region of the through electrode TSV1 of the circuit chip CH_C1.

[0119] First, using semiconductor manufacturing processes, a CMOS circuit CMOS1 is formed on a substrate (e.g., a silicon substrate) SUB1. For example... Figure 12 As shown, the CMOS circuit CMOS1 is electrically connected to the through electrode TSV1 via pad P1_2b and wiring W1_2 (or the receiving electrode of the through electrode). Furthermore, in Figure 13 The diagrams of the CMOS circuit CMOS1, pad P1_2b, and wiring W1_2 are omitted thereafter.

[0120] Next, a hole is formed in the formation region of the through electrode TSV1 using photolithography and etching techniques. A spacer insulating film SP1 is formed on the inner wall of this hole. Next, a material (e.g., copper, tungsten) for the through electrode TSV1 is filled inside the spacer insulating film (e.g., silicon oxide film) SP1 using a deposition method or similar method. Next, an interlayer insulating film ILD1_2 is deposited on the substrate SUB1. Thus, a... Figure 12 The structure shown.

[0121] Thus, the through electrode TSV1 is formed after the CMOS circuit is formed. Therefore, since the through electrode TSV1 is formed after the high-temperature heat treatment of the CMOS circuit, the material of the through electrode TSV1 (e.g., copper, tungsten) can be deposited using a plating method. The CMOS circuit side end of the through electrode TSV1 can be electrically connected to either the CMOS circuit or an external electrode.

[0122] Next, the circuit chip CH_C1 is bonded to the array chip CH_A1. At this time, the solder pads P1_1a and P1_2a are joined (see reference). Figure 2 ).

[0123] Next, as Figure 13 As shown, the substrate SUB1 is flipped vertically. Next, as... Figure 14 As shown, the back side of the substrate SUB1 is etched to expose the ends of the through electrode TSV1 and the spacer insulating film SP1.

[0124] Next, as Figure 15 As shown, insulating films 91 and 92 are deposited on the substrate SUB1 and the through electrode TSV1. Insulating film 91 is, for example, a silicon nitride film, and insulating film 92 is, for example, a silicon oxide film.

[0125] Next, as Figure 16 As shown, insulating films 91 and 92 are polished using CMP until the through electrode TSV1 is exposed. Thus, the through electrode TSV1 is formed within the substrate SUB1. The through electrode TSV1 penetrates the substrate SUB1 while being electrically insulated from it by the spacer insulating film SP1.

[0126] Next, as Figure 17 As shown, a rewiring layer RW1 is formed. Next, solder pads P1_2b are formed on the rewiring layer RW1. The structure and formation method of solder pads P1_2b are described in reference [reference needed]. Figures 3A to 11 The content described is the same.

[0127] Then, memory chips 40_1 and 40_2 are bonded together. Thus, as... Figure 2 As shown, solder pad P1_2b and solder pad P2_1b are bonded together.

[0128] Furthermore, when a through electrode is provided on the array chip CH_A1, the through electrode of the array chip CH_A1 can also be connected to... Figures 12-17 The method shown is formed in the same way.

[0129] (Variation Example 1) Figures 18A to 18DThis is a cross-sectional view showing another example of the manufacturing method of solder pad P1_1a. Furthermore, the manufacturing method of solder pad P1_2a is the same as that of solder pad P1_1a, so its detailed description is omitted.

[0130] In formation Figure 5 Following the structure shown, photolithography and etching techniques are used to process the interlayer insulating film ILD1_1 on the wiring layer W1_1. Thus, as... Figure 18A As shown, the interlayer insulating film ILD1_1 on the wiring layer W1_1 is processed into a pattern of through-hole contacts V1_1.

[0131] Next, photolithography and etching techniques are used again to process the interlayer insulating film ILD1_1, such as... Figure 18B As shown, the upper part of the interlayer insulating film ILD1_1 is processed into the pattern of the solder pad P1_1a. Thus, the pattern of the solder pad P1_1a is formed on the upper part of the interlayer insulating film ILD1_1, and the pattern of the through-hole contact V1_1 is formed below the pattern of the solder pad P1_1a.

[0132] Next, as Figure 18C As shown, a barrier metal film 101_1a and a conductive material 102_1a are deposited on the interlayer insulating film ILD1_1 and the wiring layer W1_1.

[0133] Next, the barrier metal film 101_1a and the conductive material 102_1a are polished using the CMP method until the interlayer insulating film ILD1_1 is exposed. Thus, as... Figure 18D As shown, through-hole contacts V1_1 and solder pads P1_1a, including a barrier metal film 101_1a and a conductive material 102_1a, are formed simultaneously. In this CMP process, the insulating material 103_1a acts as a support on the inside of the conductive material 102_1a, which can mitigate the disc-shaped deformation of the conductive material 102_1a.

[0134] In Variation 1, both the through-hole contact V1_1 and the solder pad P1_1a are formed simultaneously. Therefore, Variation 1 can form the solder pad P1_1a using fewer steps than in the first embodiment. The other manufacturing steps in Variation 1 can be the same as in the first embodiment. Therefore, this Variation 1 can achieve the same effects as the first embodiment.

[0135] (Variation Example 2) Figures 19A to 19G This is a cross-sectional view showing another example of the manufacturing method of solder pad P1_1a. Furthermore, the manufacturing method of solder pad P1_2a is the same as that of solder pad P1_1a, so its detailed description is omitted.

[0136] In formation Figure 5Following the structure shown, photolithography and etching techniques are used to remove the entire interlayer insulating film ILD1_1 of the bonding pad P1_1a within the interlayer insulating film ILD1_1 on the wiring layer W1_1. This yields... Figure 19A The structure shown.

[0137] Next, as Figure 19B As shown, a barrier metal film 101_1a and a conductive material 102_1a are deposited on the interlayer insulating film ILD1_1 and the wiring layer W1_1.

[0138] Next, the barrier metal film 101_1a and the conductive material 102_1a are polished using the CMP method until the interlayer insulating film ILD1_1 is exposed. Thus, as... Figure 19C As shown, the barrier metal film 101_1a and the conductive material 102_1a are formed in the entire formation area of ​​the pad P1_1a.

[0139] Next, photolithography and etching techniques are used to process the upper part of the conductive material 102_1a, removing the conductive material 102_1a located in the formation region of the insulating material 103_1a. Thus, a... Figure 19D The structure shown.

[0140] Next, as Figure 19E As shown, a barrier metal film 101_3 is deposited on the interlayer insulating film ILD1_1 and the conductive material 102_1a.

[0141] Next, as Figure 19F As shown, insulating material 103_1a is deposited on barrier metal film 101_3.

[0142] Next, the insulating material 103_1a was polished using the CMP method until the interlayer insulating film ILD1_1 was exposed. Thus, as... Figure 19G As shown, a solder pad P1_1a is formed. In this CMP process, even if the conductive material 102_1a is exposed, the insulating material 103_1a will act as a support on the inside of the conductive material 102_1a, thereby mitigating the disc-shaped deformation of the conductive material 102_1a.

[0143] In Variation 2, the through-hole contact V1_1 is provided throughout the entire formation area of ​​the solder pad P1_1a. In this case, the solder pad P1_1a is connected to the wiring layer W1_1 via the through-hole contact V1_1.

[0144] In Variation Example 2, similarly, the through-hole contact V1_1 and the solder pad P1_1a are formed simultaneously. Therefore, Variation Example 2 can form the solder pad P1_1a using fewer steps than the first embodiment. The other forming steps of Variation Example 2 can be the same as those of the first embodiment. Therefore, this Variation Example 2 can achieve the same effects as the first embodiment. Furthermore, an embodiment using the solder pad P1_1a formed by Variation Example 2 will be referred to... Figure 25 As will be described below.

[0145] (Variation Example 3) Figures 20A to 20F This is a cross-sectional view showing another example of the formation process of the through electrode TSV1 region of the circuit chip CH_C1. In this variation, the through electrode TSV1 is formed after the CMOS circuit is formed and the substrate SUB1 is reversed.

[0146] First, a CMOS circuit (not shown) is formed on a substrate SUB1, and an interlayer insulating film ILD1_2 is deposited on it. This yields... Figure 20A The structure shown.

[0147] Next, as Figure 20B As shown, a hole is formed in the formation area of ​​the through electrode TSV1 using photolithography and etching techniques.

[0148] Next, as Figure 20C As shown, a spacer insulating film SP1 is formed on the inner wall of the hole, and then etched back to remove the spacer insulating film SP1 at the bottom of the hole.

[0149] Next, as Figure 20D As shown, the material of the through electrode TSV1 is filled inside the spacer insulating film SP1 using a plating method or the like.

[0150] Thus, the through electrode TSV1 is formed after the CMOS circuit is formed. Therefore, since the through electrode TSV1 is formed after the high-temperature heat treatment of the CMOS circuit, the material of the through electrode TSV1 (e.g., copper, tungsten) can be deposited using a plating method.

[0151] Next, the material of the through electrode TSV1 is polished using the CMP method until the surface of the spacer insulating film SP1 is exposed. Thus, as... Figure 20E As shown, the through electrode TSV1 is formed within the substrate SUB1. The through electrode TSV1 penetrates the substrate SUB1 while being electrically insulated from the substrate SUB1 by the spacer insulating film SP1.

[0152] Next, as Figure 20F As shown, a rewiring layer RW1 is formed. Next, solder pads P1_2b are formed on the rewiring layer RW1. The structure and formation method of solder pads P1_2b are described in reference [reference needed]. Figures 3A to 11As explained.

[0153] Then, memory chips 40_1 and 40_2 are bonded together. Thus, as... Figure 2 As shown, pads P1_2b and P2_1b are bonded together.

[0154] Furthermore, when a through electrode is provided in the array chip CH_A1, the through electrode of the array chip CH_A1 can also be formed in the same way as in this variation.

[0155] (Second Implementation) Figure 21 This is a top view showing an example of the configuration of solder pad P1_2a in the second embodiment. Similar to the first embodiment, when solder pad P1_1a and solder pad P1_2a have the same configuration, if... Figure 4 If the solder pads P1_1a and P1_2a are offset relative to each other in the X direction, then it is suspected that the conductive material 102_1a and the insulating material 103_2a are aligned, and the conductive material 102_2a and the insulating material 103_1a are aligned. In this case, it is suspected that the contact area between the conductive materials 102_1a and 102_2a becomes extremely small, the contact resistance between the solder pads P1_1a and P1_2a becomes high, and becomes unstable.

[0156] In contrast, in the second embodiment, when viewed from above in the Z direction, the insulating material 103-2a of the solder pad P1_2a extends in a direction inclined relative to the X and Y directions. The configuration of the solder pad P1_1a can be the same as that of the solder pad P1_1a in the first embodiment.

[0157] Figure 22 This is a cross-sectional view showing an example of the configuration of the region of the bonding surface B_mc1 in the second embodiment. In the second embodiment, when the array chip CH_A1 and the circuit chip CH_C1 are bonded, the solder pads P1_1a and P1_2a are bonded in the bonding surface B_mc1 in such a way that the extending direction of the insulating material 103_1a (e.g., the Y direction) intersects with the extending direction of the insulating material 103_2a (a direction inclined relative to the X and Y directions). Furthermore, along... Figure 21 The cross section of the BB line is represented as Figure 22 The solder pad P1_2a.

[0158] Viewed from a direction perpendicular to the substrate, multiple insulating materials 103_1a, which are separated from each other, partially overlap with conductive material 102_2a.

[0159] Since the extending directions of insulating material 103_1a and insulating material 103_2a intersect, even if solder pads P1_1a and P1_2a are offset to some extent in the X or Y direction, the contact area between conductive materials 102_1a and 102_2a is not significantly reduced. Therefore, in the second embodiment, the offset of solder pads P1_1a and P1_2a relative to the bonding surface B_mc1 results in low and stable contact resistance.

[0160] (Third Implementation)

[0161] Figure 23 This is a top view showing an example of the configuration of the solder pad P1_1a according to the third embodiment. In the second embodiment, when viewed from the Z direction, the conductive material 102_1a of the solder pad P1_1a has a mesh structure on the surface of the interlayer insulating film ILD1_1, including elongated shapes extending in the X direction and elongated shapes extending in the Y direction. Therefore, when viewed from the Z direction, the insulating material 103_1a is formed as islands (dots) on the surface of the interlayer insulating film ILD1_1, arranged in a matrix-like two-dimensional pattern in the X and Y directions. When one of the insulating materials 103_1a is designated as the first insulating portion In1_1, a second insulating portion In2_1, which is closest to the first insulating portion In1_1 in the Y direction, and a third insulating portion In3_1, which is closest to the first insulating portion In1_1 in the X direction, are formed.

[0162] The insulating material 103_1a is formed from a material (e.g., a silicon oxide film) with a lower etching rate than the material of the conductive material 102_1a (e.g., a metallic material such as copper or tungsten). For example, the insulating material 103_1a may also be formed from a physically harder material that is more difficult to grind than the material of the conductive material 102_1a. Alternatively, the insulating material 103_1a may also be formed from a material that is more difficult to chemically etch using an abrasive (slurry) than the material of the conductive material 102_1a. Therefore, in the CMP process, the insulating material 103_1a acts as a support inside the conductive material 102_1a, mitigating the disc-shaped deformation of the conductive material 102_1a.

[0163] In addition, the solder pad P1_2a also has the same characteristics as... Figure 23The solder pad P1_1a has the same structure. Therefore, although not shown, solder pad P1_2a similarly, when viewed from the Z direction, has a mesh structure on the surface of the interlayer insulating film ILD1_2, including elongated shapes extending in the X direction and elongated shapes extending in the Y direction. That is, when viewed from the Z direction, the insulating material 103_2a is formed as islands (dots) on the surface of the interlayer insulating film ILD1_2, arranged in a matrix-like two-dimensional pattern in the X and Y directions. Therefore, in the CMP process, the insulating material 103_2a acts as a pillar on the inside of the conductive material 102_2a, which can mitigate the disc-shaped deformation of the conductive material 102_2a.

[0164] Therefore, the contact resistance between conductive material 102_1a and conductive material 102_2a can be low and stable.

[0165] Furthermore, the third embodiment can also be combined with any of the first embodiment, the second embodiment, variation 1, and variation 2. That is, the solder pad P1_1a of the third embodiment can also be bonded to the solder pad P1_2a of any of the first embodiment, the second embodiment, variation 1, and variation 2.

[0166] Furthermore, the third embodiment can also be used for bonding between memory chips 40_1 and 40_2. That is, the third embodiment can also be applied to the solder pad P1_2b of memory chip 40_1 and the solder pad P2_1b of memory chip 40_2. As a result, dish-shaped deformation of solder pads P1_2b and P2_1b can be suppressed, and the bonding between memory chips 40_1 and 40_2 is stabilized with low resistance.

[0167] (Fourth implementation)

[0168] Figure 24This is a top view showing an example of the configuration of the solder pad P1_2a according to the fourth embodiment. In the fourth embodiment, when viewed from the Z direction, the conductive material 102_2a of the solder pad P1_2a extends in a direction inclined relative to the X and Y directions. The configuration of the solder pad P1_1a can be the same as any of the first to third embodiments, and variations 1 and 2. The distance between the closest point-like insulating materials in the X and Y directions in the solder pad P1_1a of the third embodiment is different from the distance between the closest point-like insulating materials in the X and Y directions in the case of the inclination as in the fourth embodiment. For example, when one of the insulating materials 103_2a is designated as the fourth insulating portion In4_2, a fifth insulating portion In5_2 that is closest to the fourth insulating portion In4_2 in the Y direction and a sixth insulating portion In6_2 that is closest to the fourth insulating portion In4_2 in the X direction will be formed. When viewed in the Y direction, the distance between the first insulating part In1_1 and the second insulating part In2_1 is closer than the distance between the fourth insulating part In4_2 and the fifth insulating part In5_2. When viewed in the X direction, the distance between the first insulating part In1_1 and the third insulating part In3_1 is closer than the distance between the fourth insulating part In4_2 and the sixth insulating part In6_2.

[0169] In the fourth embodiment, when bonding the array chip CH_A1 to the circuit chip CH_C1, the solder pads P1_1a and P1_2a are bonded in the bonding surface B_mc1 such that the extending directions of the conductive material 102_1a and the conductive material 102_2a intersect. Since the extending directions of the insulating material 103_1a and the insulating material 103_2a intersect, even if the solder pads P1_1a and P1_2a are offset to some extent in the X or Y direction, the contact area between the conductive materials 102_1a and 102_2a does not change significantly. Therefore, the fourth embodiment can stabilize the contact resistance relative to the offset of the solder pads P1_1a and P1_2a in the bonding surface B_mc1.

[0170] The other configurations of the fourth embodiment can be the same as the corresponding configurations of the first to third embodiments. Therefore, the fourth embodiment can also obtain the effects of any of the first to third embodiments.

[0171] (Fifth Embodiment) Figure 25 This is a cross-sectional view showing an example of the configuration of the region of the mating surface B_mc1 in the fifth embodiment. In the fifth embodiment, solder pads P1_1a and P1_2a formed by the variation 2 are used.

[0172] In the fifth embodiment, the through-hole contact V1_1 is disposed below the solder pad P1_1a and is electrically connected to the conductive material 102_1a. The through-hole contact V1_1 electrically connects the conductive material 102_1a to the wiring layer W1_1. Thus, the through-hole contact V1_1 and the conductive material 102_1a are integrally disposed in the entire formation area of ​​the solder pad P1_1a. As a result, the conductive material 102_1a of the solder pad P1_1a bulges slightly from the mating surface B_mc1 due to the volume expansion (thermal expansion) of the through-hole contact V1_1 and the conductive material 102_1a.

[0173] Similarly, regarding solder pad P1_2a, the through-hole contact V1_2 is located below solder pad P1_2a and is electrically connected to the conductive material 102_2a. The through-hole contact V1_2 electrically connects the conductive material 102_2a to the wiring layer W1_2. Thus, the through-hole contact V1_2 and the conductive material 102_2a are integrally formed in the entire formation area of ​​solder pad P1_2a. As a result, the conductive material 102_2a of solder pad P1_2a bulges slightly from the mating surface B_mc1 due to the volume expansion (thermal expansion) of the through-hole contact V1_2 and the conductive material 102_2a.

[0174] The solder pads P1_1a and P1_2a bulge out from the joint surface B_mc1, and the solder pads P1_1a and P1_2a in the joint surface B_mc1 are reliably bonded to each other. Thus, the solder pads P1_1a and P1_2a can be stably connected to each other with low resistance.

[0175] Several embodiments of the present invention have been described, but these embodiments are provided as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments or variations thereof are included in the scope or spirit of the invention, and likewise included in the invention as described in the claims and its equivalents.

Claims

1. A semiconductor device, characterized in that... have: First insulating layer; The first solder pad is exposed on the surface of the first insulating layer; The second insulating layer is bonded to the first insulating layer; The second solder pad is exposed on the surface of the second insulating layer and is bonded to the first solder pad; The first wiring layer is disposed on the back side opposite to the surface of the first insulation layer; as well as The first through-hole contact is electrically connected between the first wiring layer and the first solder pad; and When viewed from a first top view approximately perpendicular to the surface of the first insulating layer, inside the first pad, there is a first conductive material and a first insulating material with an etch rate lower than that of the first conductive material. The first insulating material is arranged in an island shape inside the first conductive material. In the first top view, the first through-hole contact is located over the entire formation area of ​​the first solder pad. In the first top view, the area of ​​the first through-hole contact is larger than the area of ​​the first conductive material.

2. The semiconductor device according to claim 1, characterized in that: In the first top view, the first insulating material has an elongated shape extending in the first direction on the surface of the first insulating layer.

3. The semiconductor device according to claim 1, characterized in that: In the first top view, the area of ​​the first insulating material of the first pad is smaller than the area of ​​the first conductive material.

4. The semiconductor device according to claim 2, characterized in that: In the first top view, the area of ​​the first insulating material of the first pad is smaller than the area of ​​the first conductive material.

5. The semiconductor device according to any one of claims 1 to 4, characterized in that: When viewed from a second top view approximately perpendicular to the surface of the second insulating layer, inside the second pad, there is a second conductive material and a second insulating material with an etch rate lower than that of the second conductive material, the second insulating material being arranged in an island shape inside the second conductive material.

6. The semiconductor device according to claim 5, characterized in that: In the second top view, the second insulating material has an elongated shape extending in the third direction on the surface of the second insulating layer.

7. The semiconductor device according to claim 1, characterized in that: In the first top view, the first conductive material has a mesh structure on the surface of the first insulating layer, including a first elongated shape extending in a first direction and a second elongated shape extending in a second direction intersecting the first direction.

8. The semiconductor device according to claim 5, characterized in that: In the second top view, the second conductive material has a mesh structure on the surface of the second insulating layer, including a third elongated shape extending in a third direction and a fourth elongated shape extending in a fourth direction intersecting the third direction.

9. The semiconductor device according to claim 6, characterized in that: In the second top view, the second conductive material has a mesh structure on the surface of the second insulating layer, including a third elongated shape extending in a third direction and a fourth elongated shape extending in a fourth direction intersecting the third direction.

10. The semiconductor device according to any one of claims 1 to 4, characterized in that... have: The storage cell array is covered by the first insulating layer; CMOS circuitry, covered by the second insulating layer; and The second wiring layer is electrically connected between the CMOS circuit and the second bonding pad; and The first wiring layer is electrically connected between the memory cell array and the first pad.

11. The semiconductor device according to any one of claims 1 to 4, characterized in that... have: The first chip includes a first memory cell array covered by the first insulating layer and a first CMOS circuit disposed below the first memory cell array; and The second chip includes a second memory cell array and a second CMOS circuit disposed below the second memory cell array and covered by the second insulating layer. The first and second chips are electrically connected using the first and second bonding pads.

12. The semiconductor device according to claim 1, characterized in that: The first conductive material is a metal. The first insulating material uses a nitride film or a carbide film.

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