Semiconductor structure

Abstract

The application provides a semiconductor structure, comprising: a multilayer metal layer and a substrate, the multilayer metal layer comprising a first layer metal layer, a second layer metal layer and a third layer metal layer; a plurality of virtual metal blocks and at least one signal line are arranged on the metal layer; the virtual metal blocks on the metal layer are staggered in a direction perpendicular to the substrate; a second distance between a projection of a target signal line on the substrate and a projection of a second virtual metal block on the substrate is greater than a first distance between the projection of the target signal line on the substrate and a projection of a first virtual metal block on the substrate; the target signal line is located on the first layer metal layer; a third distance between the projection of the target signal line on the substrate and a projection of a third virtual metal block on the substrate is greater than the first distance. The scheme can reduce the parasitic capacitance between the virtual metal blocks and the parasitic capacitance on the target signal line.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and more particularly to a semiconductor structure. Background Technology

[0002] Semiconductor integrated circuit devices include a metal layer on which patterned metal is deployed. Part of the metal on the metal layer is used to transmit signals, such as clock signals and control signals of transistors.

[0003] With the increasing integration density of semiconductor integrated circuit devices, especially in some complex integrated circuits, parasitic effects generated by patterned metals on the metal layer cause delays in signal transmission on the metal layer, leading to a decrease in the performance of semiconductor integrated circuits. How to reduce the impact of parasitic effects on patterned metals has become an urgent problem to be solved. Summary of the Invention

[0004] This application provides a semiconductor structure designed to reduce parasitic capacitance of signal lines and parasitic capacitance between virtual metal blocks in the semiconductor structure, and to ensure wiring uniformity of each metal layer in the semiconductor structure.

[0005] This application provides a semiconductor structure, including: a multilayer metal layer and a substrate, wherein the multilayer metal layer includes a first metal layer, a second metal layer and a third metal layer;

[0006] The metal layer has multiple virtual metal blocks and at least one signal line;

[0007] The virtual metal blocks on the metal layer are staggered relative to each other in a direction perpendicular to the substrate;

[0008] The second distance between the projection of the target signal line onto the substrate and the projection of the second virtual metal block onto the substrate is greater than the first distance between the projection of the target signal line onto the substrate and the projection of the first virtual metal block onto the substrate; the target signal line is located in the first metal layer;

[0009] The third distance between the projection of the target signal line onto the substrate and the projection of the third virtual metal block onto the substrate is greater than the first distance;

[0010] Among them, the first virtual metal block is the virtual metal block closest to the target signal line in the first metal layer, the second virtual metal block is the virtual metal block closest to the target signal line in the second metal layer, and the third virtual metal block is the virtual metal block closest to the target signal line in the third metal layer.

[0011] In one embodiment, the projections of virtual metal blocks on the substrate do not overlap.

[0012] In one embodiment, the virtual metal blocks on each metal layer are arranged in an array.

[0013] In one embodiment, the projection matrices of the virtual metal blocks on the first metal layer onto the substrate and the projection matrices of the virtual metal blocks on other metal layers onto the substrate are arranged to intersect each other;

[0014] Other metal layers are those other than the first metal layer.

[0015] In one embodiment, there is a projection of a virtual metal block on a third metal layer between the projections of the virtual metal block on the first metal layer.

[0016] In one embodiment, two adjacent virtual metal blocks on the first metal layer are adjacent virtual metal blocks located in the same row.

[0017] In one embodiment, the projections of two adjacent virtual metal blocks on the first metal layer and the projections of virtual metal blocks on the third metal layer are in contact with each other.

[0018] In one embodiment, there is a projection of a virtual metal block on a second metal layer between the projections of two adjacent virtual metal blocks on the third metal layer.

[0019] In one embodiment, two adjacent virtual metal blocks on the third metal layer are adjacent virtual metal blocks located in the same column.

[0020] In one embodiment, the projections of two adjacent virtual metal blocks on the third metal layer and the projections of virtual metal blocks on the second metal layer are in contact with each other.

[0021] In one embodiment, the third distance and the second distance are equal.

[0022] In one embodiment, the second metal layer is higher than the first metal layer, and the third metal layer is higher than the second metal layer.

[0023] In one embodiment, the target signal line is selected from at least one signal line according to the layout of at least one signal line.

[0024] In one embodiment, the projection of the virtual metal block onto the substrate is quadrilateral.

[0025] In one embodiment, the signal line is used to transmit a clock signal.

[0026] This application provides a semiconductor structure including a substrate and multiple metal layers. Signal lines and dummy metal blocks are disposed on the metal layers. By staggering the dummy metal blocks in each metal layer in a direction perpendicular to the substrate, the parasitic capacitance between the dummy metal blocks can be effectively reduced. Under the premise of ensuring that the dummy metal blocks in each metal layer are staggered in a direction perpendicular to the substrate, the distances from the dummy metal blocks on the second metal layer to the target signal line and the distances from the dummy metal blocks on the third metal layer to the target signal line are both greater than the distances from the dummy metal blocks on the first metal layer to the target signal line. This ensures the uniformity of wiring on the first metal layer and also reduces the parasitic capacitance between the target signal line and the dummy metal blocks on the second and third metal layers. Attached Figure Description

[0027] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0028] Figure 1 A front view of a semiconductor structure provided in an embodiment of this application;

[0029] Figure 2 This is a schematic diagram of the signal line layout provided in an embodiment of this application;

[0030] Figure 3 This is a schematic diagram of the fabrication of a metal layer in a semiconductor structure provided in an embodiment of this application;

[0031] Figure 4 This is a schematic diagram of the layout of signal lines and virtual metal blocks provided in an embodiment of this application;

[0032] Figure 5 This is a schematic diagram of the layout of a virtual metal block in a semiconductor structure provided in an embodiment of this application;

[0033] Figure 6 for Figure 5 A schematic diagram of the layout of the virtual metal block in the semiconductor structure provided in the embodiment shown;

[0034] Figure 7 A schematic diagram of the parasitic capacitance between a signal line and a virtual metal block provided in an embodiment of this application;

[0035] Figure 8 This is a schematic diagram showing the layout of virtual metal blocks in each metal layer according to an embodiment of this application.

[0036] The accompanying drawings illustrate specific embodiments of this application, which will be described in more detail below. These drawings and descriptions are not intended to limit the scope of the concept in any way, but rather to illustrate the concept of this application to those skilled in the art through reference to particular embodiments. Detailed Implementation

[0037] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0038] like Figure 1 As shown, the semiconductor structure includes a substrate 30, electronic components 20, and multiple metal layers 10. Electronic components 20, such as transistors, are disposed on the substrate 30. Multiple metal layers 10 are disposed above the electronic components 20, for example, metal layers M0, Mn, Mn+1, and Mn+2 with sequentially increasing heights, where n is a natural number; that is, metal layer Mn is higher than metal layer M0, metal layer Mn+1 is higher than metal layer Mn, and metal layer Mn+2 is higher than metal layer Mn+1. The metal layers are electrically connected through conductive plugs 40. Signal lines are arranged on some of the metal layers 10 to enable interconnection between the various electronic components and to connect the electronic components to ground pads or power pads.

[0039] Dry etching is typically used to fabricate signal lines for integrated circuits. A typical fabrication process includes the following steps: First, the layout pattern of the signal lines is drawn. Then, photolithography is used to transfer the layout pattern onto a semiconductor substrate, which is the semiconductor structure to be dry-etched. Next, dry etching is performed on the semiconductor structure to remove the metal or dielectric layers not covered by the photolithography medium, thus forming the desired semiconductor structure.

[0040] like Figure 2 As shown, the distribution of signal lines in each layer is typically non-uniform. Based on the distribution area of ​​the signal lines, each layer can be divided into a dense signal line region 103 and a sparse signal line region 104. Non-uniform distribution of metal lines can affect the fabrication process of semiconductor structures. For example... Figure 3 As shown, especially when the distance between two layers exceeds a certain value, when a dielectric layer 105 is covered on the current layer 106, the dielectric layer 105 will be disc-shaped in the sparse region 104 of the signal line, resulting in a significant difference in the dielectric layer thickness between the dense region 103 of the signal line and the sparse region 104 of the signal line.

[0041] Dry etching is a chemical or chemical-mechanical hybrid process whose etching rate is related to the density of components on the semiconductor substrate. Due to the uneven density of signal lines on the semiconductor substrate, the etching rate differs significantly between areas of high and low signal line density, causing etching difficulties; this is known as the loading effect.

[0042] Furthermore, another factor affecting the etching process is the thickness of the subsequently formed dielectric layer 105. Due to the varying density of signal lines on the semiconductor substrate, dish-shaped patterns can form in areas with sparse signal lines, making it difficult to detect the etching endpoint during the dielectric layer etching process. This can lead to over-etching or stopping etching before reaching the endpoint, thus affecting the yield rate in the semiconductor structure fabrication process.

[0043] like Figure 4 As shown, to overcome the problems caused by uneven signal lines, virtual metal blocks are typically placed in the sparse areas of each layer to make the density of the dense areas of signal lines the same as the density of the sparse areas. Unlike signal lines, virtual metal blocks do not transmit signals.

[0044] The virtual metal block can be grounded, connected to a power source, or floating. Because grounding or connecting the virtual metal block to a power source increases parasitic capacitance, it is typically floating. It should be noted that the connection state of the virtual metal block is not restricted here.

[0045] One embodiment of this application provides a semiconductor structure including a substrate 30 and multiple metal layers 10, wherein each metal layer is provided with signal lines, and virtual metal blocks are provided on metal layers where the signal lines are not uniformly distributed, so as to make the wiring on the metal layers uniform.

[0046] Let's take three adjacent metal layers, Mn, Mn+1, and Mn+2, as an example. Signal lines are deployed on all three metal layers, and the distribution of signal lines on the three metal layers is uneven. That is, each layer has areas with dense signal lines and areas with sparse signal lines.

[0047] Figure 5 and Figure 6 This is a top view of the same semiconductor structure. Figure 5 This is a layout diagram of the virtual metal blocks for metal layers Mn and Mn+1. Figure 6 The layout diagram shows the virtual metal blocks of metal layers Mn+1 and Mn+2.

[0048] like Figure 5 As shown, virtual metal blocks are deployed in an array on the metal layer Mn. Each virtual metal block on the metal layer Mn is deployed along a first direction, for example, from top to bottom.

[0049] Virtual metal blocks are deployed in an array on metal layer Mn+1. Each virtual metal block on metal layer Mn+1 is deployed along a second direction, which is different from the first direction; for example, the second direction is a left-to-right deployment. The projections of the virtual metal blocks on metal layer Mn onto the substrate partially overlap with the projections of the virtual metal blocks on metal layer Mn+1 onto the substrate.

[0050] like Figure 6 As shown, virtual metal blocks are deployed in an array on metal layer Mn+1. Each virtual metal block on metal layer Mn+1 is deployed along a second direction. Similarly, virtual metal blocks are deployed in an array on metal layer Mn+2. Each virtual metal block on metal layer Mn+2 is deployed along a first direction, and the projections of the virtual metal blocks on metal layer Mn and metal layer Mn+2 onto the substrate completely overlap.

[0051] The above arrangement can effectively compensate for the wiring density of metal layers Mn, Mn+1 and Mn+2, making the wiring of each metal layer more uniform.

[0052] However, Figure 5 and Figure 6 The semiconductor structure shown introduces relatively large parasitic capacitance into the signal line. For example... Figure 7 As shown, the parasitic capacitance C1 generated by signal line 102 and virtual metal block 101 on the same layer, the parasitic capacitance C2 generated by signal line 102 and virtual metal block 101 located directly above layer Mn+1, the parasitic capacitance C3 generated by signal line 102 and virtual metal block 101 located to the upper right of layer Mn+1, the parasitic capacitance C4 generated by signal line 102 and virtual metal block 101 located directly above layer Mn+2, and the parasitic capacitance C5 generated by signal line 102 and virtual metal block 101 located to the upper right of layer Mn+2.

[0053] It should also be noted that, in addition to the parasitic capacitance generated on the metal signal lines, parasitic capacitance also occurs between the virtual metal blocks. This parasitic capacitance is particularly large when the projections of the virtual metal blocks onto the substrate overlap. When the parasitic capacitance between the virtual metal blocks is large, charge easily accumulates on the virtual metal blocks during manufacturing, thus affecting the yield of semiconductor structure manufacturing.

[0054] like Figure 8 As shown, one embodiment of this application provides a semiconductor structure including multiple metal layers 10 and a substrate 30. Signal lines are disposed on each metal layer, and virtual metal blocks are deployed on the metal layers where the signal lines are unevenly distributed.

[0055] In this design, the virtual metal blocks on the metal layers are staggered in a direction perpendicular to the substrate. Specifically, the virtual metal blocks on all metal layers with deployed virtual metal blocks are staggered in this direction. For example, a semiconductor structure has L metal layers, with virtual metal blocks deployed on metal layers Mn to Mn+2. The virtual metal blocks on metal layer Mn are staggered from those on metal layer Mn+1, Mn and Mn+2, and Mn+1 and Mn+2, respectively. Here, n+2 ≤ L, and n and L are both positive integers. This staggering of the virtual metal blocks reduces the effective area for parasitic capacitance between them, thereby reducing the amount of charge collected on the virtual metal blocks during manufacturing and ultimately improving the yield of the semiconductor structure.

[0056] The multilayer metal structure includes a first metal layer, a second metal layer, and a third metal layer. The height relationship between the three metal layers can be arbitrary; that is, the first metal layer can be higher than the second metal layer, and the second metal layer can be higher than the third metal layer. Alternatively, the first metal layer can be lower than the second metal layer, and the second metal layer can be lower than the third metal layer. There are no restrictions here.

[0057] For example: the first metal layer is metal layer Mn, the second metal layer is metal layer Mn+1, and the third metal layer is metal layer Mn+2.

[0058] Select one signal line from at least one signal line located on the first metal layer as the target signal line 107, and mark the virtual metal block in the first metal layer that is closest to the target signal line 107 as the first virtual metal block 108. Mark the virtual metal block in the second metal layer that is closest to the target signal line 107 as the second virtual metal block 109, and mark the virtual metal block in the third metal layer that is closest to the target signal line 107 as the third virtual metal block 110.

[0059] It should be noted that when calculating the distance between each virtual metal block and the target signal line 107, the distance between the geometric center of the projection of the virtual metal block on the substrate and the geometric center of the projection of the target signal line 107 on the substrate can be calculated.

[0060] Specifically, the second distance between the projection of the target signal line onto the substrate and the projection of the second virtual metal block onto the substrate is greater than the first distance between the projection of the target signal line onto the substrate and the projection of the first virtual metal block onto the substrate, and the third distance between the projection of the target signal line onto the substrate and the projection of the third virtual metal block onto the substrate is greater than the first distance. Compared to the distance from the first virtual metal block to the target signal line, the distances from the second and third virtual metal blocks to the target signal line are greater, which can reduce the parasitic capacitance between the target signal line and the virtual metal blocks on the second and third metal layers, and also reduce the parasitic capacitance between the target signal line and the virtual metal blocks on the third metal layer. Furthermore, the distance between the first virtual metal block 108 and the target signal line 107 is closer, which can ensure the uniformity of wiring on the first metal layer.

[0061] In the above technical solution, by staggering the virtual metal blocks in each metal layer in the direction perpendicular to the substrate, the parasitic capacitance between the virtual metal blocks can be effectively reduced. Under the premise of ensuring that the virtual metal blocks in each metal layer are staggered in the direction perpendicular to the substrate, the virtual metal blocks on the second and third metal layers are farther away from the target signal line, while the virtual metal blocks on the first metal layer are closer to the target signal line. This ensures the uniformity of wiring on the first metal layer and also reduces the parasitic capacitance between the target signal line and the virtual metal blocks on the second and third metal layers, thereby improving the quality of the signal transmitted on the target signal line.

[0062] In one embodiment, the projections of virtual metal blocks on the substrate do not overlap; that is, the projections of virtual metal blocks on all metal layers in which virtual metal blocks are deployed do not overlap. This can further reduce the effective area of ​​parasitic capacitance between any two virtual metal blocks, thereby reducing the parasitic capacitance between any two virtual metal blocks.

[0063] In one embodiment, the virtual metal blocks on each metal layer are distributed in an array, which can improve the wiring uniformity on each metal layer, avoid the generation of dish-shaped metal layers when fabricating semiconductor structures, and improve the yield of semiconductor structures.

[0064] In one embodiment, the projection matrices of virtual metal blocks on the substrate on the first metal layer and the projection matrices of virtual metal blocks on the substrate on other metal layers are arranged to intersect each other, wherein the other metal layers are metal layers other than the first metal layer. That is, the projections of some or all of the virtual metal blocks on the substrate on the other metal layers are located between the projections of two virtual metal blocks on the first metal layer, or the projections of some or all of the virtual metal blocks on the first metal layer are located between the projections of two virtual metal blocks on the other metal layers. By setting it this way, the projections of virtual metal blocks on the substrate on each metal layer are ensured not to overlap, reducing parasitic capacitance between virtual metal blocks, and also making the wiring in each metal layer uniform, thereby improving the yield of the semiconductor structure.

[0065] In one embodiment, there is a projection of a virtual metal block on a third metal layer between the projections of the virtual metal blocks on the first metal layer. This ensures that the distance from the third virtual metal block on the third metal layer to the target signal line is greater than the distance from the first virtual metal block on the first metal layer to the target signal line, thereby reducing the parasitic capacitance between the target signal line and the virtual metal block on the third metal layer. This can further reduce the impact on the wiring uniformity of the first and third metal layers due to the staggered arrangement of the virtual metal blocks, making the wiring of the first and third metal layers more uniform.

[0066] In one embodiment, there is a projection of a virtual metal block on a third metal layer between the projections of adjacent virtual metal blocks in the same row on the first metal layer. (Continue to refer to...) Figure 8 The projections of adjacent virtual metal blocks in the same row on metal layer Mn are separated by the projection of a virtual metal block on metal layer Mn+2. This configuration fully utilizes the gap between two adjacent virtual metal blocks on the first metal layer, ensuring uniform wiring in each metal layer while maintaining staggered virtual metal blocks.

[0067] In one embodiment, the projections of two adjacent virtual metal blocks on the first metal layer and the projections of virtual metal blocks on the third metal layer are in contact with each other, and reference continues. Figure 8 The projections of adjacent virtual metal blocks in the same row on metal layer Mn and the projections of virtual metal blocks on metal layer Mn+2 are in contact with each other. By setting it up in this way, the density of virtual metal blocks on each metal layer can be increased, thereby effectively balancing the density of dense and sparse areas when there is a large difference between dense and sparse areas of signal lines, and ensuring the uniformity of wiring in each metal layer.

[0068] In one embodiment, the projections of two adjacent virtual metal blocks on the third metal layer are separated by the projection of a virtual metal block on the second metal layer. This ensures that the distance from the second virtual metal block on the second metal layer to the target signal line is greater than the distance from the first virtual metal block on the first metal layer to the target signal line, and also ensures that the distance from the third virtual metal block on the third metal layer to the target signal line is greater than the distance from the first virtual metal block on the first metal layer to the target signal line. This reduces the parasitic capacitance between the target signal line and the virtual metal blocks on the second and third metal layers. Furthermore, it reduces the impact of staggered virtual metal block placement on the uniformity of wiring across the first, second, and third metal layers, resulting in more uniform wiring from the first to the third metal layer.

[0069] In one embodiment, there is a projection of a virtual metal block on a second metal layer between the projections of adjacent virtual metal blocks in the same column on the third metal layer. (Continue to refer to...) Figure 8 The projections of adjacent virtual metal blocks in the same column on metal layer Mn+2 are separated by the projection of a virtual metal block on metal layer Mn+1. This configuration fully utilizes the gap between two adjacent virtual metal blocks on the third metal layer, ensuring uniform wiring in each metal layer while maintaining staggered virtual metal blocks.

[0070] In one embodiment, the projections of two adjacent virtual metal blocks on the third metal layer and the projections of virtual metal blocks on the second metal layer are in contact with each other, and reference continues. Figure 8 The projections of adjacent virtual metal blocks in the same column on metal layer Mn+2 and the projections of virtual metal blocks on metal layer Mn+1 are in contact with each other. By setting it up in this way, the density of virtual metal blocks on each metal layer can be increased, thereby effectively balancing the density of dense and sparse areas when there is a large difference between dense and sparse areas of the signal lines, and ensuring the uniformity of wiring in each metal layer.

[0071] In one embodiment, there is a projection of a virtual metal block on a third metal layer between the projections of two adjacent virtual metal blocks in the same row on the first metal layer, and a projection of a virtual metal block on a second metal layer between the projections of two adjacent virtual metal blocks in the same column on the third metal layer. The third distance between the projection of the target signal line on the substrate and the projection of the third virtual metal block on the substrate is equal to the second distance between the projection of the target signal line on the substrate and the projection of the second virtual metal block on the substrate. This reduces the parasitic capacitance between the target signal line and the virtual metal blocks on the second and third metal layers, and also makes the wiring from the first metal layer to the third metal layer more uniform.

[0072] In one embodiment, the second metal layer is higher than the first metal layer, and the third metal layer is higher than the second metal layer. A projection of a virtual metal block on the third metal layer is between the projections of two adjacent virtual metal blocks in the same row on the first metal layer, and a projection of a virtual metal block on the second metal layer is between the projections of two adjacent virtual metal blocks in the same column on the third metal layer. The parasitic capacitance between the virtual metal blocks on the first and second metal layers is larger than that between the virtual metal blocks on the first and third metal layers. By placing the projection of the virtual metal block on the third metal layer between the projections of two adjacent virtual metal blocks in the same row on the first metal layer, and placing the projection of the virtual metal block on the second metal layer between the projections of two adjacent virtual metal blocks in the same column on the third metal layer, the effective area for generating parasitic capacitance between the virtual metal blocks on the first and second metal layers is reduced, thereby reducing the parasitic capacitance between the virtual metal blocks on the first and second metal layers.

[0073] In one embodiment, the target signal line 107 is selected from at least one signal line based on the layout of at least one signal line. The target signal line 107 can be selected from the signal line dense area that is closest to the boundary of the signal line sparse area. It can also be selected by combining the distance to the boundary of the signal line sparse area and the routing direction of the signal line. It can also be selected by combining the distance to the boundary of the signal line sparse area, the routing direction of the signal line and the signal type transmitted by the signal line. There are no limitations here.

[0074] In one embodiment, the projection of the virtual metal block onto the substrate is quadrilateral. By setting it in this way, when the virtual metal blocks are arranged in an array, the space of the sparse signal line area can be fully utilized, thereby balancing the wiring density of the sparse signal line area and the dense signal line area, making the wiring on each metal layer uniform, and improving the yield of the semiconductor structure.

[0075] In one embodiment, the target signal line 107 is used to transmit a clock signal. The clock signal has high requirements for rising / falling edges. Using the signal line used to transmit the clock signal as the target signal line 107 can reduce the parasitic capacitance of the signal line used to transmit the clock signal and ensure that the rising / falling edges of the clock signal are relatively steep.

[0076] Another embodiment of this application provides a semiconductor structure, which includes a substrate, a first metal layer, a second metal layer, and a third metal layer. The first metal layer is the bottom metal layer, the second metal layer is higher than the first metal layer, and the third metal layer is higher than the second metal layer.

[0077] Signal lines are provided on all three metal layers, and multiple virtual metal blocks are arranged in an array on each of the three metal layers. The signal line on the first metal layer is selected as the target signal line. The first virtual metal block is located on the first metal layer, the second virtual metal block is located on the second metal layer, and the third virtual metal block is located on the third metal layer.

[0078] Between the projections of two adjacent virtual metal blocks in the same row on the first metal layer, there is a projection of a virtual metal block on the third metal layer; between the projections of two adjacent virtual metal blocks in the same column on the third metal layer, there is a projection of a virtual metal block on the second metal layer; and the third distance between the projection of the target signal line on the substrate and the projection of the third virtual metal block on the substrate is equal to the second distance between the projection of the target signal line on the substrate and the projection of the second virtual metal block on the substrate.

[0079] In the above technical solution, the layout allows the virtual metal blocks in the first to third metal layers to be staggered in the direction perpendicular to the substrate, effectively reducing parasitic capacitance between the virtual metal blocks. While ensuring the virtual metal blocks in each metal layer are staggered in the direction perpendicular to the substrate, the virtual metal blocks on the second and third metal layers are further away from the target signal line, while the virtual metal blocks on the first metal layer are closer to the target signal line. This ensures wiring uniformity on the target metal layer and also reduces parasitic capacitance between the target signal line and virtual metal blocks on other metal layers. Positioning the virtual metal blocks on the third metal layer between the virtual metal blocks on the first metal layer, and the virtual metal blocks on the second metal layer between the virtual metal blocks on the third metal layer, reduces the effective area of ​​parasitic capacitance between the virtual metal blocks on the first and second metal layers, thereby reducing parasitic capacitance.

[0080] Other embodiments of this application will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this application that follow the general principles of this application and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this application are indicated by the following claims.

[0081] It should be understood that this application is not limited to the precise structure described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this application is limited only by the appended claims.

Claims

1. A semiconductor structure, characterized in that, include: A multilayer metal layer and a substrate, wherein the multilayer metal layer includes a first metal layer, a second metal layer and a third metal layer; The metal layer is provided with multiple virtual metal blocks and at least one signal line; The virtual metal blocks on the metal layer are staggered and do not overlap in a direction perpendicular to the substrate; The second distance between the projection of the target signal line onto the substrate and the projection of the second virtual metal block onto the substrate is greater than the first distance between the projection of the target signal line onto the substrate and the projection of the first virtual metal block onto the substrate; the target signal line is located in the first metal layer; The third distance between the projection of the target signal line onto the substrate and the projection of the third virtual metal block onto the substrate is greater than the first distance; Wherein, the first virtual metal block is the virtual metal block in the first metal layer that is closest to the target signal line, the second virtual metal block is the virtual metal block in the second metal layer that is closest to the target signal line, and the third virtual metal block is the virtual metal block in the third metal layer that is closest to the target signal line; The virtual metal blocks on each metal layer are arranged in an array; The projection matrices of the virtual metal blocks on the first metal layer onto the substrate and the projection matrices of the virtual metal blocks on other metal layers onto the substrate are arranged to intersect each other; The other metal layers are metal layers other than the first metal layer.

2. The semiconductor structure according to claim 1, characterized in that, There is a projection of the virtual metal block on the third metal layer between the projections of the virtual metal block on the first metal layer.

3. The semiconductor structure according to claim 2, characterized in that, Two adjacent virtual metal blocks on the first metal layer are adjacent virtual metal blocks located in the same row.

4. The semiconductor structure according to claim 3, characterized in that, The projections of two adjacent virtual metal blocks on the first metal layer and the projection of a virtual metal block on the third metal layer are in contact with each other.

5. The semiconductor structure according to claim 1, characterized in that, Between the projections of two adjacent virtual metal blocks on the third metal layer, there is a projection of a virtual metal block on the second metal layer.

6. The semiconductor structure according to claim 5, characterized in that, The two adjacent virtual metal blocks on the third metal layer are adjacent virtual metal blocks located in the same column.

7. The semiconductor structure according to claim 6, characterized in that, The projections of two adjacent virtual metal blocks on the third metal layer and the projections of virtual metal blocks on the second metal layer are in contact with each other.

8. The semiconductor structure according to claim 7, characterized in that, The third distance is equal to the second distance.

9. The semiconductor structure according to any one of claims 1 to 8, characterized in that, The second metal layer is higher than the first metal layer, and the third metal layer is higher than the second metal layer.

10. The semiconductor structure according to any one of claims 1 to 8, characterized in that, The target signal line is selected from the at least one signal line according to the layout of the at least one signal line.

11. The semiconductor structure according to any one of claims 1 to 8, characterized in that, The projection of the virtual metal block onto the substrate is quadrilateral.

12. The semiconductor structure according to any one of claims 1 to 8, characterized in that, The signal line is used to transmit clock signals.

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