Fuse structure and method of manufacturing the same

Abstract

The application relates to a fuse structure and a manufacturing method thereof, wherein the fuse structure comprises a substrate, a fin located on the substrate and comprising a first fin area, and a gate stack structure arranged around the top and sidewall of the first fin area; the gate stack structure comprises a first gate stack and a second gate stack, the first gate stack covers the first fin area, the second gate stack covers the first gate stack, the first gate stack is used for receiving a first gate voltage, the second gate stack is used for receiving a second gate voltage, and the first gate voltage is greater than the second gate voltage. The application can improve the integration of the fuse circuit.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular to a fuse structure and its fabrication method. Background Technology

[0002] Fuse memory cells are widely used in integrated circuits for repair work, and their classic structure is a separate structure for the control gate and the fuse gate. However, due to design constraints between the two gate structures, this fuse structure suffers from excessive area. As the integration density of integrated circuits continues to increase, the disadvantage of excessive area will gradually become apparent. Summary of the Invention

[0003] Therefore, it is necessary to provide a fuse structure and its manufacturing method to address the problem of excessively large fuse structure area in existing technologies.

[0004] A fuse structure, comprising:

[0005] Substrate;

[0006] Fins, located on the substrate, include a first fin region;

[0007] A gate stack structure is disposed around the top and sidewalls of the first fin region;

[0008] The gate stack structure includes a first gate stack and a second gate stack. The first gate stack covers the first fin region, and the second gate stack covers the first gate stack. The first gate stack is used to receive a first gate voltage, and the second gate stack is used to receive a second gate voltage. The first gate voltage is greater than the second gate voltage.

[0009] In one embodiment, the fin further includes a second fin region located on both sides of the first fin region, and the second fin region located on both sides of the first fin region is provided with a source region and a drain region respectively.

[0010] In one embodiment,

[0011] The first gate stack includes a first gate dielectric layer and a fuse gate layer covering the first gate dielectric layer. The first gate dielectric layer covers the first fin region, and the fuse gate layer is used to receive a first gate voltage.

[0012] The second gate stack includes a second gate dielectric layer and a control gate layer covering the second gate dielectric layer, wherein the second gate dielectric layer at least partially covers the fuse gate layer, and the fuse gate layer is used to receive a second gate voltage.

[0013] In one embodiment, the thickness of the first gate dielectric layer is less than the thickness of the second gate dielectric layer.

[0014] In one embodiment, the first gate stack is connected to a first voltage supply terminal, the second gate stack is connected to a second voltage supply terminal, and the first voltage supply terminal and the second voltage supply terminal extend to opposite sides of the gate stack structure.

[0015] In one embodiment, the extension directions of the first voltage supply terminal and the second voltage supply terminal are parallel to the extension direction of the gate stack structure.

[0016] In one embodiment, the substrate is further provided with an isolation structure located on opposite sides of the fins and between the substrate and the gate stack structure.

[0017] A method for fabricating a fuse structure includes:

[0018] Provide substrate;

[0019] A fin is formed on the substrate, the fin including a first fin region;

[0020] A gate stack structure is formed around the top and sidewalls of the first fin region. The gate stack structure includes a first gate stack and a second gate stack. The first gate stack covers the first fin region, and the second gate stack covers the first gate stack. The first gate stack is used to receive a first gate voltage, and the second gate stack is used to receive a second gate voltage. The first gate voltage is greater than the second gate voltage.

[0021] In one embodiment, the fin further includes a second fin region located on both sides of the first fin region. After forming the gate stack structure surrounding the top and sidewalls of the first fin region, the method further includes:

[0022] Ion implantation is performed on the second fin regions on both sides of the first fin region to form source and drain regions.

[0023] In one embodiment, forming a gate stack structure on the top and sidewalls of the first fin region includes:

[0024] A first gate dielectric layer is formed on the surface of the first fin region;

[0025] A fuse gate layer is formed on the surface of the first gate dielectric layer, and the first gate dielectric layer and the fuse gate layer constitute the first gate stack;

[0026] A second gate dielectric layer is formed on at least a portion of the surface of the fuse gate layer;

[0027] A control gate layer is formed on the surface of the second gate dielectric layer, and the second gate dielectric layer and the fuse gate layer constitute the second gate stack.

[0028] In one embodiment, the thickness of the first gate dielectric layer is less than the thickness of the second gate dielectric layer.

[0029] In one embodiment, after forming the gate stack structure surrounding the top and sidewalls of the first fin region, the method further includes:

[0030] A first voltage power supply terminal is formed on one side of the gate stack structure to connect to the first gate stack.

[0031] On the other side of the gate stack structure, a second voltage supply terminal is formed to connect the second gate stack, and the second voltage supply terminal is disposed opposite to the first voltage supply terminal.

[0032] In one embodiment, the extension directions of the first voltage supply terminal and the second voltage supply terminal are parallel to the extension direction of the gate stack structure.

[0033] In one embodiment, forming fins on the substrate includes:

[0034] A patterned mask layer is formed on the substrate;

[0035] The substrate is patterned based on the patterned mask layer to form the fins.

[0036] In one embodiment, prior to forming the gate stack structure surrounding the top and sidewalls of the first fin region, the method further includes:

[0037] An isolation structure is formed on the opposite sides of the fin.

[0038] In the aforementioned fuse structure, the first gate stack and the second gate stack are stacked and merged into a single gate stack structure. Therefore, this embodiment can effectively reduce the area of ​​the fuse unit and greatly improve the integration of the fuse circuit. Simultaneously, the fin-type structure allows conductive channels to be formed on the top and sidewalls of the fins, resulting in a smaller area occupied by devices of the same communication length, thus enabling further miniaturization and saving more space. Attached Figure Description

[0039] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0040] Figure 1 This is a three-dimensional schematic diagram of the fuse structure provided in one embodiment;

[0041] Figure 2 This is a cross-sectional schematic diagram of the fuse structure provided in one embodiment;

[0042] Figure 3 This is a three-dimensional schematic diagram of the fuse structure provided in another embodiment;

[0043] Figure 4 A flowchart of a method for fabricating a fuse structure provided in one embodiment;

[0044] Figure 5 This is a flowchart of a method for fabricating a gate stack structure provided in one embodiment;

[0045] Figures 6 to 12 This is a three-dimensional structural diagram of the formation process of the fuse structure provided in one embodiment.

[0046] Explanation of reference numerals in the attached figures:

[0047] 100 - Substrate; 110 - Fin; 111 - Source region; - Drain region; 110a - First fin region; 110b - Second fin region; 200 - Gate stack structure; 210 - First gate stack; 211 - First gate dielectric layer; 212 - Fuse gate layer; 220 - Second gate stack; 221 - Second gate dielectric layer; 222 - Fuse gate layer; 300 - First voltage supply terminal; 400 - Second voltage supply terminal; 500 - Isolation structure. Detailed Implementation

[0048] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate preferred embodiments of the application. However, this application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0049] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0050] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Therefore, without departing from the teachings of this invention, the first element, component, region, layer, doping type, or portion discussed below may be referred to as a second element, component, region, layer, or portion.

[0051] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, the element or feature described as “below,” “under,” or “below” will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein will be interpreted accordingly.

[0052] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that when the terms “comprise” and / or “comprising” are used in this specification, the presence of the stated feature, integer, step, operation, element, and / or part is established, but the presence or addition of one or more other features, integers, steps, operations, elements, parts, and / or groups is not excluded. Meanwhile, when used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0053] Embodiments of the invention are described herein with reference to cross-sectional views that serve as schematic diagrams of ideal embodiments (and intermediate structures), thus allowing for the anticipation of variations in the illustrated shapes due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of the invention should not be limited to the specific shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing techniques. Consequently, the regions shown in the figures are substantially schematic, and their shapes do not represent the actual shapes of regions of the device, nor do they limit the scope of the invention.

[0054] Please see Figure 1 as well as Figure 2 The present invention provides a fuse structure, including a substrate 100, a fin 110 and a gate stack structure 200.

[0055] The substrate 100 includes, but is not limited to, a silicon substrate. The fin 110 is located on the substrate 100 and may be a component of the substrate 100 or a semiconductor structure formed on the substrate 100; this application does not limit this.

[0056] The fin 110 includes a first fin region 110a. The gate stack structure 200 is a gate structure consisting of multiple stacked film layers, which is disposed around the top and sidewalls of the first fin region 110a. Active regions and drain regions can be formed on both sides of the first fin region 110a.

[0057] Specifically, the gate stack structure 200 includes a first gate stack 210 and a second gate stack 220. The first gate stack 210 covers the first fin region 110a. The second gate stack 220 covers the first gate stack 210.

[0058] Meanwhile, the first gate stack 210 is used to receive the first gate voltage, and the second gate stack 220 is used to receive the second gate voltage, wherein the first gate voltage is greater than the second gate voltage.

[0059] When the first gate voltage is not applied to the first gate stack 210, the outer layer of the fin 110 wraps the gate structures on both sides (the first gate stack 210 and the second gate stack 220), so that when the second gate stack 220 receives the second gate voltage to form a conductive channel, the source-drain current is small.

[0060] When the first gate voltage is applied to the first gate stack 210, the first gate stack 210 is broken down due to its large voltage. At this time, when the outermost second gate stack 220 receives the second gate voltage and forms a conductive channel, the source-drain current increases.

[0061] Therefore, this embodiment can change the gate control capability by breaking down the first gate stack 210, thereby realizing the distinction between "0" and "1".

[0062] Specifically, in the application of the fuse structure, the different logic states "0" and "1" of the fuse structure can be read by controlling whether the first gate stack 210 is applied with a first gate voltage.

[0063] Furthermore, a reasonable second gate voltage can be set so that when the logic state of the fuse structure is read and the second gate stack 220 is applied, the conductive communication in the fin 110 is turned on, and then the "0" and "1" are read by the difference between the source and drain currents.

[0064] In this embodiment, the first gate stack 210 and the second gate stack 220 are stacked and merged into a single gate stack structure 200. Therefore, this embodiment can effectively reduce the area of ​​the fuse unit and greatly improve the integration of the fuse circuit. Simultaneously, the fin-type structure allows conductive communication to be formed on the top and sidewalls of the fins, resulting in a smaller area occupied by devices of the same communication length, thus enabling further miniaturization and saving more area.

[0065] In one embodiment, see Figure 1 The fin 110 also includes a second fin region 110b.

[0066] The second fin region 110b is located on both sides of the first fin region 110a. The second fin region 110b located on both sides of the first fin region 110a is provided with a source region and a drain region respectively.

[0067] Specifically, the source and drain regions can be formed by ion implantation into the second fin region 110b.

[0068] In other embodiments, the fin 110 may not include the second fin region 110b. In this case, the source region and the drain region can be formed by epitaxial growth on both sides of the first fin region 110a.

[0069] In one embodiment, see Figure 1 as well as Figure 2 The first gate stack 210 includes a first gate dielectric layer 211 and a fuse gate layer 212. The first gate dielectric layer 211 can be an insulating layer such as oxide, which covers the first fin region 110. The fuse gate layer 212 can be a conductive layer such as polysilicon, which covers the first gate dielectric layer 211 and is used to receive the first gate voltage.

[0070] When the fuse gate layer 212 receives the first gate voltage, the first gate dielectric layer 211 covered by it is broken down by the first gate voltage, thereby changing from an insulating state to a conductive state, which will increase the source and drain current.

[0071] The second gate stack 220 includes a second gate dielectric layer 221 and a control gate layer 222. The second gate dielectric layer 221 may be an insulating layer such as oxide, which at least partially covers the fuse gate layer 212. The control gate layer 222 may be a conductive layer such as polysilicon, which covers the second gate dielectric layer 221 and is used to receive a second gate voltage.

[0072] When the control gate layer 222 receives the second gate voltage, the conductive communication in the fin 110 is turned on.

[0073] It is understood that the materials of the first gate dielectric layer 211 and the second gate dielectric layer 221 may be the same or different, and this application does not impose any restrictions on this. The materials of the control gate layer 222 and the fuse gate layer 212 may be the same or different, and this application does not impose any restrictions on this.

[0074] Furthermore, in this embodiment, the thickness of the second gate dielectric layer 221 can be set to be greater than the thickness of the first gate dielectric layer 211.

[0075] Since the second gate dielectric layer 221 and the first gate dielectric layer 211 are located on opposite sides of the control gate layer 222, the second gate dielectric layer 221 will inevitably be affected when the control gate layer 222 receives the first gate voltage signal and breaks down the first gate dielectric layer 211.

[0076] In this embodiment, the thickness of the second gate dielectric layer 221 is set to be greater than the thickness of the first gate dielectric layer 211, thereby effectively reducing the impact on the second gate dielectric layer 221 when the first gate dielectric layer 211 is broken down.

[0077] As an example, the thickness of the first gate dielectric layer 211 can be set to 1.5nm to 2.5nm, and the thickness of the second gate dielectric layer 221 can be set to 4.5nm to 6nm. This ensures that the second gate dielectric layer 221 will not be damaged during the breakdown and melting process of the first gate dielectric layer 211, thereby ensuring product reliability. In this case, the range of the first gate voltage can be further set to 5V to 6V, and the range of the second gate voltage to 2V to 3V.

[0078] Of course, in other embodiments, the second gate dielectric layer 221 can also be protected in other ways. For example, the dielectric constant of the second gate dielectric layer 221 can be set to be greater than the dielectric constant of the first gate dielectric layer 211.

[0079] In one embodiment, see Figure 3 The first gate stack 210 is connected to the first voltage power supply terminal 300. The first voltage power supply terminal 300 is the structural terminal that receives the first gate voltage. Specifically, a fuse gate layer 212 can be provided to be connected to the first voltage power supply terminal 300.

[0080] The second gate stack 220 is connected to the second voltage supply terminal 400. The second voltage supply terminal 400 is the structural terminal that receives the second gate voltage. Specifically, the control gate layer 222 can be connected to the second voltage supply terminal 400.

[0081] Meanwhile, in this embodiment, the first voltage supply terminal 300 and the second voltage supply terminal 400 are arranged to extend to the opposite side of the gate stack structure 200, that is, the two are located on opposite sides of the gate stack structure 200, thereby effectively preventing signal coupling interference between the first voltage supply terminal 300 and the second voltage supply terminal 400.

[0082] In one embodiment, the extension directions of the first voltage supply terminal 300 and the second voltage supply terminal 400 are further configured to be parallel to the extension direction of the gate stack structure 200. In this case, the first voltage supply terminal 300 and the second voltage supply terminal 400 can be conveniently and effectively designed while ensuring the integrity of the gate stack structure 200.

[0083] In one embodiment, see Figure 1 as well as Figure 2 An isolation structure 500 is also provided on the substrate 100. The isolation structure 500 is located on opposite sides of the fin 110 and between the substrate 100 and the gate stack structure 200.

[0084] Multiple fins 110 can be provided on the substrate 100. At this time, by setting the isolation structure 500, each fin 110 can be effectively isolated, thereby forming multiple device regions.

[0085] In one embodiment, see Figure 4 A method for fabricating a fuse structure is provided, comprising:

[0086] Step S100, providing substrate 100, please refer to... Figure 6 ;

[0087] In step S200, fins 110 are formed on the substrate 100. The fins 110 include a first fin region 110a. (See also...) Figure 7 ;

[0088] Step S400: A gate stack structure 200 is formed around the top and sidewalls of the first fin region 110a. The gate stack structure 200 includes a first gate stack 210 and a second gate stack 220. The first gate stack 210 covers the first fin region 110a, and the second gate stack 220 covers the first gate stack 210. The first gate stack 210 is used to receive a first gate voltage, and the second gate stack 220 is used to receive a second gate voltage. The first gate voltage is greater than the second gate voltage. Please refer to [link to relevant documentation]. Figure 12 .

[0089] In this embodiment, the first gate stack 210 and the second gate stack 220 are stacked together to form a single gate stack structure 200. Therefore, this embodiment can effectively reduce the area of ​​the fuse unit and greatly improve the density of the fuse circuit. At the same time, the finned structure can further reduce the size and save more area.

[0090] In one embodiment, the fin 100 further includes a second fin region 110b. The second fin region 100b is located on both sides of the first fin region 110a.

[0091] At this point, after step S400, the following steps are also included:

[0092] Step S500: Ion implantation is performed on the second fin regions 110b on both sides of the first fin region 110a to form the source region and the drain region. Please refer to [link to relevant documentation]. Figure 1 .

[0093] The fins 110 between the source and drain regions form a channel region. The channel region is used to form a conductive channel and is located near the surface of the fins 110 close to the gate stack structure 200.

[0094] Of course, in other embodiments, the fin 100 may not have a second fin region 110b. In this case, after step S400, a source region and a drain region can be grown on both sides of a fin region 110a by means of epitaxial growth or the like.

[0095] In one embodiment, step S400 includes:

[0096] Step S410: A first gate dielectric layer 211 is formed on the surface of the first fin region 110a. Please refer to [link / reference]. Figure 9 ;

[0097] In step S420, a fuse gate layer 212 is formed on the surface of the first gate dielectric layer 211. The first gate dielectric layer 211 and the fuse gate layer 212 constitute a first gate stack 210. Please refer to [link to relevant documentation]. Figure 10 ;

[0098] Step S430: A second gate dielectric layer 221 is formed on at least a portion of the fuse gate layer 210 surface. (See also...) Figure 11 ;

[0099] In step S440, a control gate layer 222 is formed on the surface of the second gate dielectric layer 221. The second gate dielectric layer 221 and the fuse gate layer 222 constitute a second gate stack 220. Please refer to [link to relevant documentation]. Figure 12 .

[0100] In one embodiment, the thickness of the first gate dielectric layer 211 is less than the thickness of the second gate dielectric layer 221.

[0101] In one embodiment, after step S400, the method further includes:

[0102] In step S600, a first voltage supply terminal 300 connecting the first gate stack is formed on one side of the gate stack structure 200. (See also...) Figure 3 ;

[0103] In step S700, a second voltage supply terminal 400 is formed on the other side of the gate stack structure 200, connecting to the second gate stack. The second voltage supply terminal 400 is disposed opposite to the first voltage supply terminal 300. Please refer to [link to relevant documentation]. Figure 3 .

[0104] In one embodiment, the extending directions of the first voltage supply terminal 300 and the second voltage supply terminal 400 are parallel to the extending direction of the gate stack structure 200.

[0105] In one embodiment, step S200 includes:

[0106] Step S210: A patterned mask layer is formed on the substrate 100;

[0107] In step S220, the substrate 100 is patterned based on the patterned mask layer to form fins 110.

[0108] In step S210, specifically, a mask material layer may first be formed on the substrate 100. Then, a photoresist layer is formed on the mask material layer, and a patterned photoresist is formed through exposure and development. Then, the mask material layer is etched based on the patterned photoresist to form a patterned mask layer.

[0109] In step S220, the substrate 100 can be etched using an anisotropic etching method based on a patterned mask layer to form the fin 110.

[0110] Of course, the method of forming fin 110 is not limited to this. For example, fin 110 can be obtained by growing an epitaxial layer on substrate 100 and then patterning the epitaxial layer, etc.

[0111] In one embodiment, the method further includes the following steps prior to step S400:

[0112] In step S300, an isolation structure 500 is formed on both opposite sides of the fin 110. Please refer to [link / reference]. Figure 8 .

[0113] Specifically, an isolation material layer can be deposited first to cover the fins 110 and the substrate 100 using a chemical vapor deposition method. Then, chemical mechanical polishing can be performed based on the patterned mask layer formed in step S220 to planarize the isolation material layer and expose the patterned mask layer. Next, excess isolation material between the fins 110 is removed by high-selectivity wet etching, leaving the bottom isolation material layer as the isolation structure 500. Finally, the patterned mask layer is removed.

[0114] For specific limitations on the fabrication method and technical effects of the fuse structure, please refer to the limitations on the fuse structure method mentioned above, which will not be repeated here.

[0115] It should be understood that, although Figure 4 , Figure 5 The steps in the flowchart are shown sequentially as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order in which these steps are executed, and they can be performed in other orders. Figure 4 , Figure 5 At least some of the steps in the process may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but may be executed at different times. The execution order of these steps or stages is not necessarily sequential, but may be executed in turn or alternately with other steps or at least some of the steps or stages in other steps.

[0116] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0117] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A fuse structure, characterized in that, include: Substrate; Fins, located on the substrate, include a first fin region; A gate stack structure is disposed around the top of the first fin region and an opposite sidewall; The gate stack structure includes a first gate stack and a second gate stack. The first gate stack covers the first fin region, and the second gate stack covers the first gate stack. The first gate stack is used to receive a first gate voltage, and the second gate stack is used to receive a second gate voltage. The first gate voltage is greater than the second gate voltage.

2. The fuse structure according to claim 1, characterized in that, The fin also includes a second fin region, which is located on both sides of the first fin region that are not wound with a gate, and the second fin region located on both sides of the first fin region is respectively provided with a source region and a drain region.

3. The fuse structure according to claim 1, characterized in that, The first gate stack includes a first gate dielectric layer and a fuse gate layer covering the first gate dielectric layer. The first gate dielectric layer covers the first fin region, and the fuse gate layer is used to receive a first gate voltage. The second gate stack includes a second gate dielectric layer and a control gate layer covering the second gate dielectric layer, wherein the second gate dielectric layer at least partially covers the fuse gate layer, and the fuse gate layer is used to receive a second gate voltage.

4. The fuse structure according to claim 3, characterized in that, The thickness of the first gate dielectric layer is less than the thickness of the second gate dielectric layer.

5. The fuse structure according to claim 1, characterized in that, The first gate stack is connected to a first voltage supply terminal, and the second gate stack is connected to a second voltage supply terminal. The first voltage supply terminal and the second voltage supply terminal are located on opposite sides of the extension direction of the gate stack structure.

6. The fuse structure according to claim 5, characterized in that, The extension directions of the first voltage supply terminal and the second voltage supply terminal are parallel to the extension direction of the gate stack structure.

7. The fuse structure according to claim 1, characterized in that, The substrate is further provided with an isolation structure, and the substrate is provided with a plurality of fins, with the isolation structure located between adjacent fins.

8. A method for fabricating a fused wire structure, characterized in that, include: Provide substrate; A fin is formed on the substrate, the fin including a first fin region; A gate stack structure is formed around the top of the first fin region and an opposite sidewall. The gate stack structure includes a first gate stack and a second gate stack. The first gate stack covers the first fin region, and the second gate stack covers the first gate stack. The first gate stack is used to receive a first gate voltage, and the second gate stack is used to receive a second gate voltage. The first gate voltage is greater than the second gate voltage.

9. The method for manufacturing the fuse structure according to claim 8, characterized in that, The fin further includes a second fin region located on both sides of the first fin region that are not wound with gates. After forming the gate stack structure wound around the top of the first fin region and an opposite sidewall, the method further includes: Ion implantation is performed on the second fin regions on both sides of the first fin region to form source and drain regions.

10. The method for manufacturing the fuse structure according to claim 8, characterized in that, The formation of a gate stack structure on the top and sidewalls of the first fin region includes: A first gate dielectric layer is formed on the surface of the first fin region; A fuse gate layer is formed on the surface of the first gate dielectric layer, and the first gate dielectric layer and the fuse gate layer constitute the first gate stack; A second gate dielectric layer is formed on at least a portion of the surface of the fuse gate layer; A control gate layer is formed on the surface of the second gate dielectric layer, and the second gate dielectric layer and the fuse gate layer constitute the second gate stack.

11. The method for manufacturing the fuse structure according to claim 10, characterized in that, The thickness of the first gate dielectric layer is less than the thickness of the second gate dielectric layer.

12. The method for manufacturing the fuse structure according to claim 8, characterized in that, After forming the gate stack structure surrounding the top and sidewalls of the first fin region, the method further includes: A first voltage supply terminal is formed on one side of the extending direction of the gate stack structure to connect to the first gate stack. On the other side of the extending direction of the gate stack structure, a second voltage supply terminal is formed to connect the second gate stack, and the second voltage supply terminal is disposed opposite to the first voltage supply terminal.

13. The method for manufacturing the fuse structure according to claim 12, characterized in that, The extension directions of the first voltage supply terminal and the second voltage supply terminal are parallel to the extension direction of the gate stack structure.

14. The method for manufacturing the fuse structure according to claim 8, characterized in that, Forming fins on the substrate includes: A patterned mask layer is formed on the substrate; The substrate is patterned based on the patterned mask layer to form the fins.

15. The method for manufacturing the fuse structure according to claim 8, characterized in that, Before forming the gate stack structure surrounding the top of the first fin region and an opposite sidewall, the method further includes: The substrate has a plurality of fins, and an isolation structure is formed between adjacent fins.

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