Semiconductor structure and method for forming the same

Abstract

A semiconductor structure and a method for forming the same, the method comprising: providing a substrate, comprising a first device region for forming a first device and a second device region for forming a second device; forming a channel structure on the substrate in the first device region, forming a device fin on the substrate in the second device region, the channel structure comprising one or more channel stacks, the channel stack comprising a first sacrificial layer and a channel layer located on the first sacrificial layer, along the extension direction of the channel structure or the device fin, the channel structure and the device fin both comprising a channel region; removing the sacrificial layer in the channel region; after removing the sacrificial layer in the channel region, forming a gate structure, in the first device region, the gate structure surrounds the channel layer covering the channel region, in the second device region, the gate structure crosses the device fin and covers the sidewall and top of the device fin in the channel region. The present invention adopts a hybrid integration method to simultaneously meet the performance requirements of the first device and the second device, which is conducive to improving the working performance of the semiconductor structure.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular to a semiconductor structure and a method for forming the same. Background Art

[0002] With the rapid development of semiconductor manufacturing technology, semiconductor devices are moving towards higher component density and higher integration, and the semiconductor process nodes are decreasing in accordance with the development trend of Moore's Law.

[0003] Therefore, in order to better adapt to the requirements of device size reduction, semiconductor processes have gradually begun to transition from planar transistors to three-dimensional transistors with higher efficiency, such as FinFET and Gate-all-around (GAA) transistors. In FinFET, the gate surrounds the area where the channel is located from the top and both sides, and in GAA transistor, the gate surrounds the area where the channel is located from all sides. Compared with planar transistors, the gates of FinFET and GAA transistors have stronger control over the channel and can better suppress the short channel effect. Summary of the invention

[0004] The problem solved by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, so as to improve the performance of the semiconductor structure.

[0005] To solve the above problems, an embodiment of the present invention provides a semiconductor structure, comprising: a substrate, the substrate comprising a first device region for forming a first device and a second device region for forming a second device; a channel layer structure, suspended on the substrate in the first device region, the channel layer structure comprising one or more channel layers spaced apart; a device fin, protruding from the substrate in the second device region; a gate structure, located on the substrate, in the first device region, the gate structure spans the channel layer, in the second device region, the gate structure spans the device fin, the gate structure comprises a gate dielectric layer, and a gate electrode layer located on the gate dielectric layer, in the first device region, the gate dielectric layer surrounds and covers the channel layer, in the second device region, the gate dielectric layer covers part of the sidewalls and part of the top of the device fin; a source-drain doped layer, in the first device region, the source-drain doped layer is located on the substrate on both sides of the gate structure and contacts the end of the channel layer structure below the gate structure, in the second device region, the source-drain doped layer is located on the substrate on both sides of the gate structure and contacts the end of the device fin below the gate structure.

[0006] Correspondingly, an embodiment of the present invention also provides a method for forming a semiconductor structure, comprising: providing a substrate, the substrate comprising a first device region for forming a first device and a second device region for forming a second device; forming a channel structure on the substrate in the first device region, and forming a device fin on the substrate in the second device region, the channel structure comprising one or more channel stacks, the channel stack comprising a first sacrificial layer and a channel layer located on the first sacrificial layer, along the extension direction of the channel structure or the device fin, the channel structure and the device fin both comprise a channel region; removing the sacrificial layer in the channel region; after removing the sacrificial layer in the channel region, forming a gate structure, in the first device region, the gate structure surrounds the channel layer covering the channel region, and in the second device region, the gate structure spans the device fin and covers the sidewalls and top of the device fin in the channel region.

[0007] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:

[0008] An embodiment of the present invention provides a semiconductor structure, including a channel layer structure suspended on a substrate of the first device region, wherein the channel layer structure includes one or more channel layers spaced apart, and also includes a device fin protruding from the substrate of the second device region; the embodiment of the present invention adopts a hybrid integration approach to simultaneously meet the performance requirements of the first device and the second device, while reducing the probability of excess performance resulting from the unified use of a channel layer structure. For example, in an embodiment of the present invention, for a first device with higher performance requirements and a shorter channel length, the channel layer in the channel layer structure can be used as a channel, and for a second device with lower performance requirements and a longer channel length, the device fin can be used as a channel, which is beneficial to improving the working performance of the semiconductor structure.

[0009] In the formation method provided by the embodiment of the present invention, a channel structure is formed on the substrate of the first device area, and a device fin is formed on the substrate of the second device area; the embodiment of the present invention adopts a hybrid integration approach to simultaneously meet the performance requirements of the first device and the second device, while reducing the probability of excess performance resulting from the unified use of the channel structure. For example, for a first device with higher performance requirements and a shorter channel length, the channel layer in the channel structure can be used as a channel, and for a second device with lower performance requirements and a longer channel length, the device fin can be used as a channel, which is beneficial to improving the working performance of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 and Figure 2 is a schematic structural diagram of an embodiment of a semiconductor structure of the present invention;

[0011] Figures 3 to 18It is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention. DETAILED DESCRIPTION

[0012] In order to better adapt to the requirements of device size reduction, semiconductor technology has gradually begun to transition from planar transistors to three-dimensional transistors with higher efficiency, such as gate-all-around (GAA) transistors. In a gate-all-around transistor, the gate surrounds the area where the channel is located from all sides. The gate of a gate-all-around transistor has a stronger control ability over the channel and can better suppress the short channel effect.

[0013] However, it is difficult to apply all types of devices to all types of gate-all-around transistors. For example, when all-around gate transistors are applied to devices with longer channel sizes, the channel structure is prone to deformation. For devices with higher operating voltages, the use of all-around gate transistors is prone to overperformance.

[0014] In order to solve the technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate, the substrate comprising a first device region for forming a first device and a second device region for forming a second device; forming a channel structure on the substrate in the first device region, and forming a device fin on the substrate in the second device region, the channel structure comprising one or more channel stacks, the channel stack comprising a first sacrificial layer and a channel layer located on the first sacrificial layer, and along the extension direction of the channel structure or the device fin, the channel structure and the device fin both comprise a channel region; removing the first sacrificial layer in the channel region; after removing the first sacrificial layer in the channel region, forming a gate structure, in the first device region, the gate structure surrounds the channel layer covering the channel region, and in the second device region, the gate structure spans the device fin and covers the sidewalls and top of the device fin in the channel region.

[0015] In the formation method provided by the embodiment of the present invention, a channel structure is formed on the substrate of the first device area, and a device fin is formed on the substrate of the second device area; the embodiment of the present invention adopts a hybrid integration approach to simultaneously meet the performance requirements of the first device and the second device, while reducing the probability of excess performance resulting from the unified use of the channel structure. For example, for a first device with higher performance requirements and a shorter channel length, the channel layer in the channel structure can be used as a channel, and for a second device with lower performance requirements and a longer channel length, the device fin can be used as a channel, which is beneficial to improving the working performance of the semiconductor structure.

[0016] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0017] Figure 1 and Figure 2 is a schematic diagram of a semiconductor structure according to an embodiment of the present invention, wherein: Figure 1 is a cross-sectional view along the extension direction of the fin and the channel layer. Figure 2 It is a cross-sectional view in a direction perpendicular to the extending direction of the fin and the channel layer.

[0018] The semiconductor structure comprises: a substrate 11, wherein the substrate 11 comprises a first device region 101A for forming a first device and a second device region 101B for forming a second device; a channel layer structure 231, which is suspended on the substrate 11 in the first device region 101A, wherein the channel layer structure 231 comprises one or more channel layers 251 arranged at intervals; a device fin 311, which protrudes from the substrate 11 in the second device region 101B; a gate structure 431, which is located on the substrate 11, wherein the gate structure 431 surrounds and covers the channel layer 251 in the first device region 101A, and the gate structure 431 surrounds and covers the channel layer 251 in the first device region 101A. In the second device area 101B, the gate structure 431 spans across the device fin 311 and covers the sidewalls and top of the device fin 311; the source-drain doped layer 511, in the first device area 101A, the source-drain doped layer 511 is located on the substrate 11 on both sides of the gate structure 431 and contacts the end of the channel layer structure 231 below the gate structure 431; in the second device area 100B, the source-drain doped layer 511 is located on the substrate 11 on both sides of the gate structure 431 and contacts the end of the device fin 311 below the gate structure 431.

[0019] The embodiment of the present invention adopts a hybrid integration approach to simultaneously meet the performance requirements of the first device and the second device, while reducing the probability of excess performance due to the unified use of the channel layer structure 231. For example, for the first device with higher performance requirements and a smaller channel length, the channel layer 251 in the channel layer structure 231 can be used as the channel, and for the second device with lower performance requirements and a larger channel length, the device fin 311 can be used as the channel, which is beneficial to improving the working performance of the semiconductor structure.

[0020] The substrate 11 provides a process operation basis for the formation process of the semiconductor structure. In this embodiment, the semiconductor structure includes two types of fin field effect (FinFET) and gate-all-around (GAA) transistors.

[0021] In this embodiment, a hybrid integration method is adopted. Taking the semiconductor structure as a fin field effect transistor and a fully enclosed gate transistor as an example, the base 11 includes a substrate 101 and a bottom fin 171 protruding from the substrate 101. In the first device area 101A, the bottom fin 171 is located between the channel layer structure 231 and the substrate. In the second device area 101B, the bottom fin 171 is located between the device fin 311 and the substrate.

[0022] In this embodiment, the material of the substrate 101 is silicon. In other embodiments, the material of the substrate may also be one or more of germanium, silicon germanium, silicon carbide, gallium arsenide, and indium gallium, and the substrate may also be other types of substrates such as a silicon substrate on an insulator or a germanium substrate on an insulator. The material of the substrate may be a material suitable for process requirements or easy to integrate. As an example, the material of the bottom fin 171 is the same as that of the substrate 101. Specifically, the bottom fin 171 and the substrate 101 are an integral structure.

[0023] In this embodiment, the base 11 further includes an isolation layer 141 located on the substrate 101 where the bottom fin 171 is exposed. The isolation layer 141 is used to achieve insulation between different devices. For example, in a CMOS manufacturing process, an isolation layer is usually formed between an NMOS transistor and a PMOS transistor.

[0024] In this embodiment, the isolation layer 141 covers the sidewalls of the bottom fin 171. The isolation layer 141 is made of an insulating material. As an example, the isolation layer 141 is made of silicon oxide.

[0025] The substrate 11 includes a first device region 101A and a second device region 101B. In this embodiment, the channel length of the first device is shorter than the channel length of the second device.

[0026] If the channel length of the first device is short, the operating voltage of the first device is low and the performance requirement is high. If the channel layer structure 231 is located in the first device area 101A, the channel layer 251 in the channel layer structure 231 is used as the channel, which can meet the high performance requirement of the first device. Moreover, if the channel length of the first device is short, the length of the channel layer 251 is short, which reduces the probability of deformation of the channel layer 251 due to excessive length. If the channel length of the second device is long, the operating voltage of the second device is high and the performance requirement is low. If the device fin 311 is located in the second device area 101B, the device fin 311 is used as the channel, which is sufficient to meet the relatively low performance requirement of the second device. At the same time, it is beneficial to avoid the problem of excess performance caused by forming the channel layer structure 231 in the second device area 101B with low performance requirement.

[0027] Moreover, the channel layer structure 231 is obtained by removing the sacrificial layer between the channel layers. When the channel layer structure 231 is formed, since the channel length in the second device area 101B is longer and the channel length in the first device area 101A is shorter, when removing the sacrificial layer, it takes a longer time to remove the sacrificial layer in the second device area 101B, and a shorter time to remove the first device area 101A. This embodiment adopts a hybrid integration method, which reduces the probability of over-etching the channel layer 251 in the first device area 101A during the removal of the sacrificial layer, thereby improving the performance of the semiconductor structure.

[0028] In this embodiment, the first device is a core device, and the second device is an input-output (IO) device. The core device is used to realize the main functions of the integrated circuit, and the input-output device is used to provide corresponding input signals to the core device or output corresponding signals of the core device. The operating voltage of the input-output device is higher than the operating voltage of the core device. For example, the operating voltage of the core device is 0.4V to 1.2V, and the operating voltage of the input-output device is 1.0V to 3.5V.

[0029] The top, bottom and sidewalls of the channel layer 251 covered by the gate structure 431 are used as channels. In this embodiment, the channel layer structure 231 is suspended on the substrate 11 of the first device area 101A. The channel layer structure 231 includes one or more layers of spaced channel layers 251. The top, bottom and sidewalls of the channel layer 251 can all be used as channels. Therefore, the channel layer structure 231 increases the area used as a channel, thereby increasing the operating current of the semiconductor structure.

[0030] As an example, the number of the channel layers 251 is multiple layers, and the multiple channel layers 251 are stacked and spaced apart along the normal direction of the surface of the substrate 11 .

[0031] In this embodiment, the material of the channel layer 251 includes silicon, germanium, silicon germanium or III-V semiconductor materials. As an example, the material of the channel layer 251 is silicon. In other embodiments, the material of the channel layer is determined according to the type and performance of the transistor.

[0032] The device fin 311 protrudes from the substrate 11 in the second device region 101B to provide a channel of a fin field effect transistor.

[0033] In this embodiment, the device fin 311 is a semiconductor layer epitaxially grown on the substrate 11, so as to achieve the purpose of accurately controlling the height of the device fin 311. In other embodiments, the device fin 311 may also be an integral structure with the substrate.

[0034] In this embodiment, the material of the device fin 311 includes silicon, germanium, silicon germanium or III-V semiconductor material. As an example, the material of the device fin 311 is silicon. In other embodiments, the material of the device fin is determined according to the type and performance of the transistor.

[0035] In this embodiment, the heights of the channel layer structure 231 and the device fin 311 are equal. When the heights of the channel layer structure 231 and the device fin 311 are equal, it is beneficial to simplify the process flow during the formation of the channel layer structure 231 and the device fin 311, and it is beneficial to form the channel layer structure 231 and the device fin 311 in the first device area 101A and the second device area 101B at the same time.

[0036] The gate structure 431 is a device gate structure, which is used to control the opening or closing of the channel of the transistor.

[0037] In this embodiment, the gate structure 431 includes a gate dielectric layer 441 and a gate electrode layer 451 located on the gate dielectric layer 441 .

[0038] The gate dielectric layer 441 is used to isolate the gate electrode layer 451 from the channel layer 251, and the gate electrode layer 451 from the device fin 311. The material of the gate dielectric layer 441 includes one or more of HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, SiO2 and La2O3.

[0039] In this embodiment, the gate structure 431 is a metal gate structure, and accordingly, the gate dielectric layer 441 includes a high-k gate dielectric layer, and the material of the high-k gate dielectric layer includes a high-k dielectric material. Among them, the high-k dielectric material refers to a dielectric material whose relative dielectric constant is greater than the relative dielectric constant of silicon oxide. Specifically, the high-k dielectric material includes HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO or Al2O3, etc.

[0040] In this embodiment, the gate dielectric layer 441 may further include a gate oxide layer located between the high-k gate dielectric layer and the channel layer 251, and between the high-k gate dielectric layer and the device fin 311. As an example, the material of the gate oxide layer is silicon oxide.

[0041] Therefore, in this embodiment, in the first device region 101A, the gate electrode layer 451 spans the channel layer structure 231 and covers the gate dielectric layer 441 , and in the second device region 101B, the gate electrode layer 451 spans the device fin 311 and covers the gate dielectric layer 441 .

[0042] The gate electrode layer 451 is used to electrically lead out the metal gate structure. The material of the gate electrode layer 451 includes one or more of TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN and TiAlC.

[0043] As an example, the gate electrode layer 451 includes a work function layer (not shown) and an electrode layer (not shown) located on the work function layer. The work function layer is also used to adjust the threshold voltage of the transistor.

[0044] In other embodiments, according to process requirements, the gate structure may also be other types of device gate structures such as a polysilicon gate structure.

[0045] The source-drain doped layer 511 is used as a source region or a drain region of the formed fin field effect transistor. Specifically, the doping type of the source-drain doped layer 511 is the same as the channel conductivity type of the corresponding transistor.

[0046] In this embodiment, the semiconductor structure also includes: an inner sidewall 261, which is located between adjacent channel layers 251 and between the channel layer 251 and the substrate 11 in the longitudinal direction, and in the extension direction of the channel layer structure 231, the inner sidewall 261 is located between the gate structure 431 and the source-drain doping layer 511.

[0047] The inner sidewall 261 serves to isolate the gate structure 431 and the source-drain doped layer 511, so as to reduce the parasitic capacitance between the device gate structure 431 and the source-drain doped layer 511. The material of the inner sidewall 261 is an insulating material. The material of the inner sidewall 261 includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride oxide, silicon nitride oxide, boron nitride and boron carbonitride. In this embodiment, the material of the inner sidewall 261 is silicon nitride.

[0048] In this embodiment, the semiconductor structure further includes: a gate sidewall 411, which is located on the sidewall of the gate structure 431. The gate sidewall 411 is used to protect the sidewall of the gate structure 431. The gate sidewall can also be a stacked structure, and the material of the gate sidewall can also be one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride, silicon oxynitride, silicon oxynitride, boron nitride and boron carbonitride. In this embodiment, the gate sidewall 411 is a single-layer structure, and the material of the gate sidewall 411 is silicon nitride.

[0049] In this embodiment, the semiconductor structure further includes an interlayer dielectric layer 601 , which covers the sidewalls of the gate structure 431 , the channel layer structure 231 , and the device fin 311 , and exposes the top of the gate structure 431 .

[0050] The interlayer dielectric layer 601 is used to isolate adjacent devices and is made of insulating material, including one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon carbon oxynitride.

[0051] Correspondingly, an embodiment of the present invention further provides a method for forming a semiconductor structure.

[0052] Figures 3 to 18 It is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention.

[0053] refer to Figure 3 , providing a substrate 10, wherein the substrate 10 includes a first device region 100A for forming a first device and a second device region 100B for forming a second device.

[0054] The substrate 10 provides a process operation basis for the formation process of the semiconductor structure, wherein the semiconductor structure includes a fin field effect (FinFET) or a gate-all-around (GAA) transistor.

[0055] In this embodiment, a hybrid integration method is adopted, and taking the semiconductor structure as a fin field effect transistor and a fully surrounded gate transistor as an example, the base 10 also includes a substrate (not marked) and a bottom fin material layer (not marked) located on the substrate.

[0056] In this embodiment, the material of the substrate is silicon. In other embodiments, the material of the substrate may also be one or more of germanium, silicon germanium, silicon carbide, gallium arsenide and indium gallium, and the substrate may also be other types of substrates such as a silicon substrate on an insulator or a germanium substrate on an insulator. The material of the substrate may be a material suitable for process requirements or easy to integrate. As an example, the material of the bottom fin material layer is the same as that of the substrate. Specifically, the bottom fin material layer and the substrate are an integral structure.

[0057] The substrate 10 includes a first device region 100A and a second device region 100B. In this embodiment, the channel length of the first device is shorter than the channel length of the second device.

[0058] If the channel length of the first device is relatively short, the operating voltage of the first device is relatively low, and the performance requirement is relatively high. If a channel structure is subsequently formed in the first device area 100A, the channel layer in the channel structure is used as the channel, which can meet the higher performance requirement of the first device. Moreover, the channel length of the first device is relatively short, which reduces the probability of deformation of the channel layer due to excessive length. If the channel length of the second device is relatively long, the operating voltage of the second device is relatively high, and the performance requirement is relatively low. If a device fin is subsequently formed in the second device area 100B, the device fin is used as the channel, which is sufficient to meet the lower performance requirement of the second device. At the same time, it is beneficial to avoid the problem of excess performance caused by forming a channel structure in the second device area 100B with lower performance requirements.

[0059] Moreover, the subsequent formation of the channel layer is obtained by removing the sacrificial layer between the channel layers. Therefore, when the channel layer is formed, since the channel length in the second device area 100B is longer and the channel length in the first device area 100A is shorter, when removing the sacrificial layer, it takes a longer time to remove the sacrificial layer in the second device area 100B, and a shorter time to remove the first device area 100A. This embodiment adopts a hybrid integration method, which reduces the probability of over-etching the channel layer in the first device area 100A during the removal of the sacrificial layer, thereby improving the performance of the semiconductor structure.

[0060] In this embodiment, the first device is a core device, and the second device is an input-output device.

[0061] Combined with reference Figures 3 to 12 A channel structure 230 is formed on the substrate 10 of the first device region 100A, and a fin 310 is formed on the substrate 10 of the second device region 100B, wherein the channel structure 230 includes one or more channel stacks 270, and the channel stack 270 includes a first sacrificial layer 240 and a channel layer 250 located on the first sacrificial layer 240, and along the extension direction of the channel structure 230 or the device fin 310, the channel structure 230 and the device fin 310 both include a channel region 20c (such as Fig.12 shown).

[0062] The embodiment of the present invention adopts a hybrid integration approach to simultaneously meet the performance requirements of the first device and the second device, while reducing the probability of excess performance due to the unified use of the channel structure 230. For example, for the first device with higher performance requirements and a smaller channel length, the channel layer 250 in the channel structure 230 can be used as the channel, and for the second device with lower performance requirements and a larger channel length, the device fin 310 can be used as the channel, which is beneficial to improving the working performance of the semiconductor structure.

[0063] The top, bottom and sidewalls of the channel layer 250 that are subsequently covered by the gate structure are used as a channel. In this embodiment, the channel structure 230 is located on the substrate 10 of the first device area 100A. The channel structure 230 includes one or more layers of spaced channel layers 250. The top, bottom and sidewalls of the channel layer 250 can all be used as channels. Therefore, the channel structure 230 increases the area used as a channel, thereby increasing the operating current of the semiconductor structure.

[0064] As an example, the number of the channel layers 250 is multiple layers, and the multiple channel layers 250 are arranged along the normal direction of the surface of the substrate 10 and at intervals.

[0065] In this embodiment, the material of the channel layer 250 includes silicon, germanium, silicon germanium or III-V semiconductor materials. As an example, the material of the channel layer 250 is silicon. In other embodiments, the material of the channel layer is determined according to the type and performance of the transistor.

[0066] In this embodiment, the material of the channel layer 250 is silicon, and therefore, the material of the first sacrificial layer 240 is silicon germanium. Silicon germanium and silicon can form a large etching selectivity ratio, which is beneficial to the subsequent removal of the first sacrificial layer 240 and reduces damage to the channel layer 250. In other embodiments, a suitable material having an etching selectivity ratio with the channel layer can be selected according to the material of the channel layer, so as to reduce damage to the channel layer when the first sacrificial layer is removed later.

[0067] The device fin 310 protrudes from the substrate 10 in the second device region 100B to provide a channel of a fin field effect transistor.

[0068] In this embodiment, the device fin 310 is a semiconductor layer epitaxially grown on the substrate 10, so as to achieve the purpose of accurately controlling the height of the device fin 310. In other embodiments, the device fin 310 may also be an integral structure with the substrate.

[0069] In this embodiment, the material of the device fin 310 is silicon. In other embodiments, the material of the device fin may also be one or more of germanium, silicon germanium or III-V group semiconductor materials.

[0070] In this embodiment, the heights of the channel structure 230 and the device fin 310 are equal, which is beneficial to simplify the process flow during the formation of the channel structure 230 and the device fin 310, and is beneficial to simultaneously form the channel structure 230 and the device fin 310 in the first device area 100A and the second device area 100B, respectively.

[0071] refer to Fig.12 , Fig.12It is a top view of any channel structure 230 and device fin 310. Along the extension direction of the channel structure 230 and the device fin 310, the channel structure 230 and the device fin 310 both include a channel region 20c, and the channel layer 250 of the channel region 20c and the device fin 310 are used as the channel of the transistor.

[0072] Specifically, in conjunction with reference Figures 3 to 8 The steps of forming a channel structure 230 on the substrate 10 of the first device area 100A and forming a device fin 310 on the substrate 10 of the second device area 100B include: forming a channel structure material layer 200 (such as Figure 5 As shown), the channel structure material layer 200 includes one or more channel material stacks 280 (as shown Figure 5 As shown), the channel material stack 280 includes a first sacrificial material layer 210 (as shown Figure 5 ) and a channel material layer 220 (as shown) located on the first sacrificial material layer 210 Figure 5 shown).

[0073] The channel structure material layer 200 is used to form a channel structure 230. In this embodiment, the channel structure material layer 200 is used to form multiple channel structures 230 in multiple regions at the same time, simplifying the process flow and improving the process efficiency. Among them, the channel material stack 280 is used to form the channel stack 270, the first sacrificial material layer 210 is used to form the first sacrificial layer 240, and the channel material layer 220 is used to form the channel layer 250.

[0074] The material of the channel material layer 220 includes silicon, germanium, silicon germanium or Group III-V semiconductor material, which is used to directly form the channel layer 250 . The material of the first sacrificial material layer 210 includes silicon germanium, which is used to directly form the first sacrificial layer 240 .

[0075] In this embodiment, an epitaxial growth process is used to form the channel structure material layer 200. The epitaxial growth process can better control the process parameters, the process controllability is high, and it is easy to obtain a more accurate film thickness size, and the epitaxial growth process is easy to form a film layer with less impurities, so that the quality of the channel structure material layer 200 is high. Moreover, the material of the first sacrificial material layer 210 is silicon germanium, and the material of the channel material layer 220 is silicon. Then, the epitaxial growth process can be used to grow the first sacrificial material layer 210 on the channel material layer 220, and the channel material layer 220 on the first sacrificial material layer 210, so that the channel structure material layer 200 is formed in the same process.

[0076] In this embodiment, the forming method further includes: forming a device fin material layer 300 on the substrate 10 in the second device region 100B.

[0077] The device fin material layer 300 is used to form a device fin 310 . In this embodiment, the device fin material layer 300 is used to form multiple device fins 310 in multiple regions at the same time, which simplifies the process flow, improves the process efficiency, and saves the process cost.

[0078] The device fin material layer 300 is made of silicon and is used to directly form the device fin 310 .

[0079] In this embodiment, an epitaxial growth process is used to form the device fin material layer 300. The epitaxial growth process can better control process parameters, has high process controllability, and is easy to obtain a more accurate film thickness size. The epitaxial growth process is easy to form a film layer with less impurities, so that the device fin material layer 300 has a higher quality.

[0080] The following reference Figures 3 to 8 , the steps of forming the channel structure material layer 200 and the device fin material layer 300 are described in detail.

[0081] Combined with reference Figure 3 and Figure 4 , a first mask layer 110 is formed on the substrate 10 of the second device region 100B, and the first mask layer 110 also covers a portion of the substrate 10 at the junction of the second device region 100B and the first device region 100A.

[0082] Subsequently, a first material layer is formed on the substrate 10 exposed by the first mask layer 110, wherein when the first mask layer 110 is located in the second device area 100B, the first material layer is the channel structure material layer 200, and when the first mask layer 110 is located in the first device area 100A, the first material layer is the device fin material layer 300, and the first mask layer 110 serves as a mask for the subsequent formation of the first material layer.

[0083] In this embodiment, taking the first material layer as the channel structure material layer 200 as an example, the first mask layer 110 allows the channel structure material layer 200 to grow in the vertical direction. Moreover, compared with the solution of first forming the channel structure material layer on the substrate of the first device region and the second device region and then removing the channel structure material layer located in the second device region, this solution does not need to perform an etching process to form the channel structure material layer 200, so that the sidewall quality of the formed channel structure material layer 200 is high. At the same time, the first mask layer 110 exposes the substrate 10 of the first device region 100A or the second device region 100B, preparing for the subsequent formation of the second material layer. Wherein, when the first material layer is the channel structure material layer 200, the second material layer is the device fin material layer 300, and when the first material layer is the device fin material layer 300, the second material layer is the channel structure material layer 200.

[0084] refer to Figure 3 The step of forming the first mask layer 110 includes: forming a mask material layer 150 on the substrate, wherein the mask material layer 150 covers the substrate 10 of the first device area 100A and the second device area 100B.

[0085] The mask material layer 150 is used to form the first mask layer 110. In this embodiment, the material of the mask material layer 150 includes a dielectric material, and the dielectric material includes silicon oxide.

[0086] The first mask layer 110 formed by the mask material layer 150 also needs to isolate the channel structure material layer 200 and the device fin material layer 300 , so the material of the mask material layer 150 includes a dielectric material. Meanwhile, the silicon oxide has a good isolation effect.

[0087] refer to Figure 4 , remove part of the mask material layer 150 of the first device area 100A, retain part of the mask material layer 150 located in the second device area 100B and at the junction of the second device area 100B and the first device area 100A, and form a first mask layer 110 exposing the substrate 10 of the first device area 100A.

[0088] refer to Figure 5 , a first material layer (not shown) is formed on the substrate 10 exposed by the first mask layer 110 , and the first material layer is the channel structure material layer 200 .

[0089] The formation of the first material layer is a preparation for the subsequent formation of the channel structure 230 or the device fin 310 .

[0090] refer to Figure 6, forming a second mask layer 160 covering the first material layer and the first mask layer 110 .

[0091] The second mask layer 160 is used to protect the top of the first material layer and is used for subsequently forming a third mask layer.

[0092] In this embodiment, the material of the second mask layer 160 includes a dielectric material, and the dielectric material includes silicon oxide.

[0093] The second mask layer 160 is also used to enhance the isolation effect between the channel structure material layer 200 and the device fin material layer 300. Therefore, the material of the second mask layer 160 includes a dielectric material, and the silicon oxide has a good isolation effect. At the same time, the second mask layer 160 uses the same material as the first mask material layer 150, which is conducive to simplifying the subsequent process flow of removing the first mask layer 110 and the third mask layer, thereby saving process costs.

[0094] refer to Figure 7 , remove part of the second mask layer 160 and part of the first mask layer 110 on the side of the first material layer, and retain the remaining first mask layer 110 located at the junction of the second device area 100B and the first device area 100A, and the remaining second mask layer 160 covering the top of the first material layer as the third mask layer 120.

[0095] The third mask layer 120 serves as an isolation structure between the first material layer and the subsequently formed second material layer. The third mask layer 120 is also used to protect the top of the first material layer, reduce the contamination of the first material layer during the subsequent formation of the second material layer, and prevent subsequent epitaxial growth on the first material layer. The third mask layer 120 exposes the substrate 10 of the second device area 100B or the first device area 100A to prepare for the formation of the second material layer.

[0096] refer to Figure 8 , a second material layer (not shown) is formed on the substrate 10 exposed by the third mask layer 120 , and the second material layer is the device fin material layer 300 .

[0097] The second material layer is formed to prepare for forming the device fin 310 or the channel structure 230 .

[0098] It should be noted that since the formation of the channel structure material layer 200 is relatively complicated than the formation of the device fin material layer 300, and the channel structure 230 formed by the channel structure material layer 200 is used for the first device area 100A with higher performance requirements, the formation quality requirements of the channel structure material layer 200 are relatively higher. Therefore, in this embodiment, the channel structure material layer 200 is formed first, and then the device fin material layer 300 is formed. That is to say, the first material layer is the channel structure material layer 200, and the second material layer is the device fin material layer 300, thereby reducing the probability of contamination of the first device area 100A by the formation of the device fin material layer 300.

[0099] In this embodiment, by forming the first mask layer 110, the second mask layer 160 and the third mask layer 120, only the epitaxial process is used in the process of forming the channel structure material layer 200 and the device fin material layer 300, without undergoing an additional etching step, which is conducive to improving the quality of the channel structure material layer 200 and the device fin material layer 300. In addition, the first mask layer 110 blocks the lateral growth of the channel structure material layer 200 and the device fin material layer 300, so that the channel structure material layer 200 and the device fin material layer 300 grow vertically, with good directionality.

[0100] In this embodiment, the channel structure material layer 200 is formed first and the device fin material layer 300 is formed later. In other embodiments, the device fin material layer may be formed first and the channel structure material layer may be formed later. Accordingly, a first mask layer is formed on the substrate of the first device region; the first material layer is the device fin material layer, and the second material layer is the channel structure material layer.

[0101] Combined with reference Fig. 9 and Fig.10 Before patterning the channel structure material layer 200 and the device fin material layer 300 , the formation method further includes: removing the third mask layer 120 located on the top of the first material layer.

[0102] The third mask layer 120 located on the top of the first material layer is removed to expose the top of the channel structure material layer 200 and the device fin material layer 300 , in preparation for patterning the channel structure material layer 200 and the device fin material layer 300 .

[0103] refer to Fig. 9 The step of removing the third mask layer 120 located on the top of the first material layer includes: forming a second sacrificial layer 130 covering the third mask layer 120 and the second material layer.

[0104] The second sacrificial layer 130 is used to protect the top of the second material layer during the process of removing the third mask layer 120 .

[0105] In this embodiment, the material of the second sacrificial layer 130 includes a dielectric material, and the dielectric material includes silicon oxide.

[0106] The material of the second sacrificial layer 130 includes a dielectric material, which enhances the isolation effect between the channel structure material layer 200 and the device fin material layer 300 , and the silicon oxide has a good isolation effect.

[0107] In this embodiment, the materials of the second sacrificial layer 130, the second mask layer 160 and the first mask layer 110 are the same. Therefore, in the process of removing part of the second mask layer 160 and part of the first mask layer 110 on the side of the first material layer, it is beneficial to remove part of the second mask layer 160 and part of the first mask layer 110 together. In the subsequent process of removing the third mask layer 120 and the second sacrificial layer 130, it is beneficial to remove the third mask layer 120 and the second sacrificial layer 130 together, thereby simplifying the process flow and saving process costs.

[0108] refer to Fig.10 The third mask layer 120 and the second sacrificial layer 130 are planarized to remove the third mask layer 120 and the second sacrificial layer 130 that are higher than the top of the channel structure material layer 200 and the top of the device fin material layer 300 .

[0109] The third mask layer 120 and the second sacrificial layer 130 that are higher than the top of the channel structure material layer 200 and the top of the device fin material layer 300 are removed by planarization treatment, which is beneficial to improving the planarity of the top of the channel structure material layer 200 and the top of the device fin material layer 300 .

[0110] In this embodiment, a chemical mechanical polishing process is used for planarization treatment. The process operation is simple and is conducive to achieving a higher flatness of the top of the channel structure material layer 200 and the top of the device fin material layer 300 .

[0111] refer to Fig.11 In the same step, the channel structure material layer 200 and the device fin material layer 300 are patterned, the channel structure material layer 200 is patterned into a channel structure 230 , and the device fin material layer 300 is patterned into a device fin 310 .

[0112] In the same step, the channel structure material layer 200 and the device fin material layer 300 are patterned, which simplifies the process flow, improves the process efficiency, and saves the process cost.

[0113] In this embodiment, a dry etching process (for example, an anisotropic dry etching process) is used to pattern the channel structure material layer 200 and the device fin material layer 300. The dry etching process has the characteristics of anisotropic etching. Therefore, by selecting a dry etching process, it is beneficial to reduce damage to the substrate 10. At the same time, the dry etching is more directional, which is beneficial to improve the side wall morphology quality and dimensional accuracy of the channel structure 230 and the device fin 310.

[0114] In this embodiment, during the process of patterning the channel structure material layer 200 and the device fin material layer 300 , the remaining third mask layer 120 located at the junction of the second device region 100B and the first device region 100A is removed.

[0115] The remaining second mask layer 130 located at the junction of the second device region 100B and the first device region 100A is removed to provide a process basis for the subsequent formation of a dummy gate structure.

[0116] In this embodiment, during the process of patterning the channel structure material layer 200 and the device fin material layer 300 , the bottom device fin material layer is also patterned to form the bottom device fin 170 .

[0117] In this embodiment, the bottom device fin 170 and the substrate are an integrated structure.

[0118] In this embodiment, after forming the bottom device fin 170 and before subsequently forming the dummy gate structure, the method further includes: forming an isolation layer 140 on the substrate, wherein the isolation layer 140 covers the sidewalls of the bottom device fin.

[0119] The isolation layer 140 is used to achieve insulation between different devices. For example, in a CMOS manufacturing process, an isolation layer 140 is usually formed between an NMOS transistor and a PMOS transistor. The material of the isolation layer 140 is an insulating material. As an example, the material of the isolation layer 140 is silicon oxide.

[0120] Combined with reference Figures 13 to 17 , removing the first sacrificial layer 240 in the channel region 20c.

[0121] The first sacrificial layer 240 of the channel region 20 c is removed to achieve the suspended arrangement of the channel layer 250 , which is also used to provide a space position for forming a gate structure.

[0122] In this embodiment, an isotropic etching process is used to remove the first sacrificial layer 240. The isotropic etching process has relatively low cost, simple operation steps, and can achieve a large etching selectivity, which is beneficial to reduce damage to the channel layer 250 during the process of removing the first sacrificial layer 240.

[0123] refer to Fig.13 , after forming a channel structure 230 on the substrate 10 of the first device area 100A, and forming a device fin 310 on the substrate 100 of the second device area 100B, and before removing the first sacrificial layer 240 of the channel area, it also includes: forming a dummy gate structure 400 on the substrate 10, the dummy gate structure 400 spanning the channel structure 230 and the device fin 310 respectively, and covering the sidewalls and top of the channel structure 230 in the channel area, and the sidewalls and top of the device fin 310 in the channel area.

[0124] The dummy gate structure 400 is formed to occupy a space for the subsequent formation of a gate structure.

[0125] Specifically, the dummy gate structure 400 is a stacked structure, including a dummy gate oxide layer (not shown) and a dummy gate layer (not shown) covering the dummy gate oxide layer. As an example, the dummy gate oxide layer is made of silicon oxide, and the dummy gate layer is made of polysilicon.

[0126] refer to Fig.14 , Fig.14 It is a cross-sectional view along the extension direction of the channel structure 230 and the device fin 310 and perpendicular to the substrate 10. After forming the pseudo gate structure 400 and before subsequently forming the interlayer dielectric layer, the formation method also includes: forming a gate sidewall 410 on the sidewall of the pseudo gate structure 400.

[0127] It should be noted that Fig.14 FIG. 2 shows a schematic diagram of a channel structure 230 in a first device region 100A and a device fin 310 in a second device region 100B. However, the channel structure 230 and the device fin 310 are not necessarily adjacent to each other.

[0128] The gate sidewall 410 is used to subsequently protect the sidewall of the gate structure. The gate sidewall 410 can be a single-layer structure or a stacked structure, and the material of the gate sidewall 410 includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride oxide, silicon nitride oxide, boron nitride and boron carbonitride. In this embodiment, the gate sidewall 410 is a single-layer structure, and the material of the gate sidewall 410 is silicon nitride.

[0129] refer to Fig.15 , Fig.15 is based on Fig.14 , after forming the pseudo gate structure 400 and before subsequently forming the interlayer dielectric layer, it also includes: removing the channel structure 230 on both sides of the pseudo gate structure 400 in the first device area 100A, and the device fins 310 on both sides of the pseudo gate structure 400 in the second device area 100B.

[0130] The channel structure 230 on both sides of the dummy gate structure 400 in the first device region 100A and the device fins 310 on both sides of the dummy gate structure 400 in the second device region 100B are removed to provide space for the subsequent formation of source and drain doping layers.

[0131] Continue to refer Fig.15 After removing the channel structure 230 on both sides of the pseudo gate structure 400 in the first device area 100A and the device fins 310 on both sides of the pseudo gate structure 400 in the second device area 100B, in the first device area 100A, on both sides of the pseudo gate structure 400, the exposed first sacrificial layer 240 of the channel structure 230 is laterally etched to form a groove (not shown).

[0132] The groove is formed to provide a space for the subsequent formation of the inner side wall.

[0133] In this embodiment, an inner sidewall 260 is formed in the groove. The inner sidewall 260 subsequently serves to isolate the gate structure and the source-drain doping layer to reduce the parasitic capacitance between the device gate structure and the source-drain doping layer. The material of the inner sidewall 260 is an insulating material. In this embodiment, the material of the inner sidewall 260 includes silicon nitride.

[0134] refer to Fig.16 After forming the inner sidewall 260, a source-drain doped layer 510 is formed on the substrate 10 on both sides of the dummy gate structure 400. In the first device area 100A, the source-drain doped layer 510 is in contact with the channel layer 250 below the dummy gate structure 400. In the second device area 100B, the source-drain doped layer 510 is in contact with the device fin 310 below the dummy gate structure 400.

[0135] The source-drain doped layer 510 is used as a source region or a drain region of the formed transistor. Specifically, the doping type of the source-drain doped layer 510 is the same as the channel conductivity type of the corresponding transistor.

[0136] Continue to refer Fig.16 After the dummy gate structure 400 is formed, an interlayer dielectric layer 600 is formed on the substrate at the side of the dummy gate structure 400 , and the interlayer dielectric layer 600 exposes the top of the dummy gate structure 400 .

[0137] The interlayer dielectric layer 600 is used to isolate adjacent devices, and is also used to provide a process basis for the subsequent removal of the dummy gate structure 400 to form a gate opening. The material of the interlayer dielectric layer 600 is an insulating material, including one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon carbon oxynitride.

[0138] refer to Fig.17, the dummy gate structure 400 is removed, and a gate opening 420 is formed in the interlayer dielectric layer 600 , wherein the gate opening 420 exposes the first sacrificial layer 240 .

[0139] The gate opening provides a space for subsequently forming a gate structure. The gate opening 420 exposes the first sacrificial layer 240 to prepare for removing the first sacrificial layer 240 .

[0140] Continue to refer Fig.17 , removing the first sacrificial layer 240 exposed by the gate opening 420 to provide a space for forming a gate structure.

[0141] refer to Fig.18 After removing the first sacrificial layer 240 of the channel region 20c, a gate structure 430 is formed. In the first device region 100A, the gate structure 430 surrounds the channel layer 250 covering the channel region 20c. In the second device region 100B, the gate structure 430 spans the device fin 310 and covers the sidewalls and top of the device fin 310 of the channel region 20c.

[0142] The gate structure 430 is a device gate structure used to control the opening or closing of the channel of the transistor.

[0143] In this embodiment, the gate structure 430 includes a gate dielectric layer 440 and a gate electrode layer 450 located on the gate dielectric layer 440 .

[0144] The gate dielectric layer 440 is used to isolate the gate electrode layer 450 from the channel layer 250, and the gate electrode layer 450 from the device fin 310. The material of the gate dielectric layer 440 includes one or more of HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, SiO2 and La2O3.

[0145] In this embodiment, the gate structure 430 is a metal gate structure, and accordingly, the gate dielectric layer 440 includes a high-k gate dielectric layer, and the material of the high-k gate dielectric layer includes a high-k dielectric material. Among them, the high-k dielectric material refers to a dielectric material whose relative dielectric constant is greater than the relative dielectric constant of silicon oxide. Specifically, the high-k dielectric material includes HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO or Al2O3, etc.

[0146] In this embodiment, the gate dielectric layer 440 may further include a gate oxide layer located between the high-k gate dielectric layer and the channel layer 250, and between the high-k gate dielectric layer and the device fin 310. As an example, the material of the gate oxide layer is silicon oxide.

[0147] Therefore, in this embodiment, in the first device region 100A, the gate electrode layer 450 spans the channel layer structure 231 and covers the gate dielectric layer 440 , and in the second device region 100B, the gate electrode layer 450 spans the device fin 310 and covers the gate dielectric layer 440 .

[0148] The gate electrode layer 450 is used to electrically lead out the metal gate structure. The material of the gate electrode layer 450 is one or more of TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN and TiAlC.

[0149] As an example, the gate electrode layer 450 includes a work function layer (not shown) and an electrode layer (not shown) located on the work function layer. The work function layer is also used to adjust the threshold voltage of the transistor.

[0150] In other embodiments, according to process requirements, the gate structure may also be other types of device gate structures such as a polysilicon gate structure.

[0151] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate, the substrate comprising a first device region for forming a first device and a second device region for forming a second device; Forming a channel structure on the substrate of the first device region, and forming a device fin on the substrate of the second device region, wherein the channel structure includes one or more channel stacks, and the channel stack includes a first sacrificial layer and a channel layer located on the first sacrificial layer, and along the extension direction of the channel structure or the device fin, the channel structure and the device fin both include a channel region; removing the first sacrificial layer in the channel region; After removing the first sacrificial layer in the channel region, a gate structure is formed, wherein in the first device region, the gate structure surrounds the channel layer covering the channel region, and in the second device region, the gate structure spans the device fin and covers the sidewall and top of the device fin in the channel region; The steps of forming a channel structure on the substrate of the first device region and forming a device fin on the substrate of the second device region include: forming a channel structure material layer on the substrate of the first device region, the channel structure material layer including one or more channel material stacks, the channel material stacks including a first sacrificial material layer and a channel material layer located on the first sacrificial material layer; forming a device fin material layer on the substrate in the second device region; The step of forming the channel structure material layer and the device fin material layer includes: forming a first mask layer on the substrate of the first device region or the second device region, wherein the first mask layer also covers a portion of the substrate at the junction of the second device region and the first device region; forming a first material layer on the substrate exposed by the first mask layer, wherein when the first mask layer is located in the second device region, the first material layer is the channel structure material layer, and when the first mask layer is located in the first device region, the first material layer is the device fin material layer; forming a second mask layer covering the first material layer and the first mask layer; removing part of the second mask layer and part of the first mask layer on the side of the first material layer, and retaining the remaining first mask layer located at the junction of the second device area and the first device area, and the remaining second mask layer covering the top of the first material layer as a third mask layer; A second material layer is formed on the substrate exposed by the third mask layer, and when the first material layer is the channel structure material layer, the second material layer is the device fin material layer, and when the first material layer is the device fin material layer, the second material layer is the channel structure material layer.

2. The method for forming a semiconductor structure according to claim 1, wherein The step of forming the channel structure and the device fin includes: in the same step, patterning the channel structure material layer and the device fin material layer, patterning the channel structure material layer into the channel structure, and patterning the device fin material layer into the device fin.

3. The method for forming a semiconductor structure according to claim 1, wherein: Before patterning the channel structure material layer and the device fin material layer, the forming method further includes: removing the third mask layer located on the top of the first material layer; In the process of patterning the channel structure material layer and the device fin material layer, the remaining third mask layer located at the junction of the second device region and the first device region is removed.

4. The method for forming a semiconductor structure according to claim 1, wherein: The step of forming the first mask layer includes: forming a mask material layer on the substrate, the mask material layer covering the substrate of the first device region and the second device region; Removing a portion of the mask material layer in the first device area, retaining the mask material layer in the second device area and a portion of the mask material layer at the junction of the second device area and the first device area, to form a first mask layer exposing the substrate of the first device area; Alternatively, a portion of the mask material layer in the second device area is removed, and the mask material layer in the first device area and a portion of the mask material layer at the junction of the second device area and the first device area are retained to form a first mask layer exposing the substrate of the second device area.

5. The method for forming a semiconductor structure according to claim 3, wherein: The step of removing the third mask layer located on top of the first material layer includes: forming a second sacrificial layer covering the third mask layer and the second material layer; The third mask layer and the second sacrificial layer are planarized to remove the third mask layer and the second sacrificial layer that are higher than the top of the channel structure material layer and the top of the device fin material layer.

6. The method for forming a semiconductor structure according to claim 1, wherein: After forming a channel structure on the substrate of the first device region and forming a device fin on the substrate of the second device region, and before removing the first sacrificial layer of the channel region, the method further includes: forming a dummy gate structure on the substrate, the dummy gate structure respectively spanning the channel structure and the device fin, and covering the sidewall and top of the channel structure in the channel region, and the sidewall and top of the device fin in the channel region; After forming the dummy gate structure, forming an interlayer dielectric layer on the substrate at the side of the dummy gate structure, wherein the interlayer dielectric layer exposes the top of the dummy gate structure; removing the dummy gate structure, and forming a gate opening in the interlayer dielectric layer, wherein the gate opening exposes the first sacrificial layer; In the step of forming the gate structure, the gate structure is formed in the gate opening.

7. The method for forming a semiconductor structure according to claim 6, wherein: In the step of providing a substrate, the substrate further comprises a substrate and a bottom fin material layer located on the substrate; In the process of patterning the channel structure material layer and the device fin material layer, the bottom fin material layer is also patterned to form a bottom fin; After forming the bottom fin and before forming the dummy gate structure, the method further includes: forming an isolation layer on the substrate, wherein the isolation layer covers the sidewall of the bottom fin.

8. The method for forming a semiconductor structure according to claim 6, wherein: After forming the dummy gate structure and before forming the interlayer dielectric layer, the method further includes: removing the channel structure on both sides of the dummy gate structure in the first device region and the device fins on both sides of the dummy gate structure in the second device region; After removing the channel structure on both sides of the dummy gate structure in the first device region and the device fins on both sides of the dummy gate structure in the second device region, in the first device region, the first sacrificial layer of the exposed channel structure is laterally etched on both sides of the dummy gate structure to form a groove; forming an inner side wall in the groove; After forming the inner sidewall, a source-drain doped layer is formed on the substrate on both sides of the dummy gate structure. In the first device area, the source-drain doped layer is in contact with the end of the channel layer below the dummy gate structure. In the second device area, the source-drain doped layer is in contact with the device fin below the dummy gate structure.

9. The method for forming a semiconductor structure according to claim 1, wherein: The channel structure material layer is formed by an epitaxial growth process, and the device fin material layer is formed by an epitaxial growth process.

10. The method for forming a semiconductor structure according to claim 1, wherein: In the step of forming the channel structure material layer and the device fin material layer, the channel structure material layer and the device fin material layer have the same height.

11. The method for forming a semiconductor structure according to claim 5, wherein: The second sacrificial layer, the second mask layer and the mask material layer are all made of dielectric materials, and the second sacrificial layer, the second mask layer and the mask material layer are made of the same material.

12. A semiconductor structure formed by the forming method according to any one of claims 1 to 11, characterized in that: include A substrate, the substrate comprising a first device region for forming a first device and a second device region for forming a second device; A channel layer structure, suspended on the substrate of the first device region, the channel layer structure comprising one or more channel layers spaced apart; A device fin protrudes from the base of the second device region; A gate structure is located on the substrate, wherein in the first device region, the gate structure crosses the channel layer, and in the second device region, the gate structure crosses the device fin, the gate structure comprises a gate dielectric layer and a gate electrode layer located on the gate dielectric layer, in the first device region, the gate dielectric layer surrounds and covers the channel layer, and in the second device region, the gate dielectric layer covers part of the sidewall and part of the top of the device fin; Source-drain doped layers, wherein in the first device region, the source-drain doped layers are located on the substrate at both sides of the gate structure and contact the end of the channel layer structure below the gate structure, and in the second device region, the source-drain doped layers are located on the substrate at both sides of the gate structure and contact the end of the device fin below the gate structure; A channel length of the first device is smaller than a channel length of the second device.

13. The semiconductor structure according to claim 12, wherein: The channel layer structure and the device fin have the same height.

14. The semiconductor structure according to claim 12, wherein: The base comprises: a substrate and a bottom fin protruding from the substrate; In the first device region, the channel structure is suspended on the bottom fin; In the second device region, the device fin is located on the bottom fin; The semiconductor structure further includes an isolation layer located on the substrate and covering a sidewall of the bottom fin.

15. The semiconductor structure according to claim 12, wherein: The semiconductor structure further includes an inner sidewall, which is located between adjacent channel layers and between the channel layer and the substrate in the longitudinal direction, and in the extension direction of the channel layer structure, the inner sidewall is located between the gate structure and the source-drain doping layer.

16. The semiconductor structure according to claim 12, wherein: The first device is a core device, and the second device is an input-output device.

17. The semiconductor structure according to claim 12, wherein: The material of the channel layer includes silicon, germanium, silicon germanium or III-V semiconductor material; the material of the device fin includes silicon, germanium, silicon germanium or III-V semiconductor material.

18. The semiconductor structure according to claim 12, wherein: The material of the gate dielectric layer includes one or more of HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, SiO2 and La2O3, and the material of the gate electrode layer includes one or more of TiN, TaN, Ta, Ti, TiAl, W, AL, TiSiN and TiAlC.

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