Microelectronic devices including memory cell structures, and related methods and electronic systems

Abstract

The present application relates to microelectronic devices including memory cell structures and related methods and electronic systems. A microelectronic device includes memory cell structures extending from a base material. At least one memory cell structure of the memory cell structures includes a central portion in contact with a digit line, extending from the base material and including opposing arcuate surfaces, a terminal portion in contact with a storage node contact on a side of the central portion, and an additional terminal portion in contact with an additional storage node contact on an opposite side of the central portion. Related microelectronic devices, electronic systems, and methods are also described.

Description

[0001] Priority requirements

[0002] This application claims the filing date benefit of U.S. Patent Application No. 17 / 323,516, entitled “Microelectronic Devices Including Memory Cell Structures, and Relatted Methods and Electronic Systems,” filed May 18, 2021. Technical Field

[0003] In various embodiments, this disclosure generally relates to the field of microelectronic device design and fabrication. More specifically, this disclosure relates to methods of forming microelectronic devices including memory device structures, and to related microelectronic devices and electronic systems. Background Technology

[0004] Semiconductor device designers typically aim to increase the integration or density of features within a semiconductor device by reducing the size of individual features and by decreasing the spacing between adjacent features. Furthermore, semiconductor device designers often seek architectures that are not only compact but also offer performance advantages and simplify the design process.

[0005] A relatively common type of semiconductor device is the memory device. A memory device can comprise a memory array having several memory cells arranged in a grid pattern. One type of memory cell is Dynamic Random Access Memory (DRAM). In its simplest design configuration, a DRAM cell contains an access device, such as a transistor, and a storage device, such as a capacitor. Modern applications of memory devices utilize large numbers of DRAM cells arranged in arrays of rows and columns. DRAM cells can be electrically accessed via digital lines and word lines arranged along the rows and columns of the array.

[0006] The decreasing size and spacing of memory device features creates an increasing demand for methods used to form these features. For example, one limiting factor in the continued shrinking of memory devices is the unintentional shorting between contacts associated with the various components of a DRAM cell. As used herein, "contact" refers to a connection that facilitates a conductive path between at least two structures. For instance, in a DRAM device presenting a dual-cell memory structure, digital line contacts are provided between digital lines and access devices (e.g., transistors) formed in or over a substrate, and memory node contacts are formed between access devices and memory nodes (e.g., capacitors) capable of storing charge. As the size of memory device (e.g., DRAM device) features decreases, the packing density of the associated contacts increases, leading to an increased likelihood of unintentional shorting between various components, which can adversely affect memory device performance. In some instances, digital line contacts can unintentionally contact memory node contacts, electrically shorting the digital line to the memory node and causing a failure of the memory cell associated with the memory node. Summary of the Invention

[0007] In some embodiments, a microelectronic device includes a memory cell structure extending from a substrate material, at least one of the memory cell structures including: a central portion that contacts a digital line contact, extends from the substrate material and includes an opposing arcuate surface; an end portion that contacts a storage node contact on a side of the central portion; and another end portion that contacts an additional storage node contact on an opposite side of the central portion.

[0008] In other embodiments, a microelectronic device includes memory cell structures, each of which includes a semiconducting pillar structure extending from a substrate material. At least one memory cell structure of the memory cell structure includes: a first end portion and a second end portion, each of the first end portion and the second end portion individually including at least one arcuate surface; a central portion located between the first end portion and the second end portion, the central portion including a substantially parallel surface extending between the first end portion and the second end portion, at least one surface of the substantially parallel surface being connected to the at least one arcuate surface of the first end portion; a memory node contact contacting the first end portion; and a digital line contact contacting the central portion.

[0009] In another embodiment, a method of forming a microelectronic device includes: forming lines of a material comprising at least some nonlinear surfaces by extreme ultraviolet lithography; forming spacers on the lines of the material; removing the lines of the material; forming a mask over the spacers; removing a portion of the spacers through the mask to form isolation structures, each isolation structure including a central portion between a first end portion and a second end portion; and transferring a pattern of the isolation structures onto a semiconductive material.

[0010] In another embodiment, a method of forming a microelectronic device includes: forming a pattern of a first structure in a hard mask material by extreme ultraviolet lithography; forming a first spacer on the first structure; forming a pattern of a second structure in the hard mask material; forming a second spacer on the second structure; forming a material in a region between the first spacer and the second spacer to form a pattern of a third structure; removing the first spacer and the second spacer; and removing portions of a semiconductive material exposed beneath the hard mask material through the first structure, the second structure, and the third structure to form a pattern of the first structure, the second structure, and the third structure in the semiconductive material.

[0011] In an additional embodiment, a method of forming a microelectronic device includes: forming a pattern of a first structure in a hard mask material; forming a pattern of a second structure offset from the first structure in the hard mask material; and forming a pattern of a third structure laterally offset from the first and second structures in the hard mask material, the third structure having substantially the same size and shape as the first and second structures.

[0012] In another additional embodiment, an electronic system includes: an input device; an output device; a processor device operatively coupled to the input device and the output device; and a memory device operatively coupled to the processor device and including at least one microelectronic device. The at least one microelectronic device includes memory cell structures spaced apart from each other. The at least one memory cell structure includes: a central portion between two end portions, each of the end portions being oriented at an angle relative to the central portion; and a digital line electrically connected to the central portion, the surface of the digital line being oriented at an angle relative to the surface of the central portion. Attached Figure Description

[0013] Figures 1A to 1S A simplified partial perspective view illustrating a method for forming a microelectronic device structure according to an embodiment of the present disclosure. Figure 1A , Figure 1C , Figure 1E , Figure 1G , Figure 1I and Figures 1K to 1N ), Simplified top view ( Figure 1B , Figure 1D , Figure 1F , Figure 1H , Figure 1J and Figure 10 ), and simplified partial cross-sectional views ( Figures 1P to 1S );

[0014] Figures 2A to 2J A simplified partial perspective view illustrating a method for forming a microelectronic device structure according to an additional embodiment of the present disclosure. Figure 2A , Figure 2C and Figures 2E to 2H ) and simplified top view ( Figure 2B , Figure 2D , Figure 2I and Figure 2J );

[0015] Figures 3A to 3E A simplified partial perspective view illustrating a method for forming a microelectronic device structure according to an additional embodiment of the present disclosure. Figures 3A to 3D ) and simplified top view ( Figure 3E );

[0016] Figures 4A to 4D A simplified top view illustrating a method of forming a microelectronic device according to yet another embodiment of the present disclosure;

[0017] Figure 5 A simplified top view is shown for illustrating a microelectronic device according to an embodiment of the present disclosure.

[0018] Figure 6 A block diagram of an electronic system according to an embodiment of the present disclosure; and

[0019] Figure 7 This is a block diagram of a processor-based system according to an embodiment of the present disclosure. Detailed Implementation

[0020] The illustrations contained herein are not intended to be actual views of any particular system, microelectronic structure, microelectronic device, or its integrated circuit, but are merely idealized representations for describing the embodiments herein. Elements and features shared between the figures may retain the same numerical designations, but for ease of the following description, the reference numerals begin with the designation of the figure on which the element is introduced or most fully describes.

[0021] The following description provides specific details, such as material type, material thickness, and processing conditions, to provide a full description of the embodiments described herein. However, those skilled in the art will understand that the embodiments disclosed herein can be practiced without these specific details. In fact, the embodiments can be practiced in conjunction with conventional manufacturing techniques used in the semiconductor industry. Furthermore, the descriptions provided herein do not form a complete process flow for manufacturing microelectronic devices (e.g., memory devices, such as DRAM memory devices, 3D NAND flash memory devices) or a complete microelectronic device. The structures described below do not form a complete microelectronic device. Only those process actions and structures necessary for understanding the embodiments described herein are described in detail below. Additional actions to form a complete microelectronic device from said structures can be performed using conventional manufacturing techniques.

[0022] The materials described herein can be formed using conventional techniques, including but not limited to spin coating, blanket coating, chemical vapor deposition (CVD), atomic layer deposition (ALD), plasma-enhanced ALD, physical vapor deposition (PVD), plasma-enhanced chemical vapor deposition (PECVD), or low-pressure chemical vapor deposition (LPCVD). Alternatively, the materials can be grown in situ. Depending on the specific material to be formed, the technique used for depositing or growing the material can be selected by those skilled in the art. Unless the context otherwise indicates, material removal can be achieved by any suitable technique including but not limited to etching, planarization (e.g., chemical-mechanical planarization), or other known methods.

[0023] As used herein, the term “configuration” refers to the size, shape, material composition, material distribution, orientation, and arrangement of one or more of at least one structure and at least one device in order to facilitate the operation of one or more of the structure and device in a predetermined manner.

[0024] As used herein, the terms “longitudinal,” “vertical,” “lateral,” and “horizontal” refer to the principal plane of a substrate (e.g., substrate material, substrate structure, substrate configuration, etc.) on which one or more structures and / or features are formed and are not necessarily defined by the Earth’s gravitational field. A “lateral” or “horizontal” direction is a direction generally parallel to the principal plane of the substrate, while a “longitudinal” or “vertical” direction is a direction generally perpendicular to the principal plane of the substrate. The principal plane of the substrate is defined by the surface of the substrate, which has a relatively large area compared to the other surfaces of the substrate.

[0025] As used herein, the term "generally" means and includes the degree to which a given parameter, attribute, or condition conforms to deviations (such as within acceptable tolerances) as would be understood by one of ordinary skill in the art. By way of example, depending on the specific parameter, attribute, or condition that is substantially satisfied, it may satisfy at least 90.0%, at least 95.0%, at least 99.0%, at least 99.9%, or even 100.0%.

[0026] As used herein, the term "about" or "approximately" when referring to a value for a particular parameter includes the value, and a deviation from the value that will be understood by one of ordinary skill in the art to be within acceptable tolerances of the particular parameter. For example, "about" or "approximately" with respect to a value may include additional values ​​that are in the range of 90.0% to 110.0% of the value, such as in the range of 95.0% to 105.0%, 97.5% to 102.5%, 99.0% to 101.0%, 99.5% to 100.5%, or 99.9% to 100.1%.

[0027] As used herein, spatial relative terms such as “below,” “under,” “lower,” “bottom,” “above,” “upper,” “top,” “front,” “rear,” “left,” “right,” and similar spatial relative terms are used to conveniently describe the relationship of one element or feature to another, as illustrated in the figures. Unless otherwise specified, spatial relative terms are intended to cover different orientations of material other than those depicted in the figures. For example, if the material in the figures were inverted, then an element described as being “below,” “under,” “down,” or “on the bottom” of another element or feature would be oriented “above” or “on the top” of said other element or feature. Thus, the term “below” may encompass both above and below orientations, depending on the context in which the term is used, as will be apparent to those skilled in the art. Material may be oriented in other ways (e.g., rotated 90 degrees, reversed, flipped, etc.), and the spatial relative descriptive terms used herein may be interpreted accordingly.

[0028] As used herein, features described as “proximate” to each other (e.g., areas, materials, structures, devices) refer to and include features of the disclosed identity (or multiple identities) that are most closely positioned (e.g., closest to, adjacent to) each other. Additional features (e.g., additional areas, additional materials, additional structures, additional devices) of a disclosed identity (or multiple identities) that do not match a “proximate” feature may be positioned between said “proximate” features. In other words, “proximate” features may be positioned directly adjacent to each other such that no other features intervene between “proximate” features; or “proximate” features may be positioned indirectly adjacent to each other such that at least one feature having an identity other than the identity associated with at least one “proximate” feature is positioned between “proximate” features. Therefore, features described as “vertically proximate” to each other refer to and include features of the disclosed identity (or multiple identities) that are most vertically close to each other (e.g., vertically closest to, vertically adjacent to). Furthermore, features described as “horizontally proximate” to each other refer to and include features of the disclosed identity (or multiple identities) that are horizontally closest to each other (e.g., horizontally closest to, horizontally adjacent to).

[0029] As used herein, the term "memory device" means and includes, but is not limited to, microelectronic devices that exhibit memory functionality but are not limited to memory functionality. In other words, and by way of example only, the term "memory device" refers to microelectronic devices that include not only conventional memory (e.g., conventional volatile memory, such as conventional dynamic random access memory (DRAM); conventional non-volatile memory, such as conventional NAND memory), but also application-specific integrated circuits (ASICs) (e.g., system-on-a-chip (SoC)), combinational logic and memory, and graphics processing units (GPUs) incorporating memory.

[0030] As used herein, “conductive material” means and includes one or more of the following conductive materials: metals (e.g., tungsten (W), titanium (Ti), molybdenum (Mo), niobium (Nb), vanadium (V), hafnium (Hf), tantalum (Ta), chromium (Cr), zirconium (Zr), iron (Fe), ruthenium (Ru), osmium (Os), cobalt (Co), rhodium (Rh), iridium (Ir), nickel (Ni), palladium (Pa), platinum (Pt), copper (Cu), silver (Ag), gold (Au), aluminum (Al)); alloys (e.g., Co-based alloys, Fe-based alloys). Alloys based on Ni, alloys based on Fe and Ni, alloys based on Co and Ni, alloys based on Fe and Co, alloys based on Co, Ni, and Fe, alloys based on Al, alloys based on Cu, alloys based on magnesium (Mg), alloys based on Ti, steel, low-carbon steel, stainless steel; materials containing conductive metals (e.g., conductive metal nitrides, conductive metal silicides, conductive metal carbides, conductive metal oxides); conductive doped semiconductor materials (e.g., conductive doped polycrystalline silicon, conductive doped germanium (Ge), conductive doped silicon-germanium (SiGe)). Furthermore, "conductive structure" means and includes structures formed from and containing conductive materials.

[0031] As used herein, “insulating material” means and includes electrically insulating materials, such as at least one dielectric oxide material (e.g., silicon oxide (SiO2)). x Phossilicate glass, borosilicate glass, borosilicate-phosphorus glass, fluorosilicate glass, alumina (AlO) x ), hafnium oxide (HfO) x ), niobium oxide (NbO) x Titanium oxide (TiO) x Zirconium oxide (ZrO) x ), tantalum oxide (TaO) x ) and magnesium oxide (MgO) x One or more of the following), at least one dielectric nitride material (e.g., silicon nitride (SiN) y ()), at least one dielectric oxide material (e.g., silicon oxynitride (SiO) x N y and at least one dielectric carbon oxynitride material (e.g., silicon carbon oxynitride (SiO2)). x C z N y One or more of the chemical formulas “x”, “y”, and “z” are included in this document (e.g., SiO2). x AlO x HfO x NbO x TiO x SiN y SiOx N y SiO x C z N y A chemical formula represents a material containing "x" atoms of one element, "y" atoms of another element, and "z" atoms of an additional element (if present) relative to each atom of another element (e.g., Si, Al, Hf, Nb, Ti). Because chemical formulas represent relative atomic ratios and non-strict chemical structures, insulating materials can include one or more stoichiometric compounds and / or one or more non-stoichiometric compounds, and the values ​​of "x", "y", and "z" (if present) can be integers or non-integers. As used herein, the term "non-stoichiometric compound" means and includes compounds composed of an element that cannot be expressed by a well-defined ratio of natural numbers and violates the law of definite proportions. Furthermore, "insulating structure" means and includes structures formed of and containing insulating materials.

[0032] As used herein, “selectively removable” material means and includes materials that exhibit a greater removal rate in response to the same treatment conditions relative to another material exposed to treatment conditions (e.g., exposure to radiation (e.g., heat)). A material selectively removable relative to another material is substantially completely removable without substantially removing said other material (e.g., without removing either substantially of the other material).

[0033] As used herein, a “selectively etchable” material means and includes a material that exhibits a greater etching rate in response to exposure to the same etching chemicals and / or processing conditions compared to another material exposed to a given etching chemical and / or processing condition. For example, the material may exhibit an etching rate at least about five times greater than that of another material, such as about ten times, about twenty times, or about forty times greater than that of another material. Those skilled in the art can select the etching chemicals and etching conditions used to selectively etch the desired material.

[0034] According to the embodiments described herein, a microelectronic device includes isolated memory cell structures (e.g., isolated elongated semiconducting pillar structures with a length greater than their width), each memory cell structure individually including a digital line contact area laterally arranged between two memory node contact areas. The digital line contact area may be electrically connected to a digital line contact, which in turn is electrically connected to a digital line extending in a first lateral direction. Each memory node contact area is individually electrically connected to a memory node contact, each of which is electrically connected to a memory node (e.g., a capacitor, which may also be referred to herein as a cell capacitor). Each memory cell structure may include a central portion comprising the digital line contact area, a first end portion at a first end of the central portion, and a second end portion at a second opposite end of the central portion. The first end portion comprises a first memory node contact area and the second end portion comprises a second memory node contact area. The central portion may extend in the first lateral direction and include a longitudinal axis generally parallel to the digital line. In other words, the central portion may extend in the direction in which the digital line extends. In some embodiments, each of the first and second end portions includes a longitudinal axis oriented at an angle relative to the longitudinal axis of the central portion. In other words, each of the first and second end portions extends at an angle relative to the central portion. In some embodiments, the central portion includes opposing arcuate surfaces. In other embodiments, the central portion includes opposing substantially parallel surfaces. In some embodiments, each of the first and second end portions individually includes opposing substantially linear surfaces. In other embodiments, each of the first and second end portions individually includes at least one arcuate surface and at least one substantially linear surface. In some such embodiments, at least one arcuate surface may be opposite at least one linear surface. In some embodiments, the memory cell structure presents a so-called "S" shape. In other embodiments, the memory cell structure presents a so-called "Z" shape. The shape of the memory cell structure may depend at least in part on the method of forming the memory cell structure.

[0035] Orienting the first and second end portions at an angle relative to the center portion increases the distance between the memory node contact area and the digital line contact area of ​​the memory cell structure, reducing the likelihood of accidental short circuits between such features compared to conventional microelectronic devices. Furthermore, orienting the first and second end portions at an angle relative to the center portion increases the active area of ​​the memory cell structure (e.g., increasing the active area of ​​bit line contacts and each memory node contact). Additionally, forming the end portions at an angle relative to the center portion increases the area for forming digital line contacts on the digital line contact area (e.g., greater margin). In some embodiments, the shape of the memory cell structure can reduce (e.g., eliminate) the overlap between the word line structure and the digital line contact area of ​​the memory cell structure compared to conventional memory cell structures with a linear shape. In some embodiments, forming the first and second end portions at an angle relative to the center portion of the pillars of the memory cell structure increases the mechanical stability of the pillars (and reduces the risk of tipping over) compared to the pillars of a conventional memory cell structure with a linear shape. In some embodiments, the size and shape of the memory cell structure facilitate improved stacking margin, better operation of the memory cells associated with the memory cell structure (e.g., improved read and write operations of the memory cells), and increased yield of the memory cell structure during the formation of the microelectronic device. Furthermore, the memory cell structure can be formed without using so-called four-fold pitch techniques.

[0036] In some embodiments, extreme ultraviolet (EUV) lithography is used to form isolated memory cell structures. Compared to the memory cell structures of conventional microelectronic devices, EUV lithography facilitates the formation of isolated memory cell structures with smaller pitch and spacing, and eliminates the need for a four-fold pitch technique.

[0037] Figures 1A to 1S A simplified partial perspective view including a method of forming a microelectronic device structure (e.g., a memory device structure, such as a DRAM device structure) for a microelectronic device (e.g., a memory device, such as a DRAM device structure) according to embodiments of the present disclosure. Figure 1A , Figure 1C , Figure 1E , Figure 1G , Figure 1I and Figures 1K to 1N ), Simplified top view ( Figure 1B , Figure 1D , Figure 1F , Figure 1H , Figure 1J and Figure 10 ), and simplified partial cross-sectional views ( Figures 1P to 1SIn conjunction with the description provided below, it will be apparent to those skilled in the art that the methods described herein can be used in a variety of devices. In other words, the methods of this disclosure can be used whenever it is desired to form a microelectronic device containing a memory cell structure.

[0038] Figure 1A A simplified partial perspective view of the microelectronic device 100 and Figure 1B A simplified top view of part of the microelectronic device 100. (Reference) Figure 1A The microelectronic device 100 includes a substrate material 102, a first oxide material 104 vertically (e.g., in the Z direction) overlying the substrate material 102, a hard mask material 106 vertically overlying the first oxide material 104, a second oxide material 108 vertically overlying the hard mask material 106, a first sacrificial material 110 vertically overlying the second oxide material 108, a third oxide material 112 vertically overlying the first sacrificial material 110, a second sacrificial material 114 vertically overlying the third oxide material 112, a carbon-containing material 116 vertically overlying the second sacrificial material 114, a dielectric antireflective coating (DARC) material 118 vertically overlying the carbon-containing material 116, and a photoresist material 120 (also referred to herein as a "photomask material") vertically overlying the DARC material 118.

[0039] Photoresist material 120 can be arranged into lines 122 spaced apart from each other by a first groove 124. In some embodiments, each line 122 can individually present a braided shape, including widened circular portions 126 (also referred to herein as “bubble portions”), which are spaced apart from each other by narrower curved portions 128 whose width (e.g., in the X direction) is smaller than the width of the widened circular portions 126. For clarity and ease of understanding of the description, Figure 1A The portion of the photoresist material 120 is not shown in the crosshairs. Throughout the figures, and in some partial perspective views, crosshairs may not be used to show portions of the material for clarity and ease of understanding of the description and figures.

[0040] In some embodiments, the spacing P1 of the lines 122 can be in the range of about 40 nanometers (nm) to about 60 nm, for example, about 40 nm to about 50 nm, or about 50 nm to about 60 nm. However, this disclosure is not limited thereto, and the spacing P1 may be different from those described above.

[0041] In some embodiments, the distance D1 between the widened circular portions 126 of adjacent lines 122 may be in the range of about 10 nm to about 30 nm, for example, about 10 nm to about 20 nm, or about 20 nm to about 30 nm. In some embodiments, the distance D2 between the narrower curved portions 128 of adjacent lines 122 may be in the range of about 20 nm to about 40 nm, for example, about 20 nm to about 30 nm, or about 30 nm to about 40 nm.

[0042] The substrate material 102 may comprise a semiconductor substrate, a substrate semiconductor material on a supporting substrate, metal electrodes, or a semiconductor substrate on which one or more materials, structures, or regions are formed. The substrate material 102 may include a semiconducting material, such as a conventional silicon substrate or other bulk substrate containing semiconductor material. As used herein, the term "bulk substrate" means and includes not only silicon wafers but also silicon-on-insulator ("SOI") substrates, such as silicon-on-sapphire ("SOS") or silicon-on-glass ("SOG") substrates, silicon epitaxial layers on a substrate semiconductor, or other semiconductor or optoelectronic materials, such as silicon-germanium (Si-G) substrates. 1- x Ge x Where x is, for example, a mole fraction between 0.2 and 0.8, germanium (Ge), gallium arsenide (GaAs), gallium nitride (GaN), or indium phosphide (InP), etc. Furthermore, when referred to as "substrate" or "base material" in the following description, previous process stages may have been used to form materials, regions, or junctions in the substrate semiconductor structure or base. The substrate material 102 may comprise one or more materials associated with integrated circuit manufacturing. Such materials may comprise one or more of, for example, refractory metals, barrier materials, diffusion materials, and insulating materials. The substrate material 102 may comprise, for example, a complementary metal-oxide-semiconductor (CMOS) structure or other semiconductor structures. Different portions of the substrate material 102 may be electrically isolated from each other by one or more dielectric materials.

[0043] The first oxide material 104 may be formed of and comprise one or more dielectric materials, such as one or more of silicon dioxide (SiO2), fluorosilicate glass (FSG), phosphosilicate glass (PSG), borosilicate glass (BSG), borosilicate glass (BPSG), and another insulating material. The first oxide material 104 may be formed by thermal oxidation, deposition (e.g., deposition with tetraethyl orthosilicate (TEOS)), or another method of the substrate material 102. In some embodiments, the first oxide material 104 comprises silicon dioxide.

[0044] Hard mask material 106 may be formed of and comprise one or more materials exhibiting etch selectivity to various mask materials (e.g., shredded masks), as will be described herein. As a non-limiting example, hard mask material 106 may exhibit etch selectivity relative to various materials such as sacrificial materials (e.g., amorphous carbon), dielectric materials (e.g., silicon dioxide, silicon nitride), dielectric antireflective coating (DARC) materials, and bottom antireflective coating (BARC) materials. Hard mask material 106 may be formed of and comprise one or more of metal nitrides (e.g., titanium nitride, tungsten nitride, tantalum nitride, aluminum nitride), metal oxides (e.g., aluminum oxide, titanium oxide, tungsten oxide, tantalum oxide, hafnium oxide, zirconium oxide), oxynitride materials, silicon oxycarbonate, silicon oxycarbonate, amorphous carbon, or another material. In some embodiments, hard mask material 106 comprises titanium nitride.

[0045] The second oxide material 108 may be formed from and comprise one or more of the materials described above with reference to the first oxide material 104. In some embodiments, the second oxide material 108 comprises substantially the same material composition as the first oxide material 104. In other embodiments, the second oxide material 108 comprises a different material composition than the first oxide material 104. In some embodiments, the second oxide material 108 comprises silicon dioxide.

[0046] The first sacrificial material 110 can be made of amorphous silicon (α-silicon), silicon nitride (Si3N4), or silicon oxynitride (SiO2). x N y It is formed and contains one or more of another material. In some embodiments, the first sacrificial material 110 comprises amorphous silicon.

[0047] The third oxide material 112 may be formed from and comprise one or more of the materials described above with reference to the first oxide material 104. In some embodiments, the third oxide material 112 comprises substantially the same material composition as the first oxide material 104. In other embodiments, the third oxide material 112 comprises a different material composition than the first oxide material 104. In some embodiments, the third oxide material 112 comprises silicon dioxide.

[0048] The second sacrificial material 114 may be formed from and comprise one or more of the materials described above with reference to the first sacrificial material 110. In some embodiments, the second sacrificial material 114 comprises substantially the same material composition as the first sacrificial material 110. In other embodiments, the second sacrificial material 114 comprises a different material composition than the first sacrificial material 110. In some embodiments, the second sacrificial material 114 comprises amorphous silicon.

[0049] The carbon-containing material 116 may be formed from and comprise a carbon-containing mask material. In some embodiments, the carbon-containing material 116 comprises amorphous hydrocarbons (also referred to as "amorphous carbon"). In some embodiments, the carbon-containing material 116 comprises spin carbon (SOC) material.

[0050] DARC material 118 can be formed from and contain silicon oxynitride material, such as Si x O y N z Where x is between about 10 and about 60, y is between about 20 and about 50, and z is between about 10 and about 20. However, this disclosure is not so limited and DARC material 118 may include other suitable DARC materials known in this art. DARC material 118 may be formulated and configured to substantially prevent reflection of electromagnetic radiation (e.g., light source) during exposure of the photoresist material (e.g., photoresist material 120) during patterning of the photoresist material.

[0051] The photoresist material 120 may be formed of and comprise an extreme ultraviolet (EUV) photoresist material. As a non-limiting example, the photoresist material 120 may be formed of and comprise a stack comprising alternating amounts of silicon and molybdenum. However, this disclosure is not so limited, and the photoresist material 120 may comprise one or more other materials.

[0052] refer to Figure 1C and Figure 1D Photoresist material 120 ( Figure 1A , Figure 1B ) line 122 ( Figure 1A , Figure 1B The pattern can be obtained using DARC material 118 ( Figure 1A ) and carbon-containing materials 116 ( Figure 1A The transfer is made onto the second sacrificial material 114 to form the first line 125. Spacers 130 may be formed on the sidewalls of the first line 125 of the second sacrificial material 114. In some embodiments, this can be achieved through grooves 124 (…). Figure 1A , Figure 1BThe DARC material 118 and the carbon-containing material 116 are patterned to form a first line 125 within the DARC material 118 and the carbon-containing material 116. After the first line 125 is formed within the DARC material 118 and the carbon-containing material 116, the photoresist material 120 can be removed (e.g., stripped) from the microelectronic device 100. In some embodiments, the first line 125 is formed by a spacing doubling process.

[0053] Continue to refer to Figure 1C and Figure 1D The second sacrificial material 114 can be patterned using DARC material 118 and carbon-containing material 116 to form a first line 125 of the second sacrificial material 114. In some embodiments, the size of the first line 125 of the second sacrificial material 114 may be smaller than that of the photoresist material 120. Figure 1A , Figure 1B ) line 122 ( Figure 1A , Figure 1B For example, in some embodiments, the photoresist material 120 may be exposed to the finishing process before the pattern is transferred to the DARC material 118 and the carbon-containing material 116.

[0054] The spacer 130 may be formed of and comprise one or more materials, which are formulated and configured to exhibit etch selectivity relative to the second sacrificial material 114 and the third oxide material 112. As a non-limiting example, the spacer 130 may be formed of and comprise a carbon-containing material (e.g., silicon carbon nitride (SiCN)), an oxynitride material (e.g., silicon oxynitride, silicon carbon oxynitride (SiOCN)), or other materials. In some embodiments, since the spacer 130 is formed on the sidewall of the second sacrificial material 114, the spacer 130 may have a shape corresponding to the shape of the sidewall of the second sacrificial material 114.

[0055] Figure 1E A simplified partial perspective view of the microelectronic device 100 and Figure 1F for Figure 1E A partially simplified top view of the microelectronic device 100. (Reference) Figure 1E and Figure 1F The second sacrificial material 114 can be selectively removed from the microelectronic device 100. Figure 1C , Figure 1D Meanwhile, the spacer 130 remains on the third oxide material 112.

[0056] Now for reference Figure 1G and Figure 1HAn underlayer material 132 may be formed between the laterally adjacent (e.g., in the X direction) spacers 130 and over the third oxide material 112. The underlayer material 132 may substantially fill the space between the spacers 130. In some embodiments, after the underlayer material 132 is formed, it may be exposed to a planarization process, such as a chemical mechanical planarization (CMP) process. In other embodiments, the underlayer material 132 may not be exposed to a planarization process.

[0057] The underlayer material 132 may be formed from and comprise one or more of the EUV underlayer materials, such as a polymer matrix material (e.g., a crosslinkable polymer matrix material). As a non-limiting example, the underlayer material 132 may comprise one or more of the following: methacrylates, polyhydroxystyrene (PHS), triphenylsulfonic acid (TPS) trifluorophosphate, oxides, metals (e.g., hafnium, cobalt, tungsten, titanium), conductive metal nitrides (e.g., titanium nitride), silicides (e.g., titanium silicide, cobalt silicide), dielectric materials (e.g., silicon dioxide, silicon nitride, silicon oxynitride), amorphous carbon, or antireflective materials. In some embodiments, the underlayer material 132 comprises spin carbon (SOC).

[0058] refer to Figure 1I and Figure 1J In forming the underlying material 132 ( Figure 1G , Figure 1H Afterwards, the spacer 130 can be selectively removed from the microelectronic device 100 relative to the underlying material 132. Figure 1G , Figure 1H Meanwhile, the underlayer material 132 remains vertical (e.g., in the Z direction) on the third oxide material 112. After removing the spacer 130, the third oxide material 112 can be patterned with the underlayer material 132 to transfer the pattern of the first line 125 onto the third oxide material 112, and a second line 135 is formed between the first lines 125 laterally (e.g., in the X direction). The second line 135 may be formed in relation to the photoresist material 120 ( Figure 1A , Figure 1B ) lateral adjacent line 122 ( Figure 1A , Figure 1B The positions corresponding to the areas between ) are shown. The position of the first line 125 can correspond to the position of line 122 of the photoresist material 120.

[0059] For example, spacer 130 can be selectively removed by exposing microelectronic device 100 to one or more etchants. As a non-limiting example, spacer 130 can be removed by exposing spacer 130 to one or more of oxygen (O2), nitrous oxide (N2O), nitrogen trifluoride (NF3), nitrogen dioxide (NO2), or other materials.

[0060] After the first line 125 and the second line 135 are formed in the third oxide material 112, the underlying material 132 can be selectively removed from the microelectronic device 100. Figure 1G , Figure 1H In some embodiments, the underlayer material 132 is removed by ashing. As a non-limiting example, the underlayer material 132 may be exposed to a plasma containing one or more of hydrogen (H2), nitrogen (N2), fluorine (F2), sulfur hexafluoride (SF6), hexafluoroethane (C2F6), or another material. In other embodiments, the underlayer material 132 is exposed to a plasma containing one or more other dry etchants, such as oxygen, nitrogen, fluorine-containing gases (e.g., nitrogen trifluoride (NF3), sulfur hexafluoride (SF6), carbon tetrafluoride (CF4)), and hydrogen bromide (HBr) to selectively remove the underlayer material 132.

[0061] Now for reference Figure 1K A first line 125 is formed in the third oxide material 112. Figure 1J ) and second line 135 ( Figure 1J After that, an additional underlayer material 134 can be formed on the third oxide material 112, and a multilayer resist (MLR) material 136 (also referred to herein as “three-layer photo-stacking”) can be formed on the additional underlayer material 134.

[0062] The multilayer photoresist material 136 may be formed from and comprise one or more photoresist materials, such as one or more of polymethyl methacrylate (PMMA), one or more of the materials described above with reference to photoresist material 120, deep ultraviolet (DUV) photoresist, diazonaphthoquinone (DNQ) material, and additional photoresist materials. However, this disclosure is not so limited, and the multilayer photoresist material 136 may comprise materials other than those described.

[0063] In some embodiments, the multilayer resist material 136 may be formed and patterned, for example, by extreme ultraviolet patterning. Trench 138 may be formed in the multilayer resist material 136. In some embodiments, the trench 138 may extend at an angle θ relative to an axis (e.g., the X-axis) of the microelectronic device 100. As a non-limiting example, the angle θ may be greater than about zero (0) degrees and less than about ninety (90) degrees, for example, in the range of about (20) degrees to about seventy (70) degrees, about thirty (30) degrees to about sixty (60) degrees, or about forty (40) degrees to about fifty (50) degrees. In some embodiments, the angle θ may be about forty-one (41) degrees. However, this disclosure is not so limited, and the angle θ may differ from the angle described above.

[0064] In some embodiments, the exposed portion of the additional underlayer material 134 can be removed via the trench 138 to expose a portion of the third oxide material 112. (See reference...) Figure 1L Multilayer corrosion resist material 136 ( Figure 1K The material can be removed from the microelectronic device 100. In some embodiments, after removing the multilayer resist material 136, the exposed portion of the third oxide material 112 can be removed via the trench 138. After removing the exposed portion of the third oxide material 112, an additional underlayer material 134 can be removed. In some embodiments, the additional underlayer material 134 is removed by ashing, as described above with reference to the removal of underlayer material 132. Figure 1G As stated in the above.

[0065] Continue to refer to Figure 1L Removing the exposed portion of the third oxide material 112 can form an isolation structure 140 of the second oxide material 108. In some embodiments, the isolation structure 140 is S-shaped. As described herein, the shape and pattern of the isolation structure 140 can be transferred to the substrate material 102 to form a memory cell structure.

[0066] refer to Figure 1M The pattern of the isolation structure 140 can be obtained from the third oxide material 112 ( Figure 1L The material is transferred to a hard mask material 106. In some embodiments, the exposed portion of the first sacrificial material 110 is removed by a third oxide material 112, and the third oxide material 112 is selectively removed. After the third oxide material 112 is removed, the exposed portion of the second oxide material 108 may be removed, and the first sacrificial material 110 may be removed.

[0067] The exposed portion of the hard mask material 106 can be removed by the second oxide material 108 to transfer the isolation structure 140 onto the hard mask material 106. After the isolation structure 140 is formed in the hard mask material 106, the second oxide material 108 can be removed. In some embodiments, the first oxide material 104 is removed to expose the surface of the substrate material 102.

[0068] refer to Figure 1N In hard mask material 106 ( Figure 1M After the isolation structure 140 is formed in the substrate, the exposed portion of the first oxide material 104 and a portion of the substrate material 102 can be removed by the hard mask material 106 to form an isolated memory cell structure 145 (also referred to herein as an "isolated semiconducting pillar structure") within the substrate material 102. In some embodiments, the memory cell structure 145 can be isolated by an isolation structure including an insulating material 144 (also referred to herein as a "shallow trench isolation structure").

[0069] Insulating material 144 may be formed of and contain insulating materials, such as at least one dielectric oxide material (silicon dioxide, phosphosilicate glass, borosilicate glass, borosilicate glass, fluorosilicate glass, alumina (Al₂O₃)). x ), hafnium oxide (HfO) x ), niobium oxide (NbO) x Titanium oxide (TiO) x Zirconium oxide (ZrO) x ), tantalum oxide (TaO) x ) and magnesium oxide (MgO) x At least one dielectric nitride material (e.g., silicon nitride (SiN)). y ()), at least one dielectric oxynitride material (e.g., silicon oxynitride (SiO2) x N y and at least one dielectric carbonitride material (e.g., silicon carbonitride (SiO2)). x C z N y One or more of the following. In some embodiments, the insulating material 144 comprises silicon dioxide.

[0070] refer to Figures 10 to 1S Additional processing actions can be performed on the microelectronic device 100. Figure 10 This is a simplified top view of the microelectronic device 100. Figure 1P For the section cut by PP Figure 10 A simplified cross-sectional view of the microelectronic device 100; Figure 1Q To pass Figure 10 The section line RR intercepted Figure 10 A simplified cross-sectional view of the microelectronic device 100; Figure 1R For the section cut by section line RR Figure 10 A simplified cross-sectional view of the microelectronic device 100; and Figure 1S For section cut by SS Figure 10 A simplified cross-sectional view of a microelectronic device.

[0071] refer to Figure 10 Furthermore, when viewed from a top view, each of the isolated memory cell structures 145 may present an S-shape, each individually comprising a central portion 150 located between opposing end portions 152 (e.g., a first end portion spaced laterally (e.g., in the Y direction) from the second end portion 152).

[0072] Each end portion 152 may be at least partially defined by a basic linear surface 154. The linear surface 154 may be defined by the location of the groove 138. Figure 1KEach of the end portions 152 may further include material 114 made of the second sacrificial material. Figure 1C ) surface (and line 122 of photoresist material 120) Figure 1A , Figure 1B The spacer 130 (defined by the corresponding surface of the ) Figure 1C The curved surface 156 corresponds to the arcuate (e.g., curved) surface 156 of the curved surface of the first end portion 152. In some embodiments, the substantially linear surface 154 of each end portion 152 may be opposite to the arcuate surface 156 of the corresponding end portion 152. In some embodiments, the substantially linear surface 154 of the first end portion 152 may be located at the relatively lateral (e.g., in the Y direction) end of the microelectronic device 100 relative to the substantially linear surface 154 of the second end portion 152. In some embodiments, the substantially linear surface 154 of the first end portion 152 of the isolated memory cell structure 145 and the substantially linear surface 154 of the second end portion 152 of the isolated memory cell structure 145 are substantially laterally aligned (e.g., substantially parallel) in a second lateral direction (e.g., in the X direction). In some embodiments, the arcuate surface 156 of the first end portion 152 may be located at the relatively lateral (e.g., in the X direction) end of the microelectronic device 100 relative to the arcuate surface 156 of the second end portion 152.

[0073] The central portion 150 may be individually defined by an inwardly oriented, arcuate (e.g., curved) surface 158, at least partially defined by the spacer 130. Figure 1C ) and second sacrificial material 114 ( Figure 1C The curved surface is defined by photoresist material 120 ( Figure 1A , Figure 1B ) line 122 ( Figure 1A , Figure 1B The widened circular portion 126 ( Figure 1B ) and the narrower curved section 128 ( Figure 1B The central portion 150 is defined by an inwardly oriented arcuate surface 158 that defines a minimum width of the central portion 150 (e.g., in the X direction) and is positioned close to a digital line (e.g., bit line) contact area 160. In some embodiments, the opposing arcuate surfaces 158 of the central portion 150 may be non-linear and may not be parallel.

[0074] Continue to refer to Figure 10 Each of the isolated memory cell structures 145 may individually include a digital line contact area 160 located on the central portion 150 of the isolated memory cell structure 145 and a memory node (e.g., memory cell) contact area 162 located on the end portion 152 of the respective isolated memory cell structure 145. As will be described herein, digital line contacts (e.g., digital line contacts 174) Figure 1P )) and storage node contacts (e.g., storage node contact 184 ( Figure 1R This can be formed on the corresponding digital line contact area 160 and storage node contact area 162. Although the digital line contact area 160 and storage node contact area 162 are... Figure 10 The digital line contact area 160 and the memory node contact area 162 are shown to have specific lateral dimensions, but it should be understood that the lateral dimensions of the digital line contact area 160 and the memory node contact area 162 may differ. Figure 10 The lateral dimension is shown. In some embodiments, the central portion 150 may have a minimum lateral dimension (e.g., width in the X direction) at the digital line contact area 160.

[0075] Storage node contact areas 162 may be located near (e.g., above or above) the end portion 152 of the isolated memory cell structure 145. Digital line contact areas 160 may be located near (e.g., above or above) the center portion 150 of the isolated memory cell structure 145. In some embodiments, the digital line contact areas 160 of the first isolated memory cell structure 145 are laterally adjacent to the end portion 152 of the adjacent isolated memory cell structure 145. In some embodiments, the storage node contact areas 162 of the upper end portion 152 of the first isolated memory cell structure 145 are laterally aligned with the storage node contact areas 162 of the lower end portion 152 of the adjacent isolated memory cell structure 145.

[0076] In some embodiments, the digital line contact area 160 of the first isolated memory cell structure 145 is laterally (e.g., in the X direction) aligned with the lateral (e.g., in the Y direction) adjacent memory cell structure 145.

[0077] Continue to refer to Figure 10 In some embodiments, the lateral (e.g., in the X direction, in the Y direction) spacing between laterally adjacent isolated memory cell structures 145 can be based on, for example, a multilayer resist material 136 ( Figure 1K ) and the grooves 138 in the multilayer resist material 136 Figure 1K The alignment is different. Although Figure 10 The illustration shows that the end portions 152 of each isolated memory cell structure 145 are substantially the same size, but this disclosure is not so limited. In other embodiments, based on the alignment (e.g., alignment) of the trenches 138 within the multilayer resist material 136, the size and corresponding cross-sectional area of ​​the upper (e.g., in the Y direction) end portion 152 of each isolated memory cell structure 145 may be larger or smaller than the lower (e.g., in the Y direction) end portion 152 of the corresponding isolated memory cell structure 145.

[0078] refer to Figure 10 and Figure 1PWord lines 164 can be formed in isolation trenches between memory node contact areas 162 and digital line contact areas 160 using conventional techniques. In some embodiments, each of the isolated memory cell structures 145 may intersect with two word lines 164. The end portion 152 of each isolated memory cell structure 145 may intersect with the word lines 164.

[0079] Insulating material 166 (For clarity and ease of understanding, the description is as follows) Figure 10 (Not shown) may be formed on the microelectronic device 100 and may fill the area between adjacent isolated memory cell structures 145. The insulating material 166 may be formed of and contain a dielectric material, such as the insulating material 144 mentioned above. Figure 1N The insulating material 166 is one or more materials as described. In some embodiments, the insulating material 166 includes silicon dioxide.

[0080] After the insulating material 166 is formed, portions of the insulating material 166 and portions of the isolation memory cell structure 145 between the central portion 150 and the terminal portion 152 can be removed. For example, a mask material can be formed over the microelectronic device 100 with openings (e.g., trenches) extending in a first lateral direction (e.g., in the X direction), and portions of the insulating material 166 and the isolation structure 140 can be removed through the openings in the mask material.

[0081] In some embodiments, after the opening is formed, the exposed portion of the substrate material 102 may be exposed to the ion implantation process to form the channel region 181 of the transistor structure. A dielectric material 168 (e.g., a gate dielectric material) may be formed within the opening and a conductive material 170 may be formed over the dielectric material 168 to form a word line 164. The dielectric material 168 may be formed from one or more of the following and includes one or more of the following: phosphosilicate glass, borosilicate glass, borosilicate glass (BPSG), fluorosilicate glass, silicon dioxide, titanium dioxide, zirconium dioxide, hafnium dioxide, tantalum oxide, magnesium oxide, aluminum oxide, niobium oxide, molybdenum oxide, strontium oxide, barium oxide, yttrium oxide, nitride material (e.g., silicon nitride (Si3N4)), oxynitride (e.g., silicon oxynitride), another gate dielectric material, dielectric carbon nitride material (e.g., silicon carbon nitride (SiCN)), dielectric carbon oxynitride material (e.g., silicon carbon oxynitride (SiOCN)), or combinations thereof.

[0082] The conductive material 170 may be formed from and include one or more of the following: titanium nitride, tantalum nitride, aluminum titanium nitride, elemental titanium, elemental platinum, elemental rhodium, elemental iridium, iridium oxide, elemental ruthenium, elemental ruthenium oxide, elemental molybdenum, elemental tungsten, elemental cobalt, polycrystalline silicon, germanium, and silicon-germanium. In some embodiments, the conductive material 170 includes one or more of elemental molybdenum, elemental tungsten, and elemental cobalt, and one or more of polycrystalline silicon, germanium, and silicon-germanium.

[0083] In some embodiments, and with reference to Figure 10 Word lines 164 can separate the central portion 150 from the terminal portion 152. In other words, in some embodiments, word lines 164 can be inserted between the central portion 150 and the terminal portion 152 of the isolated memory cell structure 145. Therefore, word lines 164 can be located in isolation trenches (e.g., containing insulating material 166) that separate digital line contact areas 160 from the memory node contact areas 162 of each isolated memory cell structure 145. Thus, each isolated memory cell structure 145 as described herein may include a central portion 150 spaced apart from terminal portions 152 (e.g., first terminal portion 152 and second terminal portion 152) by word lines 164 (e.g., first word lines 164 and second word lines 164). After the word lines 164 are formed, the remaining portion of the opening may be filled with an insulating material 172, which may comprise one or more of the materials described above with reference to insulating material 166. In some embodiments, insulating material 172 comprises the same material composition as insulating material 166.

[0084] Continue to refer to Figure 10 The longitudinal axis L1 of the end portion 152 of the isolated memory cell structure 145 may be oriented at an angle α relative to the longitudinal axis L2 of the central portion 150. The longitudinal axis L2 of the central portion 150 may correspond to and be substantially parallel to the digital line 178 vertically overlying the central portion 150. The angle α may be greater than about zero (0) degrees and less than about ninety (90) degrees, for example, in the range of about (20) degrees to about seventy (70) degrees, about thirty (30) degrees to about sixty (60) degrees, or about forty (40) degrees to about fifty (50) degrees. In some embodiments, the angle α may be about forty-nine (49) degrees. In some embodiments, the angle α and the angle θ ( Figure 1K The sum of ) can be approximately ninety (90) degrees.

[0085] refer to Figure 1P and Figure 1QAfter the word line 164 is formed, an opening can be formed through portions of insulating material 172 and insulating material 166 to expose the surface of the digital line contact area 160 of the isolated memory cell structure 145. The opening can be formed, for example, by forming and patterning a mask over the microelectronic device 100 and exposing the microelectronic device 100 to a suitable etchant. The digital line contact 174 can be formed within the opening and on the digital line contact area 160.

[0086] Digital line contact 174 may be formed of and comprise at least one conductive material. In some embodiments, digital line contact 174 comprises one or more of the following: titanium nitride, tantalum nitride, titanium aluminum nitride, elemental titanium, elemental platinum, elemental rhodium, elemental iridium, iridium oxide, elemental ruthenium, elemental ruthenium oxide, elemental molybdenum, elemental tungsten, elemental cobalt, polycrystalline silicon, germanium, and silicon germanium. In some embodiments, digital line contact 174 comprises one or more of elemental molybdenum, elemental tungsten, and elemental cobalt, and one or more of polycrystalline silicon, germanium, and silicon germanium. In some embodiments, digital line contact 174 comprises doped polycrystalline silicon. As a non-limiting example, digital line contact 174 may comprise at least about 10 20 atoms / cm 3 , or even at least about 10 21 atoms / cm 3 .

[0087] In some embodiments, the digital line contact 174 is recessed relative to the upper surface of the insulating material 172. After the digital line contact 174 is formed, a conductive material 176 may be formed over the microelectronic device structure 100 and contact the digital line contact 174 to form a digital line 178. The conductive material 176 of the digital line 178 may be formed of and contain one or more of the materials described above with reference to the word line 164.

[0088] After forming the digital line contact 174 and the digital line 178, an insulating material 180 may be formed over the digital line 178. In some embodiments, a spacer 182 (e.g., a "bit line spacer", "digital line spacer") may be formed on the side of the digital line 178. The insulating material 180 and the spacer 182 may be formed individually of one or more of the materials described above with reference to insulating materials 166 and 172, and may contain one or more of said materials.

[0089] refer to Figure 1R Storage node contacts 184 may be formed above the storage node contact area 162 of the isolation structure 140. Storage node contacts 184 may be formed of and contain one or more of the materials described above with reference to digital line contacts 174.

[0090] Storage node contact 184 may be electrically connected to storage node contact region 162 of isolation structure 140. Storage node contact 184 may be located between adjacent portions of insulating material 172 and insulating material 180. Storage node contact 184 may be formed of and comprise one or more of the materials described above with reference to digital line contact 174. In some embodiments, storage node contact 184 comprises doped polysilicon. As a non-limiting example, storage node contact 184 may comprise at least about 10 20 atoms / cm 3 , or even at least about 10 21 atoms / cm 3 In some embodiments, the microelectronic device 100 is exposed to annealing conditions to diffuse dopant from digital line contacts 174 and memory node contacts 184 to form source regions, drain regions, and channel regions 181 of, for example, transistor structures.

[0091] Continue to refer to Figures 10 to 1R In some embodiments, the digital line contact 174 may be aligned in the Y direction and offset from the storage node contact 184 in the X direction. In some embodiments, the digital line contact 174 may not be aligned with any of the storage node contacts 184 in the direction in which the digital line 178 extends. Additionally, the storage node contacts 184 may be aligned with each other in the Y direction.

[0092] Microelectronic device 100 may include memory cells, each of which includes an access transistor (e.g., a transistor with a gate along word line 164) coupled to a memory node structure 186 (e.g., a capacitor structure). Figure 1R The diagram shows only one storage node structure 186, but it should be understood that all storage node contacts 184 can be coupled to the storage node structure 186.

[0093] Continue to refer to Figure 1R The storage node structure 186 may be formed above and electrically connected to the storage node contact 184. For the sake of clarity and ease of understanding of this disclosure, Figure 10 The storage node structure 186 is not shown in the diagram.

[0094] In some embodiments, a re-fabricated material (RDM) structure 188 (also referred to as a "re-fabricated layer (RDL) structure") may be formed on or above the storage node contact 184, and the storage node structure 186 may be electrically connected to the storage node structure 186 and the storage node contact 184.

[0095] RDM structure 188 can be configured to effectively shift (e.g., interleave, adjust, modify) the lateral position (e.g., in the X direction, in the Y direction) of memory node contacts 184 to accommodate a desired arrangement (e.g., close-packed hexagonal arrangement) of the memory node structure 184 above and electrically connected to the memory node contacts 186. RDM structures 188 can each be individually formed of and contain conductive materials, including but not limited to metals (e.g., tungsten, titanium, nickel, platinum, gold), metal alloys, metal-containing materials (e.g., metal nitrides, metal silicides, metal carbides, metal oxides), and conductive doped semiconductor materials (e.g., conductive doped silicon, conductive doped germanium, conductive doped silicon-germanium). As a non-limiting example, RDM structure 188 can individually include W, TiN, TaN, WN, TiAlN, Ti, Pt, Rh, Ir, IrO. x 、Ru、RuO x One or more of its alloys.

[0096] The storage node structure 186 can be configured to store charges representing programmable logic states. For example, a charged state of the storage node structure 186 can represent a first logic state (e.g., logic 1), and a de-charged state of the storage node structure 186 can represent a second logic state (e.g., logic 0). In some embodiments, the storage node structure 186 includes a dielectric material configured to store charges associated with logic states. The dielectric material may include, for example, one or more of the following: silicon dioxide, silicon nitride, polyimide, titanium dioxide (TiO2), tantalum oxide (Ta2O5), aluminum oxide (Al2O3), oxide-nitride-oxide materials (e.g., silicon dioxide-silicon nitride-silicon dioxide), strontium titanate (SrTiO3) (STO), barium titanate (BaTiO3), hafnium dioxide (HfO2), zirconium oxide (ZrO2), ferroelectric materials (e.g., ferroelectric hafnium dioxide, ferroelectric zirconium oxide, lead zirconate titanate (PZT), etc.), and high-k dielectric materials. In some embodiments, the storage node structure 186 includes zirconium oxide.

[0097] The RDM structure 188 and the storage node structure 186 can be formed using conventional processes (e.g., conventional deposition processes such as in-situ growth, spin coating, blanket coating, CVD, ALD and PVD; conventional patterning and material removal processes such as conventional alignment, conventional photolithography, conventional development and etching) and conventional processing equipment that are not described in detail herein.

[0098] Figure 1S This is a simplified partial cross-sectional view of the microelectronic device 100 through a single isolated memory cell structure 145. (Reference) Figure 1SEach memory cell structure 145 may include a first semiconducting post 190 located at a first end portion 152 of the memory cell structure 145, a second semiconducting post 192 located at a central portion 150 of the memory cell structure 145, and a third semiconducting post 194 located at the second end portion 152 of the memory cell structure 145. The second semiconducting post 192 may be located between the first semiconducting post 190 and the third semiconducting post 194. A first word line 164 is located between the first semiconducting post 190 and the second semiconducting post 192, and a second word line 164 is located between the second semiconducting post 192 and the third semiconducting post 194. An insulating material 166 may isolate the isolated memory cell structure 145 from laterally adjacent isolated memory cell structures 145.

[0099] Since each memory cell structure 145 contains two memory node structures 186, in some embodiments, the memory cell structure 145 may be referred to as a dual-bit memory cell.

[0100] Compared to conventional microelectronic devices, forming an isolated memory cell structure 145 comprising a central portion 150 and an end portion 152 extending at an angle α relative to the longitudinal axis L2 of the central portion 150 can facilitate an increase in the active area of ​​the digital line contacts 174 on the central portion 150. Furthermore, compared to conventional microelectronic device structures, the size and shape of the isolated memory cell structure 145 can facilitate an increase in the landing area of ​​the memory node contacts 184 (e.g., from about 4 nm to about 5 nm or more). Moreover, forming the isolated memory cell structure 145 by the methods described herein facilitates the formation of an isolated memory cell structure 145 having the desired size, shape, and spacing without complex process flows such as four times the spacing.

[0101] although Figures 1A to 1S As described and shown to form a microelectronic device 100, it includes forming a spacer 130. Figure 1C ) and transferring the pattern of spacer 130 onto third oxide material 112 ( Figure 1E ) to form the first line 125 ( Figure 1J ) and second line 135 ( Figure 1J However, this disclosure is not so limited. In other embodiments, the first line 125 and the second line 135 may be formed by other methods. As a non-limiting example, in some embodiments, as referenced above... Figure 1C As described, spacers 130 are formed on the second sacrificial material 114. After the spacers 130 are formed, second lines 135 can be formed (e.g., printed) on the third oxide material 112 through the spaces between laterally adjacent spacers 130. Figure 1J The pattern is as follows. In some such embodiments, the spacer 130 may facilitate the connection between the second line 135 and the first line 125. Figure 1J Alignment. In other words, spacer 130 compensates for possible misalignment errors during the printing of the second line 135. After the second line 135 is formed, spacer 130 can be removed, and the pattern of the first line 125 and the second line 135 can be transferred to the third oxide material 112, and then the first sacrificial material 110 is removed. See above for reference. Figure 1K to Figure 1S The formation of the microelectronic device 100 is described.

[0102] Figures 2A to 2J A method for forming a microelectronic device according to an embodiment of the present disclosure is shown. Figure 2A This is a simplified partial perspective view of a microelectronic device 200. The microelectronic device 200 may include a substrate material 202, a first oxide material 204 vertically (e.g., in the Z direction) coated on the substrate material 202, a hard mask material 206 vertically coated on the first oxide material 204, a second oxide material 208 vertically coated on the hard mask material 206, a sacrificial material 210 vertically coated on the second oxide material 208, a carbon-containing material 212 vertically coated on the sacrificial material 210, a DARC material 214 vertically coated on the carbon-containing material 212, and a photoresist material 216 vertically coated on the DARC material 214. Each of the substrate material 202, the first oxide material 204, the hard mask material 206, the second oxide material 208, the sacrificial material 210, the carbon-containing material 212, the DARC material 214, and the photoresist material 216 may be substantially the same as described above. Figure 1A The corresponding substrate material 102, first oxide material 104, hard mask material 106, second oxide material 108, first sacrificial material 110, carbon-containing material 116, DARC material 118 and photoresist material 120 are the same.

[0103] Figure 2B It is shown Figure 2A A simplified top view of two of the lines 218 in the photoresist material 216 of the microelectronic device 200. (Common Reference) Figure 2A and Figure 2B The lines 218 of the photoresist material 216 can be spaced apart from each other by grooves 220. The lines 218 can present a so-called braided pattern, with each line 218 exhibiting peaks 222 separated from each other by valleys 223. In some embodiments, the lines 218 present a sinusoidal shape.

[0104] Now for reference Figure 2C and Figure 2D Photoresist material 216 ( Figure 2A The photoresist material 216 is exposed to one or more etching (e.g., trimming) chemical reactions to reduce the width of lines 218 of the photoresist material 216. This process reduces the width of lines 218. Figure 2A , Figure 2B After the width of the photoresist material 216 is determined, the exposed portions of the DARC material 214 and the carbon-containing material 212 can be removed via the trimming lines 218 of the photoresist material 216. After removing the exposed portions of the DARC material 214 and the carbon-containing material 212, the photoresist material 216 can be removed, for example, by stripping.

[0105] Continue to refer to Figure 2C The exposed portion of the sacrificial material 210 can be removed using DARC material 214 and carbon-containing material 212. After removing the exposed portion of the sacrificial material 210, DARC material 214 and carbon-containing material 212 can be removed.

[0106] Spacers 224 may be formed on the side of the sacrificial material 210 to form second lines 226. After the spacers 224 are formed, the sacrificial material 210 may be removed to form the second lines 226 spaced apart by gaps 228. The gaps 228 may be formed by the sacrificial material 210 ( Figure 2C The dimensions of the spacer (e.g., in the X direction, in the Y direction) are defined. Spacer 224 may be defined by spacer 130 (referenced above). Figure 1C The spacer 224 may be formed of and comprise one or more materials as described in the description. As a non-limiting example, the spacer 224 may comprise a carbon-containing material (e.g., silicon carbon nitride (SiCN)), an oxynitride material (e.g., silicon oxynitride, silicon carbon oxynitride (SiOCN)) or another material.

[0107] The spacer 224 may be presented with a pitch P2 in the range of about 15 nanometers (nm) to about 30 nm, for example, about 15 nm to about 20 nm, about 20 nm to about 25 nm, or about 25 nm to about 30 nm.

[0108] The second lines 226 may each individually exhibit a substantially sinusoidal shape (e.g., substantially corresponding to a sine wave). In some embodiments, each of the second lines 226 of the spacer 224 exhibits an amplitude A in the range of about 2 nm to about 10 nm, such as about 2 nm to about 4 nm, about 4 nm to about 6 nm, or about 6 nm to about 10 nm. In some embodiments, the amplitude is about 5 nm. The second lines 226 may each individually exhibit a period λ in the range of about 30 nm to about 40 nm, such as about 30 nm to about 35 nm, or about 35 nm to about 40 nm.

[0109] refer to Figure 2E After the spacer 224 is formed, as described above... Figure 1E As mentioned above, sacrificial material 210 ( Figure 2C The second sacrificial material 114 can be selectively removed from the microelectronic device 200. During the removal of the sacrificial material 210 ( Figure 2CAfter that, the bottom layer material 230 can be formed above the spacer 224 and in the gap 228 between the spacers 224. Figure 2D Within the substrate, a multilayer resist material 232 may be formed on top of the base material 230. The base material 230 may be formed from an additional base material 134 as described above. Figure 1K The material described herein forms and comprises one or more of the materials, and the multilayer resist material 232 may be derived from the multilayer resist material 136 mentioned above. Figure 1K () describes one or more of the materials that form and contain one or more of the materials.

[0110] In some embodiments, the multilayer resist material 232 may be formed and patterned, for example, by extreme ultraviolet patterning. Trench 234 may be formed in the multilayer resist material 232. In some embodiments, as referenced above, trench 238 (… Figure 1K As described, the trench 234 may extend at an angle θ relative to the axis (e.g., the X-axis) of the microelectronic device 200. In some embodiments, the angle θ is in the range of about (20) degrees to about seventy (70) degrees, for example about forty-one (41) degrees.

[0111] In some embodiments, exposed portions of the underlying material 230 may be removed via trench 234 to expose portions of the second oxide material 208. (See reference...) Figure 2F The exposed portions of the second oxide material 208 and spacer 224 can be removed via trench 234. Removing the second oxide material 208 can form a pattern of the isolation structure 236 of the spacer 224. In some embodiments, the multilayer resist material 232 can be removed before removing the exposed portions of the second oxide material 208. After removing the exposed portions of the second oxide material 208, the underlayer material 230 can be removed. In some embodiments, as referred above, removing the underlayer material 132 ( Figure 1G As described, the underlying material 230 has plasma.

[0112] refer to Figure 2G Second oxide material 208 ( Figure 2F The exposed portion of ) can be separated by spacer 224 ( Figure 2F The spacer 224 can be removed. In some embodiments, the exposed portion of the hard mask material 206 can be removed by the second oxide material 208, and the second oxide material 208 can be removed. Removing the exposed portion of the hard mask material 206 can transfer the pattern of the isolation structure 236 onto the hard mask material 206. Each of the first oxide material 204 and the substrate material 202 can be patterned by the hard mask material 206 to form a trench 238 in the substrate material 202. The location of the trench 238 can correspond to the gap 228. Figure 2D ) and trench 234 ( Figure 2F The position of ).

[0113] refer to Figure 2H The insulating material 240 may be formed above the microelectronic device 200 and in the trench 238 within the substrate material 202. Figure 2G Insulating material 240 can be derived from insulating material 144 (see above). Figure 1N The insulating material 240 may be formed from or comprise one or more of the materials described herein. In some embodiments, the insulating material 240 comprises silicon dioxide.

[0114] In the trench 238 of the substrate material 202 Figure 2G After the insulating material 240 is formed inside, the hard mask material 206 and the first oxide material 204 can be selectively removed, leaving a pattern of the isolated memory cell structure 245 including the substrate material 202.

[0115] As referenced above Figures 10 to 1S As described, additional processing actions can be performed to complete the microelectronic device 200. Figure 2I yes Figure 2H A simplified top view of a microelectronic device, and Figure 2J This is a simplified top view of one of the isolated memory cell structures 245 after further processing has been performed. As a non-limiting example, word lines 264 and digital lines 278 may be formed within the microelectronic device 200, as referenced above. Figures 10 to 1S As described, it is used to form word line 164 and number line 178.

[0116] refer to Figure 2J The isolated memory cell structure 245 may be S-shaped, each S-shape individually comprising a central portion 250 laterally (e.g., in the X direction, in the Y direction) located between end portions 252. The central portion 250 may be defined by substantially parallel and linear walls 254 extending substantially parallel to, for example, digital lines 278. In some embodiments, the longitudinal axis of the central portion 250 is substantially aligned with and parallel to the digital lines 278. The end portions 252 may comprise, for example, portions formed in a multilayer resist material 232 (… Figure 2E )Middle groove 234( Figure 2E The wall 256 is defined as substantially parallel and linear. In some embodiments, the lateral end portion of the end portion 252 may present an arcuate surface 258, which may be made of, for example, a photoresist material 216 ( Figure 2A , Figure 2B ) line 218 ( Figure 2A , Figure 2B The shape of the line 218 further defines the spacer 224. Figure 2C , Figure 2D) line 226 ( Figure 2C , Figure 2D (The shape of)

[0117] Continue to refer to Figure 2J As mentioned above (refer to the reference) Figures 10 to 1S As described in the isolated memory cell structure 145, the isolated memory cell structure 245 may each include a digital line contact area 260 located at the central portion 250 and a memory node contact area 262 located at each end portion 252.

[0118] although Figures 2A to 2J Microelectronic devices 200 have been described and shown to include isolated memory cell structures 245 having a particular shape, but this disclosure is not so limited. Figure 3A This is a simplified partial perspective view of a microelectronic device 300 according to an embodiment of the present disclosure. Except that the multilayer resist material 232 may not include trenches 234. Figure 2E However, apart from the pattern that may include the hole 302, the microelectronic device 300 may be substantially the same as... Figure 2E The same as the microelectronic device 200.

[0119] refer to Figure 3B The underlying material 230 exposed through hole 302 can be removed. Figure 3A The exposed portion of the substrate 230 is used to form a hole in the substrate 230. After removing the exposed portion of the substrate 230, the multilayer resist material 232 can be removed. The hole in the substrate 230 exposes a portion of the spacer 224, which can be removed through the hole in the substrate 230 to form a pattern of the isolation structure 304 of the spacer 224. The adjacent isolation structure 304 can be removed through the hole 302 ( Figure 3A The sizes and spacing of the spaces are separated from each other.

[0120] refer to Figure 3C As mentioned above (refer to the reference) Figure 2G As described, isolation structure 304 ( Figure 3B The pattern can be transferred onto the hard mask material 206, the first oxide material 204, and the substrate material 202. For example, the exposed portion of the second oxide material 208 can be removed by the spacer 224, and the spacer 224 can be removed. The exposed portions of the first oxide material 204 and the substrate material 202 can be removed by the hard mask material 206, and the trench 308 can be formed within the substrate material 202.

[0121] refer to Figure 3D As mentioned above, see insulation material 240 ( Figure 2H As described, insulating material 310 can be formed above microelectronic device 300 and in trenches 308 of substrate material 202. Figure 3CThe insulating material 310 may comprise one or more materials described above with reference to the insulating material 240. In some embodiments, the insulating material 310 comprises silicon dioxide.

[0122] After the insulating material 310 is formed, the hard mask material 206 and the first oxide material 204 can be removed. Removing the hard mask material 206 and the first oxide material 204 leaves at least partially exposed by the hole 302. Figure 3A The pattern of the isolated memory cell structure 312 of the substrate material 202 is defined.

[0123] Figure 3E This is after further processing. Figure 3D A simplified top view of a microelectronic device 300. As a non-limiting example, see above reference. Figures 10 to 1S As described in the microelectronic device 100, the microelectronic device 300 may be further processed to include digital line contacts (not shown), memory node contacts (not shown), digital lines 378, and word lines 364. (See above reference...) Figures 10 to 1S As described, storage node contacts can be formed in contact with the isolated memory cell structure 312 at the storage node contact area (not shown), and digital line contacts can be formed in contact with the digital line contact area (not shown) of the memory cell structure 312.

[0124] Except for the isolated memory cell structure 312, which may not include the central portion 250 ( Figure 2J The basically linear wall 254 ( Figure 2J ) and end portion 252 ( Figure 2J The basically linear wall 256 ( Figure 2J Apart from the isolation memory cell structure 312, it can be substantially similar to Figure 2I and Figure 2J The isolated memory cell structure. Specifically, refer to... Figure 3E The central portion 350 of each of the isolated memory cell structures 312 can be made up of spacers 224. Figure 3B The surface is defined by an arcuate (e.g., curved) surface, which is further defined by a photoresist material 216. Figure 2A , Figure 2B ) line 218 ( Figure 2A , Figure 2B The central portion 350 and the end portion 352 may each individually include an arcuate surface and may substantially contain no substantially linear surface.

[0125] Continue to refer to Figure 3EIn some embodiments, the lateral terminal portion of the end portion 352 of the isolated memory cell structure 312 may be defined by an arcuate surface 354, said arcuate surface 354 being composed of a multilayer resist material 232 ( Figure 3A Hole 302 ( Figure 3A The size and shape of the portion are defined. For example, the dashed circle 360 ​​corresponds to the hole 302 and defines the arcuate surface 354 of the isolated memory cell structure 312. In some embodiments, the arcuate surface 354 of the end portion 352 includes an inwardly oriented portion between opposite sides of the end portion 352. The inwardly oriented portion may be closer to the center portion 350 than other portions of the arcuate surface 354 of the lateral terminal portion of the end portion 352.

[0126] Figures 4A to 4D A method for forming a microelectronic device according to an additional embodiment of the present disclosure is shown. Figure 4A A simplified partial top view of a microelectronic device 400 according to an embodiment of the present disclosure is shown. The microelectronic device 400 may include a sacrificial material 402 covering a hard mask material (not shown). The hard mask material may be the same as the hard mask material 106 described above (…). Figure 1A The basic structure is the same. A hard mask material can be vertically overlaid on a substrate material, which can be the same as described above. Figure 1A The substrate material 102 described is essentially the same.

[0127] The pattern of the first structure 404 can be patterned in the sacrificial material 402, for example, by extreme ultraviolet lithography. As a non-limiting example, a photoresist material can be formed over the sacrificial material 402, and the pattern of the first structure 404 can be printed on the photoresist material. The pattern of the first structure 404 can be formed (e.g., printed) as known in the art. In some embodiments, portions of the photoresist material other than those corresponding to the first structure 404 can be removed. The pattern of the first structure 404 can be transferred to the sacrificial material 402 by the photoresist material, and the photoresist material can be removed from the surface of the sacrificial material 402 (e.g., peeled off), leaving the pattern of the first structure 404 in the sacrificial material 402.

[0128] Now for reference Figure 4B The first spacer 406 may be formed on the side of the first structure 404. The first spacer 406 may be formed from the spacer 130 mentioned above. Figure 1C The material described herein may be formed in or comprise one or more of the materials described herein. In some embodiments, the first spacer 406 comprises a carbon-containing material, such as silicon carbide.

[0129] refer to Figure 4CA pattern for the second structure 408 can be formed within the sacrificial material 402. In some embodiments, the pattern for the second structure 408 can be formed using substantially the same method as that used to form the pattern for the first structure 404. As a non-limiting example, in some embodiments, a photoresist material can be formed over the microelectronic device 400 and patterned, for example, by extreme ultraviolet lithography, to form the pattern for the second structure 408.

[0130] Except that the pattern of the second structure 408 can be moved laterally (e.g., in the X direction, in the Y direction) relative to the pattern of the first structure 404, the pattern of the second structure 408 may be substantially identical to the pattern of the first structure 404. The pattern of the second structure 408 in the photoresist material may be transferred to the sacrificial material 402. In some embodiments, a first spacer 406 surrounding the first structure 404 may facilitate the alignment of the second structure 408 relative to the first structure 404. In some embodiments, the first spacer 406 may compensate for possible misalignment (e.g., misfit) of the second structure 408 during its formation. In other words, the first spacer 406 may facilitate self-alignment of the second structure 408 with the first structure 404.

[0131] Continue to refer to Figure 4C After the pattern of the second structure 408 is transferred onto the sacrificial material 402, a second spacer 410 may be formed around the second structure 408. The second spacer 410 may be formed of and comprise one or more of the materials described above with reference to the first spacer 406.

[0132] refer to Figure 4D After the second spacer 410 is formed around the second structure 408, hard mask material can be used to fill the remaining portion of the microelectronic device 400 between the first spacer 406 and the second spacer 410. After the portion of the microelectronic device 400 is filled with hard mask material, the first spacer 406 and the second spacer 410 can be selectively removed, leaving the first structure 404, the second structure 408, and the third structure 412, including the sacrificial material 402. (Refer to the above text) Figure 1N , Figure 2H and Figure 3D As described, the patterns of the first structure 404, the second structure 408, and the third structure 412 can be transferred to the underlying hard mask material and the underlying substrate material to form an isolated memory cell structure.

[0133] Continue to refer to Figure 4D Each of the first structure 404, the second structure 408, and the third structure 412 can be separated from each other by a groove 416 formed of a base material at a position corresponding to the first spacer 406 and the second spacer 410.

[0134] In some embodiments, the first structure 404 may have substantially the same size and shape as the second structure 408. The third structure 412 may have a different size and shape than the first structure 404 and the second structure 408. In some embodiments, the third structure 412 has a relatively larger dimension along the longitudinal axis (e.g., in the Y direction) compared to the first structure 404 and the second structure 408. In some embodiments, as referenced above, the isolated memory cell structure 245 ( Figure 2J As described above, each of the first structure 404, the second structure 408, and the third structure 412 includes a central portion having substantially parallel sides and an end portion angled relative to the central portion, and also having substantially parallel sides. In some embodiments, as described above with reference to the isolated memory cell structure 245, the lateral terminal portions of the end portions of the first structure 404, the second structure 408, and the third structure 412 may not include an arcuate surface. In some embodiments, each of the first structure 404, the second structure 408, and the third structure 412 presents a “Z-shape.”

[0135] As mentioned above, refer to the isolated memory cell structure 145 ( Figure 10 ), isolated memory cell structure 245 ( Figure 2J ) and memory cell structure 312 ( Figure 3E As described above, the microelectronic device 400 can withstand additional processing actions. For example, as referenced above... Figures 10 to 1R As described in the microelectronic device 100, the microelectronic device 400 may be further processed to include digital line contacts (not shown), memory node contacts (not shown), digital lines (not shown), and word lines (not shown). (See above reference...) Figures 10 to 1S As described, the memory node contact can be formed by contacting the isolated memory cell structure of the microelectronic device 400 in the memory node contact area, and the digital line contact can be formed by contacting the digital line contact area of ​​the memory cell structure.

[0136] Figure 5 A simplified partial top view is shown for illustrating an additional embodiment of the microelectronic device 500 according to the present disclosure. The microelectronic device 500 may include a pattern of a first structure 502, a pattern of a second structure 504, and a pattern of a third structure 506 spaced apart from adjacent structures by trenches 508. Each of the first structure 502, the second structure 504, and the third structure 506 may include substantially the same material composition and may be formed in a substrate material comprising a semiconducting material, such as one or more of the materials described above with reference to substrate material 102.

[0137] In some embodiments, each of the first structure 502, the second structure 504, and the third structure 506 may have substantially the same size and shape. In some embodiments, the first structure 502, the second structure 504, and the third structure 506 are identical to the first structure 404 ( Figure 4D ) and second structure 408 ( Figure 4D They are basically the same.

[0138] In some embodiments, the microelectronic device 500 is formed using extreme ultraviolet (EUV) lithography. As a non-limiting example, the first structure 502 can be formed in a hard mask material using EUV patterning (e.g., printed onto a hard mask material). In some embodiments, the pattern of the first structure 502 can be formed in a hard mask material, for example, by EUV patterning. In some embodiments, as referenced above to the first structure 404 (… Figure 4A As described above regarding the formation of the first structure 502, a photoresist material can be formed over the hard mask material, and a first structure 502 can be printed on the photoresist material. Following the formation of the first structure 502, each of the second structure 504 and the third structure 506 can be formed in the hard mask material. After the patterns of the first structure 502, the second structure 504, and the third structure 506 are formed in the hard mask material, the hard mask material can be used to transfer the first structure 502, the second structure 504, and the third structure 506 onto the underlying substrate material to form an isolated memory cell structure.

[0139] As referenced above Figure 4D As described in the microelectronic device 400, the microelectronic device 500 can withstand additional processing operations. For example, as referenced above... Figures 10 to 1S As described in the microelectronic device 100, the microelectronic device 500 may be further processed to include digital line contacts (not shown), memory node contacts (not shown), digital lines (not shown), and word lines (not shown). (See above reference...) Figures 10 to 1S As described, the memory node contact can be formed by contacting the isolated memory cell structure of the microelectronic device 500 in the memory node contact area, and the digital line contact can be formed by contacting the digital line contact area of ​​the memory cell structure.

[0140] Therefore, according to embodiments of this disclosure, a microelectronic device includes a memory cell structure extending from a substrate material. At least one memory cell structure of the memory cell structure includes: a central portion that contacts a digital line, extends from the substrate material, and includes opposing arcuate surfaces; an end portion that contacts a memory node contact on a side of the central portion; and an additional end portion that contacts additional memory node contacts on an opposing side of the central portion.

[0141] Therefore, according to an additional embodiment of this disclosure, a microelectronic device includes memory cell structures, each of which includes a semiconducting pillar structure extending from a substrate material. At least one memory cell structure of the memory cell structure includes: a first end portion and a second end portion, each of the first end portion and the second end portion individually including at least one arcuate surface; a central portion located between the first end portion and the second end portion, the central portion including a substantially parallel surface extending between the first end portion and the second end portion, at least one surface of the substantially parallel surface being connected to the at least one arcuate surface of the first end portion; a memory node contact contacting the first end portion; and a digital line contact contacting the central portion.

[0142] Therefore, according to an additional embodiment of the present disclosure, a method of forming a microelectronic device includes: forming lines of a material comprising at least some nonlinear surfaces by extreme ultraviolet lithography; forming spacers on the lines of the material; removing the lines of the material; forming a mask over the spacers; removing a portion of the spacers through the mask to form isolation structures, each isolation structure including a central portion between a first end portion and a second end portion; and transferring a pattern of the isolation structures onto a semiconductive material.

[0143] Therefore, according to another embodiment of this disclosure, a method of forming a microelectronic device includes: forming a pattern of a first structure in a hard mask material by extreme ultraviolet lithography; forming a first spacer on the first structure; forming a pattern of a second structure in the hard mask material; forming a second spacer on the second structure; forming a material in a region between the first spacer and the second spacer to form a pattern of a third structure; removing the first spacer and the second spacer; and removing portions of the semiconductive material exposed beneath the hard mask material through the first structure, the second structure, and the third structure to form the pattern of the first structure, the second structure, and the third structure in the semiconductive material.

[0144] Therefore, according to yet another embodiment of this disclosure, a method of forming a microelectronic device includes: forming a pattern of a first structure in a hard mask material; forming a pattern of a second structure offset from the first structure in the hard mask material; and forming a pattern of a third structure laterally offset from the first and second structures in the hard mask material, the third structure having substantially the same size and shape as the first and second structures.

[0145] Microelectronic devices comprising microelectronic devices formed according to embodiments described herein (e.g., one or more of microelectronic devices 100, 200, 300, 400, 500) can be used in embodiments of the electronic systems of this disclosure. For example, Figure 6 This is a block diagram of an electronic system 603 according to an embodiment of the present disclosure. The electronic system 603 may include, for example, a computer or computer hardware component, a server or other networking hardware component, a cellular phone, a digital camera, a personal digital assistant (PDA), a portable media (e.g., music) player, etc. or Tablet computers with Wi-Fi or cellular capabilities, e-book readers, navigation devices, etc. Electronic system 603 includes at least one memory device 605. Memory device 605 may include embodiments of microelectronic devices, such as those previously described herein (e.g., previously referenced...). Figures 1A to 5 The microelectronic devices described are one or more of the following: 100, 200, 300, 400, and 500.

[0146] The electronic system 603 may further include at least one electronic signal processor device 607 (generally referred to as a “microprocessor”). The electronic signal processor device 607 may optionally include embodiments of the microelectronic devices previously described herein (e.g., previously referenced...). Figures 1A to 5 The electronic system 603 may further include one or more input devices 609 for users to input information into the electronic system 603, such as a mouse or other pointing device, a keyboard, a touchpad, buttons, and / or a control panel. The electronic system 603 may further include one or more output devices 611 for outputting information (e.g., visual or audio output) to the user, such as a monitor, display, printer, audio output jack, speaker, etc. In some embodiments, the input device 609 and output device 611 may include a single touchscreen device that can be used both to input information into the electronic system 603 and to output visual information to the user. The input device 609 and output device 611 may be electrically connected to one or more of the memory device 605 and the electronic signal processor device 607.

[0147] refer to Figure 7The present disclosure describes a processor-based system 700. The processor-based system 700 may include various microelectronic devices and microelectronic device structures (e.g., microelectronic devices 100, 200, 300, 400, 500) manufactured according to embodiments of the present disclosure. The processor-based system 700 may be any of a variety of types, such as a computer, pager, cellular phone, personal assistant, control circuitry, or other electronic device. The processor-based system 700 may include one or more processors 702 (e.g., microprocessors) to control system functions and request processing within the processor-based system 700. The processor 702 and other sub-components of the processor-based system 700 may include microelectronic devices and microelectronic device structures (e.g., microelectronic devices 100, 200, 300, 400, 500) manufactured according to embodiments of the present disclosure.

[0148] The processor-based system 700 may include a power supply 704 operatively communicatively with the processor 702. For example, if the processor-based system 700 is a portable system, the power supply 704 may include one or more of a fuel cell, an energy purification device, a permanent battery, a replaceable battery, and a rechargeable battery. For example, the power supply 704 may also include an AC adapter; thus, the processor-based system 700 can be plugged into a wall outlet. For example, the power supply 704 may also include a DC adapter, allowing the processor-based system 700 to be plugged into a vehicle cigarette lighter or a vehicle power port.

[0149] Various other devices may be coupled to processor 702 depending on the functions performed by processor-based system 700. For example, user interface 706 may be coupled to processor 702. User interface 706 may include input devices such as buttons, switches, keyboards, light pens, mice, and digitizers and styluses, touchscreens, voice recognition systems, microphones, or combinations thereof. Display 708 may also be coupled to processor 702. Display 708 may include LCD displays, SED displays, CRT displays, DLP displays, plasma displays, OLED displays, LED displays, 3D projections, audio displays, or combinations thereof. Furthermore, RF subsystem / baseband processor 710 may also be coupled to processor 702. RF subsystem / baseband processor 710 may include antennas coupled to RF receivers and RF transmitters (not shown). Communication port 712 or more may also be coupled to processor 702. The communication port 712 may be adapted to couple to one or more peripheral devices 714, such as a modem, printer, computer, scanner or camera, or to a network, such as a local area network, remote local area network, intranet or Internet.

[0150] Processor 702 can control processor-based system 700 by implementing software programs stored in memory. For example, the software programs may include operating systems, database software, graphics software, word processing software, media editing software, or media playback software. Memory is operatively coupled to processor 702 to store and facilitate the execution of various programs. For example, processor 702 may be coupled to system memory 716, which may include one or more of spin torque transfer magnetic random access memory (STT-MRAM), magnetic random access memory (MRAM), dynamic random access memory (DRAM), static random access memory (SRAM), racetrack memory, and other known memory types. System memory 716 may include volatile memory, non-volatile memory, or combinations thereof. System memory 716 is typically large enough to dynamically store loaded applications and data. In some embodiments, system memory 716 may include semiconductor devices, such as the microelectronic devices described above (e.g., microelectronic devices 100, 200, 300, 400, 500).

[0151] Processor 702 may also be coupled to non-volatile memory 718, which does not imply that system memory 716 is necessarily volatile. Non-volatile memory 718 may include one or more of STT-MRAM, MRAM, such as EPROM, resistive read-only memory (RROM), and flash memory to be used in conjunction with system memory 716. The size of non-volatile memory 718 is typically chosen to be sufficient to store only the necessary operating system, applications, and fixed data. Furthermore, non-volatile memory 718 may include, for example, mass storage such as disk drive memory, such as a hybrid drive containing resistive memory, or other types of non-volatile solid-state memory. Non-volatile memory 718 may include microelectronic devices, such as those described above (e.g., microelectronic devices 100, 200, 300, 400, 500).

[0152] Therefore, according to embodiments of this disclosure, an electronic system includes an input device, an output device, a processor device operatively coupled to the input and output devices, and a memory device operatively coupled to the processor device and including at least one microelectronic device. The at least one microelectronic device includes memory cell structures spaced apart from each other. The at least one memory cell structure includes: a central portion between two end portions, each of the two end portions being oriented at an angle relative to the central portion; and a digital line electrically connected to the central portion, the surface of the digital line being oriented at an angle relative to the surface of the central portion.

[0153] Additional non-limiting example embodiments of this disclosure are described below.

[0154] Example 1: A microelectronic device comprising: a memory cell structure extending from a substrate material, at least one of the memory cell structures comprising: a central portion contacting a digital line contact, extending from the substrate material and including an opposing arcuate surface; an end portion contacting a memory node contact on a side of the central portion; and another end portion contacting an additional memory node contact on an opposite side of the central portion.

[0155] Example 2: According to the microelectronic device of Example 1, the longitudinal axis of the end portion of the at least one memory cell structure is oriented at a certain angle relative to the longitudinal axis of the central portion.

[0156] Example 3: In the microelectronic device according to Example 1 or Example 2, the central portion of the at least one memory cell structure presents a width close to the minimum width of the digital line contact.

[0157] Example 4: A microelectronic device according to any one of Examples 1 to 3, wherein the end portion of the at least one memory cell structure includes at least one arcuate surface and at least one substantially linear surface.

[0158] Example 5: A microelectronic device according to any one of Examples 1 to 4, wherein the distal end of the terminal portion of the at least one memory cell structure presents an arcuate surface.

[0159] Example 6: A microelectronic device according to any one of Examples 1 to 5, wherein the end portion of the at least one memory cell structure includes a relative arcuate surface.

[0160] Example 7: A microelectronic device according to any one of Examples 1 to 6, wherein the at least one memory cell structure is located between at least two other memory cell structures.

[0161] Example 8: In the microelectronic device according to Example 7, the distance between the at least one memory cell structure and the first of the at least two other memory cell structures is different from the distance between the at least one memory cell structure and the second of the at least two other memory cell structures.

[0162] Example 9: A microelectronic device according to any one of Examples 1 to 8, further comprising a word line between the central portion and the terminal portion of the at least one memory cell structure.

[0163] Example 10: The microelectronic device according to Example 9 further includes an additional word line between the central portion and another end portion of the at least one memory cell structure.

[0164] Example 11: A microelectronic device comprising: a memory cell structure, each including a semiconducting pillar structure extending from a substrate material, at least one memory cell structure comprising: a first end portion and a second end portion, each of the first end portion and the second end portion individually including at least one arcuate surface; a central portion between the first end portion and the second end portion, the central portion including a substantially parallel surface extending between the first end portion and the second end portion, at least one surface of the substantially parallel surface being connected to the at least one arcuate surface of the first end portion; a memory node contact contacting the first end portion; and a digital line contact contacting the central portion.

[0165] Example 12: The microelectronic device according to Example 11, wherein the first end portion is substantially free of linear surfaces.

[0166] Example 13: The microelectronic device according to Example 11 or Example 12, wherein each of the memory cell structures presents substantially the same size and shape.

[0167] Example 14: A microelectronic device according to Example 11 or Example 12, wherein at least some of the memory cell structures present a different size and shape than other memory cell structures of the memory cell structure.

[0168] Example 15: A microelectronic device according to any one of Examples 11 to 14, wherein the longitudinal axis of the first end portion of the at least one memory cell structure is substantially parallel to the longitudinal axis of the second end portion of the at least one memory cell structure.

[0169] Example 16: The microelectronic device according to Example 15, wherein the longitudinal axis of the central portion of the at least one memory cell structure is oriented at an angle ranging from about thirty (30) degrees to about sixty (60) degrees relative to the longitudinal axis of the first end portion of the at least one memory cell structure.

[0170] Example 17: A microelectronic device according to any one of Examples 11 to 16, wherein the first end portion of the at least one memory cell structure includes a terminal portion, the terminal portion including an arcuate surface.

[0171] Example 18: A microelectronic device according to any one of Examples 11 to 17, wherein the first end portion of the at least one memory cell structure is substantially aligned with the first end portion of an additional memory cell structure adjacent to the at least one memory cell structure.

[0172] Example 19: A microelectronic device according to any one of Examples 11 to 18, further comprising: a digital line electrically connected to a digital line contact; and a word line extending perpendicularly to the digital line between the first terminal portion and the central portion of the at least one memory cell structure.

[0173] Example 20: A method for forming a microelectronic device, the method comprising: forming lines of a material including at least some nonlinear surfaces by extreme ultraviolet lithography; forming spacers on the lines of the material; removing the lines of the material; forming a mask over the spacers; removing a portion of the spacers through the mask to form isolation structures, each isolation structure including a central portion between a first end portion and a second end portion; and transferring a pattern of the isolation structures onto a semiconductive material.

[0174] Example 21: The method according to Example 20, wherein forming a line of material comprising at least some nonlinear surfaces includes forming a line exhibiting a sinusoidal shape.

[0175] Example 22: According to the method of Example 20, the forming of a line of material comprising at least some nonlinear surfaces includes forming a line comprising a first portion and a second portion, each line comprising the first portion, the first portion comprising an arcuate surface and having a size larger than the second portion between adjacent first portions of the line.

[0176] Example 23: The method according to any of Examples 20 to 22, wherein forming a mask over the spacer includes forming the mask to include a groove extending at an angle relative to the spacer.

[0177] Example 24: The method according to Example 23 further includes removing a portion of the spacer through the groove in the mask.

[0178] Example 25: The method according to any of Examples 20 to 24, wherein forming a mask over the spacer includes forming the mask to include a circular opening.

[0179] Example 26: The method according to Example 25 further includes removing a portion of the spacer through the circular opening in the mask.

[0180] Example 27: The method according to any of Examples 20 to 26, wherein removing a portion of the spacer through the mask to form an isolation structure includes forming an isolation structure including a central portion, the central portion including opposing arcuate surfaces.

[0181] Example 28: The method according to any of Examples 20 to 27, wherein removing a portion of the spacer through the mask to form an isolation structure includes forming the isolation structure to include a central portion between a first end portion and a second end portion, each of the first end portion and the second end portion individually including a terminal portion, the terminal portion including an arcuate surface.

[0182] Example 29: A method for forming a microelectronic device, the method comprising: forming a pattern of a first structure in a hard mask material by extreme ultraviolet lithography; forming a first spacer on the first structure; forming a pattern of a second structure in the hard mask material; forming a second spacer on the second structure; forming a material in a region between the first spacer and the second spacer to form a pattern of a third structure; removing the first spacer and the second spacer; and removing portions of a semiconductive material exposed beneath the hard mask material through the first structure, the second structure, and the third structure to form a pattern of the first structure, the second structure, and the third structure in the semiconductive material.

[0183] Example 30: The method according to Example 29, wherein forming the pattern of the second structure includes forming a second structure having substantially the same size and shape as the first structure.

[0184] Example 31: The method according to Example 29 or Example 30, wherein forming the pattern of the third structure includes forming the third structure to present a different size and shape from the first structure and the second structure.

[0185] Example 32: A method of forming a microelectronic device, the method comprising: forming a pattern of a first structure in a hard mask material; forming a pattern of a second structure offset from the first structure in the hard mask material; and forming a pattern of a third structure laterally offset from the first and second structures in the hard mask material, the third structure having substantially the same size and shape as the first and second structures.

[0186] Example 33: The method according to Example 32, wherein forming the pattern of the first structure includes forming the first structure by extreme ultraviolet lithography.

[0187] Example 34: An electronic system comprising: an input device; an output device; a processor device operatively coupled to the input device and the output device; and a memory device operatively coupled to the processor device and including at least one microelectronic device, the at least one microelectronic device including: memory cell structures spaced apart from each other, the at least one memory cell structure including: a central portion between two end portions, each end portion oriented at an angle relative to the central portion; and a digital line electrically connected to the central portion, the surface of the digital line oriented at an angle relative to the surface of the central portion.

[0188] While certain illustrative embodiments have been described in conjunction with the drawings, those skilled in the art will recognize and understand that the embodiments included in this disclosure are not limited to those explicitly shown and described herein. Rather, various additions, deletions, and modifications can be made to the embodiments described herein without departing from the scope of the embodiments encompassed by this disclosure (such as those claimed herein, including legal equivalents). Furthermore, features of one disclosed embodiment may be combined with features of another disclosed embodiment while still being included within the scope of this disclosure.

Claims

1. A microelectronic device comprising: A memory cell structure comprising elongated pillars extending from a substrate material, wherein at least one memory cell structure in the memory cell structure includes: A central portion that contacts a digital line contact element, the central portion extending from the base material and including inwardly oriented opposing arcuate surfaces to define a minimum width of the central portion; The end portion contacts the storage node contact on the side of the central portion; and The other end portion contacts an additional storage node contact on the opposite side of the central portion.

2. The microelectronic device according to claim 1, wherein the longitudinal axis of the end portion of the at least one memory cell structure is oriented at an angle relative to the longitudinal axis of the central portion.

3. The microelectronic device of claim 1, wherein the central portion of the at least one memory cell structure presents a width close to the minimum width of the digital line contact.

4. The microelectronic device of claim 1, wherein the terminal portion of the at least one memory cell structure comprises at least one arcuate surface and at least one substantially linear surface.

5. The microelectronic device of claim 1, wherein the distal end of the terminal portion of the at least one memory cell structure presents an arcuate surface.

6. The microelectronic device of claim 1, wherein the end portion of the at least one memory cell structure includes an opposing arcuate surface.

7. The microelectronic device of claim 1, wherein the at least one memory cell structure is located between at least two other memory cell structures.

8. The microelectronic device of claim 7, wherein the distance between the at least one memory cell structure and the first of the at least two other memory cell structures is different from the distance between the at least one memory cell structure and the second of the at least two other memory cell structures.

9. The microelectronic device according to any one of claims 1 to 8, further comprising a word line between the central portion and the terminal portion of the at least one memory cell structure.

10. The microelectronic device of claim 9, further comprising an additional word line between the central portion and another end portion of the at least one memory cell structure.

11. A method of forming a microelectronic device, the method comprising: Lines of material comprising at least some nonlinear surfaces are formed by extreme ultraviolet lithography; Spacers are formed along the lines of the material; Remove the line from the material; A mask is formed above the spacer; A portion of the spacer is removed through the mask to form an isolation structure; as well as The pattern of the isolation structure is transferred onto a semiconductive material to form a memory cell structure, the memory cell structure including elongated pillars extending from a substrate material, and at least one memory cell structure comprising: A central portion that contacts a digital line contact element, the central portion extending from the base material and including inwardly oriented opposing arcuate surfaces to define a minimum width of the central portion; The end portion contacts the storage node contact on the side of the central portion; and The other end portion contacts an additional storage node contact on the opposite side of the central portion.

12. The method of claim 11, wherein forming a line of material comprising at least some nonlinear surfaces comprises forming a line exhibiting a sinusoidal shape.

13. The method of claim 11, wherein forming a line of material comprising at least some nonlinear surfaces comprises forming a line comprising a first portion and a second portion, each line comprising the first portion, the first portion comprising an arcuate surface and having a size larger than the second portion between adjacent first portions of the line.

14. The method of claim 11, wherein forming a mask over the spacer includes forming the mask to include a groove extending at an angle relative to the spacer.

15. The method of claim 14, further comprising removing a portion of the spacer through the groove in the mask.

16. The method of claim 11, wherein forming a mask over the spacer includes forming the mask to include a circular opening.

17. The method of claim 16, further comprising removing a portion of the spacer through the circular opening in the mask.

18. The method of any one of claims 11 to 17, wherein removing a portion of the spacer through the mask to form an isolation structure includes forming the isolation structure to include the central portion, the central portion including the inwardly oriented opposing arcuate surfaces.

19. The method of any one of claims 11 to 17, wherein removing a portion of the spacer through the mask to form an isolation structure includes forming the isolation structure to include the central portion between the end portion and the other end portion, each of the end portion and the other end portion individually including a terminal portion, the terminal portion including an arcuate surface.

20. An electronic system comprising: Input device; Output device; A processor device operatively coupled to the input device and the output device; as well as A memory device operatively coupled to the processor device and including at least one microelectronic device, the at least one microelectronic device comprising: A memory cell structure spaced apart from each other, at least one memory cell structure comprising an elongated pillar, the elongated pillar comprising: The central portion extends from the base material, contacts the digital line contact, and includes inwardly oriented opposing arcuate surfaces to define the minimum width of the central portion. The end portion contacts the storage node contact on the side of the central portion; and The other end portion contacts an additional storage node contact on the opposite side of the central portion; and A digital line electrically connected to a digital line contact, wherein the surface of the digital line is oriented at a certain angle relative to the surface of the central portion.

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