Integrated chip structure and method of forming the same

Abstract

The present invention relates to methods of forming integrated chip structures. The methods include etching a base substrate to form a recess defined by one or more interior surfaces of the base substrate. A doped epitaxial layer is formed along the one or more interior surfaces of the base substrate, and an epitaxial material is formed on horizontally and vertically extending surfaces of the doped epitaxial layer. A first doped photodiode region is formed within the epitaxial material, and a second doped photodiode region is formed within the epitaxial material. The first doped photodiode region has a first doping type, and the second doped photodiode region has a second doping type. Embodiments of the present application also relate to integrated chip structures.

Description

Technical Field

[0001] Embodiments of this application relate to integrated chip structures and methods for forming the same. Background Technology

[0002] An image sensor is a solid-state device configured to convert incident light (e.g., photons) into electrical signals. These electrical signals are then fed to a processor that can convert them into data that can be stored and / or viewed by a user. Integrated circuits (ICs) with image sensors are widely used in modern electronic devices such as mobile phones, security cameras, and medical devices. Summary of the Invention

[0003] Some embodiments of this application provide a method for forming an integrated chip structure, comprising: etching a substrate to form a groove defined by one or more inner surfaces of the substrate; forming a doped epitaxial layer along the one or more inner surfaces of the substrate; forming an epitaxial material on horizontal and vertical extension surfaces of the doped epitaxial layer; forming a first doped photodiode region within the epitaxial material, the first doped photodiode region including a first doping type; and forming a second doped photodiode region within the epitaxial material, the second doped photodiode region including a second doping type.

[0004] Other embodiments of this application provide a method for forming an integrated chip structure, comprising: etching a substrate comprising a first semiconductor material to form a groove defined by one or more inner surfaces of the substrate; performing a first deposition process to form a doped epitaxial layer along the one or more inner surfaces of the substrate; performing a second deposition process to form an epitaxial material comprising a second semiconductor material on the doped epitaxial layer, the epitaxial material having a lower dopant concentration than the maximum dopant concentration of the doped epitaxial layer; performing a first implantation process to form a first doped photodiode region within the epitaxial material; and performing a second implantation process to form a second doped photodiode region within the epitaxial material, wherein the second doped photodiode region laterally surrounds the first doped photodiode region.

[0005] Further embodiments of this application provide an integrated chip structure, including: a substrate, including one or more inner surfaces defining a groove within an upper surface of the substrate; an epitaxial material disposed within the groove; a first doped photodiode region disposed within the epitaxial material and including a first doping type; a second doped photodiode region disposed within the epitaxial material and including a second doping type, wherein the second doped photodiode region laterally surrounds the first doped photodiode region; and a doped epitaxial layer horizontally and vertically disposed between the substrate and the epitaxial material, the doped epitaxial layer having the second doping type. Attached Figure Description

[0006] The various aspects of the invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industrial practice, the components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the components may be arbitrarily increased or decreased.

[0007] Figures 1A to 1B Some embodiments of an image sensing structure including a doped epitaxial layer disposed along the outer surface of an epitaxial material comprising a photodetector are shown.

[0008] Figures 2A to 2B Some additional embodiments of an image sensing structure including a doped epitaxial layer disposed along the outer surface of an epitaxial material comprising a photodetector are shown.

[0009] Figures 3 to 4 Cross-sectional views of some additional embodiments of the image sensing structure including the disclosed doped epitaxial layer are shown.

[0010] Figures 5A to 5B Cross-sectional views of some additional embodiments of the image sensing structure including the disclosed doped epitaxial layer are shown.

[0011] Figures 6A to 6B Cross-sectional views of some additional embodiments of an image sensing structure including multiple doped epitaxial layers are shown.

[0012] Figure 7A Cross-sectional views of some embodiments of an image sensing structure including the disclosed doped epitaxial layer are shown.

[0013] Figures 7B to 7D The display shows along Figure 7A The graphs show the dopant concentration distribution of the cross-sectional lines of the image sensing structure in various embodiments.

[0014] Figure 8A Cross-sectional views of some embodiments of an image sensing structure including the disclosed doped epitaxial layer are shown.

[0015] Figures 8B to 8D The display shows along Figure 8A The graphs show the dopant concentration distribution of the cross-sectional lines of the image sensing structure in various embodiments.

[0016] Figure 9A Cross-sectional views of some embodiments of an image sensing structure including the disclosed doped epitaxial layer are shown.

[0017] Figure 9B It shows along Figure 9A A diagram showing some embodiments of the dopant concentration distribution along the cross-sectional lines of an image sensing structure.

[0018] Figure 10 Cross-sectional views of some embodiments of a multidimensional integrated chip structure including a doped epitaxial layer disposed along the outer surface of an epitaxial material including a photodetector are shown.

[0019] Figures 11 to 29 Cross-sectional views of some additional embodiments of a method for forming an integrated chip structure including a doped epitaxial layer disposed along the outer surface of an epitaxial material including a photodetector are shown.

[0020] Figure 30 Flowcharts illustrating some embodiments of a method for forming an integrated chip structure comprising a doped epitaxial layer disposed along the outer surface of an epitaxial material including a photodetector are shown. Detailed Implementation

[0021] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the invention. Of course, these are merely examples and are not intended to limit the invention. For example, in the following description, forming a first component on or over a second component can include embodiments where the first and second components are in direct contact, and can also include embodiments where an additional component can be formed between the first and second components, such that the first and second components are not in direct contact. Furthermore, reference numerals and / or characters may be repeated in various instances of the invention. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0022] Furthermore, for ease of description, this document uses spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” to describe the relationship between one element or component and another (or other elements or components) as shown in the figures. In addition to the orientations shown in the figures, spatial relative terms are intended to include different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein can be interpreted accordingly.

[0023] In recent years, image sensor integrated circuits (ICs) capable of detecting near-infrared (NIR) radiation (e.g., radiation with wavelengths between approximately 900 nm and approximately 2,500 nm) have become increasingly common. One reason is that image sensor ICs capable of detecting NIR can operate effectively in the presence of little to no visible light, making them ideal for machines and / or night vision cameras. Furthermore, because the night sky contains more NIR photons than visible photons, the ability of image sensor ICs to detect NIR radiation allows for the capture of good images without the use of additional illumination (e.g., LEDs), thereby reducing power consumption and increasing battery life associated with the image sensor IC.

[0024] Image sensor ICs typically include image sensing elements (e.g., photodetectors) disposed within a silicon substrate. However, the absorption coefficient of silicon decreases with increasing wavelength of radiation. Therefore, image sensor ICs are typically able to detect NIR radiation with relatively low quantum efficiency (e.g., the ratio of the number of photons contributing to the electrical signal generated by the image sensing element within the pixel region to the number of photons incident on the pixel region).

[0025] Germanium-based photodiodes may offer a better option for NIR photodetectors. This is because germanium is a direct bandgap material and therefore can operate in the NIR spectrum with higher efficiency than silicon. Germanium-based photodiodes can be fabricated by forming a photodetector (e.g., a photodiode) within a germanium-based material formed within a groove in a silicon substrate. However, it has been recognized that defects (e.g., dislocation defects) can form along the interface between the silicon and germanium-based materials during the fabrication of such photodiodes. These defects can cause dark current leakage within the photodetector (e.g., through thermal generation of free charge carriers), thereby degrading the performance of NIR sensing (e.g., limiting NIR applications for 3D sensing).

[0026] In some embodiments, the present invention relates to an integrated chip structure having a photodetector disposed within an epitaxial material (e.g., a germanium-based epitaxial material) within a substrate (e.g., a silicon substrate). The integrated chip structure includes a doped epitaxial layer disposed along the interface between the epitaxial material and the substrate. The doped epitaxial layer has a dopant configured to passivate defects along the interface, thereby reducing the formation (e.g., thermal generation) of free charge carriers that lead to dark current formation. By reducing dark current formation, the performance of the integrated chip structure can be improved. Furthermore, by introducing the dopant into the integrated chip structure using a doped epitaxial layer (e.g., instead of an implantation process), the dopant region can be better controlled, thereby limiting the negative impact of the dopant on the photodetector.

[0027] Figure 1ACross-sectional views of some embodiments of an integrated chip structure 100 including a doped epitaxial layer disposed along the interface between a substrate and an epitaxial material including a photodetector are shown.

[0028] The integrated chip structure 100 includes a substrate 102. The substrate 102 has one or more inner surfaces defining a recess extending into a first surface 102a of the substrate 102. An epitaxial material 104 is disposed within the recess. In some embodiments, the epitaxial material 104 has an upper surface extending between the outermost walls of the substrate 102. In some embodiments, the substrate 102 may include silicon. In some embodiments, the epitaxial material 104 may include a direct bandgap material. In some additional embodiments, the epitaxial material 104 may include a germanium-based material, such as germanium, silicon-germanium, etc.

[0029] A photodetector 105 is disposed within the epitaxial material 104. In some embodiments, the photodetector 105 may include a photodiode. In some such embodiments, the photodetector 105 includes a first doped photodiode region 106 and a second doped photodiode region 108 laterally surrounding the first doped photodiode region 106. The first doped photodiode region 106 may include a first doping type (e.g., n-type doping), and the second doped photodiode region 108 may include a second doping type (e.g., p-type doping). In some embodiments, such as Figure 1B As shown in top view 122, the second doped photodiode region 108 may enclose the first doped photodiode region 106. In some additional embodiments, the second doped photodiode region 108 may enclose the first doped photodiode region 106 in a continuous and uninterrupted loop.

[0030] During operation, incident photons 115 striking the epitaxial material 104 generate electron-hole pairs comprising electrons 116 and holes 118. A bias voltage can be applied to the first doped photodiode region 106 and the second doped photodiode region 108 to form an electric field within the epitaxial material 104. The electric field causes electrons 116 and holes 118 to generate a photocurrent by moving towards the first doped photodiode region 106 and the second doped photodiode region 108. In embodiments where the epitaxial material 104 comprises a direct bandgap material, the photodetector 105 is capable of providing good performance in detecting near-infrared radiation (e.g., radiation with wavelengths in the range of about 1310 nm and about 1550 nm).

[0031] A doped epitaxial layer 114 is disposed along the interface extending horizontally and vertically between the substrate 102 and the epitaxial material 104. In some embodiments, the doped epitaxial layer 114 includes a second doping type (e.g., p-type doping). The doped epitaxial layer 114 has a dopant concentration greater than the maximum dopant concentration of the epitaxial material. The doped epitaxial layer 114 is configured to passivate defects at the interface between the substrate 102 and the epitaxial material 104 in order to mitigate the generation (e.g., thermal generation) of free charge carriers 120 (e.g., free electrons formed within the epitaxial material 104) that can contribute to the flow of dark current within the photodetector 105.

[0032] The doped epitaxial layer 114 can be formed by a deposition process (e.g., by in-situ doped epitaxial growth) to have a relatively small thickness (e.g., a thickness between about 10 nm and about 1000 nm, a thickness between about 10 nm and about 500 nm, or other suitable values). Furthermore, the transition from the first doping concentration of the doped epitaxial layer 114 to the second doping concentration of the epitaxial material 104 occurs over a relatively small distance. For example, from 1e17 atoms / cm² within the doped epitaxial layer 114... 3 The first doping concentration is approximately 1e16 atoms / cm² within the epitaxial material 10⁴. 3 The transition in the second doping concentration can occur at a distance between about 10% and about 20% of the distance achievable by the implantation process (e.g., a transition at a distance of 1000 angstroms compared to a distance of 7000 angstroms achievable by the implantation process). By making the doped epitaxial layer 114 have a relatively small thickness, the size of the doped epitaxial layer 114 is relatively small and the size of the epitaxial material 104 is relatively large. The relatively large size of the epitaxial material 104 allows for the formation of electron-hole pairs over a relatively large region, thereby improving the efficiency of the photodetector 105. Furthermore, the formation of the doped epitaxial layer 114 by the deposition process avoids implantation damage that could lead to further defects, thereby further mitigating leakage current in the photodetector 105. Overall, the disclosed doped epitaxial layer 114 can reduce the dark current in the epitaxial material 104 by up to about 70% (e.g., from about 130 pI amps (pA) to about 44 pA), about 50%, about 25%, or other similar values.

[0033] Figures 2A to 2B Some additional embodiments of the image sensing structure including the disclosed doped epitaxial layer are shown.

[0034] like Figure 2A As shown in cross-sectional view 200, the image sensing structure includes an epitaxial material 104 disposed within a pixel region 201 of a substrate 102. A photodetector 105 is disposed within the epitaxial material 104. The photodetector 105 includes a first doped photodiode region 106 and a second doped photodiode region 108. Figure 2BAs shown in top view 226, in some embodiments, the first doped photodiode region 106 may have a substantially square shape. In other embodiments (not shown), the first doped photodiode region 106 may have a circular shape, a rectangular shape, a polygonal shape, etc. In some embodiments, the second doped photodiode region 108 surrounds the first doped photodiode region 106 with a square ring, a circular ring, etc.

[0035] The doped epitaxial layer 114 is disposed along the interface extending horizontally and vertically between the epitaxial material 104 and the substrate 102. In various embodiments, the doped epitaxial layer 114 may comprise the same material as the substrate 102 or the same material as the epitaxial material 104. The doped epitaxial layer 114 may comprise having a density of approximately 5e17 atoms / cm². 3 Approximately 1e20 atoms / cm 3 The dopant material has a doping concentration between [specific values]. In some embodiments, the dopant material is boron. In other embodiments, the dopant material may be aluminum, gallium, etc. The doping concentration distribution of the doped epitaxial layer 114 changes abruptly over a relatively small distance, thereby allowing the doped epitaxial layer 114 to achieve a high doping concentration (e.g., greater than about 5e17) while maintaining a relatively small width. For example, the doping concentration distribution may vary from about 50% to about 60% over a distance less than or equal to about 100 nm (e.g., from about 1e16 atoms / cm). 3 Approximately 5e17 atoms / cm 3 The high doping concentration enables the doped epitaxial layer 114 to effectively reduce dark current.

[0036] In some embodiments, the doped epitaxial layer 114 has a first width 202 that is relatively small compared to the second width 204 of the epitaxial material 104. The first width 202 of the doped epitaxial layer 114 leaves a relatively large volume of epitaxial material 104 in which electron-hole pairs can be formed, thereby improving the efficiency of the photodetector 105. In some embodiments, the first width 202 is between about 0.1% and about 7.5% of the second width 204, between about 1% and about 5% of the second width 204, or other similar values. In some embodiments, the doped epitaxial layer 114 has a height directly below the epitaxial material, which is between about 0.3% and about 15% of the first height 206 of the epitaxial material 104, between about 1% and about 10% of the first height 206, or other similar values.

[0037] In some embodiments, the first height 206 of the epitaxial material 104 can be between about 1 micrometer and about 3 micrometers, between about 1 micrometer and about 2 micrometers, or other similar values. In some embodiments, the first width 202 of the doped epitaxial layer 114 can be about 100 angstroms. Peace Treaty Between, at approximately 100 angstroms Peace Treaty Between, in the agreement Peace Treaty Between, in the agreement Peace Treaty Between, in the agreement Peace Treaty The width 202 (e.g., thickness) of the doped epitaxial layer 114 may be substantially uniform along the sidewalls and horizontally extending surface of the epitaxial material 104. In some embodiments, the second width 204 of the epitaxial material 104 may be between about 2 micrometers and about 10 micrometers, between about 3 micrometers and about 5 micrometers, or other similar values.

[0038] In some embodiments, the doped epitaxial layer 114 may be laterally separated from the first doped photodiode region 106 by a distance 208, which is in the range of about 10% to about 25% of the second width 204 of the epitaxial material 104. In some embodiments, the distance 208 may be in the range of about 500 nanometers (nm) and about 2.5 micrometers, about 750 nm and about 2 micrometers, or other similar values.

[0039] A first doped isolation region 210 is disposed along a first surface 102a of the substrate 102, and a second doped isolation region 212 is disposed along the first surface 102a of the substrate 102. In some embodiments, the first doped isolation region 210 is laterally located between the epitaxial material 104 and the second doped isolation region 212. In some embodiments, the second doped isolation region 212 may include a first portion 212a and a second portion 212b disposed below the first portion 212a. In some embodiments, the first portion 212a may have a higher doping concentration than the second portion 212b in order to provide a lower contact resistance for the contacts above it. In some embodiments, such as Figure 2B As shown in top view 226, the first doped isolation region 210 can wrap the second photodiode region 108 as a first closed loop, and the second doped isolation region 212 can wrap the first doped isolation region 210 as a second closed loop.

[0040] A silicide 214 is disposed on one or more of the first doped photodiode region 106, the second doped photodiode region 108, the first doped isolation region 210, and the second doped isolation region 212. In some embodiments, the silicide 214 may include, for example, nickel silicide. One or more interconnects 110 are disposed within a dielectric structure 112 above the substrate 102. The one or more interconnects 110 are coupled to the silicide 214. The one or more interconnects 110 may be configured to provide a bias to one or more of the first doped photodiode region 106, the second doped photodiode region 108, the first doped isolation region 210, and the second doped isolation region 212. In some embodiments, the one or more interconnects 110 are configured to provide a bias to the first doped isolation region 210 and the second doped isolation region 212 to form a depletion region providing junction isolation between the photodetector 105 and an adjacent photodetector (not shown).

[0041] One or more isolation structures 216 are disposed within a second surface 102b of the substrate 102 opposite to the first surface 102a. In some embodiments, the one or more isolation structures 216 may each comprise a dielectric material disposed within one or more trenches defined by the sidewalls of the substrate 102. In some embodiments, a dielectric planarization structure 218 may be disposed along the second surface 102b of the substrate 102. In some embodiments, the dielectric planarization structure 218 may comprise one or more of oxides, nitrides, high-k dielectric materials, etc.

[0042] In some embodiments, a grid structure 220 is disposed on a dielectric planarization structure 218. In some embodiments, the grid structure 220 may be disposed directly above one or more isolation structures 216. In some embodiments, the grid structure 220 may extend along a closed path around the pixel region 201. In some embodiments, the grid structure 220 may include a metal, such as aluminum, cobalt, copper, silver, gold, tungsten, etc. In some embodiments, a filter 222 is disposed between the sidewalls of the grid structure 220. The filter 222 is configured to transmit incident radiation of a specific wavelength (e.g., wavelengths in the infrared and / or near-infrared regions of the electromagnetic spectrum). In some embodiments, the filter 222 may include silicon. A microlens 224 may be disposed on the filter 222. The microlens 224 is configured to focus incident radiation (e.g., light) toward the photodetector 105.

[0043] Figure 3 Cross-sectional views of some additional embodiments of the image sensing structure 300 including the disclosed doped epitaxial layer are shown.

[0044] The image sensing structure 300 includes a capping layer 302 disposed over an epitaxial material 104 within a substrate 102. In some embodiments, the capping layer 302 may include a semiconductor material, such as silicon. A first doped photodiode region 106 and a second doped photodiode region 108 extend from within the capping layer 302 into the epitaxial material 104. In some embodiments, the capping layer 302 may have an outermost wall aligned with the outermost wall of the epitaxial material 104. In such embodiments, the capping layer 302 and the epitaxial material 104 may have substantially equal widths along the top surface (e.g., first surface 102a) of the substrate 102. A doped epitaxial layer 114 extends along the interface between the substrate 102 and the epitaxial material 104. In some embodiments, the doped epitaxial layer 114 may have an uppermost surface laterally located outside the capping layer 302.

[0045] A dielectric structure 112 is disposed above the capping layer 302 and the upper surface of the substrate 102. In some embodiments, the dielectric structure 112 includes a first dielectric material 304 disposed above the substrate 102. The first dielectric material 304 extends laterally from directly above the capping layer 302 to directly above a first surface 102a of the substrate 102. The first dielectric material 304 has one or more sidewalls with openings formed above the top of the first doped photodiode region 106, the second doped photodiode region 108, the first doped isolation region 210, and the second doped isolation region 212.

[0046] In some additional embodiments, the dielectric structure 112 further includes a contact etch stop layer (CESL) 306 disposed above the first dielectric material 304 and along one or more sidewalls of the first dielectric material 304. In various embodiments, the CESL 306 may include nitrides, carbides, etc. In still other embodiments, the dielectric structure 112 includes one or more interlayer dielectric (ILD) layers 308a-308b stacked on top of each other. In some embodiments, the one or more ILD layers 308a-308b may include nitrides (e.g., silicon nitride, silicon oxynitride), carbides (e.g., silicon carbide), oxides (e.g., silicon oxide), borosilicate glass (BSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), low-k oxides (e.g., carbon-doped oxides, SiCOH), etc.

[0047] The dielectric structure 112 laterally surrounds one or more interconnects 110 coupled to the photodetector 105 and / or one or more doped isolation regions 210 and 212. In some embodiments, the one or more interconnects 110 may include conductive contacts 110a, interconnect vias, and / or interconnects 110b. In various embodiments, the one or more interconnects may include tungsten, aluminum, copper, ruthenium, etc.

[0048] Figure 4 Cross-sectional views of some additional embodiments of the image sensing structure 400 including the disclosed doped epitaxial layer are shown.

[0049] The image sensing structure 400 includes a capping layer 302 disposed above an epitaxial material 104 within a substrate 102. A first doped photodiode region 106 and a second doped photodiode region 108 extend from within the epitaxial material 104 into the capping layer 302. A doped epitaxial layer 114 extends along the interface between the substrate 102 and the epitaxial material 104. In some embodiments, the doped epitaxial layer 114 may have a top surface located directly below the capping layer 302. In some additional embodiments, the top surface of the doped epitaxial layer 114 may be completely covered by the capping layer 302.

[0050] Figure 5A Cross-sectional views of some additional embodiments of the image sensing structure 500 including the disclosed doped epitaxial layer are shown.

[0051] The image sensing structure 500 includes epitaxial material 104 disposed within a groove in a substrate 102. A doped epitaxial layer 114 extends along the interface between the substrate 102 and the epitaxial material 104. In some embodiments, an additional doped region 502 may be disposed within the substrate 102 along the outer edge of the doped epitaxial layer 114. The additional doped region 502 may be formed by an implantation process to mitigate potential damage during groove formation within the substrate 102. After groove formation, the implantation process implants dopant into the substrate 102. Compared to the doped epitaxial layer 114, the additional doped region 502 may have a longer decreasing dopant concentration at the interface toward the substrate 102. In some embodiments, the additional doped region 502 may laterally and vertically contact the doped epitaxial layer 114. In other embodiments (not shown), the additional doped region 502 may be laterally and vertically separated from the doped epitaxial layer 114 by a non-zero distance.

[0052] In some embodiments, the doped epitaxial layer 114 and the additional doped region 502 may both comprise or be the same material as the substrate 102. For example, the doped epitaxial layer 114 and the additional doped region 502 may comprise or be silicon. In other embodiments, the doped epitaxial layer 114 may comprise a first material (e.g., germanium), and the additional doped region 502 may comprise a second material (e.g., silicon).

[0053] In some embodiments, the additional doped region 502 may have a first dopant concentration, and the doped epitaxial layer 114 may have a second dopant concentration that is different from (e.g., higher than) that of the additional doped region 502. For example, in some embodiments, the doped epitaxial layer 114 may have a dopant concentration of about 5e17 atoms / cm².3 Approximately 1e20 atoms / cm 3 The dopant concentration (e.g., boron concentration) between these values, while the additional doped region 502 can have a concentration of approximately 5e16 atoms / cm². 3 Approximately 1e19 atoms / cm 3 The dopant concentration (e.g., boron concentration) varies between these parameters. In some embodiments, the doped epitaxial layer 114 may have a first dopant material (e.g., boron), and the additional doped region 502 may have a second dopant material (e.g., gallium) that is different from the first dopant material. In other embodiments, the doped epitaxial layer 114 and the additional doped region 502 may have the same dopant material (e.g., boron).

[0054] In some embodiments, the doped epitaxial layer 114 may have a top surface and the additional doped region 502 may have a top boundary, both of which are laterally disposed between the capping layer 302 and the first doped isolation region 210. In such an embodiment, the top surface of the doped epitaxial layer 114 and the top boundary of the additional doped region 502 are laterally located outside the capping layer 302. In other embodiments, such as Figure 5B As shown in cross-sectional view 504, the doped epitaxial layer 114 may have an uppermost surface located directly below the capping layer 302, and the additional doped region 502 may have an uppermost boundary laterally located outside the capping layer 302. In some such embodiments, the uppermost surface of the doped epitaxial layer 114 may be vertically offset (e.g., above or below) from the uppermost boundary of the additional doped region 502.

[0055] Figure 6A Cross-sectional views of some embodiments of an image sensing structure 600 including multiple doped epitaxial layers disposed along the outer surface of an epitaxial material including a photodetector are shown.

[0056] The image sensing structure 600 includes an epitaxial material 104 disposed within a recess in a substrate 102. A doped epitaxial layer 114 extends along the outer edge of the epitaxial material 104. An additionally doped epitaxial layer 602 extends along the outer edge of the doped epitaxial layer 114. The doped epitaxial layer 114 laterally and vertically separates the epitaxial material 104 from the additionally doped epitaxial layer 602, and the additionally doped epitaxial layer 602 laterally and vertically separates the substrate 102 from the doped epitaxial layer 114. In some embodiments, a capping layer 302 may be disposed above the top surfaces of the doped epitaxial layer 114 and the additionally doped epitaxial layer 602. In some embodiments, the additionally doped epitaxial layer 602 and the doped epitaxial layer 114 are doped during an epitaxial process. The dopant concentration distribution of the layer doped during the epitaxial process differs from the dopant concentration distribution of the layer implanted after the epitaxial process.

[0057] In some embodiments, the doped epitaxial layer 114 may include a first material, and the additional doped region 602 may include a second material different from the first material. For example, in some embodiments, the doped epitaxial layer 114 may include a germanium-based material, and the additional doped epitaxial layer 602 may include silicon. In some embodiments, both the doped epitaxial layer 114 and the additional doped epitaxial layer 602 may include the same dopant material (e.g., boron). In other embodiments, the doped epitaxial layer 114 may include a different dopant material than the additional doped epitaxial layer 602. In some embodiments, both the doped epitaxial layer 114 and the additional doped epitaxial layer 602 may have a density greater than or equal to about 1e18 atoms / cm². 3 The dopant concentration. In various embodiments, the doped epitaxial layer 114 and / or the additional doped epitaxial layer 602 may have a constant dopant concentration distribution, a gradient dopant concentration distribution, or a step dopant concentration distribution.

[0058] Figure 6B Cross-sectional views of some additional embodiments of the image sensing structure 604, which includes multiple doped epitaxial layers, are shown.

[0059] The image sensing structure 604 includes a doped epitaxial layer 114 extending along the outer edge of an epitaxial material 104 disposed within a groove in a substrate 102. An additionally doped epitaxial layer 602 extends along the outer edge of the doped epitaxial layer 114, and an additionally doped region 502 extends along the outer edge of the additionally doped epitaxial layer 602. The doped epitaxial layer 114 laterally and vertically separates the epitaxial material 104 from the additionally doped epitaxial layer 602, and the additionally doped epitaxial layer 602 laterally and vertically separates the doped epitaxial layer 114 from the additionally doped region 502.

[0060] In some embodiments, the doped epitaxial layer 114 and the additionally doped epitaxial layer 602 may extend over the top of the additionally doped region 502 and / or the top of the substrate 102. In some such embodiments, the first dielectric material 304 may extend along the sidewalls of the additionally doped epitaxial layer 602 and extend over the uppermost surface of the additionally doped epitaxial layer 602. In some embodiments, the capping layer 302 covers the uppermost surface of the doped epitaxial layer 114 and the additionally doped epitaxial layer 602.

[0061] Figure 7A Cross-sectional views of some embodiments of an image sensing structure 700 including a doped epitaxial layer are shown.

[0062] The image sensing structure 700 includes a doped epitaxial layer 114, which comprises a germanium-based material disposed along the interface between a substrate 102 and an epitaxial material 104. The dopant concentration distribution varies along cross-sectional lines A-A' and B-B' extending through the substrate 102, the doped epitaxial layer 114, and the epitaxial material 104, respectively. In some embodiments, the dopant concentration distributions along cross-sectional lines A-A' and B-B' may be substantially the same. It should be understood that the doped epitaxial layer 114 disclosed herein can have various dopant concentration distributions. For example, Figures 7B to 7D The display shows along Figure 7A Some examples of graphs showing the dopant concentrations of cross-sections A-A' and B-B'.

[0063] like Figure 7B As shown in Figure 702, in some embodiments, the dopant concentration distribution has a first value that is substantially constant across most of the epitaxial material 104. The dopant concentration distribution rapidly increases to a second value greater than the first value at a first distance 704 along the edge of the epitaxial material 104. In some embodiments, the first distance 704 can be controlled to approximately [value missing] by the formation of the doped epitaxial layer 114. Peace Treaty Within the doped epitaxial layer 114, the dopant concentration distribution remains substantially constant at the second value. Within the substrate 102, the dopant concentration distribution decreases to a third value less than the second value. In some embodiments, the first value may be less than or equal to approximately 1e16 atoms / cm². 3 Such as 1e15 atoms / cm 3 The second value can be approximately 1e17 atoms / cm. 3 Approximately 1e19 atoms / cm 3 Between or at approximately 1e18 atoms / cm 3 Approximately 1e19 atoms / cm 3 Within the range between, and the third value can be less than or equal to approximately 1e16 atoms / cm 3 Such as 1e15 atoms / cm 3 In other embodiments, the first, second, and third values ​​may have different values. In some embodiments, the first distance 704 may be a transition region due to the difference in dopant concentration between the doped epitaxial layer 114 and the epitaxial material 104. Because the doped epitaxial layer 114 is doped during its epitaxial process, the transition region adjacent to the doped epitaxial layer 114 along cross-section lines A-A' and B-B' may be narrower than the transition region adjacent to the implanted layer. to For example, if boron dopant is implanted at the interface between epitaxial material 104 and substrate 102 to form a structure with 2e17 atoms / cm², 3 The injection layer, then the transition region of the epitaxial material 104 has The width, which extends from the interface between the epitaxial material 104 and the doped epitaxial layer 114 to a width of 1e16 atoms / cm² 3 Point 104 of the epitaxial material with boron concentration.

[0064] like Figure 7C As shown in Figure 706, in some embodiments, the dopant concentration distribution within the doped epitaxial layer 114 has a stepped distribution that increases in steps between a plurality of different values.

[0065] like Figure 7D As shown in Figure 708, in some embodiments, the dopant concentration distribution within the doped epitaxial layer 114 has a gradient distribution that gradually increases between the second and fourth values.

[0066] Figure 8A Cross-sectional views of some embodiments of an image sensing structure 800 including a doped epitaxial layer are shown.

[0067] The image sensing structure 800 includes a doped epitaxial layer 114 comprising silicon and disposed along the interface between a substrate 102 and an epitaxial material 104. The dopant concentration distribution varies along cross-sectional lines A-A' and B-B' extending through the substrate 102, the doped epitaxial layer 114, and the epitaxial material 104, respectively. In some embodiments, the dopant concentration distributions along cross-sectional lines A-A' and B-B' may be substantially the same. It should be understood that the doped epitaxial layer 114 disclosed herein can have various dopant concentration distributions. For example, Figures 8B to 8D The display shows along Figure 8A Some examples of graphs showing the dopant concentrations of cross-sections A-A' and B-B'.

[0068] like Figure 8B As shown in Figure 802, in some embodiments, the dopant concentration distribution has a first value that is substantially constant throughout most of the epitaxial material 104. The dopant concentration distribution increases rapidly along the edges of the epitaxial material 104 (e.g., at approximately...). Peace Treaty The dopant concentration distribution is maintained at a value greater than the first value (within the range of the distance between the two values). Within the doped epitaxial layer 114, the dopant concentration distribution remains substantially constant at the second value. Within the substrate 102, the dopant concentration distribution decreases to a third value less than the second value. In some embodiments, the first value may be equal to approximately 1e16 atoms / cm². 3 The second value can be approximately 1e19 atoms / cm. 3 Approximately 1e20 atoms / cm 3 Within the range between, and the third value can be equal to approximately 1e16 atoms / cm². 3 In other embodiments, the first value, the second value, and the third value may have different values.

[0069] like Figure 8C As shown in Figure 804, in some embodiments, the dopant concentration distribution within the doped epitaxial layer 114 has a stepped distribution that increases in steps between a number of different values.

[0070] like Figure 8D As shown in Figure 806, in some embodiments, the dopant concentration distribution within the doped epitaxial layer 114 has a gradient distribution that gradually increases between the second and fourth values.

[0071] Figure 9A Cross-sectional views of some additional embodiments of the image sensing structure 900 including the disclosed doped epitaxial layer are shown.

[0072] The image sensing structure 900 includes an epitaxial material 104 disposed within a groove defined by the inner surface of a substrate 102. A doped epitaxial layer 114 extends along the interface between the substrate 102 and the epitaxial material 104. An additional doped region 502 is disposed within the substrate 102 along the outer edge of the doped epitaxial layer 114.

[0073] Figure 9B The display shows along Figure 9A Some embodiments of the dopant concentration distribution along cross-sections A-A' and B-B' are shown in Figure 902. As shown in Figure 902, the dopant concentration within the epitaxial material 104 and / or the doped epitaxial layer 114 increases abruptly over short distances to limit the extension of high dopant concentration into the depth of the epitaxial material 104, and thus limit the dopant concentration from extending into the photodetector (e.g., within the epitaxial material 104). Figure 9A The negative impact of 105). In some embodiments, the doping concentration within the epitaxial material 104 varies by orders of magnitude over a distance of less than or equal to about 1000 angstroms. For example, in some embodiments, the doping concentration within the epitaxial material 104 can vary from about 1e16 atoms / cm over a distance of less than or equal to about 1000 angstroms. 3 Changes to approximately 1e17 atoms / cm 3 In some additional embodiments, the doping concentration within the epitaxial material 104 can range from approximately 1e16 atoms / cm over a distance of less than or equal to approximately 1000 angstroms. 3 Changes to approximately 5e17 atoms / cm 3 In some embodiments, the dopant concentration distribution within the doped epitaxial layer 114 and the additional doped region 502 has a relatively high dopant concentration (e.g., greater than or equal to 1e17 atoms / cm). 3 ).

[0074] Figure 10Cross-sectional views of some embodiments of a multidimensional integrated chip structure 1000 including a doped epitaxial layer disposed along the outer surface of an epitaxial material including a photodetector are shown.

[0075] The multidimensional integrated chip structure 1000 includes multiple layers 1002-1004 stacked on top of each other. The multiple layers 1002-1004 include a first layer 1002, which includes a substrate 102 having multiple pixel regions 201a-201b. Each pixel region 201a-201b includes a photodetector 105 disposed along the interface between the epitaxial material 104 and the substrate 102 within the epitaxial material 104 having a doped epitaxial layer 114. The first layer 1002 also includes a dielectric structure 112 disposed on a first surface 102a (e.g., the front side) of the substrate 102. Multiple interconnects 110 are disposed within the dielectric structure 112. In some embodiments, the substrate 102 may have sidewalls extending through the substrate 102 and defining bonding pad openings 1001. Bonding pads 1003 are disposed between the sidewalls of the substrate 102.

[0076] A grid structure 220 is disposed on a second surface 102b (e.g., the back side) of a substrate 102 along opposite sides of a plurality of pixel regions 201a-201b. In some embodiments, the grid structure 220 includes a curved surface 220c disposed between the sidewalls 220s of the grid structure 220 and facing away from the substrate 102.

[0077] Isolation structures 216 are disposed within one or more trenches extending along opposite sides of the plurality of pixel regions 201 into a second surface 102b of the substrate 102. In some embodiments, the one or more trenches are defined by sidewalls of the substrate 102 coupled to a curved lower surface of the substrate 102. In some embodiments, the one or more trenches may extend to a depth in the substrate 102 greater than the height of the grid structure 220. In some embodiments, the one or more trenches may be laterally offset from the grid structure 220 by a non-zero distance. For example, a line bisecting a trench may be laterally separated from a line bisecting the nearest grid structure, as seen in the cross-sectional view.

[0078] The multiple layers 1002-1004 also include a second layer 1004, which includes an additional substrate 1006 and an additional dielectric structure 1012. In some embodiments, one or more transistor devices 1008 are disposed within the additional substrate 1006. A plurality of additional interconnects 1010 are disposed within the additional dielectric structure 1012 and coupled to one or more of the transistor devices 1008.

[0079] The first layer 1002 is bonded to the second layer 1004 via a bonding structure 1014 including a first bonding pad 1016 and a second bonding pad 1018. In some embodiments, the first bonding pad 1016 may be disposed within a first passivation layer 1020 on the dielectric structure 112, and the second bonding pad 1018 may be disposed within a second passivation layer 1022 on the additional dielectric structure 1012. In some embodiments, the bonding structure 1014 may include a hybrid bonding structure having a first interface between the first bonding pad 1016 and the second bonding pad 1018 and a second interface between the first passivation layer 1020 and the second passivation layer 1022. In some embodiments, the first bonding pad 1016 and the second bonding pad 1018 may include metals such as aluminum, copper, tungsten, etc. In some embodiments, the first bonding pad 1016 and the second bonding pad 1018 may each include a conductive copper core and a surrounding barrier layer (e.g., including a refractory metal such as tantalum, titanium, etc.). In some embodiments, the first bonding pad 1016 contacts the second bonding pad 1018 and the second passivation layer 1022. In some embodiments, the first bonding pad 1016 and the second bonding pad 1018 are in a basic trapezoidal shape and they contact each other at the largest base of the basic trapezoidal shape.

[0080] Figures 11 to 29 Cross-sectional views 1100-2900 illustrate some embodiments of a method for forming an integrated chip structure comprising a doped epitaxial layer disposed along the outer surface of an epitaxial material including a photodetector. While the method is described... Figures 11 to 29 However, it should be understood that Figures 11 to 29 The structures disclosed herein are not limited to this method, but can exist independently of this method.

[0081] like Figure 11 As shown in cross-sectional view 1100, a sacrificial dielectric 1102 is formed over a first surface 102a of a substrate 102. In various embodiments, the substrate 102 can be any type of semiconductor host (e.g., silicon, SiGe, SOI, etc.), such as a semiconductor wafer and / or one or more dies on the wafer, and any other type of semiconductor and / or associated epitaxial layer. In various embodiments, the sacrificial dielectric 1102 can include oxides, nitrides, etc. In some embodiments, the sacrificial dielectric 1102 can be formed by a thermal oxidation process (e.g., wet thermal oxidation, dry thermal oxidation, etc.). In other embodiments, the sacrificial dielectric 1102 can be formed by a deposition process (e.g., chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PE-CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), molecular organic chemical vapor deposition (MOCVD), etc.).

[0082] like Figure 12 As shown in cross-sectional view 1200, one or more doped isolation regions are formed within a substrate 102. The one or more doped isolation regions may include a first doped isolation region 210 having a first doping type and a second doped isolation region 212 having a second doping type different from the first doping type. In some embodiments, the first doped isolation region 210 may be formed by a first implantation process that implants a first dopant type (e.g., boron, aluminum, gallium, etc.) into the substrate 102 according to a first implantation mask (not shown). In some embodiments, the second doped isolation region 212 may be formed by one or more additional implantation processes that implant a second dopant type (e.g., phosphorus, arsenic, antimony, etc.) into the substrate 102 according to a second implantation mask (not shown). In some embodiments, the one or more additional implantation processes may include different implantation processes forming a first portion 212a of the second doped isolation region 212 and a second portion 212b of the second doped isolation region 212. The first implantation process and the one or more additional implantation processes may be implemented with the sacrificial dielectric 1102 located appropriately above the substrate 102, such that the implantation process implants the dopant through the sacrificial dielectric 1102.

[0083] like Figure 13 As shown in cross-sectional view 1300, the sacrificial dielectric is removed from above the first surface 102a of the substrate 102. Figure 12 (1102). After removing the sacrificial dielectric, an intermediate first dielectric material 1302 is subsequently formed on the first surface 102a of the substrate 102. In some embodiments, the intermediate first dielectric material 1302 may include oxides (e.g., silicon dioxide), nitrides (e.g., silicon oxynitride), etc. In some embodiments, the intermediate first dielectric material 1302 may be formed by a deposition process (e.g., CVD process, PE-CVD process, ALD process, PVD process, MOCVD process, etc.).

[0084] like Figure 14 As shown in cross-sectional view 1400, a first patterning process is performed on the intermediate first dielectric material 1302 to form an opening 1402 extending through the intermediate first dielectric material 1302 and exposing a portion of the first surface 102a of the substrate 102. In some embodiments, the first patterning process can be performed by selectively exposing the intermediate first dielectric material 1302 to a first etchant 1404 according to a first mask 1406. In some embodiments, the first etchant 1404 may include a dry etchant (e.g., a reactive ion etchant, a sputtering etchant, etc.). In some embodiments, the first mask 1406 may include a photoresist, a hard mask, etc.

[0085] like Figure 15 As shown in cross-sectional view 1500, a second patterning process is performed on an exposed portion of the first surface 102a of the substrate 102. The second patterning process removes a portion of the substrate 102 to form a recess 1502 defined by one or more inner surfaces of the substrate 102. In some embodiments, the recess 1502 may be formed to have a depth in the range of about 1 micrometer to about 3 micrometers and a width in the range of about 2 micrometers to about 10 micrometers. In some embodiments, the second patterning process may be performed by selectively exposing the substrate 102 to a second etchant 1504 according to a second mask 1506. In some embodiments, the second etchant 1504 may include a dry etchant (e.g., a reactive ion etchant, a sputtering etchant, etc.). In some embodiments, the second mask 1506 may include a photoresist, a hard mask, etc. In some additional embodiments, the second mask 1506 may include an intermediate first dielectric material 1302.

[0086] like Figure 16 As shown in cross-sectional view 1600, a doped epitaxial layer 114 is formed within a recess 1502 and along one or more inner surfaces of a substrate 102. In some embodiments, the doped epitaxial layer 114 can be formed by a first deposition process that introduces a dopant into the epitaxial material during the first deposition process (e.g., such that the doped epitaxial layer 114 is doped while it is being formed along one or more inner surfaces of the substrate 102). Forming the doped epitaxial layer 114 by the first deposition process allows the dopant within the doped epitaxial layer 114 to form over a relatively small width. Furthermore, it eliminates the need for photomasks (e.g., compared to implantation processes) and / or activated annealing, thereby reducing the cost of the manufacturing process.

[0087] In various embodiments, the first deposition process may include chemical vapor deposition (CVD), physical vapor deposition (PVD), epitaxial growth, etc. In some embodiments, the first deposition process may be implemented by introducing a boron-containing gas (e.g., diborane) into the process chamber during the deposition of the epitaxial material. In various embodiments, the doped epitaxial layer 114 may include silicon, germanium, silicon-germanium, etc. In some embodiments, the doped epitaxial layer 114 may be formed as approximately... Peace Treaty Between, in the agreement Peace Treaty Between, in the agreement Peace Treaty The thickness is within a range of between or other similar values. In some embodiments, the first deposition process can be carried out in a process chamber maintained at a pressure between about 5 Torr and about 200 Torr. In other embodiments, the first deposition process can be carried out in a process chamber maintained at atmospheric pressure.

[0088] In some embodiments (not shown), an additional doped epitaxial layer can be formed over the doped epitaxial layer 114 using a subsequent deposition process. For example, in some embodiments, the doped epitaxial layer 114 can be formed by a first deposition process of forming a first doped semiconductor material on the substrate 102, and the second doped epitaxial layer can be formed by an additional deposition process of forming a second doped semiconductor material on the first doped semiconductor material.

[0089] like Figure 16 As shown in cross-sectional view 1602, an intermediate epitaxial material 1604 is formed within the groove 1502 and along the inner surface of the doped epitaxial layer 114. In some embodiments, the intermediate epitaxial material 1604 can be formed by a second deposition process that does not introduce dopant into the intermediate epitaxial material 1604. In various embodiments, the second deposition process may include CVD, PVD, epitaxial growth, etc. In some embodiments, the second deposition process can be implemented by stopping the introduction of boron-containing gas (e.g., diborane) into the process chamber during the deposition (e.g., segmented deposition, continuous deposition, etc.) of the doped epitaxial layer 114 and the intermediate epitaxial material 1604. In other embodiments, the second deposition process can be implemented by introducing a new set of gases into the process chamber. In various embodiments, the intermediate epitaxial material 1604 may include germanium, silicon-germanium, etc. In some embodiments, during the formation of the intermediate epitaxial material 1604, dopant from within the doped epitaxial layer 114 may diffuse into the substrate 102, producing, for example, approximately Peace Treaty The dopant concentration distribution decreases within the depth range of the substrate 102.

[0090] like Figure 17 As shown in the cross-sectional view 1700, the intermediate epitaxial material is removed from above the intermediate first dielectric material 1302. Figure 16 A portion of the intermediate epitaxial material 104 is used to form the epitaxial material 104. In some embodiments, a portion of the intermediate epitaxial material is removed by an etching process. In other embodiments, a portion of the intermediate epitaxial material is removed by a planarization process (e.g., chemical mechanical planarization (CMP) process). In some embodiments, the epitaxial material 104 may be recessed below the upper surface of the first dielectric material 304. In other embodiments, the epitaxial material 104 may have an upper surface that is substantially coplanar with the upper surface of the intermediate first dielectric material 1302 (e.g., coplanar within the tolerances of the CMP process). In some such embodiments, the doped epitaxial layer 114 may have an uppermost surface located above the first surface 102a of the substrate 102.

[0091] like Figure 18As shown in cross-sectional view 1800, a capping layer 302 is formed on the epitaxial material 104. The capping layer 302 may be formed on the epitaxial material 104 and directly between the sidewalls of the intermediate first dielectric material 1302. In some embodiments, the capping layer 302 may include oxides, nitrides, etc. In various embodiments, the capping layer 302 may be formed by a deposition process (e.g., CVD process, PE-CVD process, ALD process, PVD process, MOCVD process, etc.).

[0092] like Figure 19 As shown in the cross-sectional view 1900, the intermediate first dielectric material is modified (e.g., Figure 18 (1302) to form a first dielectric material 304. The first dielectric material 304 has a greater thickness than the intermediate first dielectric material and extends above the capping layer 302. In some embodiments, the intermediate first dielectric material can be modified by a deposition process (e.g., CVD process, PE-CVD process, ALD process, PVD process, MOCVD process, etc.).

[0093] like Figure 20 As shown in the cross-sectional view 2000, a first doped photodiode region 106 and a second doped photodiode region 108 are formed within the epitaxial material 104. In some embodiments, the first doped photodiode region 106 may be formed by a third implantation process, which implants a first dopant type (e.g., boron, aluminum, gallium, etc.) into the epitaxial material 104 and the capping layer 302 according to a third implantation mask (not shown). In some embodiments, the second doped photodiode region 108 may be formed by a fourth implantation process, which implants a second dopant type (e.g., phosphorus, arsenic, antimony, etc.) into the epitaxial material 104 and the capping layer 302 according to a fourth implantation mask (not shown).

[0094] like Figure 21 As shown in cross-sectional view 2100, a third patterning process is performed to selectively etch a first dielectric material 304 to define a first plurality of contact openings 2102 extending through the first dielectric material 304. The first plurality of contact openings 2102 expose a first doped photodiode region 106, a second doped photodiode region 108, a first doped isolation region 210, and a second doped isolation region 212. In some embodiments, the third patterning process can be implemented by selectively exposing the first dielectric material 304 to a third etchant 2104 according to a third masking layer 2106. In some embodiments, the third etchant 2104 may include a dry etchant (e.g., a reactive ion etchant, a sputtering etchant, etc.). In some embodiments, the third masking layer 2106 may include a photoresist, a hard mask, etc.

[0095] like Figure 22As shown in cross-sectional view 2200, a silicide process is performed to form silicide 214 on the first doped photodiode region 106, the second doped photodiode region 108, the first doped isolation region 210, and the second doped isolation region 212. In some embodiments, the silicide process can be performed by depositing a nickel layer and then performing a thermal annealing process (e.g., rapid thermal annealing) to form a nickel-containing silicide 214.

[0096] like Figure 23 As shown in cross-sectional view 2300, a contact etch stop layer (CESL) 306 is formed on the first dielectric material 304 and the silicide 214. In some embodiments, the CESL 306 may include carbides (e.g., silicon carbide, silicon oxynitride, etc.), nitrides (e.g., silicon nitride, silicon oxynitride, etc.), etc. In some embodiments, the CESL 306 may be formed by a deposition process (e.g., CVD process, PE-CVD process, ALD process, PVD process, MOCVD process, etc.).

[0097] like Figure 24 As shown in cross-sectional view 2400, a first ILD layer 308a is formed on CESL 306. In some embodiments, the first ILD layer 308a may include oxides (e.g., silicon oxide), low-k dielectric materials, etc. In various embodiments, the first ILD layer 308a may be formed by a deposition process (e.g., CVD process, PE-CVD process, ALD process, PVD process, MOCVD process, etc.).

[0098] like Figure 25 As shown in cross-sectional view 2500, an anti-reflective coating 2502 is formed on the first ILD layer 308a. The anti-reflective coating 2502 is configured to reduce the reflectivity of incident radiation used in the photolithography process in order to mitigate critical dimension (CD) errors. In various embodiments, the anti-reflective coating 2502 can be formed by a deposition process (e.g., CVD process, PE-CVD process, ALD process, PVD process, MOCVD process, etc.).

[0099] like Figure 26 As shown in cross-sectional view 2600, a fourth patterning process is performed to selectively etch the first ILD layer 308a and CESL 306 to define a second plurality of contact openings 2602 extending through the first ILD layer 308a and CESL 306. In some embodiments, the fourth patterning process can be performed by selectively exposing the first ILD layer 308a and CESL 306 to a fourth etchant 2604 according to a fourth masking layer 2606. In some embodiments, the fourth etchant 2604 may include a dry etchant (e.g., a reactive ion etchant, a sputtering etchant, etc.). In some embodiments, the fourth masking layer 2606 may include a photoresist.

[0100] like Figure 27 As shown in cross-sectional view 2700, a plurality of conductive contacts 110a are formed within the second plurality of contact openings 2602. In some embodiments, the plurality of conductive contacts 110a may be formed by forming a first conductive material within the second plurality of contact openings 2602. A planarization process is then performed to remove excess portions of the first conductive material from above the first ILD layer 308a. In some embodiments, the planarization process may include a chemical mechanical planarization (CMP) process. In some embodiments, the first conductive material may include tungsten, ruthenium, copper, gold, etc.

[0101] like Figure 28 As shown in cross-sectional view 2800, interconnect lines 110b are formed over the first ILD layer 308a and a plurality of conductive contacts 110a. In some embodiments, interconnect lines 110b can be formed by depositing a second conductive material on the first ILD layer 308a and the plurality of conductive contacts 110a. The second conductive material is then patterned to define the interconnect lines 110b. In some embodiments, the second conductive material may include tungsten, ruthenium, copper, gold, etc.

[0102] like Figure 29 As shown in cross-sectional view 2900, a second ILD layer 308b is formed over the first ILD layer 308a and the interconnect 110b. In some embodiments, the second ILD layer 308b may include oxides (e.g., silicon oxide), low-k dielectric materials, etc. In various embodiments, the second ILD layer 308b may be formed by a deposition process (e.g., CVD process, PE-CVD process, ALD process, PVD process, MOCVD process, etc.).

[0103] Figure 30 Flowcharts of some embodiments of a method 3000 for forming an integrated chip structure including a doped epitaxial layer disposed along the outer surface of an epitaxial material including a photodetector are shown.

[0104] While the disclosed method 3000 is shown and described herein as a series of steps or events, it should be understood that the order in which such steps or events are shown should not be construed as limiting. For example, some steps may occur in a different order and / or simultaneously with other steps or events in addition to those shown and / or described herein. Furthermore, it may not be necessary to implement all the steps shown to achieve one or more aspects or embodiments described herein. Moreover, one or more steps described herein may be performed in one or more separate steps and / or stages.

[0105] In step 3002, a sacrificial dielectric is formed over the substrate. Figure 11A cross-sectional view 1100 is shown, corresponding to some embodiments of step 3002.

[0106] In step 3004, one or more isolation regions may be formed within the substrate. Figure 12 A cross-sectional view 1200 is shown corresponding to some embodiments of step 3004.

[0107] In step 3006, the sacrificial dielectric is removed from above the first substrate, and an intermediate first dielectric material is formed above the base substrate. Figure 13 A cross-sectional view 1300 is shown corresponding to some embodiments of step 3006.

[0108] In step 3008, the substrate is patterned to form a groove defined by the inner surface of the substrate. Figures 14 to 15 Cross-sectional views 1400-1500 are shown for some embodiments corresponding to step 3008.

[0109] In step 3010, a doped epitaxial layer is formed along the inner surface of a defined groove in the semiconductor substrate. Figure 16 A cross-sectional view 1600 corresponding to some embodiments of step 3010 is shown.

[0110] In step 3012, epitaxial material is formed on the doped epitaxial layer and in the groove. Figures 16 to 17 Cross-sectional views 1602 and 1700 are shown for some embodiments corresponding to step 3012.

[0111] In step 3014, a capping layer is formed over the epitaxial material. Figure 18 A cross-sectional view 1800 corresponding to some embodiments of step 3014 is shown.

[0112] In step 3016, the intermediate first dielectric material is modified to form the first dielectric material covering the cover layer. Figure 19 A cross-sectional view 1900 corresponding to some embodiments of step 3016 is shown.

[0113] In step 3018, a first doped photodiode region and a second doped photodiode region are formed within the epitaxial material. Figure 20 Cross-sectional view 2000 is shown for some embodiments corresponding to step 3018.

[0114] In step 3020, a first ILD layer is formed over the first dielectric material. Figure 24 A cross-sectional view 2400 corresponding to some embodiments of step 3020 is shown.

[0115] In step 3022, a plurality of conductive contacts are formed within the first ILD layer and the first dielectric material. Figure 25A cross-sectional view 2500 corresponding to some embodiments of step 3022 is shown.

[0116] Therefore, in some embodiments, the present invention relates to an integrated chip structure comprising a doped epitaxial layer disposed along the outer surface of an epitaxial material including a photodetector.

[0117] In some embodiments, the present invention relates to a method of forming an integrated chip structure. The method includes: etching a substrate to form a recess defined by one or more inner surfaces of the substrate; forming a doped epitaxial layer along one or more inner surfaces of the substrate; forming an epitaxial material on horizontal and vertically extending surfaces of the doped epitaxial layer; forming a first doped photodiode region having a first doping type within the epitaxial material; and forming a second doped photodiode region having a second doping type within the epitaxial material. In some embodiments, the method further includes: performing a planarization process to remove a portion of the epitaxial material after forming the epitaxial material and before forming the first doped photodiode region. In some embodiments, the epitaxial material comprises germanium. In some embodiments, the doped epitaxial layer has a substantially constant dopant concentration distribution across its width. In some embodiments, the doped epitaxial layer has a dopant concentration distribution that increases along a direction extending from the epitaxial material to the substrate. In some embodiments, the doped epitaxial layer has a width of less than about 100 nm. In some embodiments, the doped epitaxial layer has a first height directly below the epitaxial material, the first height being less than about 10% of a second height of the epitaxial material. In some embodiments, the method further includes performing an implantation process between etching a substrate to define a groove and forming a doped epitaxial layer, the implantation process implanting a dopant material along one or more inner surfaces of the substrate.

[0118] In other embodiments, the present invention relates to a method of forming an integrated chip structure. The method includes: etching a substrate having a first semiconductor material to form a groove defined by one or more inner surfaces of the substrate; performing a first deposition process to form a doped epitaxial layer along one or more inner surfaces of the substrate; performing a second deposition process to form an epitaxial material having a second semiconductor material on the doped epitaxial layer, the epitaxial material having a lower dopant concentration than the maximum dopant concentration of the doped epitaxial layer; performing a first implantation process to form a first doped photodiode region within the epitaxial material; and performing a second implantation process to form a second doped photodiode region within the epitaxial material, wherein the second doped photodiode region laterally surrounds the first doped photodiode region. In some embodiments, the first deposition process is performed by introducing a dopant into a process chamber while epitaxially growing a semiconductor material on one or more inner surfaces of the substrate. In some embodiments, the first deposition process forms the doped epitaxial layer to be the same material as the substrate. In some embodiments, the method further includes: performing an additional deposition process to form an additional doped epitaxial layer along the sidewalls of the doped epitaxial layer, wherein the additional doped epitaxial layer is a different material from the doped epitaxial layer. In some embodiments, the first deposition process forms the doped epitaxial layer to be a different material from the substrate. In some embodiments, the doped epitaxial layer is laterally separated from the second doped photodiode region by a non-zero distance. In some embodiments, the doped epitaxial layer has a top surface perpendicularly located above the top surface of the substrate. In some embodiments, the method further includes forming a capping layer on the top surface of the epitaxial material and the doped epitaxial layer.

[0119] In some other embodiments, the present invention relates to an integrated chip structure. The integrated chip structure includes: a substrate having one or more inner surfaces defining a recess within an upper surface of the substrate; an epitaxial material disposed within the recess; a first doped photodiode region disposed within the epitaxial material and having a first doping type; a second doped photodiode region disposed within the epitaxial material and having a second doping type, wherein the second doped photodiode region laterally surrounds the first doped photodiode region; and a doped epitaxial layer horizontally and vertically disposed between the substrate and the epitaxial material, the doped epitaxial layer having a second doping type. In some embodiments, the doped epitaxial layer is the same material as the epitaxial material. In some embodiments, the doped epitaxial layer is the same material as the substrate. In some embodiments, the doped epitaxial layer is vertically and laterally separated from the second doped photodiode region.

[0120] Some embodiments of this application provide a method for forming an integrated chip structure, comprising: etching a substrate to form a recess defined by one or more inner surfaces of the substrate; forming a doped epitaxial layer along the one or more inner surfaces of the substrate; forming an epitaxial material on horizontal and vertical extension surfaces of the doped epitaxial layer; forming a first doped photodiode region within the epitaxial material, the first doped photodiode region comprising a first doping type; and forming a second doped photodiode region within the epitaxial material, the second doped photodiode region comprising a second doping type. In some embodiments, the method further comprises: performing a planarization process to remove a portion of the epitaxial material after forming the epitaxial material and before forming the first doped photodiode region. In some embodiments, the epitaxial material comprises germanium. In some embodiments, the doped epitaxial layer has a substantially constant dopant concentration distribution over its width. In some embodiments, the doping concentration within the epitaxial material varies by orders of magnitude over distances less than or equal to 1000 angstroms. In some embodiments, a dopant is introduced into the doped epitaxial layer during the formation of the doped epitaxial layer along the one or more inner surfaces of the substrate. In some embodiments, the doped epitaxial layer has a first height directly beneath the epitaxial material, the first height being less than 10% of a second height of the epitaxial material. In some embodiments, the method further includes performing an implantation process between etching the substrate to define the groove and forming the doped epitaxial layer, wherein the implantation process implants dopant material along one or more inner surfaces of the substrate.

[0121] Other embodiments of this application provide a method for forming an integrated chip structure, comprising: etching a substrate comprising a first semiconductor material to form a groove defined by one or more inner surfaces of the substrate; performing a first deposition process to form a doped epitaxial layer along the one or more inner surfaces of the substrate; performing a second deposition process to form an epitaxial material comprising a second semiconductor material on the doped epitaxial layer, the epitaxial material having a lower dopant concentration than the maximum dopant concentration of the doped epitaxial layer; performing a first implantation process to form a first doped photodiode region within the epitaxial material; and performing a second implantation process to form a second doped photodiode region within the epitaxial material, wherein the second doped photodiode region laterally surrounds the first doped photodiode region. In some embodiments, the first deposition process is performed by introducing a dopant into a process chamber while epitaxially growing a semiconductor material on the one or more inner surfaces of the substrate. In some embodiments, the first deposition process forms the doped epitaxial layer as the same material as the substrate. In some embodiments, the method further comprises: performing an additional deposition process to form an additional doped epitaxial layer along the sidewalls of the doped epitaxial layer, wherein the additional doped epitaxial layer is a different material from the doped epitaxial layer. In some embodiments, the first deposition process forms the doped epitaxial layer to be a material different from the substrate. In some embodiments, the doped epitaxial layer is laterally separated from the second doped photodiode region by a non-zero distance. In some embodiments, the doped epitaxial layer has an uppermost surface perpendicular to the uppermost surface of the substrate. In some embodiments, the method further includes forming a capping layer on the epitaxial material and the uppermost surface of the doped epitaxial layer.

[0122] Further embodiments of this application provide an integrated chip structure, including: a substrate including one or more inner surfaces defining a recess within an upper surface of the substrate; an epitaxial material disposed within the recess; a first doped photodiode region disposed within the epitaxial material and including a first doping type; a second doped photodiode region disposed within the epitaxial material and including a second doping type, wherein the second doped photodiode region laterally surrounds the first doped photodiode region; and a doped epitaxial layer horizontally and vertically disposed between the substrate and the epitaxial material, the doped epitaxial layer having the second doping type. In some embodiments, the doping concentration within the epitaxial material ranges from 1e16 atoms / cm at a distance less than or equal to 1000 angstroms. 3 Change to 1e17 atoms / cm 3In some embodiments, the doped epitaxial layer is the same material as the substrate. In some embodiments, the doping concentration within the epitaxial material varies by orders of magnitude over a distance of less than or equal to 1000 angstroms.

[0123] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand aspects of the invention. Those skilled in the art should understand that they can readily use this invention as a basis to design or modify other processes and structures for implementing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the invention, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of the invention.

Claims

1. A method for forming an integrated chip structure, comprising: Etching a substrate of a first semiconductor material to form a groove defined by one or more inner surfaces of the substrate; A doped epitaxial layer is formed along one or more inner surfaces of the substrate. An epitaxial material is formed on the horizontal and vertical extended surfaces of the doped epitaxial layer, wherein the epitaxial material is a second semiconductor material, and the doped epitaxial layer is composed of the second semiconductor material and a dopant, wherein the second semiconductor material is different from the first semiconductor material; A first doped photodiode region is formed within the epitaxial material, the first doped photodiode region comprising a first doping type; and A second doped photodiode region is formed within the epitaxial material, the second doped photodiode region comprising a second doping type; The substrate has an upper surface that is in physical contact with the bottom surface of the doped epitaxial layer, and the upper surface of the substrate has a lower dopant concentration than the bottom surface of the doped epitaxial layer.

2. The method according to claim 1, further comprising: After the epitaxial material is formed and before the first doped photodiode region is formed, a planarization process is performed to remove a portion of the epitaxial material.

3. The method according to claim 1, wherein, The epitaxial material includes germanium.

4. The method according to claim 1, wherein, The doped epitaxial layer has a substantially constant dopant concentration distribution across its width.

5. The method according to claim 1, wherein, The doping concentration within the epitaxial material changes by orders of magnitude over a distance of less than or equal to 1000 angstroms.

6. The method according to claim 1, wherein, A dopant is introduced into the doped epitaxial layer during the formation of the doped epitaxial layer along one or more inner surfaces of the substrate.

7. The method according to claim 1, wherein, The doped epitaxial layer has a first height directly below the epitaxial material, the first height being less than 10% of the second height of the epitaxial material.

8. The method according to claim 1, further comprising: An implantation process is performed between etching the substrate to define the groove and forming the doped epitaxial layer, wherein the implantation process implants dopant material along one or more inner surfaces of the substrate.

9. A method for forming an integrated chip structure, comprising: Etching a substrate comprising a first semiconductor material to form a groove defined by the sidewalls and upper surface of the substrate; Additional doped regions are formed along the sidewalls and the upper surface of the substrate, the additional doped regions being vertically and laterally surrounded by the substrate along opposite sides; A first deposition process is performed to form a doped epitaxial layer along the sidewalls and the upper surface of the substrate, the doped epitaxial layer and the additional doped region having the same dopant, wherein the doped epitaxial layer and the additional doped region are laterally and vertically separated by a region of the substrate having a lower dopant concentration than the doped epitaxial layer and the additional doped region; A second deposition process is performed to form an epitaxial material comprising a second semiconductor material on the doped epitaxial layer, the epitaxial material having a lower dopant concentration than the maximum dopant concentration of the doped epitaxial layer; Perform a first implantation process to form a first doped photodiode region within the epitaxial material; and A second implantation process is performed to form a second doped photodiode region within the epitaxial material, wherein the second doped photodiode region laterally surrounds the first doped photodiode region.

10. The method according to claim 9, wherein, The first deposition process is carried out by introducing a dopant into the process chamber while epitaxially growing a semiconductor material on the sidewalls and the upper surface of the substrate.

11. The method according to claim 9, wherein, The first deposition process forms the doped epitaxial layer to be the same material as the substrate.

12. The method of claim 11, further comprising: An additional deposition process is performed to form an additional doped epitaxial layer along the sidewalls of the doped epitaxial layer, wherein the additional doped epitaxial layer is a different material from the doped epitaxial layer.

13. The method according to claim 9, wherein, The first deposition process forms the doped epitaxial layer as a material different from the substrate.

14. The method according to claim 9, wherein, The doped epitaxial layer is laterally separated from the second doped photodiode region by a non-zero distance.

15. The method according to claim 9, wherein, The doped epitaxial layer has an uppermost surface that is perpendicular to the uppermost surface of the substrate.

16. The method of claim 9, further comprising: A capping layer is formed on the uppermost surface of the epitaxial material and the doped epitaxial layer.

17. An integrated chip structure, comprising: A substrate, including one or more inner surfaces that define a groove within the upper surface of the substrate; Epitaxial material is disposed within the groove; A first doped photodiode region is disposed within the epitaxial material and includes a first doping type; A second doped photodiode region is disposed within the epitaxial material and includes a second doping type, wherein the second doped photodiode region laterally surrounds the first doped photodiode region; and A doped epitaxial layer is disposed horizontally and vertically between the substrate and the epitaxial material, the doped epitaxial layer having the second doping type; An additional doped region is disposed horizontally and vertically between the substrate and the doped epitaxial layer, the doped epitaxial layer and the additional doped region having the same dopant, wherein the doped epitaxial layer and the additional doped region are laterally and vertically separated by a region of the substrate having a lower dopant concentration than the doped epitaxial layer and the additional doped region.

18. The integrated chip structure according to claim 17, wherein, The doping concentration within the epitaxial material ranges from 1e16 atoms / cm over a distance less than or equal to 1000 angstroms. 3 Change to 1e17 atoms / cm 3 .

19. The integrated chip structure according to claim 17, wherein, The doped epitaxial layer is made of the same material as the substrate.

20. The integrated chip structure according to claim 17, in, The doping concentration within the epitaxial material varies by orders of magnitude over a distance of less than or equal to 1000 angstroms.

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