Power semiconductor device

Abstract

A power semiconductor device comprises: a semiconductor body; a first load terminal structure and a second load terminal structure; an active region; a drift region; a backside region comprising a first backside emitter zone and a second backside emitter zone. At least one of the first backside emitter zone and the second backside emitter zone comprises: a plurality of first segments comprising at least one first region of a second conductivity type having a minimum lateral extension of at most 50 pm; and / or a plurality of second segments being in contact with the second load terminal structure and having a minimum lateral extension of at least 50 pm. The second backside emitter zone differs from the first backside emitter zone in: the presence of first segments; the presence of second segments; the minimum lateral extension of first segments; the minimum lateral extension of second segments; a lateral distance between first segments; a lateral distance between second segments; the minimum lateral extension of first regions; a lateral distance between adjacent first regions within the same first segment.

Description

Technical Field

[0001] This specification relates to embodiments of power semiconductor devices. In particular, this specification relates to aspects of power semiconductor devices having one or more back-side emitter bands included in a semiconductor body, wherein the back-side emitter bands exhibit different emitter efficiencies and / or different injection efficiencies. Background Technology

[0002] Many functions of modern devices in automotive, consumer, and industrial applications—such as converting electrical energy and driving electric motors or generators—rely on power semiconductor devices. For example, to name a few, insulated-gate bipolar transistors (IGBTs), metal-oxide-semiconductor field-effect transistors (MOSFETs), and diodes have been used in a variety of applications, including, but not limited to, switching in power supplies and power converters.

[0003] Power semiconductor devices typically include a semiconductor body with active regions configured to conduct load current along a load current path between the two load terminals of the device. During operation of such a power semiconductor device, the spatial temperature distribution within the semiconductor body generally tends to be non-uniform, exhibiting a maximum value, for example, at the center of the active region. As a result, the power cycle reliability and thermal short-circuit or surge current withstand capability of the power semiconductor device may be reduced, potentially necessitating costly safety margins in the thermal design of the power semiconductor device.

[0004] Therefore, it is desirable to influence, for example, the temperature distribution within the semiconductor body of a power semiconductor device to increase device reliability. Furthermore, it may be desirable to improve the trade-off between the softness and power loss of the power semiconductor device. Summary of the Invention

[0005] The aspects described herein relate to specific novel designs for the back-side region of power semiconductor devices, which, compared to conventional designs, can, for example, produce improved thermal robustness and an improved trade-off between softness and power loss.

[0006] According to an embodiment, a power semiconductor device includes: a semiconductor body having a front side and a back side; a first load terminal structure coupled to the front side and a second load terminal structure coupled to the back side; an active region of the semiconductor body configured to conduct load current between the first load terminal structure and the second load terminal structure; a drift region of the semiconductor body having a first conductivity type and configured to conduct load current; and a back-side region of the semiconductor body disposed on the back side and including a first back-side emitter region strip and a second back-side emitter region strip within the active region. The first back-side emitter region strip is disposed within the active region and has a larger distance to the outer boundary of the active region compared to the second back-side emitter region strip. Therefore, the first back-side emitter region strip can present a larger distance to the non-active regions of the power semiconductor device, such as edge-terminating regions, which laterally surround the active region, compared to the second back-side emitter region strip. The first back-side emitter region strip includes a plurality of first segments, each first segment including at least one first region of a second conductivity type, the first regions being arranged to contact the second load terminal structure. In other words, each first segment may include multiple first regions, or each first segment may consist of only one first region. The second back-side emitter region band includes multiple second segments, each second segment including at least one second region of a second conductivity type, the second regions being arranged to contact the second load terminal structure. In other words, each second segment may include multiple second regions, or each second segment may consist of only one second region. The spacing defining the lattice constant along at least a first lateral direction is at least substantially equal in the first and second back-side emitter region bands. The first back-side emitter region band differs from the second back-side emitter region band in that the minimum lateral extension of the first segment is greater than the minimum lateral extension of the second segment. Alternatively or additionally, the first back-side emitter region band may differ from the second back-side emitter region band in that the minimum lateral extension of the first region is greater than the minimum lateral extension of the second region.

[0007] According to another embodiment, a power semiconductor device includes: a semiconductor body having a front side and a back side; a first load terminal structure coupled to the front side and a second load terminal structure coupled to the back side; an active region of the semiconductor body configured to conduct load current between the first and second load terminal structures; a drift region of the semiconductor body having a first conductivity type and configured to conduct load current; and a back-side region of the semiconductor body disposed on the back side and including a second back-side emitter region strip within the active region. The second back-side emitter region strip includes a plurality of second segments, each second segment including at least one second region of a second conductivity type, the second regions being arranged to contact the second load terminal structure. Along an imaginary line, for at least three, at least five, or at least eight adjacent second segments, their minimum lateral extension strictly monotonically increases. In other words, at least three adjacent second segments are arranged along an imaginary line, wherein their minimum lateral extension strictly monotonically increases along the imaginary line. The middle second segment of at least three adjacent second segments—which may be arranged among the surrounding second segments of at least three adjacent second segments—may exhibit a minimum lateral extension smaller than one of the surrounding second segments and larger than the other of the surrounding second segments. The imaginary line may be a straight line. The second segments may be arranged according to a lattice having a spacing defined by a lattice constant along at least a first lateral direction, wherein the spacing may be at least substantially constant for the at least three adjacent second segments along the imaginary line. The minimum lateral extension of the at least three adjacent second segments may increase with increasing distance to the outer boundary of the active region. In other words, the more the at least three adjacent second segments are spaced apart from the boundary of the active region or from non-active regions laterally surrounding the active region, the larger their size may be with respect to their minimum lateral extension.

[0008] According to another embodiment, a power semiconductor device includes: a semiconductor body having a front side and a back side; a first load terminal structure coupled to the front side and a second load terminal structure coupled to the back side; an active region of the semiconductor body configured to conduct load current between the first load terminal structure and the second load terminal structure; a drift region of the semiconductor body having a first conductivity type and configured to conduct load current; a back side region of the semiconductor body disposed on the back side and including a first back side emitter region strip and a second back side emitter region strip in the active region, wherein the first back side emitter region strip includes a plurality of first segments, each first segment including at least one first region of a second conductivity type, the first region being arranged to contact the second load terminal structure; and wherein the second back side emitter region strip includes a plurality of second segments, each second segment including at least one island region of a second conductivity type, the island region being insulated from the second load terminal structure. The first back side emitter region strip differs from the second back side emitter region strip in that the island region is isolated from the second load terminal and the first region is connected to the second load terminal. "Insulation" means that there is no ohmic connection between the corresponding island region and the second load terminal. For example, a portion of the first conductivity type or a portion of the insulating material may be arranged between the island region and the second load terminal. For example, the island region may be omitted in the first back-side emitter region band. For example, the island region may not be arranged in the first back-side emitter region band. For example, the first region may be omitted in the second back-side emitter region band. For example, the first back-side emitter region band may not be arranged in the active region at a greater distance to the outer boundary of the active region compared to the second back-side emitter region band. Therefore, the first back-side emitter region band may present a greater distance to the non-active region of the power semiconductor device—the non-active region that laterally surrounds the active region—e.g., the edge-terminating region—compared to the second back-side emitter region band. In the first and second back-side emitter regions, the spacing defining the lattice constant along at least the first lateral direction may be at least substantially equal. Alternatively, the spacing between the first and second back-side emitter zones can be different.

[0009] For example, the first region may have a minimum lateral extension of up to 50 μm and / or the second region may have a minimum lateral extension of at least 50 μm.

[0010] For example, the lateral distance between adjacent first segments in the first dorsal emitter zone can be up to three times the minimum lateral extension of the first segment, and / or the lateral distance between adjacent second segments in the second dorsal emitter zone can be up to three times the minimum lateral extension of the second segment.

[0011] At the nominal current of the power semiconductor device, the first back-side emitter region can exhibit each of a first emitter efficiency and a first injection efficiency, and the second back-side emitter region can exhibit each of a second emitter efficiency and a second injection efficiency. According to an embodiment, the first emitter efficiency differs from the second emitter efficiency by at least 1% or even at least 3% or even at least 10%, and / or the first injection efficiency differs from the second injection efficiency by at least 1% or even at least 3% or even at least 10%.

[0012] For example, the relationship between the first injection efficiency and the second injection efficiency described above can refer to the first injection efficiency and the second injection efficiency at a current that reaches 0.1 times the nominal current of the power semiconductor device.

[0013] Alternatively, the above relationship between the first injection efficiency and the second injection efficiency may refer to the first injection efficiency and the second injection efficiency at the nominal current of the power semiconductor device or at twice the nominal current of the power semiconductor device.

[0014] According to a further embodiment, a power semiconductor device includes: a semiconductor body having a front side and a back side; a first load terminal structure coupled to the front side and a second load terminal structure coupled to the back side; an active region of the semiconductor body configured to conduct a load current between the first load terminal structure and the second load terminal structure; a drift region of the semiconductor body having a first conductivity type and configured to conduct the load current; a back-side region of the semiconductor body, the back-side region being disposed on the back side and including a first back-side emitter region band and a second back-side emitter region band in the active region, wherein each of the first back-side emitter region band and the second back-side emitter region band includes a plurality of regions of a second conductivity type arranged to contact the second load terminal structure and a plurality of regions of a first conductivity type arranged to contact the second load terminal structure; wherein the dopant concentration in the corresponding central portion of the second conductivity type region in the first back-side emitter region band is... The dopant concentration is essentially equal to the dopant concentration in the corresponding central portion of the region of the second conductivity type in the second back emitter zone; wherein the dopant concentration in the corresponding central portion of the region of the first conductivity type in the first back emitter zone is essentially equal to the dopant concentration in the corresponding central portion of the region of the first conductivity type in the second back emitter zone; wherein the first back emitter zone exhibits each of a first emitter efficiency and a first injection efficiency at the nominal current of the power semiconductor device; wherein the second back emitter zone exhibits each of a second emitter efficiency and a second injection efficiency at the nominal current of the power semiconductor device; wherein the first emitter efficiency differs from the second emitter efficiency by at least 1%, or even at least 5%, or even at least 10%, or even at least 20%, and / or the first injection efficiency differs from the second injection efficiency by at least 1%, or even at least 5%, or even at least 10%, or even at least 20%.

[0015] For example, the relationship between the first injection efficiency and the second injection efficiency described above can refer to the first injection efficiency and the second injection efficiency at a current that reaches 0.1 times the nominal current of the power semiconductor device.

[0016] Alternatively, the above relationship between the first injection efficiency and the second injection efficiency may refer to the first injection efficiency and the second injection efficiency at the nominal current of the power semiconductor device or at twice the nominal current of the power semiconductor device.

[0017] For example, the backside region may further include a third backside zone, which includes at least one region of a first conductivity type and a plurality of regions of a second conductivity type arranged in an alternating sequence to contact the second load terminal structure, the regions of the first conductivity type and the regions of the second conductivity type. The regions of the first conductivity type and / or the regions of the second conductivity type may have a minimum lateral extension of up to 50 μm. For example, the third backside zone is disposed in the edge termination region of the semiconductor body. For example, the third backside zone is disposed below the gate channel electrode disposed on the front side. For example, the lateral extension of the third backside zone may reach at least 0.5 times the vertical thickness of the drift region. Alternatively, the lateral extension of the third backside zone may reach at least the same as the vertical thickness of the drift region, or reach two or even four times the vertical thickness of the drift region.

[0018] According to an embodiment, the back-side region further includes a spacer region that laterally separates the second back-side emitter region band from the third back-side region band. The spacer region may laterally completely surround the second back-side emitter region band. The third region may laterally completely surround the spacer region. The minimum lateral extension of the spacer region may be at least 0.5 times the vertical thickness of the drift region. Alternatively, the minimum lateral extension of the spacer region may be at least the same as the vertical thickness of the drift region, or two or even four times the vertical thickness of the drift region.

[0019] Those skilled in the art will recognize the additional features and advantages upon reading the following detailed description and reviewing the accompanying drawings. Attached Figure Description

[0020] The components in the figures are not necessarily to scale. Instead, the focus is on illustrating the principles of the invention. Furthermore, in each figure, the same reference numerals indicate corresponding components. In the figures: Figures 1A to 1B Each of the illustrations schematically and exemplary depicts a portion of a vertical cross-section of a power semiconductor device according to one or more embodiments; Figures 2 to 12 Each of the illustrations schematically and exemplary depicts a portion of a vertical cross-section of a power semiconductor device according to one or more embodiments; Figures 13A to 13E Each of the schematic and exemplary illustrations depicts a portion of a horizontal cross-section of a power semiconductor device according to one or more embodiments; Figures 14A to 14F Each of the schematic and exemplary illustrations depicts a portion of a horizontal cross-section of a power semiconductor device according to one or more embodiments; Figures 15A to 15B Each of the schematic and exemplary illustrations depicts a portion of a horizontal cross-section of a power semiconductor device according to one or more embodiments; Figures 16A to 16CEach schematically and exemplary illustration depicts a portion of a horizontal cross-section of a power semiconductor device according to one or more embodiments; and Figures 17A to 17D Each schematic and exemplary illustration is based on the Figures 15A to 16C The horizontal cross-section of a different embodiment of the third region of a power semiconductor device is depicted in the figure. Detailed Implementation

[0021] In the following detailed description, reference is made to the accompanying drawings, which form a part herein, and which illustrate specific embodiments in which the invention may be practiced.

[0022] In this regard, directional terms such as “top,” “bottom,” “below,” “front,” “back,” “rear,” “front,” “end,” and “above” can be used with reference to the orientation of the described figures. Because components of the embodiments can be positioned in many different orientations, the directional terms are for illustrative purposes and are by no means limiting. It should be understood that other embodiments can be utilized and structural or logical changes can be made without departing from the scope of the invention. Therefore, the following detailed description should not be viewed in a limiting sense, and the scope of the invention is defined by the appended claims.

[0023] Referring now to various embodiments, one or more examples of various embodiments are illustrated in the figures. Each example is provided by way of explanation and is not intended to limit the invention. For example, features partially illustrated or described as one embodiment may be used in other embodiments or in combination with other embodiments to produce yet another further embodiment. The invention is intended to include such modifications and variations. Examples are described using specific language, which should not be construed as limiting the scope of the appended claims. The drawings are not to scale and are for illustrative purposes only. For clarity, unless otherwise stated, the same elements or manufacturing steps are indicated by the same reference numerals in different drawings.

[0024] As used herein, the term "horizontal" is intended to describe the orientation of a horizontal surface that is substantially parallel to a semiconductor substrate or semiconductor structure. This can be, for example, the surface of a semiconductor wafer, die, or chip. For example, both the first lateral (or horizontal) direction X and the second lateral (or horizontal) direction Y mentioned below and / or shown in the figures can be horizontal directions, wherein the first lateral direction X and the second lateral direction Y can be perpendicular to each other.

[0025] As used herein, the term "vertical" is intended to describe an orientation substantially perpendicular to a horizontal surface arrangement, i.e., a direction parallel to the normal to the surface of a semiconductor wafer / chip / die. For example, the vertical direction Z mentioned below and / or shown in the figures may be a direction perpendicular to both the first lateral direction X and the second lateral direction Y.

[0026] In this specification, n-doping generally refers to "first conductivity type" and p-doping refers to "second conductivity type". Alternatively, the opposite doping relationship can be used, so that the first conductivity type can be p-doped and the second conductivity type can be n-doped.

[0027] In the context of this specification, the terms "ohmic contact," "electrical contact," "ohmic connection," and "electrical connection" are intended to describe a low-ohmic electrical connection or low-ohmic current path between two regions, segments, zones, portions, or components of a semiconductor device, or between different terminals of one or more devices, or between terminals or metallizations or electrodes and portions or components of a semiconductor device. Further, in the context of this specification, the term "contact" is intended to describe a direct physical connection between two elements of a respective semiconductor device; for example, a transition between two elements in contact with each other may not include further intermediate elements, etc.

[0028] Furthermore, in the context of this specification, unless otherwise stated, the term "electrically insulated" is used in its generally valid understanding and is therefore intended to describe two or more components that are positioned separately from each other and where there is no ohmic connection connecting these components. However, components that are electrically insulated from each other can still be coupled to each other, for example, mechanically coupled and / or capacitively coupled and / or inductively coupled. To give an example, the two electrodes of a capacitor can be electrically insulated from each other and simultaneously mechanically and capacitively coupled to each other, for example, by means of an insulating medium, such as a dielectric.

[0029] The specific embodiments described in this specification relate to, but are not limited to, power semiconductor devices presenting a single cell, strip cell, or honeycomb (also referred to as "needle" or "pillar") cell configuration, such as power semiconductor devices that can be used within a power converter or power supply. Therefore, in embodiments, such devices can be configured to carry load currents to be fed to a load and / or corresponding load currents provided by a power source. For example, a power semiconductor device may include one or more active power semiconductor cells, such as monolithically integrated diode cells, derivatives of monolithically integrated diode cells (e.g., a monolithically integrated cell of two diodes connected in reverse series), monolithically integrated transistor cells (e.g., a monolithically integrated IGBT or MOSFET cell), and / or derivatives thereof. Such diode / transistor cells can be integrated in a power semiconductor module. Multiple such power cells can constitute a cell field of an active region where power semiconductor devices are arranged.

[0030] As used in this specification, the term "power semiconductor device" is intended to describe a semiconductor device on a single chip that has high voltage blocking and / or high current carrying capacity. In other words, such a power semiconductor device is intended for use with high current (typically in the ampere range, such as tens or hundreds of amperes) and / or for use with high voltage (typically above 15V, more typically 100V and above, such as at least 400V or even higher, such as in the range of 1.2kV to 2kV, or at least 3kV, or even 6kV or higher).

[0031] For example, the power semiconductor devices described below can be single semiconductor chips presenting a single-cell configuration (such as a single diode cell), a strip cell configuration, or a cellular configuration, and can be configured for use as power components in low, medium, and / or high voltage applications.

[0032] For example, the term "power semiconductor device" as used in this specification does not refer to other types of logic semiconductor devices used for, for example, storing data, computing data, and / or semiconductor-based data processing.

[0033] Figure 1A A portion of a vertical cross-section of a power semiconductor device 1 according to one or more embodiments is schematically and exemplaryly shown. The power semiconductor device 1 includes a semiconductor body 10 having a front side 10-1 and a back side 10-2. For example, the semiconductor body 10 may include or be composed of a silicon-based substrate, a silicon carbide-based substrate, a gallium nitride-based substrate, or, for example, another wide-bandgap semiconductor substrate.

[0034] The semiconductor body 10 includes an active region 15, which may also be referred to as an active cell region 15. The active cell region 15 may include one or more power cells 14, which may be configured to conduct and / or control the load current between a first load terminal structure 11 and a second load terminal structure 12, the first load terminal structure 11 being disposed on the front side 10-1 of the semiconductor body 10, and the second load terminal structure 12 being disposed on the back side of the semiconductor body 10. Therefore, according to some embodiments, the power semiconductor device 1 may be configured as a vertical power semiconductor device 1.

[0035] For example, power semiconductor device 1 is or includes at least one of the following: power diode, MOSFET, IGBT, reverse-biased IGBT (RC-IGBT), high electron mobility transistor (HEMT) (such as gallium-based HEMT), and thyristor.

[0036] When the power semiconductor device 1 is or includes a power diode, the active region 15 may include, for example, a high-power unit 14, such as in... Figure 1A As illustrated in the exemplary diagram. For example, power unit 14 may include a p-doped semiconductor region configured as an anode region and in front-side metallization contact forming part of the first load terminal structure 11. For example, the anode region may form a pn junction with the n-doped drift region 100 of the semiconductor body 10.

[0037] Alternatively, in the case of a transistor configuration (e.g., in the form of a MOSFET or IGBT), the active region 15 may include an active cell field 14 comprising a plurality of transistor cells, which may, in each case, include a source region, a body region, and a gate electrode (such as a trench gate electrode), the gate electrode being configured to selectively switch the power semiconductor device 1 to one of a forward conduction state and a forward blocking state. Such active cell field designs for power semiconductor devices are also well known to those skilled in the art and therefore will not be explained in further detail here.

[0038] In addition to the active region 15, the power semiconductor device 1 may include an edge-terminating region 16 extending between the active region 15 and the lateral chip edge (not shown) of the semiconductor body 10. For example, the edge-terminating region 16 may laterally surround the active region 15.

[0039] As used herein, the terms "edge termination region" and "active region" are associated with their respective technical meanings, typically used by those skilled in the art in the context of power semiconductor devices. That is, the active region 15 is primarily configured for load current conduction and, in the case of a transistor configuration, for switching purposes, while the edge termination region 16 primarily fulfills functions related to reliable blocking capability, proper guidance of the electric field, and sometimes also fulfills functions related to charge carrier discharge, and / or further functions related to the protection and proper termination of the active region 15.

[0040] Edge termination region 16 may include edge termination structure 18, which may be disposed on the front side 10-1 of semiconductor body 10. Such edge termination structure 18 may also be referred to as junction termination structure or simply junction termination. For example, edge termination structure 18 may include one or more components disposed within semiconductor body 10 and / or one or more components disposed above the front surface 10-1 of semiconductor body 10. Figure 1A In the illustration, the edge termination structure 18 is only schematically shown as a structure arranged at the front side 10-1 within the semiconductor body 10, without showing specific structural details.

[0041] Common examples of edge-terminating structures 18 are field rings (sometimes also called guard rings), field plates, combinations of field rings and field plates, and junction termination extension (JTE) edge-terminating structures, such as lateral doping variation (VLD) edge-terminating structures. These types of edge-terminating structures are well known to those skilled in the art. Therefore, they will not be explained in detail at this point.

[0042] The power semiconductor device 1 further includes a backside region 17 disposed within the semiconductor body 10 at a backside 10-1. The backside region 17 includes at least one first backside emitter region band 171 and at least one second backside emitter region band 172, wherein the first backside emitter region band 171 and the second backside emitter region band 172 are disposed within the active region 15 of the power semiconductor device 1.

[0043] Figure 1A An exemplary diagram shows a first back-side emitter band 171 and a second back-side emitter band 172. However, it should be noted that, according to some embodiments, multiple first back-side emitter bands 171 and / or multiple second back-side emitter bands 172 may be provided.

[0044] Figure 1B The variant embodiments are illustrated schematically and exemplary, and differ from those shown. Figure 1AAn embodiment is characterized in that the semiconductor body 10 additionally includes a field stop region 100-1. The field stop region 100-1 is disposed between the drift region 100 and the back side region 17, and has a higher dopant concentration of the first conductivity type compared to the drift region 100.

[0045] The field stop region 100-1 may exhibit one or more dopant concentration peaks. For example, the field stop region 100-1 may be formed by means of one or more proton injections via the backside 10-2. Such methods and variations, sometimes referred to as buffer field stop regions, are well known in principle to those skilled in the art and therefore will not be discussed further in detail here.

[0046] In this embodiment, a field stop region 100-1 has been generated by means of one or more proton implantations, such that the edge of the shallowest dopant concentration peak is located at a depth of 1 μm to 4 μm below the back surface of the semiconductor body 10. In this context, the "shallowest" peak will refer to the only field stop peak (in the case of only one) or the field stop peak closest to the back surface among several field stop peaks.

[0047] In this embodiment, the field stop region 100-1 has been achieved by ion implantation of donor-like atoms such as phosphorus, selenium, or sulfur, followed by an implantation or annealing step, resulting in a Gaussian-like doped profile for example, the field stop region 100-1. In particular, achieving a field stop region 100-1 with deep donors such as selenium atoms can reduce the temperature dependence of hole implantation during turn-off due to p-short-circuit regions 1711, 1712, 1721, 1722. To finely tune this temperature dependence, shallow donors can be additionally introduced into the field stop region 100-1.

[0048] According to an embodiment, the respective area extension of each of the first back-side emitter zone 171 and the second back-side emitter zone 172 can reach at least 5% of the area extension of the active region 15, such as at least 25% or even at least 40%.

[0049] The first back-side emitter zone 171 and the second back-side emitter zone 172 may differ from each other in their back-side emitter characteristics.

[0050] For example, at least one first back-side emitter region 171 may exhibit each of a first emitter efficiency and a first injection efficiency at the nominal current of the power semiconductor device 1, while at least one second back-side emitter region 171 may exhibit each of a second emitter efficiency and a second injection efficiency at the nominal current.

[0051] For the purposes of this specification, emitter efficiency is defined as the ratio of the electron current at the back-side p / n or n- / n+ junction (i.e., at the interface between the field stop region 100-1 and the first back-side emitter zone 171 and / or the second back-side emitter zone 172) to the total current, wherein this amount is averaged over the respective first or second back-side emitter zones 171, 172.

[0052] Furthermore, for the purposes of this specification, the injection efficiency is defined as the ratio of the amount of holes injected during reverse commutation of the power semiconductor device 1 to the total reverse recovery charge under soft-critical conditions (i.e., at relatively low currents (e.g., 0.1 times the nominal current) and relatively low temperatures (e.g., 25°C)). In other words, the injection efficiency is the time integral of the hole current entering the device 1 during reverse recovery, compared to the time integral over the total current during reverse recovery, under said soft-critical conditions, typically referred to as Qrr.

[0053] Furthermore, for the purposes of this specification, the injected hole charge in the first back-side emitter region 171 or the second back-side emitter region 172 is defined as the hole charge injected during reverse commutation of the power semiconductor device 1 under soft-critical conditions (i.e., at a relatively low current (e.g., 0.1 times the nominal current) and at a relatively low temperature (e.g., 25°C)). In other words, the injection efficiency is the time integral of the hole current entering the device 1 during reverse commutation under said soft-critical conditions.

[0054] Furthermore, for the purposes of this specification, the average backside plasma concentration associated with the first backside emitter zone 171 or the second backside emitter zone 172 is defined as the area integral of the free electron concentration over a horizontal cross-sectional region at a distance of 1 μm from the interface between the field stop region 100-1 and the corresponding first backside emitter zone 171 or second backside emitter zone 172, which is normalized by area.

[0055] According to one or more embodiments, the first emitter efficiency differs from the second emitter efficiency by at least 1%, such as at least 5%, for example, at least 10% or even at least 20%. Alternatively or additionally, it may be provided that the first injection efficiency differs from the second injection efficiency by at least 5%, for example, at least 10% or even at least 20%.

[0056] Furthermore, according to an embodiment, the injected hole charge of the first back-side emitter region 171 differs from the injected hole charge of the second back-side emitter region 172 by at least 10%, such as at least 20%, or even at least 40%.

[0057] Further, according to an embodiment, the average back-side plasma concentration associated with the first back-side emitter zone (171) differs from the average back-side plasma concentration associated with the second back-side emitter zone (172) by at least 5%, such as at least 10%, for example at least 20%.

[0058] In terms of structural features, such differences between the first emitter injection efficiency and / or the second emitter injection efficiency, as well as between the corresponding injected hole charge or average backside plasma concentration, can be achieved, for example, by providing multiple semiconductor regions of a second conductivity type (e.g., p-type) that are complementary to the first conductivity type (e.g., n-type) of the drift region 100 within the first and / or second backside emitter region bands 171, 172.

[0059] In other words, as will be referred to below Figures 2 to 11 As explained in more detail, the first back-side emitter region 171 and the second back-side emitter region 172 can be configured as metastructures, each metastructure including regions 1711, 1721, 1712, 1722 of a second conductivity type arranged to contact the second load terminal structure 12, and various arrangements of a plurality of regions 1740 of a first conductivity type arranged to contact the second load terminal structure 12. In some embodiments, such metastructures 171 / 172 may also be characterized by the absence of regions 1711, 1721, 1712, 1722 of the second conductivity type.

[0060] Figures 2 to 11 Each of the figures schematically and exemplary illustrates a portion of a vertical cross-section of a power semiconductor device 1 (e.g., a power diode) according to one or more embodiments. In each case, the cross-section includes a portion of the semiconductor body 10 at the back side 10-1, which includes a portion of the field stop region 100-1 and a portion of the back side region 17. The illustrated portion of the back side region 17 includes a first back side emitter region band 171 and a second back side emitter region band 172. Further, a portion of the second load terminal structure 12 (in the form of back side metallization) is shown.

[0061] Figures 2 to 11 The embodiments differ from one another in the specific arrangement of the second conductivity type regions 1711, 1721, 1712, 1722 and the first conductivity type region 1740 within the first back-side emitter region 171 and the second back-side emitter region 172, as will be explained in more detail below.

[0062] according to Figures 2 to 11 In each embodiment of the above, at least one of the first back-side emitter zone 171 and the second back-side emitter zone 172 may include a plurality of first segments 171-1, 172-1 and / or a plurality of second segments 171-2, 172-2.

[0063] The first segments 171-1, 172-1 and the second segments 171-2, 172-2 can be configured such that they do not support the large-scale injection of charge carriers (e.g., electrons) of any first conductivity type during operation of the power semiconductor device 1.

[0064] For example, each first segment 171-1, 171-2 may include at least one first region 1711, 1721 of a second conductivity type, the first regions 1711, 1721 being arranged to contact the second load terminal structure 12 and having a minimum lateral extension x1, x1' of up to 50 μm, such as up to 30 μm, such as up to 10 μm.

[0065] The first regions 1711 and 1721 can be configured such that they do not support the large-scale injection of any second conductivity type of charge carriers (e.g., holes) during operation of the power semiconductor device 1.

[0066] Furthermore, each second segment 171-2, 172-2 may be composed of second regions 1712, 1722 of a second conductivity type, the second regions 1712, 1722 being arranged to contact the second load terminal structure 12 and having a minimum lateral extension x2, x2' of at least 50 μm (such as at least 100 μm, for example at least 200 μm). When the second conductivity type is "p", the second regions 1712, 1722 of the second conductivity type may also be referred to as "p-short-circuit regions".

[0067] The minimum lateral extensions x2, x2' of these p-short-circuit regions 1712, 1722 define the lateral voltage drop induced by reverse current below these regions 1712, 1722 during turn-off processing, and thereby define the starting level of hole injection during the turn-off phase. Preferably, the vertical doping profile of these p-short-circuit regions 1712, 1722 at the center of these regions 1712, 1722 is approximately the same for all these regions 1712, 1722. Alternatively, these p-regions 1712, 1722 may exhibit different vertical doping profiles.

[0068] In contrast to the first regions 1711 and 1721, the second regions 1712 and 1722 can be configured to support the injection of charge carriers of a second conductivity type (e.g., holes) during operation of the power semiconductor device 1.

[0069] A first conductivity type region 1740 is laterally located between segments 171-1, 172-1, 171-2, and 172-2, and is also arranged to contact the second load terminal structure 12. The lateral extension of these first conductivity type regions 1740 can be large enough that the first conductivity type regions 1740 can support the injection of first conductivity type charge carriers (e.g., electrons) during operation of the power semiconductor device 1. For example, in some embodiments, the lateral extension of the first conductivity type regions 1740 can reach at least 50 μm, such as at least 100 μm, for example, at least 200 μm.

[0070] Correspondingly, in some embodiments, the lateral distances d1, d1', d2, d2' between adjacent first segments 171-1, 172-1 and / or second segments 171-2, 172-2 can reach at least 50 μm, such as at least 100 μm, or even at least 200 μm.

[0071] In some embodiments, the region 1740 of the first conductivity type may have a higher dopant concentration of the first conductivity type compared to the field stop region 100-1.

[0072] For example, the region 1740 of the first conductivity type may have a higher dopant concentration of the first conductivity type compared to the average dopant concentration of the first conductivity type in the field stop region 100-1, wherein the average is obtained over the vertical thickness of the field stop region 100-1. In some embodiments, the vertical thickness of the field stop region 100-1 may be greater than 2 μm, such as greater than 5 μm, or even greater than 10 μm.

[0073] For example, such a relatively high dopant concentration in region 1740 of the first conductivity type can be achieved by means of laser thermal annealing (LTA) performed at the back side 10-1.

[0074] Additionally or alternatively, the dopant concentration of the second conductivity type in the first regions 1711 and 1721 and / or the dopant concentration of the second conductivity type in the second regions 1712 and 1722 may also be higher than the dopant concentration of the first conductivity type in the field stop region 100-1.

[0075] For example, the first regions 1711, 1721 and / or the second regions 1712, 1722 may have a higher dopant concentration of the second conductivity type compared to the average dopant concentration of the first conductivity type in the field stop region 100-1, wherein the average is obtained over the vertical thickness of the field stop region 100-1. In some embodiments, the vertical thickness of the field stop region 100-1 may be greater than 2 μm, such as greater than 5 μm, or even greater than 10 μm.

[0076] According to some embodiments, the dopant concentration in the corresponding central portions of regions 1711 and 1712 of the second conductivity type in the first back-side emitter zone 171 is substantially equal to the dopant concentration in the corresponding central portions of regions 1721 and 1722 of the second conductivity type in the second back-side emitter zone 172; and the dopant concentration in the corresponding central portion of region 1740 of the first conductivity type in the first back-side emitter zone 171 is substantially equal to the dopant concentration in the corresponding central portion of region 1740 of the first conductivity type in the second back-side emitter zone 172. In this context, the statement that the dopant concentration is "substantially equal to" should be understood to mean that one dopant concentration differs from another dopant concentration by at most a factor of 1.3, such as at most a factor of 1.1, for example at most a factor of 1.05.

[0077] Furthermore, according to some embodiments, it may be provided that the second back-side emitter region 172 differs from the first back-side emitter region 171 in at least one of the following aspects: -The existence (or non-existence) of segments 171-1 and 172-1 in the first section; -The existence (or non-existence) of the second segment 171-2 and 172-2; -Minimum lateral extensions x11 and x11' of the first segment 171-1 and 172-1; -Minimum lateral extensions x2 and x2' of the second segments 171-2 and 172-2; - The lateral distances d1 and d1' between adjacent first segments 171-1 and 172-1; - The lateral distances d2 and d2' between adjacent second segments 171-2 and 172-2; -Minimum lateral extensions x1 and x1' of zones 1711 and 1721 in the first zone; - The lateral distances d11 and d11' between adjacent first zones 1711 and 1721 within the same first zone 171-1 and 172-1.

[0078] For example, in Figure 2In the schematically illustrated embodiment, the second back-side emitter region 172 differs from the first back-side emitter region 171 in that either the first segment 172-1 or the second segment 172-2 is completely absent from the second back-side emitter region 172, while the first back-side emitter region 171 includes a plurality of second segments 171-2. The second segments 171-2 are composed of second regions 1712 of a second conductivity type (e.g., p-short-circuit regions), each region having a lateral extension x2 along the transverse direction of the cross-section and being arranged with a lateral distance d2 between them. In each case, a region 1740 of a first conductivity type having a higher dopant concentration than the field stop region 100-1 is arranged between two adjacent second regions 1712 of the second conductivity type.

[0079] For example, according to Figure 2 During operation of the power semiconductor device 1 in an exemplary embodiment, a relatively low plasma density of free charge carriers may arise from the presence of a second segment 171-2 in the first back-side emitter region 171. That is, the plasma density in the first back-side emitter region 171 and the portion of the semiconductor body 10 located above the second back-side emitter region 172 may be relatively low compared to the plasma density in the second back-side emitter region 172 and the portion of the semiconductor body 10 located above the first back-side emitter 171.

[0080] As a result, lower static and dynamic losses can occur in the region of the first back-side emitter band 171 compared to the region of the second back-side emitter band 172. The first back-side emitter band 171 is positioned closer to the center of the active region 15 compared to the second back-side emitter band 172 (see [link to relevant documentation]). Figure 2 The presence of the second segment 171-2 (as shown in the section of the edge termination region 173) can therefore contribute to temperature homogenization within the semiconductor body 10.

[0081] Furthermore, loss generation can be increased by adjusting the emitter efficiency in improved thermal cooling zones—such as below the bonding pins and / or near low-loss zones, such as current-sensing pads.

[0082] On the other hand, not only the temperature distribution but also the softness of device 1 may be affected: for example, the p-short circuit 171-2 can inject holes during commutation and thus provide sufficient softness.

[0083] Regarding the edge termination region 173, it should be noted that, Figures 2 to 11In each embodiment, the back side region 17 further includes a third back side region strip 173 disposed within the edge termination region 16. The third back side region strip 173 includes a plurality of regions 1731 of a first conductivity type and a plurality of regions 1732 of a second conductivity type arranged in an alternating sequence to contact the second load terminal structure 12, wherein the regions 1731 and 1732 of the first conductivity type have a minimum lateral extension x4, x5 of up to 50 μm, such as up to 30 μm, for example up to 10 μm.

[0084] The third backside region 173 can be configured such that no significant injection of electrons or holes occurs in this region during operation of the power semiconductor device 1; in this sense, the third backside region 173 can also be referred to as a "dead region." As a result, there will be no significant plasma in the third backside region 173 and in the portion of the semiconductor body 10 located above the third backside region 173. In this way, the concept of "high dynamic robustness (HDR)" can be achieved by means of (multiple) third backside emitter regions 173.

[0085] For example, the lateral extension x6 of the third dorsal zone 173 can reach at least 0.5 times, such as at least two times, or even at least four times, the vertical thickness z1 of the drift zone 100 (see...). Figures 1A to 1B ).

[0086] exist Figures 2 to 11 In the exemplary embodiment shown, a third backside band 173 is disposed in the edge termination region 16. In some embodiments in which the power semiconductor device 1 has a gate (e.g., in the case of a MOSFET or RC-IGBT), such a third backside band 173 may additionally or alternatively be (at least partially) disposed below the gate channel electrode disposed at the front side 10-1.

[0087] exist Figure 3In the exemplary embodiment shown, both the first back-side emitter region 171 and the second back-side emitter region 172 include a plurality of second segments 171-2 and 172-2. In this case, the essential difference between the first back-side emitter region 171 and the second back-side emitter region 172 lies in the minimum lateral extensions x2 and x2' of the corresponding second segments 171-2 and 172-2, and the lateral distances d2 and d2' between adjacent second segments 171-2 and 172-2: the second region 1722 of the second conductivity type in the second back-side emitter region 172 has a larger lateral extension x2' than the lateral extension x2 of the second region 1712 of the second conductivity type in the first back-side emitter region 171. Furthermore, the lateral distance d2' between adjacent second regions 1722 in the second back-side emitter region 172 is larger than the lateral distance d2 between adjacent second regions 1712 in the first back-side emitter region 171.

[0088] For example, the area ratio of the second region 1722 of the second conductivity type in the second back-side emitter region 172 to the area ratio of the region 1740 of the first conductivity type in the second back-side emitter region 172 can be similar to or equal to the area ratio of the second region 1712 of the second conductivity type in the first back-side emitter region 171 to the area ratio of the region 1740 of the first conductivity type in the first back-side emitter region 172. However, by means of appropriate design of the corresponding second regions 1712, 1722, different emitter efficiencies and / or injection efficiencies can be achieved in the first back-side emitter region 171 and the second back-side emitter region 172.

[0089] For example, compared to the first back-side emitter region 171, the relatively coarser structure (relatively wide p-short circuit) of the second segment 172-2 in the second back-side emitter region 172 can produce a more efficient cathode in the second back-side emitter region 172. As a result, during operation, compared to the above-mentioned... Figure 2 Similarly, compared to the region of the first back-side emitter zone 171, the plasma density, as well as the static and dynamic losses, can be higher in the region of the second back-side emitter zone 172.

[0090] In this case, it should be noted that a higher plasma density can reduce the forward voltage of diode 1. Furthermore, in a parallel connection of regions with different plasma densities and therefore different (local) forward voltages, the current preferably follows a path through the region with a relatively low forward voltage, namely the second back-side emitter region 172 in this example. As a result, higher static and dynamic losses (resulting in a localized increase in temperature) can occur in the second back-side emitter region 172 compared to the first back-side emitter region 171.

[0091] Furthermore, referring to all the embodiments described above and below, it should be noted that regarding softness, due to the different designs of the back-side emitter regions 171, 172 (which may affect, for example, the initial plasma level and may also affect the reverse recovery behavior), different back-side emitter regions 171, 172 can have their maximum dI / dt (which is the cause of overvoltage) at different times. This can allow for a significant reduction in overvoltage.

[0092] Another aspect related to softness—which may be particularly relevant to the illustrated variant having the “dead region” 171-1 as further discussed below—is as follows: Here, the plasma is strongly reduced at the back side 10-2, yet no holes are provided to impart softness during commutation. The possible early and strong reduction of free charge carriers in the back-side emitter regions 171, 172 with such a dead region 171-1 can then be suppressed by the corresponding other back-side emitter regions 171, 172, which may still contain plasma and carry current, and thus can suppress oscillations. For example, the design can be such that the “non-soft regions” 171, 172 are removed from the plasma before the “soft regions” 171, 172 are removed from the plasma.

[0093] Figure 4 Another variant embodiment is shown, wherein the lateral distance d2' between adjacent second regions 1722 in the second back-side emitter zone 172 is larger than the lateral distance d2 between adjacent second regions 1712 in the first back-side emitter zone 171. In this embodiment, the minimum lateral extensions x2, x2' of the second segments 171-2 and 172-2 in the first back-side emitter zone 171 and the second back-side emitter zone 172 are substantially equal.

[0094] exist Figure 5 In the exemplary embodiment shown, the first back-side emitter region 171 includes a plurality of first segments 171-1, each of which includes a plurality of first regions 1711, the first regions 1711 being arranged relative to each other with a lateral distance d11 of at most three times the minimum lateral extension x1 of the first region 1711. In other words, each of the first segments 171-1 includes a plurality of first regions 1711 of a second conductivity type arranged in an alternating order with the plurality of regions 1740 of the first conductivity type, similar to the third back-side region 173 in the edge-terminating region 16 described above.

[0095] On the contrary, similar to Figure 2 In one embodiment, the second back-side emitter band 172 does not include any of the first segment 172-1 or the second segment 172-2. Alternatively, in Figure 5In one embodiment, the second back-side emitter region 172 is composed of a region 1740 of a first conductivity type, which forms a continuous contact with the second load terminal structure 12 and has a lateral extension d3 that is at least ten times the minimum lateral extension x1 of the first region 1711.

[0096] For example, although the emitter efficiency may be equal or similar in the first back-side emitter region 171 and the second back-side emitter region 172, the presence of a relatively finely structured first segment 171-1 can reduce the injection efficiency of the first back-side emitter region 171 compared to the second back-side emitter region 172. Consequently, due to the finely structured segment, no free charge carrier injection or only low free charge carrier injection occurs. As a result, dynamic losses can be reduced in the region of the first back-side emitter region 171 compared to the region of the second back-side emitter region 172.

[0097] For example, the finely structured first segment 171-1 can be configured to completely prevent the large-scale injection of electrons or holes. In this case, the first segment 171-1 can also be referred to as a "dead region," similar to the third band 173 already described above with respect to the edge termination region 16.

[0098] exist Figure 6 In the exemplary embodiment shown, the first back-side emitter region 171 includes a plurality of first segments 171-1, each of which includes a plurality of first regions 1711, the first regions 1711 being arranged relative to each other with a lateral distance d11 of at most three times the minimum lateral extension x1 of the first region 1711. The second back-side emitter region 172 includes a plurality of second segments 172-2, each second segment 172-2 being composed of a second region 1722 having a minimum lateral extension x2' of at least ten times the minimum lateral extension x1 of the first region 1711.

[0099] In other words, in Figure 6 In the embodiment, the first back-side emitter zone 171 is as follows Figure 5 The second back-side emitter zone 172 is configured as described in the embodiment. Figure 3 and Figure 4 The configuration is as described in the embodiments.

[0100] For example, according to Figure 5 Compared to the configuration of the second back-side emitter region 172, the relatively coarse structure of the second region 1722 of the second conductivity type in the second back-side emitter region 172 can reduce cathode efficiency. At the same time, the relatively large lateral extension x2' of the second region 1722 (wide p-short-circuit region) can generate strong hole injection during commutation, thus improving the softness of the power semiconductor device 1.

[0101] In the first back-side emitter region 171, the relatively finely structured first segment 171-1 can produce a cathode efficiency similar to the second region 1722 in the second back-side emitter region 172. However, due to the finely structured first segment 171-1, the injection efficiency can be relatively low. Since no additional holes are injected, fewer switching losses (and therefore less significant temperature increases) may occur in this region.

[0102] exist Figure 7 In the exemplary embodiment shown, the first back-side emitter polar band 171 is as described above. Figure 5 and Figure 6 The configuration is as described in the previous embodiment. However, in... Figure 7 In one embodiment, the second back-side emitter band 172 also includes a plurality of finely structured first segments 172-1, wherein the first segments 172-1 have a larger lateral extension x11' compared to the lateral extension x11 of the first segments 171-1 in the first back-side emitter band 171. Further, the lateral distance d1' between adjacent first segments 172-1 in the second back-side emitter band 172 is greater than the lateral distance d1 between adjacent first segments 171-1 in the first emitter band 171.

[0103] exist Figure 8 In the exemplary embodiment shown, the first back-side emitter band 171 includes a plurality of second segments 171-2 (p-short-circuited), as referenced above. Figure 2 and Figure 3 As described in the first back-side emitter region 171 of the embodiment. The second back-side emitter region 172 presents a plurality of first segments 172-1, each first segment including a single relatively small first region 1721 (“micro p-short section”) of a second conductivity type. The first segments 172-1 in the second back-side emitter region 12 are spaced apart from each other by a relatively large lateral distance d1', which exceeds the lateral distance d2 between adjacent second segments 171-2 in the first back-side emitter region 171.

[0104] exist Figure 9 In the embodiment illustrated in the figure, the second back-side emitter zone 172 is as follows: Figure 8 The first back-side emitter region 171 does not include any first segment 171-1 or second segment 171-2, but is composed of a continuous region 1740 of a first conductivity type (e.g., an n++ type region).

[0105] exist Figure 10 In the exemplary embodiment shown, both the second back-side emitter band 172 and the first back-side emitter band 171 exhibit the same characteristics as... Figure 8 and Figure 9 In the embodiment, the second back-side emitter band 172 contains multiple first segments similar to the first segments 171-1, 172-1 (“micro p-short circuits”). In this case, the lateral distance d1 between adjacent first segments 1711 in the first back-side emitter band 171 is relatively large and exceeds the lateral distance d1' between adjacent first segments 1721 in the second back-side emitter band 172.

[0106] exist Figure 11 In the exemplary embodiment shown, each of the first back-side emitter region 171 and the second back-side emitter region 172 includes a plurality of second segments 171-2, 172-2 (“wide p-short-circuit portions”). Additionally, in the second back-side emitter region 172, small first regions 1721 (“micro p-short-circuit portions”) are arranged near each second region 1722. In other variant embodiments (not shown), a plurality of such micro p-short-circuit portions 1721 may be arranged near some or all of the second regions 1722.

[0107] Figure 12 The exemplary embodiments shown in the figure are similar to those shown in the figure. Figure 3 The exemplary embodiments are similar in that both the first back-side emitter region 171 and the second back-side emitter region 172 include a plurality of second segments 171-2, 172-2, wherein the minimum lateral extension x2 of the second region 1712 of the second conductivity type in the first back-side emitter region 171 is smaller than the minimum lateral extension x2' of the second region 1722 of the second conductivity type in the second back-side emitter region 172. However, in this case, as illustrated, the spacing p between adjacent second segments 171-2, 172-2 is substantially equal in the first back-side emitter region 171 and the second back-side emitter region 172.

[0108] For example, the p-region coverage in the first back-side emission polar band 171 may differ from the p-region coverage in the second back-side emission polar band 172 (the fraction of the total area of ​​the first back-side emission polar band 171 or the second back-side emission polar band 172 that is covered by the second regions 1712, 1722), where the difference may be at least 2%, such as at least 5%, at least 10%, at least 20%, or even at least 40%.

[0109] Figures 13A to 13E Each of the figures schematically and exemplary illustrates a portion of a horizontal cross-section of a power semiconductor device 1 according to one or more embodiments. In each case, the cross-section horizontally cuts through the back-side region 17, and illustrates an exemplary geometric pattern in which a second region 1712 of a second conductivity type can be arranged within a region 1740 of a first conductivity type. Figures 13A to 13EThe example shown is a second region 1712 within a first back-side emitter zone 171 (such as the first back-side emitter zone 171 of one of the embodiments described above). However, it should be noted that the same or similar geometric arrangement may also be selected for the second region 1722 within one or more second back-side emitter zones 172 (such as the second back-side emitter zone 172 of one of the embodiments described above).

[0110] As illustrated, in the horizontal cross-section, the second region 1712 can, for example, have at least one of the following: a circular configuration ( Figures 13A to 13B Ring configuration () Figure 13C ); Strip configuration ( Figure 13D ); and cellular configuration ( Figure 13E ).

[0111] Figures 14A to 14F Each schematically and exemplary illustrates a portion of the horizontal cross-section through the dorsal side region 17 according to one or more embodiments. For example, in Figure 14A In the diagram, a small portion of the first back-side emitter region 171 is shown, wherein a second region 1712 of the second conductivity type, embedded in the region 1740 of the first conductivity type, has a circular configuration, as shown in... Figure 13B As shown in the diagram.

[0112] Figure 14B Unlike Figure 14A The point is that, additionally, in the central location between the second zone 1712, the above-mentioned examples are provided, for instance. Figures 5 to 6 The first section 171-1, which describes the species in the first section 171-1 and 172-1, is structured in a very fine manner. Similar to the second section 1712, the first section 171-1 also has a circular shape.

[0113] Figure 14C Showing with Figure 14B The configuration is similar to that of the previous one, the only difference being that the first segment 171-1 of the circle has a larger diameter, and therefore... Figure 14B In the embodiments, it covers a larger area.

[0114] For example, the finely structured first segment 171-1 can be configured to completely prevent the large-scale injection of electrons or holes. In this case, the first segment 171-1 can also be referred to as a "dead region," similar to the one already discussed above. Figures 5 to 6 The first segment 171-1 and the third zone 173 in the edge termination region 16 are described in the embodiments.

[0115] exist Figures 14D to 14FThe image shows some further exemplary configurations of the second section 1712 and the first section 171-1, wherein... Figures 14D to 14E Exemplary embodiments based on, for example Figure 13D The stripe configuration is shown in the image. Figure 14F Exemplary embodiments based on, for example Figure 13C The configuration shown in the figure, wherein according to Figure 14F In the variant, the square-shaped second region 1712 is surrounded by a finely structured first section 171-1.

[0116] It should be noted that, although Figures 14A to 14F A portion of the first back-side emitter zone 171 is shown as an example, but the same or similar geometric arrangement may be selected in one or more second back-side emitter zones 172.

[0117] exist Figures 15A to 15B Another embodiment of the power semiconductor device 1 is shown in the figure. Figure 15B yes Figure 15A A detailed view of section E1. Figures 15A to 15B A power semiconductor device 1 is shown, comprising: a semiconductor body 10 having a front side 10-1 and a back side 10-2; a first load terminal structure 11 coupled to the front side 10-1 and a second load terminal structure 12 coupled to the back side 10-2; an active region 15 of the semiconductor body 10 configured to conduct load current between the first load terminal structure 11 and the second load terminal structure 12; and a drift region 100 of the semiconductor body 10 having a first conductivity type and configured to conduct load current.

[0118] in particular, Figures 15A to 15BA horizontal cross-section of the backside region 17 of the semiconductor body 10 is shown. The backside region 17 is disposed at the backside 10-1 and includes a first backside emitter region strip 171 and a second backside emitter region strip 172 within the active region 15. The first backside emitter region strip 171 is disposed within the active region 15 and has a larger distance to the outer boundary 177 of the active region 15 compared to the second backside emitter region strip 172. The first backside emitter region strip 171 includes a plurality of first segments 171-2, each first segment including a first region 1711 of a second conductivity type, the first region 1711 being arranged to contact the second load terminal structure 12. The second backside emitter region strip 172 includes a plurality of second segments 172-2, each second segment including a second region 1722 of a second conductivity type, the second region 1722 being arranged to contact the second load terminal structure 12. The spacing P, which defines the lattice constant along at least a first lateral direction X, is at least substantially equal in the first back-side emitter zone 171 and the second back-side emitter zone 172. More specifically, the spacing P is the same in the first back-side emitter zone 171 and the second back-side emitter zone 172. The first back-side emitter zone 171 differs from the second back-side emitter zone 172 in that the minimum lateral extension x2 of the first segment 171-2 is greater than the minimum lateral extension x2' of the second segment 172-2. In this embodiment, the first back-side emitter zone 171 differs from the second back-side emitter zone 172 in that the minimum lateral extension x2 of the first region 1711 is greater than the minimum lateral extension x2' of the second region 1722. In the present case, the first segment 171-2 and / or the first region 1711 are arranged in a circular configuration. In the present case, the second segment 172-2 and / or the second region 1722 are arranged in a circular configuration.

[0119] exist Figures 16A to 16C Another embodiment of the power semiconductor device 1 is shown in the figure. Figure 16B yes Figure 16A A detailed view of section E2. Figures 16A to 16C A power semiconductor device 1 is shown, comprising: a semiconductor body 10 having a front side 10-1 and a back side 10-2; a first load terminal structure 11 coupled to the front side 10-1 and a second load terminal structure 12 coupled to the back side 10-2; an active region 15 of the semiconductor body 10 configured to conduct load current between the first load terminal structure 11 and the second load terminal structure 12; and a drift region 100 of the semiconductor body 10 having a first conductivity type and configured to conduct load current.

[0120] in particular, Figures 16A to 16Cshows a horizontal cross-section of a backside region 17 of a semiconductor body 10, the backside region 17 being arranged at the backside 10-1 and including a second backside emitter strip 172 inside an active region 15. The second backside emitter strip 172 includes a plurality of second segments 172-2, each second segment includes a second region 1722 of a second conductivity type, the second region 1722 is arranged in contact with a second load terminal structure 12 and each second region has a minimum lateral extension x100, x101, x102, x103, x104. Along an imaginary straight line L1, for at least three adjacent second segments 172-2, their minimum lateral extensions x100 to x104 increase strictly monotonically.

[0121] According to Figures 16A to 16B the embodiment depicted in, the second segments 172-2 and / or the second regions 1722 have a circular or rounded configuration. The minimum lateral dimensions of five exemplary second segments 172-2 are depicted. The minimum lateral extensions x100, x101, x102, x103, x104 increase as the distance to the outer boundary 177 of the active region increases. In other words, the minimum lateral dimension of the second segments 172-2 may present a maximum value at the geometric center of the active region 15. The minimum lateral extensions may correspond to the following: x100<x101<x102<x103<x104. The pitch P is constant for the five exemplary second segments 172-2. The five exemplary second segments 172-2 are arranged according to a uniform lattice. For the five exemplary second segments 172-2, the distance d(x10n) to the boundary 177 may increase as the minimum lateral extension increases. The distance d(x10n) of the five exemplary second segments 172-2 to the boundary 177 may correspond to the following: d(x100)<d(x101) <d(x102)<d(x103)<d(x104).

[0122] According to Figure 16C the embodiment depicted in, the second segments 172-2 and / or the second regions 1722 have a strip-shaped configuration. The strip-shaped configuration of the strips may be straight, or as depicted in Figure 16C , each of the strip-shaped second segments 172-2 and / or second regions 1722 may form a closed loop (which is only depicted in Figure 16C(Excerpt from the document). The minimum lateral dimensions of three exemplary second segments 172-2 are depicted. The minimum lateral extensions x100, x101, and x102 increase with increasing distance from the outer boundary 177 of the active region. In other words, the minimum lateral dimension of the second segment 172-2 can be maximized at the geometric center of the active region 15. The minimum lateral extensions can correspond to the following: x100 < x101 < x102. For the three exemplary second segments 172-2, the spacing P can be constant or vary along an imaginary line L1. The three exemplary second segments 172-2 are arranged according to a uniform lattice. For the three exemplary second segments 172-2, the distance d(x10n) from the boundary 177 can increase with increasing minimum lateral extensions. The distance d(x10n) from the boundary 177 of the three exemplary second segments 172-2 can correspond to the following: d(x100) < d(x101) < d(x102).

[0123] Figure 15A , Figure 16A or Figure 16C The power semiconductor devices 1 depicted in the text each exhibit a third region 173. Figures 17A to 17D Different embodiments of edge termination for power semiconductor device 1 are shown. Figures 17A to 17D Each of the figures illustrates a different embodiment according to the third region 173. Figure 15A or Figure 16A A detailed view of section E3. The third region 173 may laterally surround the second back-side emitter region 172. The third region 173 may be part of or overlap with the edge termination region of the power semiconductor device 1. The third back-side region 173 may be arranged below the gate channel electrode arranged at the front side 10-1. The lateral extension x6 of the third back-side region 173 may reach at least 0.5 times the vertical thickness z1 of the drift region 100.

[0124] according to Figure 17A and Figure 17B , respectively in Figure 15A or Figure 16A The third region 173 of the power semiconductor device 1 depicted includes a region 1731 of a first conductivity type and a plurality of regions 1732 of a second conductivity type arranged in an alternating sequence to contact the second load terminal structure 12. The regions 1732 of the second conductivity type have a minimum lateral extension of at most 50 μm. The regions 1732 of the second conductivity type may have a minimum lateral extension that is at most 1 / 5, at most 1 / 10, or at most 1 / 15 of the minimum lateral extension x1', x2', x100-x104 of the second segment 172-2 and / or the second region 1722. Figure 17A and Figure 17B The second type of conductive region 1732 is arranged in a circular pattern.

[0125] according to Figure 17A and Figure 17B , respectively in Figure 15A or Figure 16A The third region 173 of the power semiconductor device 1 depicted includes a plurality of regions 1731 of a first conductivity type and a plurality of regions 1732 of a second conductivity type arranged in an alternating sequence to contact the second load terminal structure 12. Both the first conductivity type regions 1731 and the second conductivity type regions 1732 are arranged in a strip-shaped configuration. Each strip forming regions 1731 and 1732 laterally surrounds the second back-side emitter region strip 172.

[0126] according to Figure 17B and Figure 17C , respectively in Figure 15A or Figure 16A The power semiconductor device 1 depicted further includes a spacer region 175 that laterally separates the second back-side emitter region 172 from the third back-side region 173. The minimum lateral extension x7 of the spacer region 175 is at least 0.5 times the vertical thickness z1 of the drift region 100. The spacer region 175 laterally surrounds the second back-side emitter region 172.

[0127] according to Figure 17D , respectively in Figure 15A or Figure 16A The third region 173 of the power semiconductor device 1 depicted includes only a single region 1731 of the first conductivity type. Alternatively, and only according to Figure 17D A single region 1731 can exhibit a second conductive configuration. The first conductive type—or only according to… Figure 17D —A single region 1731 of the second conductivity type contacts the second load terminal structure 12. First conductivity type—or only according to Figure 17D —A single region 1731 of the second conductivity type surrounds the second back-side emitter region 172 laterally.

[0128] The above explains the embodiments related to power semiconductor devices.

[0129] For example, these semiconductor devices can be based on silicon (Si). Therefore, single-crystal semiconductor regions or layers, such as the semiconductor body 10 and its regions / zones, such as regions, can be single-crystal Si regions or Si layers. In other embodiments, polycrystalline silicon or amorphous silicon can be used.

[0130] However, it should be understood that the semiconductor body 10 and its regions / bands can be made of any semiconductor material suitable for manufacturing semiconductor devices. Examples of such materials, to name only a few, include, but are not limited to: elemental semiconductor materials such as silicon (Si) or germanium (Ge); group IV compound semiconductor materials such as silicon carbide (SiC) or silicon germanium (SiGe); binary, ternary, or quaternary group III-V semiconductor materials such as gallium nitride (GaN), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium gallium phosphide (InGaP), aluminum gallium nitride (AlGaN), aluminum indium nitride (AlInN), indium gallium nitride (InGaN), aluminum gallium indium nitride (AlGaInN), or indium gallium arsenide phosphide (InGaAsP); and binary or ternary group II-VI semiconductor materials such as cadmium telluride (CdTe) and mercury cadmium telluride (HgCdTe). The semiconductor materials mentioned above are also referred to as "homogeneous junction semiconductor materials." When two different semiconductor materials are combined, a heterojunction semiconductor material is formed. Examples of heterojunction semiconductor materials include, but are not limited to: aluminum gallium nitride (AlGaN)-aluminum gallium indium nitride (AlGaInN), indium gallium nitride (InGaN)-aluminum gallium indium nitride (AlGaInN), indium gallium nitride (InGaN)-gallium nitride (GaN), aluminum gallium nitride (AlGaN)-gallium nitride (GaN), indium gallium nitride (InGaN)-aluminum gallium nitride (AlGaN), and silicon-silicon carbide (Si). x C 1-x Silicon-SiGe heterojunction semiconductor materials are used. For power semiconductor switching applications, Si, SiC, GaAs, and GaN materials are currently the main materials used.

[0131] For ease of description, spatial relative terms such as "below," "below," "lower part," "above," and "upper part" are used to explain the positioning of one element relative to a second element. These terms are intended to cover different orientations of the corresponding devices, other than those depicted in the figures. Furthermore, terms such as "first," "second," etc., are also used to describe various elements, areas, sections, etc., without any intention of limitation. Throughout the description, the same terms refer to the same elements.

[0132] As used herein, the terms “having,” “containing,” “including,” “comprising,” and “presenting,” etc., are open-ended terms that indicate the presence of the declared element or feature but do not exclude additional elements or features.

[0133] While taking into account the above variations and scope of application, it should be understood that the invention is not limited to the foregoing description or the accompanying drawings. Rather, the invention is limited only by the following claims and their legal equivalents.

Claims

1. A power semiconductor device (1), comprising: - Semiconductor body (10) having a front side (10-1) and a back side (10-2); - A first load terminal structure (11) coupled to the front side (10-1) and a second load terminal structure (12) coupled to the back side (10-2); - An active region (15) of a semiconductor body (10) is configured to conduct load current between a first load terminal structure (11) and a second load terminal structure (12); - A drift region (100) of a semiconductor body (10), the drift region (100) having a first conductivity type and being configured to conduct load current; - The back-side region (17) of the semiconductor body (10) is arranged on the back side (10-1) and includes a first back-side emitter region band (171) and a second back-side emitter region band (172) within the active region (15). ○The first back-side emitter zone (171) is arranged within the active region (15) and has a greater distance to the outer boundary of the active region (15) compared to the second back-side emitter zone (172); ○The first back-side emitter region (171) includes a plurality of first segments (171-1, 172-1), each first segment including at least one first region (1711, 1721) of a second conductivity type, the first regions (1711, 1721) being arranged to contact the second load terminal structure (12); and ○The second back-side emitter region (172) includes a plurality of second segments (171-2, 172-2), each second segment including at least one second region (1712, 1722) of a second conductivity type, the second regions (1712, 1722) being arranged to contact the second load terminal structure (12); ○In the first back-side emitter zone (171) and the second back-side emitter zone (172), the spacing (P) defining the lattice constant along at least the first lateral direction (X) is at least substantially equal; -The first back-side emitter zone (171) differs from the second back-side emitter zone (172) in that the minimum lateral extension (x1, x2) of the first segment (171-1, 172-1) is greater than the minimum lateral extension (x1', x2') of the second segment (171-2, 172-2).

2. A power semiconductor device (1), comprising: - Semiconductor body (10) having a front side (10-1) and a back side (10-2); - A first load terminal structure (11) coupled to the front side (10-1) and a second load terminal structure (12) coupled to the back side (10-2); - An active region (15) of a semiconductor body (10) is configured to conduct load current between a first load terminal structure (11) and a second load terminal structure (12); - A drift region (100) of a semiconductor body (10), the drift region (100) having a first conductivity type and being configured to conduct load current; - The back-side region (17) of the semiconductor body (10) is arranged at the back side (10-1) and includes a second back-side emitter region (172) within the active region (15). ○The second back-side emitter region (172) includes a plurality of second segments (171-2, 172-2), each second segment including at least one second region (1712, 1722) of a second conductivity type, the second regions (1712, 1722) being arranged to contact the second load terminal structure (12) and each second region having a minimum lateral extension (x100-x104); ○ Along the imaginary line (L1), for at least three adjacent second segments (171-2, 172-2), their minimum lateral extension (x100-x104) increases strictly monotonically.

3. The power semiconductor device (1) according to claim 2, wherein the second segments (171-2, 172-2) are arranged according to a lattice having a spacing (P) that defines a lattice constant along at least a first lateral direction (X), wherein the spacing (P) is at least substantially constant for the at least three adjacent second segments (1712, 1722) along the imaginary line (L1).

4. The power semiconductor device (1) according to any one of claims 2 or 3, wherein for the at least three adjacent second regions (1712, 1722), their minimum lateral extension (x100-x104) increases with the distance to the outer boundary of the active region (15).

5. The power semiconductor device (1) according to any one of the preceding claims, wherein the area of ​​each of the first back-side emitter region (171) and the second back-side emitter region (172) extends to at least 5% or even at least 10% of the active region (15).

6. The power semiconductor device (1) according to any one of the preceding claims, wherein the lateral distance (d1, d1', d2, d2') between adjacent first and / or second segments (171-1, 172-1, 171-2, 172-2) reaches at least 50 μm.

7. The power semiconductor device (1) according to any one of the preceding claims, wherein the first region (1711, 1721) has a minimum lateral extension (x1, x2) of up to 50 μm and / or the second region (1712, 1722) has a minimum lateral extension (x1', x2', x100-x104) of at least 50 μm.

8. The power semiconductor device (1) according to any one of the preceding claims, wherein the lateral distance (d1, d2) between adjacent first segments (171-1) in the first emitter zone (171) is at most three times the minimum lateral extension (x1, x2) of the first segment (171-1), and / or the lateral distance (d1', d2') between adjacent second segments (172-1) in the second emitter zone (172) is at most three times the minimum lateral extension (x1', x2', x100-x104) of the second segment (172-1).

9. The power semiconductor device (1) according to any one of the preceding claims, wherein - The first back-side emitter zone (171) includes a plurality of first segments (171-1), wherein each of the first segments (171-1) includes a plurality of first regions (1711), the first regions (1711) being arranged relative to each other with a lateral distance (d11) of at most three times the minimum lateral extension (x1) of the first region (1711); and - The second back-side emitter zone (172) includes a plurality of second segments (172-2), each second segment consisting of a second region (1722), the second region having at least ten times the minimum lateral extension (x1) of the first region (1711) by a minimum lateral extension (x2').

10. The power semiconductor device (1) according to any one of the preceding claims, wherein the back side region (17) further includes a third back side region strip (173), the third back side region strip including at least one region (1731) of a first conductivity type and a plurality of regions (1732) of a second conductivity type arranged in an alternating sequence to contact the second load terminal structure (12), the first conductivity type region (1731) and / or the second conductivity type region (1732) having a minimum lateral extension (x4, x5) of up to 50 μm.

11. The power semiconductor device (1) according to claim 10, wherein the third backside zone (173) is arranged in the edge termination region (16) of the semiconductor body (10).

12. The power semiconductor device (1) according to claim 10 or 11, wherein the third back-side zone (173) is disposed below the gate channel electrode disposed on the front side (10-1).

13. The power semiconductor device (1) according to any one of claims 10 to 12, wherein the lateral extension (x6) of the third backside zone (173) reaches at least 0.5 times the vertical thickness (z1) of the drift region (100).

14. The power semiconductor device (1) according to any one of claims 7 to 13, wherein the back side region (17) further includes a spacer region (175) that laterally separates the second back side emitter region band (172) from the third back side region band (173).

15. The power semiconductor device (1) according to claim 14, wherein the minimum lateral extension (x7) of the spacer region (175) is at least 0.5 times the vertical thickness (z1) of the drift region (100).

16. The power semiconductor device (1) according to any one of the preceding claims, wherein The first back-side emitter zone (171) exhibits each of the first emitter efficiency and the first injection efficiency; The second back-side emitter zone (172) exhibits each of the second emitter efficiency and the second injection efficiency at the nominal current; in - The efficiency of the first emitter differs from that of the second emitter by at least 1%; and / or - The difference between the first injection efficiency and the second injection efficiency is at least 5%; and / or - The injected hole charge in the first back-side emitter zone (171) differs from the injected hole charge in the second back-side emitter zone (172) by at least 10%; and / or - The average backside plasma concentration associated with the first backside emitter zone (171) and the average backside plasma concentration associated with the second backside emitter zone (172) differ by at least 5%.

17. The power semiconductor device (1) according to any one of the preceding claims, wherein in a horizontal cross-section through a first back-side emitter region (171) and / or a second back-side emitter region (172) and / or a third back-side region (173), the regions (1711, 1721, 1712, 1722) of a second conductivity type present at least one of the following: a circular configuration; a ring configuration; a strip configuration; and a honeycomb configuration.

18. The power semiconductor device (1) according to any one of the preceding claims, wherein the semiconductor body (10) includes a field stop region (100-1) disposed between the drift region (100) and the back side region (17) and has a higher dopant concentration of a first conductivity type compared to the drift region (100).

19. The power semiconductor device (1) of claim 18, wherein the back-side region (17) comprises one or more regions (1740) of a first conductivity type, which are arranged to contact the second load terminal structure (12) and have a higher dopant concentration of the first conductivity type compared to the field stop region (100-1).

20. The power semiconductor device (1) according to claim 18 or 19, wherein the dopant concentration of the second conductivity type in the first region (1711, 1721) and / or the dopant concentration in the second region (1712, 1722) is greater than the dopant concentration of the first conductivity type in the field stop region (100-1).

21. The power semiconductor device (1) according to any one of the preceding claims, wherein the power semiconductor device (1) is or includes at least one of the following: a power diode; an RC-IGBT; a power MOSFET.

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