Semiconductor device and method of forming the same

Abstract

The inner sidewall spacers are formed prior to forming the epitaxial source / drain features, and the outer sidewall spacers are formed after forming the epitaxial source / drain features. The two-tier sidewall spacer design increases the volume of the epitaxial source / drain features, thereby improving ion performance. The thicker sidewall spacers also reduce the capacitance between the source / drain contacts and the gate electrode. In some embodiments, the semiconductor nanosheets can be etched to reduce the thickness prior to forming the replacement gate structure. The nanosheets with reduced thickness improve device swing performance, reduce DIBL effects without sacrificing channel resistance and epitaxial growth margin. Embodiments of the present application also relate to semiconductor devices and methods of forming the same.

Description

Technical Field

[0001] Embodiments of this application relate to semiconductor devices and methods of forming the same. Background Technology

[0002] The semiconductor industry has experienced sustained rapid growth due to the ever-increasing integration density of various electronic components. To a large extent, this increase in integration density stems from the repeated reduction in the minimum component size, allowing more components to be integrated into a given chip area. As the minimum component size decreases, the resistance of the source / drain components increases, which affects device performance. Summary of the Invention

[0003] Some embodiments of this application provide a semiconductor device, including: an epitaxial source / drain component having a first side, a second side opposite to the first side, and a small planar surface connecting the first side and the second side; two or more semiconductor layers contacting the first side of the epitaxial source / drain component; a gate structure enclosing the two or more semiconductor layers; an inner spacer disposed between the two or more semiconductor layers, wherein the inner spacer contacts the first side of the epitaxial source / drain component and the gate structure, and the inner spacer has a first thickness; and a sidewall spacer contacting the gate structure, the first side of the epitaxial source / drain component, and the small planar surface, wherein a portion of the sidewall spacer has a second thickness, and the ratio of the second thickness to the first thickness is in the range of 1.1 and 2.0.

[0004] Some other embodiments of this application provide a semiconductor device comprising: two or more semiconductor layers, wherein each of the two or more semiconductor layers includes a first end portion, a second end portion, and an intermediate portion connecting the first end portion and the second end portion, the first end portion having a first channel thickness, the intermediate portion having a second channel thickness, the second end portion having a third channel thickness, and the second channel thickness being less than the first channel thickness and the third channel thickness; a gate structure enclosing the intermediate portion of the two or more semiconductor layers; a first source / drain component having a first side and a first planar surface connected to the first side, wherein the first side contacts the first end portion of the two or more semiconductor layers; a second source / drain component having a second side and a second planar surface connected to the second side, wherein the second side contacts the second end portion of the two or more semiconductor layers; an inner spacer disposed between the two or more semiconductor layers; a first sidewall spacer disposed on the gate structure; and a second sidewall spacer disposed on the gate structure.

[0005] Further embodiments of this application provide a method for forming a semiconductor device, comprising: forming a fin structure, the fin structure including two or more first semiconductor layers stacked alternately with two or more second semiconductor layers; forming a sacrificial gate structure over the fin structure; forming an inner sidewall spacer over the sidewall of the sacrificial gate structure, wherein the inner sidewall spacer has a side facing away from the sacrificial gate structure, wherein the inner sidewall spacer has a reduced thickness; etching back the fin structure along the sidewall of the inner sidewall spacer; forming the inner spacer by partially removing two or more second semiconductor layers and filling them with a dielectric material; and etching the fin structure from the two or more first semiconductor layers... A source / drain component is epitaxially grown in the bulk layer, wherein the source / drain component has a side and a planar surface, and the side of the source / drain component partially contacts the side surface of the inner spacer and the inner sidewall spacer, the reduced thickness of the inner sidewall spacer increasing the volume of the source / drain component; an outer sidewall spacer is formed above the side surface of the inner sidewall spacer, wherein the outer sidewall spacer contacts the planar surface of the source / drain component; a contact etch stop layer (CESL) is deposited above the outer sidewall spacer and the source / drain component; and an interlayer dielectric (ILD) layer is deposited above the contact etch stop layer. Attached Figure Description

[0006] The various aspects of the invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industrial practice, the components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the components may be arbitrarily increased or decreased.

[0007] Figure 1 This is a flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0008] Figures 2 to 5 , Figures 5A to 5E , Figures 6A to 6B , Figures 7A to 7D , Figures 8A to 8F , Figures 9A to 9F , Figures 10A to 10F , Figures 11A to 11F , Figures 12A to 12C , Figures 13A to 13F and Figures 14A to 19H The illustrations schematically depict various stages of manufacturing a semiconductor device according to embodiments of the present invention. Detailed Implementation

[0009] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the invention. Of course, these are merely examples and are not intended to limit the invention. For example, in the following description, forming a first component on or over a second component can include embodiments where the first and second components are in direct contact, and can also include embodiments where an additional component can be formed between the first and second components, such that the first and second components are not in direct contact. Furthermore, reference numerals and / or characters may be repeated in various instances of the invention. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0010] Furthermore, for ease of description, this document may use spatial relative terms such as “below,” “under,” “lower,” “above,” “top,” and “upper” to describe the relationship between one element or component and another (or other elements or components) as shown in the figures. In addition to the orientations shown in the figures, spatial relative terms are intended to include different orientations of the device during use or operation. The device may be oriented in other ways (rotated 64 degrees or in other orientations), and the spatial relative descriptors used herein can be interpreted accordingly.

[0011] The foregoing provides a general overview of some aspects of the embodiments described herein. While some embodiments described herein are set in the context of nanosheet channel FETs, implementations of some aspects of the invention can be used in other processes and / or in other devices, such as planar FETs, FinFETs, horizontal gate all-around (HGAA) FETs, vertical gate all-around (VGAA) FETs, and other suitable devices. Those skilled in the art will readily understand that other modifications may be considered within the scope of this invention. Furthermore, while method embodiments may be described in a particular order, various other method embodiments may be implemented in any logical order and may include fewer or more steps than those described herein. In this invention, source / drain refers to the source and / or drain. Source and drain are used interchangeably.

[0012] Fins can be patterned using any suitable method. For example, fins can be patterned using one or more photolithography processes, including dual-patterning or multi-patterning processes. Typically, dual-patterning or multi-patterning processes combine photolithography and self-alignment processes, thereby allowing the creation of patterns with, for example, a smaller spacing than that achievable using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern fins.

[0013] Gate-all-around (GAA) transistor structures can be patterned using any suitable method. For example, the structure can be patterned using one or more photolithography processes, including dual-patterning or multi-patterning processes. Typically, dual-patterning or multi-patterning processes combine photolithography and self-alignment processes, thereby allowing the creation of patterns with, for example, a smaller spacing than that achievable using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the GAA structure.

[0014] Figure 1 This is a flowchart of a method 100 for manufacturing a semiconductor device according to an embodiment of the present invention. Figures 2 to 5 , Figures 5A to 5E , Figures 6A to 6B , Figures 7A to 7D , Figures 8A to 8F , Figures 9A to 9F , Figures 10A to 10F , Figures 11A to 11F , Figures 12A to 12C , Figures 13A to 13F and Figures 14A to 14F The illustrations schematically depict various stages of manufacturing an exemplary semiconductor device 200 according to embodiments of the present invention. Specifically, the semiconductor device 200 can be manufactured according to... Figure 1 Method 100 is used to manufacture it.

[0015] In operation 102 of method 100, a plurality of fin structures are formed on the substrate on which a semiconductor device will be formed. Figure 2 and Figure 3 This is a schematic three-dimensional view of semiconductor device 200 during operation 102. (See diagram below.) Figure 2 As shown, a substrate 202 is provided for forming a semiconductor device 200 thereon. The substrate 202 may include single-crystal semiconductor materials, such as, but not limited to, Si, Ge, SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, and InP. The substrate 202 may include various doping configurations depending on the circuit design. Figure 2 In the substrate 202, there are p-doped regions or p-wells 204a and n-doped regions or n-wells 204b. One or more n-type devices, such as nFETs, will be formed above and / or within the p-well 204a. One or more p-type devices, such as pFETs, will be formed above and / or within the n-well 204b. Figure 2 The p-well 204a is shown to be located in a doped local region of the doped substrate, which is not limiting. In other embodiments, the p-well 204a and n-well 204b may be separated by one or more insulators, such as shallow trench insulation (“STI”).

[0016] A semiconductor stack comprising alternating first semiconductor layers 206a and second semiconductor layers 208a is formed over the p-well 204a to facilitate the formation of nanosheet channels in a multi-gate n-type device, such as a nanosheet channel nFET. The first semiconductor layers 206a and 208a have different compositions. In some embodiments, the two semiconductor layers 206a and 208a provide different oxidation rates and / or different etch selectivity. In a later fabrication stage, a portion of the second semiconductor layer 208a forms a nanosheet channel in the multi-gate device. As an example, three first semiconductor layers 206a and three second semiconductor layers 208a are arranged alternately, such as... Figure 2 As shown in the diagram. More or fewer semiconductor layers 206a and 208a may be included, depending on the desired number of channels to be formed in the semiconductor device. In some embodiments, the number of semiconductor layers 206a and 208a is between 1 and 10.

[0017] In some embodiments, the first semiconductor layer 206a may include silicon germanium (SiGe). The first semiconductor layer 206a may be a SiGe layer comprising a molar ratio of Ge greater than 25%. For example, the first semiconductor layer 206a may be a SiGe layer comprising a molar ratio of Ge in the range of 25% to 50%. The second semiconductor layer 208a may include silicon. In some embodiments, the second semiconductor layer 208a may be a Ge layer. The second semiconductor layer 208a may include an n-type dopant, such as phosphorus (P), arsenic (As), etc.

[0018] Similarly, a semiconductor stack comprising alternating third semiconductor layer 206b and fourth semiconductor layer 208b is formed above n-well 204b to facilitate the formation of nanosheet channels in multi-gate p-type devices, such as nanosheet channel pFETs.

[0019] In some embodiments, the third semiconductor layer 206b may include silicon germanium (SiGe). The third semiconductor layer 206b may be a SiGe layer comprising a molar ratio of Ge greater than 25%. For example, the third semiconductor layer 206b may be a SiGe layer comprising a molar ratio of Ge in the range of 25% to 50%. The fourth semiconductor layer 208b may include: silicon; Ge; compound semiconductors such as SiC, GeAs, GaP, InP, InAs, and / or InSb; alloy semiconductors such as SiGe, GaAsP, AlInAs, AlGaAs, InGaAs, GaInP, and / or GaInAsP; or combinations thereof. In some embodiments, the fourth semiconductor layer 208b may be a Ge layer. The fourth semiconductor layer 208b may include p-type dopants, boron, etc.

[0020] Semiconductor layers 206a, 206b, 208a, and 208b can be formed using molecular beam epitaxy (MBE), metal-organic chemical vapor deposition (MOCVD), and / or other suitable epitaxial growth processes. The semiconductor stack above n-well 204b and p-well 204a can be formed individually using patterning techniques.

[0021] Then, by etching portions of the semiconductor stack and the underlying n-well 204b and p-well 204a respectively, fin structures 210a and 210b are formed, as shown below. Figure 3 As shown. Figure 3 As shown, each fin structure 210a, 210b has a width W1 along the y-direction. The width W1 can be selected according to the circuit design. In some embodiments, the width W1 can be in the range of about 10 nm and about 200 nm. A portion of the semiconductor layers 208a, 208b serves as a channel region connecting the source / drain components in the semiconductor device to be formed. Each semiconductor layer 208a, 208b may have a thickness CT1 along the z-direction. In some embodiments, the thickness CT1 is in the range of about 4 nm and about 10 nm. Semiconductor layers 206a, 206b are used to define the vertical distance between adjacent channel regions formed by the semiconductor layers 208a, 208b for the subsequently formed device. Each semiconductor layer 206a, 206b may have a thickness GT1 along the z-direction. In some embodiments, the thickness GT1 of the semiconductor layers 206a, 206b is equal to or greater than the thickness CT1 of the semiconductor layers 208a, 208b. In some embodiments, the thickness GT1 is in the range of about 6 nm and about 25 nm. The channel spacing S1 can be in the range of 10nm and 23nm.

[0022] In operation 104, an isolation layer 212 is formed, such as Figure 4 As shown, Figure 4 This is a schematic diagram of semiconductor device 200. An isolation layer 212 fills the trench between fin structures 210a and 210b and is then etched back beneath the semiconductor stack of fin structures 210a and 210b. The isolation layer 212 can be formed by high-density plasma chemical vapor deposition (HDP-CVD), flowable CVD (FCVD), or other suitable deposition processes. In some embodiments, the isolation layer 212 may comprise silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG), a low-k dielectric, or combinations thereof. In some embodiments, the isolation layer 212 is formed by a suitable deposition process to cover the fin structures 210a and 210b, filling the trench between the fin structures 210a and 210b, and then the isolation layer 212 is etched using a suitable anisotropic etching process to recess the isolation layer 212 to expose the active portions of the fin structures 210a and 210b.

[0023] In operation 106, a sacrificial gate structure 214 is formed above the isolation layer 212 and above the exposed portions of the fin structures 210a and 210b, and an inner sidewall spacer 216 is formed on the sidewall of the sacrificial gate structure 214, such as... Figure 5 and Figures 5A to 5E As shown in the image. Figure 5 This is a schematic 3D view of semiconductor device 200. Figure 5A It is along Figure 5 A schematic cross-sectional view of the semiconductor device 200 with line AA in the figure. Figure 5B It is along Figure 5 A schematic cross-sectional view of the semiconductor device 200 of line BB in the diagram. Figure 5C It is along Figure 5 A schematic cross-sectional view of the semiconductor device 200 with line CC in the figure. Figure 5D It is along Figure 5 A schematic cross-sectional view of the semiconductor device 200 with line DD in the figure. Figure 5E It is along Figure 5 A schematic cross-sectional view of the semiconductor device 200 with line EE in the figure.

[0024] A sacrificial gate structure 214 is formed over the portion of the fin structures 210a and 210b that will become the channel region. The sacrificial gate structure 214 may include a sacrificial gate dielectric layer 218, a sacrificial gate electrode layer 220, a pad layer 222, and a mask layer 224.

[0025] The sacrificial gate dielectric layer 218 may be conformally formed over the fin structures 210a, 210b and the isolation layer 212. In some embodiments, the sacrificial gate dielectric layer 218 may be deposited by a CVD process, a subatmospheric pressure CVD (SACVD) process, a FCVD process, an ALD process, a PVD process or other suitable processes. The sacrificial gate dielectric layer 218 may include one or more layers of dielectric material, such as SiO2, SiN, high-k dielectric material and / or other suitable dielectric material.

[0026] The sacrificial gate electrode layer 220 may be blanket-deposited over the sacrificial gate dielectric layer 218. The sacrificial gate electrode layer 220 comprises silicon, such as polycrystalline silicon or amorphous silicon. The thickness of the sacrificial gate electrode layer is in the range of about 42 nm to about 200 nm. In some embodiments, the sacrificial gate electrode layer 220 undergoes a planarization operation. The sacrificial gate electrode layer 220 may be deposited using CVD, PVD, ALD, or other suitable processes including LPCVD and PECVD.

[0027] Subsequently, a pad layer 222 and a mask layer 224 are formed over the sacrificial gate electrode layer 220. The pad layer 222 may include silicon nitride. The mask layer 224 may include silicon oxide. Next, the mask layer 224, the pad layer 222, the sacrificial gate electrode layer 220, and the sacrificial gate dielectric layer 218 are patterned to form a sacrificial gate structure 214.

[0028] Inner sidewall spacers 216 are formed on the sidewalls of each sacrificial gate structure 214, such as Figure 5A , Figure 5B and Figure 5D As shown in the diagram. After the sacrificial gate structure 214 is formed, inner sidewall spacers 216 are formed on the sidewalls of the sacrificial gate structure 214, as shown in the diagram. Figure 5A and Figure 5B As shown in the diagram, the inner sidewall spacer 216 has a thickness T1 along the x-direction and covers portions of the fin structures 210a, 210b. In some embodiments, the thickness T1 can be in the range of about 3 nm and about 12 nm. In some embodiments, the thickness T1 is selected to correspond to the thickness of the inner spacer in the fin structures 210a, 210b to be formed under the sacrificial gate structure 214. Figure 5D This is a cross-sectional view of one of the spacers 216 along the inner wall. (See figure) Figure 5D As shown, the inner wall spacer 216 is in contact with the fin structures 210a and 210b.

[0029] In some embodiments, the inner sidewall spacer 216 is formed by blanket deposition of one or more layers of insulating material. The insulating material can be deposited using any suitable deposition method. In some embodiments, the inner sidewall spacer 216 can be formed by ALD or CVD. In some embodiments, the insulating material of the inner sidewall spacer 216 may include one or more dielectric materials. In some embodiments, the insulating material of the inner sidewall spacer 216 may include a dielectric material selected from silicon oxide, silicon nitride (such as Si3N4), carbon-doped silicon oxide, nitrogen-doped silicon oxide, porous silicon oxide, or combinations thereof.

[0030] In some embodiments, the inner sidewall spacer 216 undergoes anisotropic etching to remove the inner sidewall spacer 216 from horizontal surfaces such as the top surface of mask layer 224 and the top surface of isolation layer 212. In other embodiments, the inner sidewall spacer 216 on the horizontal surface can be removed during fin structure etchback in operation 108, which is discussed below.

[0031] In operation 108, the fin structures 210a and 210b not covered by the sacrificial gate structure 214 are etched back, such as Figures 6A to 6B As shown, Figures 6A to 6B They are along Figure 5A schematic cross-sectional view of semiconductor device 200 with lines AA and BB in the figure. Even though described together in each operation, the etching processes for the region for the p-type device (i.e., above the n-well 204b) and the region for the n-type device (i.e., above the p-well 204a) are sometimes implemented separately using patterned masks and different processing schemes.

[0032] The fin structures 210a, 210b not covered by the sacrificial gate structure 214 and the inner sidewall spacer 216 are etched to expose the well portions 204a, 204b of each fin structure 210a, 210b and form the source / drain cavity 205. In some embodiments, suitable dry etching and / or wet etching may be used to remove the semiconductor layers 206a, 206b, 208a, 208b together or separately.

[0033] In operation 110, an inner spacer 226 is formed, such as Figures 7A to 7D As shown in the image. Figure 7A , Figure 7B , Figure 7D They are along Figure 5 A schematic cross-sectional view of semiconductor device 200 with lines AA, BB, and DD in the figure. Figure 7C yes Figure 7A A schematic enlarged view of the semiconductor device in region 7C marked in the middle.

[0034] To form the inner spacer 226, the semiconductor layers 206a and 206b exposed to the source / drain cavity 205 are etched from the semiconductor layers 208a and 208b in the horizontal or x-direction to form the inner spacer cavity beneath the inner sidewall spacer 216. In some embodiments, the semiconductor layers 206a and 206b can be selectively etched using a wet etchant, such as, but not limited to, ammonium hydroxide (NH4OH), tetramethylammonium hydroxide (TMAH), ethylenediamine catechol (EDP), or potassium hydroxide (KOH) solution.

[0035] After forming the inner spacer cavity, an inner spacer 226 is formed in the inner spacer cavity by conformal deposition, and then the insulating layer is partially removed by an anisotropic etching process. The insulating layer can be formed by ALD or any other suitable method. The subsequent etching process removes most of the insulating layer except for the cavity interior, producing the inner spacer 226. In some embodiments, the inner spacer 226 may include one or more dielectric materials. In some embodiments, the inner spacer 226 may include dielectric materials such as SiO2-, SiON-, SiOC-, or SiOCN-based dielectric materials, air gaps, or combinations thereof.

[0036] The inner spacer 226 and the inner sidewall spacer 216 may be formed of the same material or different materials to achieve the desired performance. In some embodiments, the inner spacer 226 may have a lower dielectric constant k than the inner sidewall spacer 216 to obtain the desired performance, such as low capacitance. In some embodiments, the inner spacer 226 may have a higher dielectric constant k than the inner sidewall spacer 216 to obtain the desired performance, such as increased device reliability.

[0037] like Figure 7C As shown, the inner spacer 226 has a thickness T2 along the x-direction. In some embodiments, the thickness T2 of the inner spacer 226 is substantially similar to the thickness T1 of the inner sidewall spacer 216. In some embodiments, the thickness T2 can be in the range of about 3 nm to about 12 nm. A thickness T2 thinner than 3 nm cannot provide sufficient isolation between the subsequently formed source / drain components and the gate electrode on the opposite side of the inner spacer 226. A thickness T2 greater than 12 nm can reduce the length of the channel region without additional benefit. The side surfaces 216s of the inner sidewall spacer 216 face the source / drain cavity 205. The side surfaces 226s of the inner spacer 226 also face the source / drain cavity 205. In some embodiments, the side surfaces 216s of the inner sidewall spacer 216 and the side surfaces 226s of the inner spacer 226 are substantially coplanar in the yz plane.

[0038] In operation 112, epitaxial source / drain components 232n and 232p are formed, such as Figures 8A to 8F As shown in the image. Figure 8A , Figure 8B , Figure 8C , Figure 8D , Figure 8E They are along Figure 5 A schematic cross-sectional view of semiconductor device 200 with lines AA, BB, CC, DD, and EE. Figure 8F yes Figure 8A A schematic partial enlarged view of the semiconductor device in region 8F marked in the middle. The epitaxial source / drain component 232n for the N-type device and the epitaxial source / drain component 232p for the P-type device are epitaxially grown from the exposed semiconductor surface of the fin structures 210a, 210b in the source / drain cavity 205.

[0039] The epitaxial source / drain component 232n for n-type devices may include one or more layers of Si, SiP, SiC, and SiCP. The epitaxial source / drain component 232n may also include N-type dopants such as phosphorus (P), arsenic (As), etc. In some embodiments, the epitaxial source / drain component 232n may be a Si layer including a phosphorus (P) dopant. Figure 8EThe epitaxial source / drain component 232n shown has a substantially elliptical shape in cross-section. However, depending on the design, the epitaxial source / drain component 232n can be other shapes. The epitaxial source / drain component 232p for a p-type device may comprise one or more layers of Si, SiGe, or Ge having a p-type dopant (such as boron (B)). In some embodiments, the epitaxial source / drain component 232p may be a SiGe material including boron as a dopant. Figure 8E The epitaxial source / drain component 232p shown has a substantially hexagonal shape in cross-section. However, the epitaxial source / drain component 232p can be other shapes depending on the design. The epitaxial source / drain components 232n and 232p can be formed by any suitable method, such as by CVD, CVD epitaxy, molecular beam epitaxy (MBE), or any suitable deposition technique.

[0040] like Figure 8A As shown, epitaxial source / drain components 232n are epitaxially grown in the source / drain cavity 205 from the exposed surfaces of the p-well 204a and the semiconductor layer 208a. Similarly, epitaxial source / drain components 232p are epitaxially grown in the source / drain cavity 205 from the exposed surfaces of the n-well 204p and the semiconductor layer 208b.

[0041] Each epitaxial source / drain component 232n, 232p also includes individual small planar surfaces 232f generated by the growth of the crystal structure. For example... Figure 8E As shown, the planar surface 232f defines the shape of the epitaxial source / drain components 232n and 232p in the cross-section. After operation 112, the planar surface 232f is typically an exposed surface. Typically, the top surface 232ft of the epitaxial source / drain components 232n and 232p is one of the planar surfaces 232f. Figure 8E In some embodiments, the top surface 232ft is substantially horizontal with the xy plane. Alternatively, the top surface 232ft may have other orientations or may be curved. In some embodiments, the top surface 232ft may be located in a vertical horizontal position along the z-direction, higher than the topmost surface of the fin structures 210a, 210b.

[0042] Each epitaxial source / drain component 232n, 232p has two sides 232s facing an adjacent sacrificial gate structure 214. A facet surface 232f connects between the two sides 232s. The sides 232s of the epitaxial source / drain components 232n, 232p are in contact with semiconductor layers 208a, 208b, which serve as channel regions in the resulting transistor. The sides 232s of the epitaxial source / drain components 232n, 232p are also in contact with the side surfaces 226s of the inner spacer 226 and the side surfaces 216s of the inner sidewall spacer 216. Figure 8EIn the diagram, the cross-sections of fin structures 210a and 210b are shown as dashed lines. The side 232s of the fin structures 210a and 210b, outside the dashed lines, contacts the side 216s of the inner sidewall spacer 216. (As shown...) Figure 8F As shown, the side 226s of the inner spacer 226 covers the side 232s of the adjacent epitaxial source / drain component 232n or 232p.

[0043] As discussed above, operations 108, 110, and 112 can be performed separately for n-type devices and p-type devices. For example, operations 108, 110, and 112 can be performed first in the n-type device region while the p-type device region is covered by a photoresist layer and / or a mask layer, and operations 108, 110, and 112 can be performed again in the p-type device region while the n-type device region is covered by a photoresist layer and / or a mask layer.

[0044] In operation 114, an outer wall spacer 234 is formed, such as Figures 9A to 9F As shown in the image. Figure 9A , Figure 9B They are along Figure 5 A schematic cross-sectional view of semiconductor device 200 with lines AA and BB in the figure. Figure 9C , Figure 9D , Figure 9E They are along Figure 9A A schematic cross-sectional view of semiconductor device 200 with lines CC, DD, and EE in the figure. Figure 9F yes Figure 9A A schematic enlarged view of the semiconductor device in region 9F marked in the middle.

[0045] The outer wall spacer 234 is formed on the exposed side 216s of the inner wall spacer 216, such as Figures 9A to 9E As shown in the diagram. The outer wall spacer 234 increases the total thickness of the sidewall spacers between the subsequently formed gate electrode and source / drain contact components. In some embodiments, the outer wall spacer 234 is formed by blanket deposition of one or more layers of insulating material followed by an anisotropic etching process. The insulating material can be deposited by any suitable deposition method. In some embodiments, the outer wall spacer 234 can be formed by ALD or CVD. In some embodiments, the insulating material of the outer wall spacer 234 may include one or more dielectric materials. In some embodiments, the insulating material of the outer wall spacer 234 may include a dielectric material selected from silicon oxide, silicon nitride (such as Si3N4), carbon-doped silicon oxide, nitrogen-doped silicon oxide, porous silicon oxide, or combinations thereof. In some embodiments, the inner wall spacer 216 and the outer wall spacer 234 may be formed of the same material. In other embodiments, the inner wall spacer 216 and the outer wall spacer 234 may be formed of different materials.

[0046] The outer sidewall spacer 234 is formed with increased thickness as the inner sidewall spacer 216, except for the portion of the inner sidewall spacer 216 disposed between the sacrificial gate structure 214 and the epitaxial source / drain components 232n, 232p, such as Figure 9C and Figure 9D As shown in the image. Figure 9E The region of the outer wall spacer 234 in the yz plane is shown. Figure 8D The region of the inner wall spacer 216 in the yz plane is shown. The outer wall spacer 234 covers a smaller region in the yz plane than the adjacent inner wall spacer 216. Figure 9A , Figure 9E and Figure 9F As shown, the outer sidewall spacer 234 contacts the source / drain components 232n, 232p at the end portion of the planar surface 232f. Each pair of inner sidewall spacers 216 and outer sidewall spacers 234 forms a sidewall spacer function to provide insulation between conductive components on opposite sides. The sidewall spacers are characterized by having two thickness levels and contacting the source / drain components 232n, 232p on the sides 232s and the planar surface 232f.

[0047] The outer sidewall spacer 234 has a thickness T3 along the x-direction and covers a portion of the adjacent inner sidewall spacer 216. In some embodiments, the thickness T3 can be in the range of about 1 nm and about 12 nm. Figure 9F As shown, the inner sidewall spacer 216 and the outer sidewall spacer 234 can be formed with a total thickness T4 along the x-direction. In some embodiments, the total thickness T4 is in the range of about 4 nm and 15 nm. By selecting thicker sidewall spacers and thinner inner spacers, embodiments of the present invention improve the performance of the transistor to be formed. For example, thicker sidewall spacers reduce the capacitance between the subsequently formed source / drain contacts and the gate electrode and improve device reliability, while thinner inner spacers increase the volume of the source / drain components 232n, 232p, thereby reducing the source / drain resistance and improving ion performance, expanding the growth margin of the source / drain components, and providing greater compressive strain for hole mobility in P-type devices.

[0048] In some embodiments, the total thickness T4 is greater than the thickness T2 of the inner spacer 226. In some embodiments, the total thickness T4 can be in the range of about 1 nm and about 5 nm. A thickness difference of less than 1 nm does not provide sufficient benefit to justify forming the sidewall spacer in two different operations, and a thickness difference of more than 5 nm reduces the spacing used for the source / drain contact components without any additional benefit. In some embodiments, the ratio of the total thickness T4 to the thickness T2 can be in the range of 1.1 and 2.0. A ratio of less than 1.1 does not provide sufficient benefit to justify forming the sidewall spacer in two different operations, and a ratio of more than 2 reduces the spacing used for the source / drain contact components without any additional benefit.

[0049] In operation 116, a contact etch stop layer (CESL) 236 and an interlayer dielectric (ILD) layer 238 are conformally formed above the semiconductor substrate, such as... Figures 10A to 10F As shown in the image. Figure 10A , Figure 10B , Figure 10C , Figure 10D , Figure 10E They are along Figure 5 A schematic cross-sectional view of semiconductor device 200 with lines AA, BB, CC, DD, and EE. Figure 10F It is along Figure 10A A schematic cross-sectional view of the semiconductor device 200 with line FF in the figure.

[0050] CESL 236 can be uniformly formed above the exposed surface of semiconductor device 200. CESL 236 is formed on the exposed planar surface 232f of epitaxial source / drain components 232n and 232p, the exposed surface of the outer sidewall spacer 234, and the exposed surface of the isolation layer 212. CESL 236 serves as an etch stop layer to provide protection for source / drain components 232n and 232p during the formation of source / drain contact components. CESL 236 may comprise Si3N4, SiON, SiCN, or any other suitable material and can be formed by CVD, PVD, or ALD.

[0051] An ILD layer 238 is formed over a CESL 236. Materials used for the ILD layer 238 include compounds comprising Si, O, C, and / or H, such as silicon oxide, SiCOH, and SiOC. Organic materials, such as polymers, may be used for the ILD layer 238. In some embodiments, the ILD layer 238 may be formed by flowable CVD (FCV). The ILD layer 238 protects the epitaxial source / drain components 232n, 232p during the removal of the sacrificial gate structure 214. A planarization process, such as a CMP process, may be performed after the deposition of the material for the ILD layer 238 to expose the sacrificial gate structure 214 for subsequent processing.

[0052] In operation 118, an optional gate-end dielectric structure 240 can be formed, such as... Figure 10C , Figure 10D and Figure 10F As shown in the diagram, the gate-end dielectric structure 240 serves as an isolation component to divide the gate structure into independent portions as independent gates according to the circuit design. The gate-end dielectric structure 240 can be formed by a photolithography process to expose portions of the sacrificial gate structure 214, as well as portions of the inner sidewall spacers 216 and the outer sidewall spacers 234. This is followed by one or more etching processes to selectively remove the exposed portions of the sacrificial gate structure 214, as well as the inner sidewall spacers 216 and the outer sidewall spacers 234. Dielectric material is then deposited to form the gate-end dielectric structure 240.

[0053] In some embodiments, the gate dielectric structure 240 may include a dielectric material selected from silicon, oxygen, carbon, nitrogen, low-k dielectrics (k < 3.5), other suitable materials, or combinations thereof. For example, the gate dielectric structure 240 may include silicon oxide, silicon nitride, silicon oxynitride, or silicon carbide. The gate dielectric structure 240 may be formed by any suitable method, such as CVD, PVD, or ALD.

[0054] In operation 120, the sacrificial gate structure 214 is removed and a replacement gate structure 248 is formed, as follows: Figures 11A to 11F As shown in the image. Figure 11A , Figure 11B , Figure 11C , Figure 11D They are along Figure 5 A schematic cross-sectional view of semiconductor device 200 with lines AA, BB, CC, and DD in the figure. Figure 11E and Figure 11F They are along Figure 11A A schematic cross-sectional view of semiconductor device 200 with lines EE and FF in the figure.

[0055] The sacrificial gate dielectric layer 218 and the sacrificial gate electrode layer 220 are removed using dry etching, wet etching, or a combination thereof. Semiconductor layers 206a and 206b are exposed and subsequently removed, creating gate cavities around nanosheets of semiconductor layers 208a and 208b. A replacement gate structure 248 is then filled into the gate cavity. The replacement gate structure 248 includes gate dielectric layers 242n and 242p and gate electrode layers 244n and 244p, respectively, for n-type and p-type devices. In some embodiments, an interface layer (not shown) may be formed on semiconductor layers 208a and 208b prior to the formation of the gate dielectric layers 242n and 242p (collectively referred to as 242).

[0056] Gate dielectric layers 242n and 242p are formed on the exposed surfaces within the gate cavity. Gate dielectric layers 242n and 242p can have different compositions and dimensions for N-type and P-type devices, and are formed individually using patterned mask layers and different deposition schemes. Gate dielectric layers 242n and 242p can comprise one or more layers of dielectric materials, such as silicon oxide, silicon nitride, or high-k dielectric materials, other suitable dielectric materials, and / or combinations thereof. Examples of high-k dielectric materials include HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, alumina, titanium oxide, hafnium dioxide-alumina (HfO2-Al2O3) alloys, other suitable high-k dielectric materials, and / or combinations thereof. Gate dielectric layers 242n and 242p can be formed by CVD, ALD, or any suitable method.

[0057] Gate electrode layers 244n and 244p (collectively referred to as 244) are formed on gate dielectric layers 242n and 242p to fill the gate cavity. Gate electrode layers 244n and 244p may comprise one or more layers of conductive materials, such as tungsten, aluminum, copper, titanium, tantalum, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, metal alloys, other suitable materials, and / or combinations thereof. In some embodiments, gate electrode layers 244n and 244p may be formed by CVD, ALD, electroplating, or other suitable methods. In some embodiments, gate electrode layers 244n and 244p may comprise different conductive materials and be formed in different processes. Optionally, gate electrode layers 244n and 244p may comprise the same conductive material and be formed in the same process. After the gate electrode layers 244n and 244p are formed, a planarization process, such as CMP, is performed to remove excess deposits of gate electrode material and expose the top surface of the ILD layer 238.

[0058] In operation 122, a self-aligned contact (SAC) layer 250 is formed above the gate structure 248, such as... Figures 12A to 12C As shown in the image. Figure 12A , Figure 12B , Figure 12C They are along Figure 5 A schematic cross-sectional view of semiconductor device 200 with lines AA, BB, and CC in the figure.

[0059] In some embodiments, a metal gate etch-back (MGEB) process is performed to form a self-aligned contact (SAC) layer 250. One or more etching processes are performed to remove portions of the gate dielectric layer 242 and the gate electrode layer 244 to form trenches in the region above the remaining gate electrode layer 244. The MGEB process may be a plasma etching process employing one or more etchants such as chlorine-containing gases, bromine-containing gases, and / or fluorine-containing gases. The etching process allows selective etching of the gate dielectric layer 242 and the gate electrode layer 244 relative to the ILD layer 238 and CESL 236. In some embodiments, the inner sidewall spacers 216 and the outer sidewall spacers 234 are also etched back to a level below the top surface of the CESL 236, such that the inner sidewall spacers 216 and the outer sidewall spacers 234 can be covered and protected by the subsequently formed SAC layer 250 while forming source / drain metal contacts.

[0060] In some embodiments, a metal gate pad (not shown) may be deposited first on the exposed surface of the trench above the gate electrode layer 244 before depositing the SAC layer 250. The metal gate pad and SAC layer 250 may be formed by a suitable deposition process, such as CVD, PVD, or ALD. The metal gate pad may act as a diffusion barrier for the gate electrode layer 244. The metal gate pad may be a dielectric layer, including but not limited to SiO, SiN, SiC, SiCN, SiOC, SiON, SiOCN, ZrO, ZrN, or combinations thereof. The SAC layer 250 may be any dielectric layer that can be used as an etch stop layer during subsequent trench and via patterning for metal contacts. In some embodiments, the SAC layer 250 may be a high-k dielectric layer. SAC layer 250 may be a dielectric layer, including but not limited to SiO, HfSi, SiOC, AlO, ZrSi, AlON, ZrO, HfO, TiO, ZrAlO, ZnO, TaO, LaO, YO, TaCN, SiN, SiOCN, Si, SiOCN, ZrN, SiCN, or any combination thereof.

[0061] After filling the trench with the SAC layer 250, a planarization process, such as a CMP process, is performed to remove excess deposition of the SAC layer 250 and the metal gate pad to expose the top surface of the ILD layer 238. In some embodiments, the SAC layer 250 has a thickness T5 along the z-direction. In some embodiments, the thickness T5 can be in the range of about 3 nm and 30 nm.

[0062] In operation 124, source / drain contact components 254 are formed, such as Figures 13A to 13F As shown in the image. Figure 13A , Figure 13B , Figure 13E They are along Figure 5 A schematic cross-sectional view of semiconductor device 200 with lines AA, BB, and EE in the figure. Figure 13C , Figure 13D They are along Figure 13A A schematic cross-sectional view of the semiconductor device 200 with lines CC and DD in the figure. Figure 13F yes Figure 13A A schematic enlarged view of the semiconductor device in region 13F marked in the middle.

[0063] Contact holes can be formed through ILD layers 238 and CESL 236 to expose epitaxial source / drain components 232n and 232p, and then the contact holes are filled with a conductive material. Suitable photolithography and etching techniques are used to form the contact holes through the respective layers. After forming the contact holes, a silicide layer 252 is selectively formed over the surfaces of the epitaxial source / drain components 232n and 232p exposed by the contact holes. The silicide layer 252 can be formed by depositing a metal source layer to cover the exposed surfaces including the exposed surfaces of the epitaxial source / drain components 232n and 232p and performing a rapid thermal annealing process. In some embodiments, the metal source layer comprises a metal layer selected from W, Co, Ni, Ti, Mo, and Ta, or a metal nitride layer selected from tungsten nitride, cobalt nitride, nickel nitride, titanium nitride, molybdenum nitride, and tantalum nitride. After forming the metal source layer, a rapid thermal annealing process is performed. During the rapid annealing process, the portion of the metal source layer above the epitaxial source / drain components 232n, 232p reacts with silicon in the epitaxial source / drain components 232n, 232p to form a silicide layer 252. The unreacted portion of the metal source layer is then removed. In some embodiments, the silicide layer 252 may include one or more of WSi, CoSi, NiSi, TiSi, MoSi, and TaSi.

[0064] After forming the silicide layer 252, a conductive material is deposited to fill the contact holes and form source / drain contact components 254. Optionally, a barrier layer (not shown) may be formed in the contact holes before forming the source / drain contact components 254. In some embodiments, the conductive material layer for the gate contact may be formed by CVD, PVD, plating, ALD, or other suitable techniques. In some embodiments, the conductive material for the source / drain contact components 254 includes TiN, TaN, Ta, Ti, Hf, Zr, Ni, W, Co, Cu, Ag, Al, Zn, Ca, Au, Mg, Mo, Cr, etc. Subsequently, a CMP process is performed to remove the portion of the conductive material layer above the top surface of the ILD layer 238.

[0065] like Figure 13A and Figure 13F As shown, the spacer disposed between the gate electrode layers 244n, 244p and the source / drain components 232n, 232p includes an inner spacer 226 or an inner sidewall spacer 216. The thickness of the spacer disposed between the gate electrode layers 244n, 244p and the source / drain components 232n, 232p is either thickness T1 or thickness T2. The spacer disposed between the gate electrode layers 244n, 244p and the source / drain contact component 254 includes an inner sidewall spacer 216 and an outer sidewall spacer 234. The thickness of the spacer disposed between the gate electrode layers 244n, 244p and the source / drain contact component 254 is thickness T4, where T4 is the sum of thickness T1 and thickness T3. The thinner spacers between the gate electrode layers 244n, 244p and the source / drain components 232n, 232p provide increased volume for the source / drain components 232n, 232p, which reduces ion resistance and improves device performance. The thicker spacers between the gate electrode layers 244n, 244p and the source / drain contact component 254 reduce the capacitance between them and increase the breakdown voltage.

[0066] In operation 126, a dielectric layer 256 is deposited on the ILD layer 238, the contact vias 258 to the source / drain contact components 254, and the gate contact 260 to the gate electrode layer 244, as follows: Figures 14A to 14F As shown in the image. Figure 14A , Figure 14B , Figure 14C , Figure 14D , Figure 14E They are along Figure 5 A schematic cross-sectional view of semiconductor device 200 with lines AA, BB, CC, DD, and EE. Figure 14F This is a schematic plan view of semiconductor device 200. Figure 14F The relative positions of the gate contact 260 and the contact via 258 in the semiconductor device 200 are schematically shown. Figure 14F The lines AA, BB, CC, DD, and EE in the diagram correspond to... Figure 5 The lines AA, BB, CC, DD, and EE indicate... Figure 14A , Figure 14B , Figure 14C , Figure 14D , Figure 14E The location of the cross section shown.

[0067] ILD layer 256 may be referred to as an inter-metal dielectric (IMD) layer to provide conductive wiring to semiconductor device 200. In some embodiments, ILD layer 256 may include a low-k dielectric material, such as compounds comprising Si, O, C and / or H, such as silicon oxide, SiCOH and SiOC. Organic materials, such as polymers, may be used in ILD layer 256.

[0068] Suitable photolithography and etching techniques are used to form contact openings, such as trenches and vias, through the ILD layer 256 to expose portions of the source / drain contact 254 and the SAC layer 250. The exposed SAC layer 250 can be removed by a suitable method to expose the underlying gate electrode layer 244. After forming the contact openings, conductive material is deposited to fill the contact openings and form the source / drain contact via 258 and the gate contact 260. Optionally, a barrier layer (not shown) can be formed in the contact openings before filling the conductive material. In some embodiments, the conductive material layers for the gate contact 260 and the source / drain contact via 258 can be formed by CVD, PVD, plating, ALD, or other suitable techniques. In some embodiments, the conductive material for the source / drain contact via 258 may include TiN, TaN, Ta, Ti, Hf, Zr, Ni, W, Co, Cu, Ag, Al, Zn, Ca, Au, Mg, Mo, Cr, etc. Subsequently, a CMP process is performed to remove the portion of the conductive material layer above the top surface of the ILD layer 256, on which subsequent layers, such as the IMD layer, can be formed.

[0069] Figures 15A to 15B and Figures 16A to 16H A semiconductor device 200a according to another embodiment of the present invention is schematically illustrated. Semiconductor device 200a is similar to semiconductor device 200, except that semiconductor device 200a includes a dielectric gate structure 262 formed between different device cells. Semiconductor device 200a can be manufactured using the method 100 described above, up to operation 118, to obtain the following... Figures 10A to 10F The semiconductor structure shown. Figures 15A to 15B The semiconductor device 200a is schematically shown after operation 120, which forms the dielectric gate structure 262. Figure 15A , Figure 15B They are along Figure 5 A schematic cross-sectional view of semiconductor device 200a with lines AA and BB in the figure.

[0070] During operation 120 of forming replacement gate structure 248, the selected sacrificial gate structure 214 and the fin structures 210a, 210b located below the selected gate structure 214 are removed to form a trench between the inner sidewall spacers 216. The trench is then filled with dielectric material 264 to form dielectric gate structure 262. In some embodiments, the trench for dielectric gate structure 262 is formed at a level below the bottom surface 232b of source / drain components 232n, 232p to effectively isolate the source / drain components of adjacent cells. In some embodiments, dielectric material 264 may comprise one or more layers of dielectric material. In some embodiments, dielectric material 264 includes silicon oxide, silicon nitride, silicon oxynitride, FSG, low-k dielectric, or combinations thereof. Dielectric material 264 may be formed by HDP-CVD, FCVD, or other suitable deposition processes.

[0071] In some embodiments, the bottom surface 264b of the dielectric material 264 may be located at a distance H1 below the bottom surface 232b of the source / drain components 232n, 232p. In some embodiments, the distance H1 is in the range of about 10 nm to about 100 nm. A distance less than 10 nm is not deep enough to isolate the well regions on opposite sides of the dielectric gate structure 262. A distance greater than 100 nm increases operating costs without providing additional benefit or impact on the well resistance.

[0072] After forming the dielectric gate structure 262 and replacing the gate structure, operations 122 to 126 of method 100 can then be performed to produce, as shown in the figure. Figures 16A to 16F The semiconductor device 200a shown is illustrated. Figure 16A , Figure 16B , Figure 16C , Figure 16D , Figure 16E They are along Figure 5 A schematic cross-sectional view of semiconductor device 200a with lines AA, BB, CC, DD, and EE. Figure 16F This is a schematic layout diagram of semiconductor device 200a. Figure 16F The lines AA, BB, CC, DD, and EE in the diagram correspond to... Figure 5 The lines AA, BB, CC, DD, and EE are indicated. Figure 16A , Figure 16B , Figure 16C , Figure 16D , Figure 16E The location of the cross section shown. Figures 16G to 16H They are along Figure 16A A schematic cross-sectional view of semiconductor device 200a with lines GG and HH in the figure.

[0073] like Figure 16A , Figure 16B , Figure 16G , Figure 16H As shown, the inner spacer 226, the inner sidewall spacer 216, and the outer sidewall spacer 234 are disposed abutting against the sidewalls 264s of the dielectric material 264 of the dielectric gate structure 262. The spacers disposed between the dielectric gate structure 262 and the source / drain contact member 254 include the inner sidewall spacer 216 and the outer sidewall spacer 234. The thickness of the spacers disposed on other portions of the dielectric gate structure 262 is thickness T4, which is the sum of thicknesses T1 and T3. The thinner spacers between the dielectric gate structure 262 and the source / drain members 232n and 232p provide increased volume for the source / drain members 232n and 232p, which reduces ion resistance and improves device performance.

[0074] Figure 17 This is a flowchart of a method 100a for manufacturing a semiconductor device according to an embodiment of the present invention. Method 100a is similar to... Figure 1 Method 100 differs from method 100a in that method 100a includes operation 119 to reduce the thickness of the channel region. Operation 119 can be performed before forming the replacement gate structure. Figures 18A to 18F and Figures 19A to 19H The diagram schematically illustrates the various stages of manufacturing a semiconductor device 200b according to method 100a. The semiconductor device 200b can be manufactured using the method 100 described above, up to operation 118, to obtain... Figures 10A to 10F The semiconductor structure shown.

[0075] Figures 18A to 18F The schematic diagram shows the semiconductor device 200b after operation 119, where the thickness of the channel region is reduced. Figure 15A , Figure 15B They are along Figure 5 A schematic cross-sectional view of semiconductor device 200b with lines AA and BB in the figure.

[0076] Figure 18A , Figure 18B , Figure 18C , Figure 18D They are along Figure 5 A schematic cross-sectional view of semiconductor device 200b with lines AA, BB, CC, and DD in the diagram. Figure 18E and Figure 18F They are along Figure 18AA schematic cross-sectional view of the semiconductor device 200b with lines EE and FF. In operation 119, the sacrificial gate dielectric layer 218 and the sacrificial gate electrode layer 220 are first removed using dry etching, wet etching, or a combination thereof. Semiconductor layers 206a and 206b are exposed and subsequently removed, creating a gate cavity surrounding the nanosheets of semiconductor layers 208a and 208b.

[0077] According to embodiments of the invention, suitable etching processes, such as dry etching, wet etching, or a combination thereof, are implemented to reduce the thickness of semiconductor layers 208a and 208b. In some embodiments, plasma etching is performed using an etchant comprising tetrafluoromethane (CF4), sulfur hexafluoride (SF6), nitrogen trifluoride (NF3), chlorine (Cl2), or fluorine (F2). In some embodiments, a reactive ion etching process using CF4, SF6, and BCl2 and Cl2 is implemented. In other embodiments, a wet etching process can be used, employing potassium hydroxide (KOH), ethylenediamine catechol (EDP), tetramethylammonium hydroxide (TMAH), or similar substances.

[0078] like Figure 18A , Figure 18C and Figure 18F As shown, the exposed portions of semiconductor layers 208a and 208b in the gate region are etched along the z-direction from the original thickness CT1 to a reduced thickness CT2. By reducing the thickness of the channel region, the drain-induced barrier reduction (DIBL) or short-channel effect in the resulting device can be reduced. The difference between CT1 and CT2 can be in the range of 0.5 nm to 3 nm. A thickness difference less than 0.5 nm does not provide sufficient benefit to justify the operating cost, and a thickness difference greater than 3 nm may affect the structural integrity of the nanosheet channel without any additional benefit. In some embodiments, the ratio of thickness CT1 to thickness CT2 can be in the range of 1.1 to 2.0. A ratio less than 1.1 does not provide sufficient benefit to justify the operating cost, and a ratio greater than 2 may affect the structural integrity of the nanosheet channel without any additional benefit.

[0079] In some embodiments, due to the etching process, the semiconductor layers 208a, 208b in the gate region also have reduced dimensions along the y-direction. For example... Figure 18F As shown, after the etching process, the semiconductor layers 208a and 208b in the gate region have a width W2 that is reduced from the original width W1. In some embodiments, the difference between width W1 and width W2 is between 0.1 nm and 3 nm. In some embodiments, etching process parameters or process gases can be adjusted to perform anisotropic etching, while the widths of the semiconductor layers 208a and 208b remain substantially the same.

[0080] After reducing the thickness of semiconductor layers 208a and 208b, operations 120-126 of method 100a can then be performed to produce, as Figures 19A to 19H The semiconductor device 200b shown is illustrated. Figure 19A , Figure 19B , Figure 19C , Figure 19D , Figure 19E They are along Figure 5 A schematic cross-sectional view of semiconductor device 200b with lines AA, BB, CC, DD, and EE. Figure 19F yes Figure 19A A schematic enlarged view of a semiconductor device 200b in region 19F. Figures 19G to 19H They are along Figure 19A A schematic cross-sectional view of semiconductor device 200b with lines GG and HH in the figure.

[0081] like Figure 19A and Figure 19F As shown, the semiconductor layers 208a, 208b (i.e., nanosheet channels) between the epitaxial source / drain components 232n or 232p are dumbbell-shaped, each having two thicker end portions 208e connected by a thinner middle portion 208m. The end portions 208e of the semiconductor layers 208a / 208b are in contact with the epitaxial source / drain components 232n or 232p. The end portions 208e are also in contact with the inner sidewall spacers 216 and 226. The end portions 208e are surrounded by the inner spacers 226 and 216. In some embodiments, the length EL along the x-direction is substantially similar to the thickness T1 of the inner sidewall spacer 216 or the thickness T2 of the inner spacer 226. The middle portion 208m of the semiconductor layers 208a / 208b is wrapped by the gate dielectric layer 242n or 242p. The end portion 208e has an original thickness CT1 along the z-direction, and the middle portion 208m has a reduced thickness CT2 along the z-direction. In some embodiments, such as Figure 19H As shown, the end portion 208e has an original thickness W1 along the y-direction, and the middle portion 208m has a reduced thickness W2 along the y-direction. The reduced thickness in the middle portion reduces the device DIBL and improves the wobbling effect. The reduced thickness in the middle portion 208m also provides increased spacing between the nanosheet channels used to form the gate dielectric layer 242 and the gate electrode layer 244, thereby improving film quality and resulting in improved device performance. By thinning the semiconductor nanosheet before forming the replacement gate structure, embodiments of the present invention improve device wobbling performance and reduce the DIBL effect without sacrificing channel resistance and epitaxial growth margin.

[0082] In some embodiments, such as Figure 19A and Figure 19FAs shown, semiconductor device 200b also has two thickness levels of spacers, similar to semiconductor devices 200 and 200a. In other embodiments, the outer wall spacer 234 may be omitted.

[0083] The various embodiments or examples described herein offer several advantages over the prior art. For example, by forming inner sidewall spacers before forming the epitaxial source / drain components and outer sidewall spacers after forming the epitaxial source / drain components, embodiments of the present invention increase the volume of the epitaxial source / drain components, thereby improving ion performance. Thicker sidewall spacers also reduce the capacitance between the source / drain contacts and the gate electrode. By thinning the semiconductor nanosheet before forming the replacement gate structure, embodiments of the present invention improve device wobbling performance, reduce the DIBL effect without sacrificing channel resistance and epitaxial growth margin.

[0084] Some embodiments of the present invention provide a semiconductor device comprising: an epitaxial source / drain component having a first side, a second side opposite to the first side, and a planar surface connecting the first side and the second side; two or more semiconductor layers in contact with the first side of the epitaxial source / drain component; a gate structure enclosing the two or more semiconductor layers; an inner spacer disposed between the two or more semiconductor layers, wherein the inner spacer is in contact with the first side of the epitaxial source / drain component and the gate structure, and the inner spacer has a first thickness; and a sidewall spacer in contact with the gate structure, the first side of the epitaxial source / drain component, and the planar surface, wherein a portion of the sidewall spacer has a second thickness, and the ratio of the second thickness to the first thickness is in the range of 1.1 and 2.0.

[0085] In some embodiments, the sidewall spacer includes: an inner sidewall spacer contacting the first side of the gate structure and the epitaxial source / drain component; and an outer sidewall spacer contacting the planar surface of the inner sidewall spacer and the epitaxial source / drain component. In some embodiments, the inner sidewall spacer has the first thickness. In some embodiments, the semiconductor device further includes: a source / drain contact component connected to the epitaxial source / drain component, wherein the inner sidewall spacer and the outer sidewall spacer are disposed between the source / drain contact component and the gate structure. In some embodiments, the semiconductor device further includes: a second gate structure disposed on the second side of the epitaxial source / drain component; and a second sidewall spacer contacting the second gate structure, the second side of the epitaxial source / drain component, and the planar surface. In some embodiments, each of the two or more semiconductor layers includes an end portion contacting the epitaxial source / drain component and an intermediate portion extending from the end portion, the end portion having a first channel thickness, and the intermediate portion having a second channel thickness less than the first channel thickness. In some embodiments, the end portion has a length substantially equal to the first thickness.

[0086] Some embodiments of the present invention provide a semiconductor device comprising: two or more semiconductor layers, wherein each of the two or more semiconductor layers includes a first end portion, a second end portion, and an intermediate portion connecting the first end portion and the second end portion, the first end portion and the second end portion having a first channel thickness, and the intermediate portion having a second channel thickness less than the first channel thickness; a gate structure enclosing the intermediate portion of the two or more semiconductor layers; a first source / drain component having a first side and a first planar surface connected to the first side, wherein the first side contacts the first end portion of the two or more semiconductor layers; a second source / drain component having a second side and a second planar surface connected to the second side, wherein the second side contacts the second end portion of the two or more semiconductor layers; an inner spacer disposed between the two or more semiconductor layers; a first sidewall spacer disposed on the gate structure; and a second sidewall spacer disposed on the gate structure.

[0087] In some embodiments, the first end portion is surrounded by the inner spacer and the first sidewall spacer. In some embodiments, the first sidewall spacer contacts the first side and the first planar surface of the first source / drain component, and the second sidewall spacer contacts the second side and the second planar surface of the second source / drain component. In some embodiments, the inner spacer has a first thickness, and the first sidewall spacer and the second sidewall spacer have a second thickness greater than the first thickness. In some embodiments, each of the first sidewall spacer and the second sidewall spacer includes: an inner sidewall spacer that contacts the side of the gate structure and the corresponding source / drain component; and an outer sidewall spacer that contacts the planar surface of the inner sidewall spacer and the corresponding source / drain component. In some embodiments, the inner sidewall spacer has the first thickness. In some embodiments, the semiconductor device further includes a source / drain contact component connected to the first source / drain component, and the inner sidewall spacer and the outer sidewall spacer are disposed between the source / drain contact component and the gate structure.

[0088] Some embodiments of the present invention provide a method comprising: forming a fin structure, the fin structure including two or more first semiconductor layers into which two or more second semiconductor layers are inserted; forming a sacrificial gate structure over the fin structure; forming an inner sidewall spacer over the sidewall of the sacrificial gate structure, wherein the inner sidewall spacer has a side facing away from the sacrificial gate structure; etching back the fin structure along the sidewall of the inner sidewall spacer; forming the inner spacer by partially removing two or more second semiconductor layers and filling them with a dielectric material; epitaxially growing source / drain components from the two or more first semiconductor layers, wherein the source / drain components have side and planar surfaces, and the side of the source / drain components partially contacts the sidewall of the inner spacer and the sidewall of the inner sidewall spacer; forming an outer sidewall spacer over the sidewall of the inner sidewall spacer, wherein the outer sidewall spacer contacts the planar surface of the source / drain component; depositing a contact etch stop layer (CESL) over the outer sidewall spacer and the source / drain component; and depositing an interlayer dielectric (ILD) layer over the CESL.

[0089] In some embodiments, the method further includes: removing the sacrificial gate structure to expose the fin structure; removing the two or more second semiconductor layers from the fin structure to expose the two or more first semiconductor layers between the inner spacers, since the inner spacers have a thickness less than the combined thickness of the inner sidewall spacers and the outer sidewall spacers, and the extended length of the two or more first semiconductor layers is exposed to improve the gate length; depositing a gate dielectric layer over the two or more first semiconductor layers; and depositing a gate electrode layer over the gate dielectric layer. In some embodiments, the method further includes: reducing the thickness of the two or more first semiconductor layers before depositing the gate dielectric layer to improve device wobbling performance and reduce drain-induced barrier reduction effects, wherein each of the two or more first semiconductor layers includes an end portion having a first thickness and an intermediate portion having a second thickness, the end portion contacting the inner spacer, and the intermediate portion contacting the gate dielectric layer. In some embodiments, the method further includes: etching back the gate electrode layer, the inner sidewall spacers, and the outer sidewall spacers; and depositing a self-aligned dielectric layer over the gate electrode layer, the inner sidewall spacers, and the outer sidewall spacers. In some embodiments, the method further includes forming a source / drain contact in the interlayer dielectric layer, wherein the inner sidewall spacer and the outer sidewall spacer are disposed between the source / drain contact and the gate electrode layer, wherein a reduced capacitance exists between the source / drain contact and the gate electrode layer. In some embodiments, forming the inner sidewall spacer includes forming the inner sidewall spacer with a reduced thickness to increase the volume of the subsequently formed source / drain component.

[0090] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand aspects of the invention. Those skilled in the art should understand that they can readily use this invention as a basis to design or modify other processes and structures for performing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the invention, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of the invention.

Claims

1. A semiconductor device, comprising: An epitaxial source / drain component has a first side, a second side opposite to the first side, and a small planar surface connecting the first side and the second side; Two or more semiconductor layers are in contact with the first side of the epitaxial source / drain component; A gate structure that encloses the two or more semiconductor layers; An inner spacer is disposed between the two or more semiconductor layers, wherein the inner spacer contacts the first side of the epitaxial source / drain component and the gate structure, and the inner spacer has a first thickness; and A sidewall spacer contacts the gate structure, the first side of the epitaxial source / drain component, and the planar surface, wherein a portion of the sidewall spacer has a second thickness, and the ratio of the second thickness to the first thickness is in the range of 1.1 to 2.

0. The inner sidewall spacer contacts the first side of the gate structure and the epitaxial source / drain component; and the outer sidewall spacer contacts the inner sidewall spacer, with the bottom surface of the outer sidewall spacer contacting the planar surface of the epitaxial source / drain component. The inner sidewall spacer is perpendicularly aligned with the inner spacer, and the outer sidewall spacer is located outside the lateral range of the inner spacer.

2. The semiconductor device according to claim 1, wherein, The inner spacer has a higher dielectric constant than the inner sidewall spacer.

3. The semiconductor device according to claim 1, wherein, The inner sidewall spacer has the first thickness.

4. The semiconductor device according to claim 1, further comprising: A source / drain contact component is connected to the epitaxial source / drain component, wherein the inner sidewall spacer and the outer sidewall spacer are disposed between the source / drain contact component and the gate structure.

5. The semiconductor device according to claim 1, further comprising: A second gate structure is disposed on the second side of the epitaxial source / drain component; as well as The second sidewall spacer is in contact with the second gate structure, the second side of the epitaxial source / drain component, and the small planar surface.

6. The semiconductor device according to claim 1, wherein, Each of the two or more semiconductor layers includes an end portion in contact with the epitaxial source / drain component and an intermediate portion extending from the end portion, the end portion having a first channel thickness and the intermediate portion having a second channel thickness less than the first channel thickness.

7. The semiconductor device according to claim 6, wherein, The end portion has a length substantially equal to the first thickness.

8. A semiconductor device, comprising: Two or more semiconductor layers, wherein each of the two or more semiconductor layers includes a first end portion, a second end portion, and an intermediate portion connecting the first end portion and the second end portion, the first end portion having a first channel thickness, the intermediate portion having a second channel thickness, the second end portion having a third channel thickness, and the second channel thickness being less than the first channel thickness and the third channel thickness; A gate structure that encloses the middle portion of the two or more semiconductor layers; A first source / drain component has a first side and a first planar surface connected to the first side, wherein the first side contacts the first end portion of the two or more semiconductor layers; The second source / drain component has a second side and a second small planar surface connected to the second side, wherein the second side contacts the second end portion of the two or more semiconductor layers; An inner spacer is disposed between the two or more semiconductor layers; A first sidewall spacer is disposed on the gate structure; and A second sidewall spacer is disposed on the gate structure. Each of the first sidewall spacer and the second sidewall spacer includes: The inner sidewall spacer contacts the gate structure and the first side of the first source / drain component and the second side of the second source / drain component; and An outer wall spacer contacts the inner wall spacer, and the bottom surface of the outer wall spacer contacts the first small plane surface of the first source / drain component and the second small plane surface of the second source / drain component. The inner wall spacer is perpendicularly aligned with the inner spacer, and the outer wall spacer is disposed outside the lateral range of the inner spacer.

9. The semiconductor device according to claim 8, wherein, The first end portion is surrounded by the inner spacer and the first sidewall spacer.

10. The semiconductor device according to claim 9, wherein, The first sidewall spacer contacts the first side and the first small plane surface of the first source / drain component, and the second sidewall spacer contacts the second side and the second small plane surface of the second source / drain component.

11. The semiconductor device according to claim 10, wherein, The inner spacer has a first thickness, and the first sidewall spacer and the second sidewall spacer have a second thickness greater than the first thickness.

12. The semiconductor device according to claim 11, wherein, The inner spacer has a higher dielectric constant than the inner sidewall spacer.

13. The semiconductor device according to claim 11, wherein, The inner sidewall spacer has the first thickness.

14. The semiconductor device of claim 11, further comprising a source / drain contact member connected to the first source / drain member, wherein the inner sidewall spacer and the outer sidewall spacer are disposed between the source / drain contact member and the gate structure.

15. A method for forming a semiconductor device, comprising: A fin structure is formed, the fin structure comprising two or more first semiconductor layers stacked alternately with two or more second semiconductor layers; A sacrificial gate structure is formed above the fin structure; An inner sidewall spacer is formed above the sidewall of the sacrificial gate structure, wherein the inner sidewall spacer has a side facing away from the sacrificial gate structure, and wherein the inner sidewall spacer has a reduced thickness; The fin structure is etched back along the side of the inner wall spacer; The inner spacer is formed by partially removing two or more second semiconductor layers and filling them with dielectric material; Source / drain components are epitaxially grown from the two or more first semiconductor layers, wherein the source / drain components have sides and planar surfaces, and the sides of the source / drain components are in partial contact with the side surfaces of the inner spacer and the inner sidewall spacer, and the reduced thickness of the inner sidewall spacer increases the volume of the source / drain components; An outer wall spacer is formed above the side surface of the inner wall spacer, wherein the bottom surface of the outer wall spacer contacts the planar surface of the source / drain component; A contact etch stop layer is deposited over the outer wall spacer and the source / drain components; and An interlayer dielectric layer is deposited above the contact etch stop layer. The inner sidewall spacer is perpendicularly aligned with the inner spacer, and the outer sidewall spacer is located outside the lateral range of the inner spacer.

16. The method of claim 15, further comprising: Remove the sacrificial gate structure to expose the fin structure; The two or more second semiconductor layers are removed from the fin structure to expose the two or more first semiconductor layers between the inner spacers, because the inner spacers have a thickness less than the combined thickness of the inner sidewall spacers and the outer sidewall spacers, and the extended length of the two or more first semiconductor layers is exposed to improve the gate length; A gate dielectric layer is deposited over the two or more first semiconductor layers; as well as A gate electrode layer is deposited above the gate dielectric layer.

17. The method of claim 16, further comprising: Before depositing the gate dielectric layer, the thickness of the two or more first semiconductor layers is reduced to improve device swing performance and reduce drain-induced barrier reduction effect, wherein each of the two or more first semiconductor layers includes an end portion having a first thickness and an intermediate portion having a second thickness, the end portion contacting the inner spacer and the intermediate portion contacting the gate dielectric layer.

18. The method of claim 16, further comprising: Etching back the gate electrode layer, the inner sidewall spacer, and the outer sidewall spacer; as well as A self-aligned dielectric layer is deposited over the gate electrode layer, the inner sidewall spacer, and the outer sidewall spacer.

19. The method of claim 18, further comprising: Source / drain contact components are formed in the interlayer dielectric layer, wherein the inner sidewall spacer and the outer sidewall spacer are disposed between the source / drain contact components and the gate electrode layer, wherein the source / drain contact components and the gate electrode layer have a reduced capacitance.

20. The method of claim 15, wherein, Forming the inner sidewall spacer includes forming the inner sidewall spacer with a reduced thickness to increase the volume of the source / drain components.

Images