Semiconductor element and method for manufacturing the same

Abstract

A semiconductor device and a method for fabricating the same are disclosed. The method for fabricating the semiconductor device includes forming a fin structure on a substrate, forming a shallow trench isolation around the fin structure, forming a gate layer on the fin structure and the shallow trench isolation, removing portions of the gate layer, the fin structure and the shallow trench isolation to form an opening, and forming a dielectric layer in the opening to form a single diffusion isolation structure.

Description

[0001] This application is a divisional application of Chinese invention patent application (application number: 201710516576.7, application date: June 29, 2017, invention title: semiconductor element and method of manufacturing thereof). Technical Field

[0002] This invention relates to a method for fabricating semiconductor devices, and more particularly to a method for using a partitioned fin structure to form a single diffusion break (SDB) structure. Background Technology

[0003] In recent years, with the continuous shrinking of field-effect transistor (FET) device dimensions, the development of existing planar FET devices has reached the limits of fabrication technology. To overcome these limitations, replacing planar FET devices with non-planar FET devices, such as fin field-effect transistors (Fin FETs), has become the mainstream development trend. Because the three-dimensional structure of Fin FETs increases the contact area between the gate and the fin structure, it further enhances the gate's control over the carrier channel region, thereby reducing the drain-induced barrier lowering (DIBL) effect faced by small-sized devices and suppressing the short-channel effect (SCE). Furthermore, since Fin FETs have a wider channel width for the same gate length, they can achieve double the drain drive current. Moreover, the threshold voltage of the transistor device can be controlled by adjusting the work function of the gate.

[0004] In current fin field-effect transistor (FET) fabrication processes, after forming shallow trench isolation around the fin structure, a portion of the fin structure and the shallow trench isolation is typically etched away to form a groove. An insulating material is then filled in to form a single-diffused isolation structure, separating the fin structure into two parts. However, current fabrication processes for single-diffused isolation structures and metal gates still present many challenges in their compatibility. Therefore, improving existing fin field-effect transistor fabrication processes and architectures is a crucial current research topic. Summary of the Invention

[0005] To address the aforementioned problems, one embodiment of the present invention discloses a method for fabricating a semiconductor device. First, a fin-like structure is formed on a substrate. Then, a shallow trench is formed around the fin-like structure. A gate layer is formed on the fin-like structure and the shallow trench. A portion of the gate layer, a portion of the fin-like structure, and a portion of the shallow trench are removed to form an opening. Finally, a dielectric layer is formed within the opening to form a single-diffusion isolation structure.

[0006] Another embodiment of the present invention discloses a semiconductor device, which mainly includes a fin structure disposed on a substrate, a single-diffusion isolation structure disposed within the fin structure and dividing the fin structure into a first part and a second part, a gate structure disposed on the first part, and a contact hole etch stop layer disposed next to the gate structure and extending to the single-diffusion isolation structure. Attached Figure Description

[0007] Figures 1 to 10 This is a schematic diagram of a method for fabricating a semiconductor device according to an embodiment of the present invention.

[0008] Explanation of main component symbols

[0009] 12 Basement 14 Fin-like structure

[0010] 16 Shallow trench isolation 18 Gate dielectric layer

[0011] 20 Gate layer 22 Patterned mask

[0012] 24 Opening 26 Opening

[0013] 28 Part One 30 Part Two

[0014] 32 Dielectric layer 34 Single-diffusion isolation structure

[0015] 36 First Hard Mask 38 Second Hard Mask

[0016] 40 Patterned mask 42 Gate structure

[0017] 44 Covering layer 46 First gap wall

[0018] 48 Second spacer wall 50 Source / drain region

[0019] 52 Contact hole etch stop layer 54 Interlayer dielectric layer

[0020] 56 Groove 58 Dielectric layer

[0021] 60 High dielectric constant dielectric layer; 62 Work function metal layer

[0022] 64 Low-impedance metal layer 66 Metal gate

[0023] 68 Hard mask 70 Contact plug Detailed Implementation

[0024] Please refer to Figures 1 to 2 ,in Figure 1 A top view of a semiconductor device according to an embodiment of the present invention. Figure 2 The left half is Figure 1 A schematic diagram of a cross-section along the tangent AA'. Figure 2 The right half is Figure 1 A schematic cross-sectional view along the tangent BB'. (See diagram below.) Figures 1 to 2 As shown, a substrate 12 is first provided, such as a silicon substrate or a silicon-on-insulator (SOI) substrate. Then, a plurality of fin structures 14 are formed on the substrate 12. In this embodiment, four fin structures 14 are provided on the substrate 12, but the number of fin structures can be adjusted arbitrarily according to product requirements and is not limited to this.

[0025] According to a preferred embodiment of the present invention, the fin structure 14 is preferably fabricated using techniques such as sidewall image transfer (SIT). The process generally includes: providing a layout pattern to a computer system and performing appropriate calculations to define the corresponding pattern in a photomask. Subsequently, multiple equidistant and equally wide patterned sacrificial layers are formed on the substrate using photolithography and etching processes, giving each layer a strip-like appearance. Then, deposition and etching processes are sequentially performed to form spacers on the sidewalls of the patterned sacrificial layers. The patterned sacrificial layers are then removed, and etching is performed under the cover of the spacers, transferring the pattern formed by the spacers into the substrate. Finally, a fin cut process is performed to obtain the desired patterned structure, such as a strip-shaped patterned fin structure.

[0026] In addition, the formation of the fin structure 14 may also include first forming a patterned mask (not shown) on the substrate 12, and then transferring the pattern of the patterned mask to the substrate 12 through an etching process to form the fin structure 14. Alternatively, the fin structure 14 may be formed by first forming a patterned hard mask layer (not shown) on the substrate 12, and then using an epitaxial fabrication process to grow a semiconductor layer, such as silicon-germanium, on the substrate 12 that exposes the patterned hard mask layer. This semiconductor layer can then serve as the corresponding fin structure 14. These embodiments of forming the fin structure 14 are all within the scope of this invention.

[0027] Then, a shallow trench isolation (STI) 16 is formed around the fin structure 14. In this embodiment, the shallow trench isolation 16 is formed by first using a flowable chemical vapor deposition (FCVD) process to form a silicon monoxide layer on the substrate 12 that completely covers the fin structure 14. Next, a chemical mechanical polishing (CMP) process combined with an etching process is used to remove part of the silicon oxide layer, leaving the remaining silicon oxide layer below the surface of the fin structure 14 to form the shallow trench isolation 16.

[0028] Next, a gate dielectric layer 18 and a gate layer 20 are sequentially formed and completely cover the fin structure 14 and the shallow trench isolation 16. Then, a patterned mask 22 is formed on the gate layer 20, wherein the patterned mask 22 has an opening 24 that exposes a portion of the surface of the gate layer 20. In this embodiment, the gate dielectric layer 18 preferably comprises silicon oxide, and the gate layer 20 may be selected from the group consisting of amorphous silicon and polycrystalline silicon. In addition, the patterned mask 22 may comprise an organic dielectric layer (ODL), a silicon-containing hard mask and an anti-reflective coating (SHB) layer, and a patterned photoresist. The step of forming the opening 24 in the patterned mask 22 can be achieved by using the patterned photoresist to remove part of the silicon-containing hard mask, the anti-reflective layer, and part of the organic dielectric layer.

[0029] like Figure 3 As shown, an etching process is then performed using a patterned mask 22 as a mask to sequentially remove part of the gate layer 20, part of the gate dielectric layer 18, and part of the fin structure 14 to form an opening 26, while simultaneously dividing the fin structure 14 into two parts, including a first part 28 located on the left side of the opening 26 and a second part 30 located on the right side of the opening 26.

[0030] Subsequently, as Figure 4 As shown, a flat dielectric layer 32 is formed within the opening 26 and on the gate layer 20, wherein the dielectric layer 32 preferably fills the opening 26 and the upper surface of the dielectric layer 32 is preferably higher than the upper surface of the gate layer 20. In this embodiment, the dielectric layer 32 and the shallow trench isolation 16 preferably contain different materials. For example, the dielectric layer 32 filling the opening 26 preferably contains silicon nitride while the shallow trench isolation 16 contains silicon oxide. However, this is not a limitation. According to one embodiment of the present invention, the dielectric layer 32 and the shallow trench isolation 16 may also use the same material, such as silicon oxide. This embodiment is also within the scope of the present invention.

[0031] Please refer to the following: Figure 5 and Figure 6 , Figure 5 To continue Figure 4 Create a top view of a semiconductor device. Figure 6 The left half is Figure 5 A schematic cross-sectional view along the tangent CC'. Figure 6 The right half is Figure 5 A schematic cross-sectional view along the tangent DD'. (See diagram below.) Figures 5 to 6 As shown, a planarization process is then performed, for example, by using a chemical mechanical polishing process to remove part of the dielectric layer 32 and making the upper surface of the remaining dielectric layer 32 approximately flush with the upper surface of the gate layer 20, thereby forming a single-diffusion isolation structure 34 protruding from the fin structure 14 and approximately flush with the upper surface of the gate layer 20. Figure 5 As shown in the top view, each fin structure 14 preferably extends along a first direction (e.g., the X direction), while the monodiffusion isolation structure 34 preferably extends along a second direction (e.g., the Y direction) across the fin structure and simultaneously divides each fin structure into two parts, such as a first part 28 on the left side and a second part 30 on the right side of the monodiffusion isolation structure 34.

[0032] like Figure 7 As shown, a pattern transfer fabrication process is then performed on the gate layer 20. For example, a first hard mask 36, a second hard mask 38, and a patterned mask 40 are sequentially formed on the gate layer, and the patterned mask 40 preferably does not cover the single diffusion isolation structure 34. In this embodiment, the first hard mask 36 and the second hard mask 38 preferably contain different materials. For example, the first hard mask 36 preferably contains silicon nitride, and the second hard mask 38 preferably contains silicon oxide, but it is not limited to this. The patterned mask 40 may contain a single patterned photoresist, or it may contain a combination of... Figure 2 The patterned mask 22 formed contains the same material, and may include a three-layer structure such as an organic dielectric layer (ODL), a silicon-containing hard mask bottom anti-reflective coating (SHB) layer, and a patterned photoresist. These embodiments are all within the scope of this invention.

[0033] like Figure 8As shown, a patterned mask 40 is then used as a mask for one or more etching processes to sequentially remove a portion of the second hard mask 38, a portion of the first hard mask 36, a portion of the gate layer 20, and a portion of the gate dielectric layer 18, thereby forming a gate structure 42 next to the single-diffusion isolation structure 34. It is worth noting that no gate structure is formed above the single-diffusion isolation structure 34 during the formation of the gate structure 42, but a dummy gate (not shown) can be provided at the edge of the fin structure 14, spanning both the fin structure 14 and the shallow trench isolation 16. The upper surface of the dummy gate can be flush with the upper surface of the gate structure 42, and in terms of height, the upper surface of the shallow trench isolation 16 is preferably slightly lower than the surface of the fin structure 14, while the upper surface of the single-diffusion isolation structure 34 is simultaneously higher than both the upper surfaces of the fin structure 14 and the shallow trench isolation 16. Furthermore, the single-diffusion isolation structure 34, protruding from the fin structure 14, will be slightly lower than the upper surface of the gate layer 20 due to this etching process, but will still protrude from the fin structure 14. A masking layer 44 can then be formed on the fin structure 14 and cover the gate structure 42 and the single-diffusion isolation structure 34. In this embodiment, the masking layer 44 may comprise silicon nitride, silicon oxide, silicon oxynitride, silicon carbide nitride, or a combination thereof, but is not limited thereto.

[0034] Then as Figure 9 As shown, an etching process is performed to remove part of the masking layer 44 to form a first spacer wall 46 on the sidewall of the gate structure 42 and simultaneously form a second spacer wall 48 on the sidewall of the single-diffusion isolation structure 34. Then, source / drain regions 50 and / or epitaxial layers (not shown) are formed in the fin structures 14 and / or substrate 12 on both sides of the first spacer wall 46 and the second spacer wall 48, and a metal silicide (not shown) is selectively formed on the surface of the source / drain regions 50 and / or epitaxial layers. In this embodiment, although the first spacer wall 46 and the second spacer wall 48 are each exemplified as a single spacer wall, they can also be composite spacers, for example, they may include a bias spacer wall and a main spacer wall. The bias spacer wall and the main spacer wall may contain the same or different materials, and both can be selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, and silicon carbide nitride. The source / drain region 50 may contain different dopants depending on the conductivity type of the transistor being disposed, such as P-type dopants or N-type dopants.

[0035] Subsequently, a contact hole etch stop layer 52 is formed on the surface of the fin structure 14 and covers the gate structure 42 and the single-diffusion isolation structure 34. Then, an interlayer dielectric layer 54 is formed on the contact hole etch stop layer 52. Then, a planarization process is performed, for example, by chemical mechanical polishing to remove part of the interlayer dielectric layer 54 and part of the contact hole etch stop layer 52 and expose the gate layer 20 made of polysilicon material, so that the upper surface of the gate layer 20 is flush with the upper surface of the interlayer dielectric layer 52.

[0036] Subsequently, a metal gate replacement fabrication process is performed to convert the gate structure 42 into a metal gate. For example, a selective dry etching or wet etching process can be performed first, such as using an etching solution such as ammonia (NH4OH) or tetramethylammonium hydroxide (TMAH) to remove the second hard mask 38, the first hard mask 36, the gate layer 20, and even the gate dielectric layer 18 in the gate structure 42, so as to form a groove 56 in the interlayer dielectric layer 54.

[0037] like Figure 10 As shown, a selective dielectric layer 58 or gate dielectric layer, a high dielectric constant dielectric layer 60, a work function metal layer 62, and a low impedance metal layer 64 are sequentially formed within the groove. Then, a planarization process is performed, for example, by using CMP to remove a portion of the low impedance metal layer 64, a portion of the work function metal layer 62, and a portion of the high dielectric constant dielectric layer 60 to form a metal gate 66. Subsequently, a portion of the low impedance metal layer 64, a portion of the work function metal layer 64, and a portion of the high dielectric constant dielectric layer 60 can be removed to form a groove (not shown). A hard mask 68, for example made of silicon nitride, is then filled into the groove, and the upper surface of the hard mask 68 is aligned with the upper surface of the interlayer dielectric layer 54. Taking the gate structure fabricated using the high dielectric constant dielectric layer fabrication process in this embodiment as an example, the formed metal gate 66 preferably includes a dielectric layer 58 or gate dielectric layer, a U-shaped high dielectric constant dielectric layer 60, a U-shaped work function metal layer 62, and a low impedance metal layer 64.

[0038] In this embodiment, the high dielectric constant dielectric layer 60 comprises a dielectric material with a dielectric constant greater than 4, such as hafnium oxide (HfO2), hafnium silicon oxide (HfSiO4), hafnium silicon oxynitride (HfSiON), aluminum oxide (Al2O3), lanthanum oxide (La2O3), tantalum oxide (Ta2O5), yttrium oxide (Y2O3), zirconium oxide (ZrO2), strontium titanate oxide (SrTiO3), zirconium silicon oxide (ZrSiO4), hafnium zirconium oxide (HfZrO4), and strontium bismuth tantalum oxide. lead zirconate titanate (SrBi₂Ta₂O₉, SBT) and lead zirconate titanate (PbZr) x Ti 1-x O3, PZT), barium strontium titanate (Ba x Sr 1- x The group consisting of TiO3, BST, or combinations thereof.

[0039] The work function metal layer 62 is preferably used to adjust the work function of the metal gate to make it suitable for N-type transistors (NMOS) or P-type transistors (PMOS). If the transistor is an N-type transistor, the work function metal layer 62 can be made of a metal material with a work function of 3.9 electron volts (eV) to 4.3 eV, such as titanium aluminide (TiAl), zirconium aluminide (ZrAl), tungsten aluminide (WAl), tantalum aluminide (TaAl), hafnium aluminide (HfAl), or titanium aluminum carbide (TiAlC), but is not limited thereto. If the transistor is a P-type transistor, the work function metal layer 62 can be made of a metal material with a work function of 4.8 eV to 5.2 eV, such as titanium nitride (TiN), tantalum nitride (TaN), or tantalum carbide (TaC), but is not limited thereto. Another barrier layer (not shown) may be included between the work function metal layer 62 and the low impedance metal layer 64. The material of the barrier layer may include titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), etc. The low impedance metal layer 64 may be selected from low resistance materials such as copper (Cu), aluminum (Al), tungsten (W), titanium-aluminum alloy (TiAl), cobalt-tungsten phosphide (CoWP), or combinations thereof.

[0040] A pattern transfer fabrication process can then be performed. For example, a patterned mask can be used to remove the interlayer dielectric layer 54 between the metal gate 66 and the single-diffusion isolation structure 34 to form multiple contact holes (not shown) and expose the underlying source / drain regions 50. Then, the desired metal material is filled into each contact hole, such as a barrier layer material including titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), etc., and a low-resistance metal layer selected from low-resistance materials or combinations thereof, such as tungsten (W), copper (Cu), aluminum (Al), titanium-aluminum alloy (TiAl), cobalt tungsten phosphide (CoWP), etc. A planarization fabrication process is then performed, for example, by chemical mechanical polishing to remove some of the metal material to form contact plugs 70 in each contact hole to electrically connect the source / drain regions 50. This completes the fabrication of the semiconductor device according to the preferred embodiment of the present invention.

[0041] Please continue to refer to Figure 10 , Figure 10 A schematic diagram of the structure of a semiconductor device according to an embodiment of the present invention is also disclosed. For example... Figure 10As shown, the semiconductor device mainly includes a fin structure 14 disposed on a substrate 12, a single-diffusion isolation structure 34 disposed within and protruding from the fin structure 14, dividing the fin structure 14 into a first portion 28 and a second portion 30, and a gate structure or metal gate 66 disposed on the first portion 28, wherein the upper surface of the metal gate 66 may be flush with or slightly higher than the upper surface of the single-diffusion isolation structure 34. In this embodiment, the fin structure 14 extends along a first direction while the single-diffusion isolation structure 34 extends along a second direction, and the first direction is preferably perpendicular to the second direction, for example... Figure 5 The top view is shown.

[0042] In addition, the semiconductor device includes a first spacer 46 disposed on the sidewall of the metal gate 66, a second spacer 48 disposed on the sidewall of the single diffusion isolation structure 34, a contact hole etch stop layer 52 disposed beside the first spacer 46 and extending to the second spacer 48 and the single diffusion isolation structure 34 and directly contacting the single diffusion isolation structure 34, and source / drain regions 50 respectively disposed in the fin structure 14 or substrate 12 on both sides of the first spacer 46 and in the fin structure 14 on both sides of the second spacer 48.

[0043] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention should be included within the scope of the present invention.

Claims

1. A method for manufacturing a semiconductor device, comprising: Multiple fin-like structures are formed on a base, each fin-like structure extending in a first direction; A shallow groove isolation membrane is formed between the fin-like structures, wherein the upper surface of the shallow groove isolation membrane is lower than the upper surface of the fin-like structures; A silicon layer is formed to completely cover the fin-like structure and the shallow trench isolation membrane; The patterned and etched portion of the silicon layer, the portion of at least one fin structure, and the portion of the shallow trench are isolated to form an opening that extends in a second direction intersecting the first direction and that the opening divides the at least one fin structure into two parts. as well as A dielectric layer is formed to completely fill the opening to create a single-diffusion isolation structure. The silicon layer is either amorphous silicon or polycrystalline silicon.

2. The method of claim 1, further comprising: planarizing the dielectric layer to have an upper surface coplanar with the silicon layer.

3. The method of claim 1, further comprising forming a gate dielectric layer on the fin structure prior to forming the silicon layer.

4. The method of claim 1, wherein the second direction is orthogonal to the first direction.

5. The method of claim 1, wherein the opening has substantially the same depth in the fin structure and the shallow trench isolation membrane.

6. The method of claim 1, wherein the opening intersects with at least two fin-like structures.

7. The method of claim 1, further comprising: patterning and etching portions of the silicon layer to form a gate pattern.

8. The method of claim 7, wherein the steps of patterning and etching a portion of the silicon layer, a portion of the at least one fin structure, and a portion of the shallow trench isolation to form the opening and the step of patterning and etching a portion of the silicon layer to form the gate pattern are different steps.

9. The method of claim 8, wherein the step of patterning and etching a portion of the silicon layer to form the gate pattern is performed after the steps of patterning and etching a portion of the silicon layer, a portion of the at least one fin structure, and a portion of the shallow trench isolation to form the opening.

10. The method of claim 7, further comprising: forming dielectric spacer walls on the sidewalls of the gate pattern and the single-diffusion isolation structure.

11. The method of claim 10, further comprising: An interlayer dielectric layer is formed on the gate pattern; Planarize the interlayer dielectric layer to have a surface coplanar with the gate pattern; Remove the gate pattern to form a gate recess.

12. The method of claim 11, further comprising: forming a high dielectric constant dielectric layer and a metal gate layer in the gate recess.

13. The method of claim 12, wherein the metal gate layer comprises a work function metal layer and a low resistance metal layer.

14. The method of claim 13, further comprising: Remove the high dielectric constant dielectric layer and the metal gate layer from the top of the gate recess; A hard mask dielectric layer is formed on the remaining high dielectric constant dielectric layer and the metal gate layer, and the hard mask dielectric layer has an upper surface that is coplanar with the interlayer dielectric layer.

15. The method of claim 1, wherein the dielectric layer comprises a material different from the shallow trench isolation membrane.

Images