LED epitaxial structure and preparation method thereof

Abstract

This invention proposes an LED epitaxial structure and its fabrication method. The LED epitaxial structure includes a substrate and a buffer layer, a transition layer, an n-type semiconductor layer, an active layer, and a p-type semiconductor layer sequentially stacked on the substrate, wherein: the n-type semiconductor layer includes a predetermined number of n-type doped GaN layers / Er a Al b Ga 1‑a‑b In an N-layer superlattice structure, the Er and Al component concentrations in each superlattice gradually increase away from the transition layer. The LED epitaxial structure proposed according to this invention can increase the barrier height, restrict longitudinal electron movement, reduce electron overflow in the quantum well, improve the electron-hole distribution in the active layer, and thus improve the luminous efficiency of electron-hole recombination in the active layer.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to an LED epitaxial structure and its preparation method. Background Technology

[0002] Light emitting diodes (LEDs) are electroluminescent devices with advantages such as energy saving, environmental protection, safety, long lifespan, low power consumption, high brightness, waterproofing, miniaturization, concentrated beam, and easy maintenance. They are widely used in traffic lights, street lights, and large-area displays.

[0003] In particular, blue light-emitting diodes made of nitride materials are the foundation of current white solid-state lighting development and a hot research topic. Existing GaN-based LED epitaxial structures include a substrate, and a buffer layer, an undoped GaN layer, an n-type GaN layer, an active layer, and a p-type GaN layer sequentially stacked on the substrate. The n-type and p-type GaN layers provide electrons and holes to the active layer, respectively, and these electrons and holes recombine in the active layer to generate photons.

[0004] However, because the carrier (electron) migration rate and concentration of the n-type GaN layer in current GaN-based LEDs are generally more than 10 times that of the p-type GaN layer, when the n-type GaN layer and the p-type GaN layer provide electrons and holes to the active layer respectively, problems such as uneven distribution of electrons and holes in the active layer and easy leakage of electrons from the active layer occur. Secondly, most GaN-based LED epitaxial layers are currently grown on heterogeneous substrates, commonly including sapphire, silicon carbide, and silicon substrates. These heterogeneous substrates have significant lattice mismatches with the GaN epitaxial layer, resulting in high crystal defect density and poor quality in the GaN epitaxial layer, leading to abnormal LED reliability. Summary of the Invention

[0005] Based on this, the purpose of this invention is to propose an LED epitaxial structure and its fabrication method to solve the problems of uneven electron and hole distribution, easy electron overflow, high crystal density and poor quality in the active layer of traditional gallium nitride-based LEDs.

[0006] The present invention proposes an LED epitaxial structure, comprising a substrate and a buffer layer, a transition layer, an n-type semiconductor layer, an active layer, and a p-type semiconductor layer sequentially stacked on the substrate, wherein:

[0007] The n-type semiconductor layer includes a predetermined period of n-type doped GaN layers / Er. a Al b Ga 1-a-bThe N-layer superlattice structure has Er and Al component concentrations that gradually increase away from the transition layer in each superlattice structure.

[0008] In summary, based on the aforementioned LED epitaxial structure, adding an ErAlGaN intercalation layer to the n-type semiconductor layer can increase the barrier height, restrict the longitudinal movement of electrons, reduce electron overflow in the quantum well, improve the electron-hole distribution in the active layer, and enhance the luminous efficiency of electron-hole recombination in the active layer. Secondly, ErAlGaN and GaN can achieve lattice constant matching and stress-free material growth, effectively controlling piezoelectric polarization, mitigating the quantum confinement Stark effect, and improving the luminous efficiency of LEDs. Simultaneously, designing an ErAlGaN layer, compared to a traditional AlGaN layer, can result in better crystal quality, thereby reducing the dislocation density in the active layer, decreasing non-radiative recombination centers and leakage channels, and enabling LED devices to exhibit superior performance and reliability. Furthermore, by gradually increasing the concentrations of Er and Al components in each superlattice structure away from the transition layer, the barrier height decreases from high to low. This effectively restricts the movement of electrons from the n-type semiconductor layer to the light-emitting layer, promotes lateral current expansion, further improves the electron-hole distribution in the active layer, and enhances the luminous efficiency of electron-hole recombination in the active layer. At the same time, by increasing the lattice constant from low to high, the lattice constant between the n-type semiconductor layer and the active layer can be better matched, achieving a good lattice transition, mitigating piezoelectric polarization effects, and improving luminous efficiency under high current.

[0009] Furthermore, in the Er superlattice structure a Al b Ga 1-a-b In layer N:

[0010] 0<a<0.4, 0<b<1, a+b≤1, a<b.

[0011] Furthermore, in the n-type doped GaN layer of the superlattice structure:

[0012] The n-type dopant of the n-type doped GaN layer is Si, and the Si doping concentration is 2×E. 18 atoms / cm 3 -5×E 19 atoms / cm 3 .

[0013] Furthermore, the Er a Al b Ga 1-a-b The thickness of the N-layer is 10-100 nm, and the thickness of the n-type doped GaN layer is 5-50 nm.

[0014] Further, the p-type semiconductor layer comprises a first p-type layer, a p-type electron blocking layer, a second p-type layer, and a p-type contact layer stacked sequentially, wherein:

[0015] The growth temperature of the first p-type layer is lower than that of the second p-type layer. Both the first p-type layer and the second p-type layer are Mg-doped p-type GaN layers. The p-type electron blocking layer is an AlGaN layer, and the p-type contact layer is a Mg-doped GaN layer.

[0016] Furthermore, the Mg doping concentration of the first p-type layer is 5×E. 19 atoms / cm 3 ~2×E 20 atoms / cm 3 The Mg doping concentration of the second p-type layer is 3×E. 18 atoms / cm 3 ~2×E 19 atoms / cm 3 The Mg doping concentration of the P-type contact layer is 2×E. 20 atoms / cm 3 ~1×E 22 atoms / cm 3 .

[0017] On the other hand, the present invention also proposes a method for preparing an LED epitaxial structure, for preparing the above-mentioned LED epitaxial structure, the preparation method comprising:

[0018] A substrate is provided, and a buffer layer is deposited on the substrate;

[0019] A transition layer is deposited on the buffer layer;

[0020] An n-type semiconductor layer is deposited on the transition layer, the n-type semiconductor layer comprising a predetermined number of n-type doped GaN layers / Er. a Al b Ga 1-a-b The N-layer superlattice structure has Er and Al component concentrations that gradually increase away from the transition layer in each superlattice structure.

[0021] An active layer is deposited on the n-type semiconductor layer;

[0022] A p-type semiconductor layer is deposited on the active layer.

[0023] Furthermore, in the step of preparing the n-type doped GaN layer of the superlattice structure:

[0024] The growth temperature is 1090–1120℃, the growth pressure is 100–500 torr, the nitrogen source flow rate is 120–160 slm, and the gallium source flow rate is 1000–1500 sccm.

[0025] Furthermore, in the preparation of superlattice structures, Er a Al b Ga 1-a-b In the steps of layer N:

[0026] The growth temperature is 1050–1100℃, the growth pressure is 100–500 torr, and the nitrogen source flow rate is 120–160 slm.

[0027] The flow rate of the gallium source is 300–600 sccm, and the flow rate of the gallium source gradually decreases over time.

[0028] The flow rate of the aluminum source is 100-500 sccm, and the flow rate of the Al source gradually increases over time.

[0029] The flow rate of the erbium source is 100-600 sccm, and the flow rate of the erbium source gradually increases over time.

[0030] Furthermore, in the step of preparing the p-type semiconductor layer:

[0031] A first p-type layer, a p-type electron blocking layer, a second p-type layer, and a p-type contact layer are sequentially deposited on the active layer, wherein:

[0032] The growth temperature of the first p-type layer is 700–800℃, and the growth temperature of the second p-type layer is 900–1050℃.

[0033] Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by means of embodiments of the invention. Attached Figure Description

[0034] Figure 1 This is a schematic diagram of the LED epitaxial structure proposed in the first embodiment of the present invention;

[0035] Figure 2 This is a flowchart of the method for preparing the LED epitaxial structure proposed in the second embodiment of the present invention.

[0036] The following detailed description, in conjunction with the accompanying drawings, will further illustrate the present invention. Detailed Implementation

[0037] To facilitate understanding of the present invention, a more complete description will be given below with reference to the accompanying drawings. Several embodiments of the invention are illustrated in the drawings. However, the invention can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

[0038] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0039] Please see Figure 1 The figure shows a schematic diagram of the LED epitaxial structure in the first embodiment of the present invention. The LED epitaxial structure includes a substrate 10 and a buffer layer 20, a transition layer 30, an n-type semiconductor layer 40, an active layer 50 and a p-type semiconductor layer 60 sequentially stacked on the substrate 10. In this embodiment, the transition layer 30 is an undoped GaN layer and the p-type semiconductor layer 60 is a p-type GaN layer.

[0040] The n-type semiconductor layer 40 includes a predetermined number of n-type doped GaN layers 401 / Er. a Al b Ga 1-a-b Regarding the N-layer 402 superlattice structure, it should be noted that in conventional techniques, to reduce stress accumulation in the active layer 50, a relatively thick electron blocking layer with a high potential height is typically grown on the p-type semiconductor layer 60 side to prevent electron overflow from the active layer 50. However, while the electron blocking layer on the p-type semiconductor layer 60 side prevents electron overflow, it also affects hole injection into the active layer 50. Therefore, in this embodiment, the n-type semiconductor layer 40 is configured as a superlattice structure, utilizing Er... a Al b Ga 1-a-b The N-layer 402 has a high barrier property to prevent electrons from entering the active layer 50. On the other hand, it can achieve strain-free growth that matches the GaN lattice, thus not affecting the stress changes during the subsequent growth of the active layer 50. This can better improve the electron-hole distribution in the active layer 50, without aggravating the piezoelectric polarization effect, and improve the luminous efficiency under high current.

[0041] The preset period is generally 2-8, that is, n-type doped GaN layer 401 / Er a Al b Ga 1-a-bThe number of cycles in an N-layer 402 superlattice structure is typically 2-8. For example, the preset period of the superlattice structure is 2, 3, 5, or 8, etc. When the preset period is less than 2, the ability to restrict the longitudinal movement of electrons weakens; when the preset period is greater than 8, it leads to increased resistance and higher operating voltage. Specifically, the layer stacked on the surface of the transition layer 30 can be either an n-type doped GaN layer 401 in the n-type semiconductor layer 40 or an Er... a Al b Ga 1-a-b The N-layer 402, i.e., the closest layer to the transition layer 30 in the n-type semiconductor layer 40, can be an n-type doped GaN layer 401 or an Er-type doped layer 402. a Al b Ga 1-a-b Similarly, the n-type semiconductor layer 40 closest to the active layer 50 can also be an n-type doped GaN layer 401 or Er-type doped layer 402. a Al b Ga 1-a-b N layer 402.

[0042] Furthermore, the n-type doped GaN layer 401 and Er a Al b Ga 1-a-b In each superlattice structure composed of N-layer 402, the Er and Al component concentrations gradually increase along the direction away from the transition layer 30, resulting in Er a Al b Ga 1-a-b The decreasing barrier height of the N-layer effectively restricts the movement of electrons from the n-type semiconductor layer 40 towards the light-emitting layer, promoting lateral current expansion and further improving the electron-hole distribution in the active layer 50. This enhances the luminescence efficiency of electron-hole recombination in the active layer 50. Simultaneously, the increasing lattice constant allows for better matching between the n-type semiconductor layer 40 and the active layer 50, achieving a smooth lattice transition, mitigating piezoelectric polarization effects, and improving luminescence efficiency under high current. Specifically, in the superlattice structure Er... a Al b Ga 1-a-b In layer N 402: 0 < a < 0.4, 0 < b < 1, a + b ≤ 1, a < b, for example, Er closest to transition layer 30. a Al b Ga 1-a-b N-level 402 specifically refers to Er 0.2 Al 0.3 Ga 0.5 N, and gradually becomes Er 0.3 Al 0.5 Ga 0.2 N.

[0043] In this layer, the n-type dopant of the n-type doped GaN layer 401 is Si, which is used to provide electrons. The Si doping concentration is 2×E. 18 atoms / cm 3 -5×E 19 atoms / cm 3 For example, the Si doping concentration in the n-type doped GaN layer 401 can be 2.5 × E. 18 atoms / cm 3 3.5×E 18 atoms / cm 3 Or 4.8×E 18 atoms / cm 3 However, this is not the only factor. It should be noted that if the Si doping concentration is too low, the electron concentration will be low, the resistivity high, the LED operating voltage high, and the number of electrons entering the active layer 50 in the light-emitting region will be limited, resulting in lower brightness. When the Si doping concentration is high, the electron concentration is high, the resistivity low, and the corresponding LED operating voltage low, allowing sufficient electrons to enter the active layer 50 in the light-emitting region, thus increasing brightness. However, when a critical value is exceeded, the brightness will decrease. The current path is concentrated directly below the electrode, resulting in a very small light-emitting area, affecting brightness. The number of holes in the active layer 50 is limited, and electron overflow to the p-type GaN affects hole injection into the active layer 50, thus affecting brightness. Based on this, the Si doping concentration in the n-type doped GaN layer 401 is set to 2×E. 18 atoms / cm 3 -5×E 19 atoms / cm 3 .

[0044] Wherein, Er a Al b Ga 1-a-b The thickness of the N layer is 10-100 nm, for example, Er a Al b Ga 1-a-b The thickness of the N-layer can be 10nm, 30nm, 50nm, 70nm or 100nm, but is not limited thereto. The thickness of the n-type doped GaN layer 401 is 5-50nm. For example, the thickness of the n-type doped GaN layer 401 can be 5nm, 20nm, 30nm or 50nm, but is not limited thereto.

[0045] It should also be noted that the p-type semiconductor layer 60 includes a first p-type layer 601, a p-type electron blocking layer 602, a second p-type layer 603, and a p-type contact layer 604 stacked sequentially. The first p-type layer 601 is stacked on the surface of the active layer 50. The growth temperature of the first p-type layer 601 is lower than that of the second p-type layer 603. Growing the first p-type layer 601 at a relatively low temperature is beneficial for the activation of Mg elements, while growing it at a relatively high temperature is beneficial for filling V-shaped pits (which are generated during chip fabrication in conventional technology).

[0046] Both the first p-type layer 601 and the second p-type layer 603 are Mg-doped p-type GaN layers, the p-type electron blocking layer 602 is an AlGaN layer, and the p-type contact layer 604 is a Mg-doped GaN layer. Specifically, the Mg doping concentration of the first p-type layer 601 is 5 × E. 19 atoms / cm 3 ~2×E 20 atoms / cm 3 The Mg doping concentration of the second p-type layer 603 is 3×E. 18 atoms / cm 3 ~2×E 19 atoms / cm 3 The Mg doping concentration of the p-type contact layer 604 is 2×E. 20 atoms / cm 3 ~1×E 22 atoms / cm 3 In this embodiment, the Mg doping concentration of the second p-type layer 603 is less than that of the first p-type layer 601, and the Mg doping concentration of the first p-type layer 601 is less than that of the p-type contact layer 604. By setting the p-type contact layer 604 to be relatively heavily doped with Mg, and the first p-type layer 601 and the second p-type layer 603 to be relatively lightly doped with Mg, the p-type contact layer 604 has a higher hole concentration, which can reduce the contact resistance between the epitaxial layer and subsequent processes, thereby reducing the operating voltage of the LED. The relatively light Mg doping can reduce the light absorption of the p-type semiconductor layer 60. For example, the Mg doping concentration of the first p-type layer 601 can be 6×E. 19 atoms / cm 3 1×E 20 atoms / cm 3 Or 1.8×E 20 atoms / cm 3 However, it is not limited to this. The Mg doping concentration of the second p-type layer 603 can be 4 × E. 18 atoms / cm 3 9×E 18 atoms / cm3 Or 1.8×E 19 atoms / cm 3 Wait a minute. The Mg doping concentration in the p-type contact layer 604 can be 3 × E. 20 atoms / cm 3 1×E 21 atoms / cm 3 9×E 21 atoms / cm 3 etc.

[0047] In addition, the active layer 50 includes x periodically alternating quantum well layers and quantum barrier layers, with each layer stacked on the surface of the n-type semiconductor layer 40 being a quantum well layer. The value of x ranges from 6 to x ≤ 12. The well layers have low potential barriers, while the barrier layers have high potential barriers, forming a quantum well structure. This structure enables carrier localization, overlaps the spatial wave functions of electrons and holes, increases the probability of radiative recombination, and improves luminescence brightness. When x < 6, the localization effect on electrons and holes weakens, and the luminescence efficiency decreases. When x > 12, the compositional differences between the quantum well layers and quantum barrier layers become large, resulting in a high period number and poor crystal quality.

[0048] In summary, based on the aforementioned LED epitaxial structure, adding an ErAlGaN intercalation layer to the n-type semiconductor layer can increase the barrier height, restrict the longitudinal movement of electrons, reduce electron overflow in the quantum well, improve the electron-hole distribution in the active layer, and enhance the luminous efficiency of electron-hole recombination in the active layer. Secondly, ErAlGaN and GaN can achieve lattice constant matching and stress-free material growth, effectively controlling piezoelectric polarization, mitigating the quantum confinement Stark effect, and improving the luminous efficiency of LEDs. Simultaneously, designing an ErAlGaN layer, compared to a traditional AlGaN layer, can result in better crystal quality, thereby reducing the dislocation density in the active layer, decreasing non-radiative recombination centers and leakage channels, and enabling LED devices to exhibit superior performance and reliability. Furthermore, by gradually increasing the concentrations of Er and Al components in each superlattice structure away from the transition layer, the barrier height decreases from high to low. This effectively restricts the movement of electrons from the n-type semiconductor layer to the light-emitting layer, promotes lateral current expansion, further improves the electron-hole distribution in the active layer, and enhances the luminous efficiency of electron-hole recombination in the active layer. At the same time, by increasing the lattice constant from low to high, the lattice constant between the n-type semiconductor layer and the active layer can be better matched, achieving a good lattice transition, mitigating piezoelectric polarization effects, and improving luminous efficiency under high current.

[0049] Please see Figure 2 The diagram shows a flowchart of a method for fabricating an LED epitaxial structure according to a second embodiment of the present invention. This method includes steps S01 to S05, wherein:

[0050] Step S01: Provide a substrate and deposit a buffer layer on the substrate;

[0051] In this step, the selected substrate includes, but is not limited to, sapphire substrates, silicon substrates, silicon carbide substrates, aluminum nitride substrates, gallium nitride substrates, and composite substrates such as those composed of silicon dioxide and sapphire. Specifically, in this embodiment, sapphire is used as the epitaxial layer growth substrate, which can be used to fabricate periodically changing structures to form a patterned substrate. Composite patterned substrates such as SiO2 to Al2O3 can also be used. Specifically, in this embodiment of the invention, a sapphire patterned substrate is used as the epitaxial layer growth substrate.

[0052] Furthermore, the buffer layer can be selected from any one of AlN buffer layer, GaN buffer layer, or AlGaN buffer layer. In a specific embodiment of the present invention, the buffer layer is a GaN buffer layer, and its specific deposition process is as follows: the temperature of the reaction chamber is controlled at 760-900℃, the pressure is controlled at 100-200 torr, the rotation speed of the graphite substrate is controlled at 800-1000 rpm, NH3 with a flow rate of 50-100 slm is introduced as the N (nitrogen) source, and TMGa with a flow rate of 20-200 sccm is introduced as the Ga (gallium) source. In this embodiment, it is preferably 180 sccm, so that a GaN buffer layer is grown, and the thickness of the deposited GaN buffer layer is controlled at 5-40 nm. In this embodiment, the thickness of the GaN buffer layer is preferably 22 nm.

[0053] Step S02: Deposit a transition layer on the buffer layer;

[0054] The specific deposition process is as follows: the reaction chamber temperature is raised to 1100–1150°C, the pressure is controlled at 100–500 torr, the graphite substrate rotation speed is controlled at 500–1000 rpm, NH3 at a flow rate of 120–160 slm is introduced as the N (nitrogen) source, and TMGa at a flow rate of 1300–1700 sccm is introduced as the Ga (gallium) source, thereby growing an undoped GaN layer, and controlling the thickness of the deposited undoped GaN layer to be 1–2 μm. The undoped GaN layer serves as the transition layer between the buffer layer and the n-type semiconductor layer. In a preferred embodiment of the invention, the reaction chamber temperature is preferably 1110°C, the pressure is preferably 150 torr, the graphite substrate rotation speed is preferably 800 rpm, the TMGa flow rate is preferably 1500 sccm, and the thickness of the deposited undoped GaN layer is preferably controlled to be 1.2 μm.

[0055] Step S03: Deposit an n-type semiconductor layer on the transition layer, the n-type semiconductor layer comprising a predetermined number of n-type doped GaN layers / Er a Al b Ga 1-a-bThe N-layer superlattice structure has Er and Al component concentrations that gradually increase away from the transition layer in each superlattice structure.

[0056] Specifically, in the step of preparing the n-type semiconductor layer, the reaction chamber temperature is reduced to 1090–1120℃, the pressure is controlled at 100–500 torr, the rotation speed of the graphite substrate is controlled at 500–1200 rpm, NH3 at a flow rate of 120–160 slm is introduced as the N (nitrogen) source, TMGa at a flow rate of 1000–1500 sccm is introduced as the Ga (gallium) source, and SiH4 is introduced as the n-type dopant for the n-type doped GaN layer, while the Si (silicon) doping concentration is 2 × E. 18 atoms / cm 3 -5×E 19 atoms / cm 3 This allows for the growth of a Si-doped n-type GaN layer, with the thickness of the deposited n-type doped GaN layer controlled to be 5–50 nm. In a preferred embodiment of the invention, the reaction chamber temperature is preferably 1110 °C, the pressure is preferably 150 torr, the graphite substrate rotation speed is preferably 800 rpm, the TMGa flow rate is preferably 1300 sccm, and the Si doping concentration is 2.5 × E. 19 atoms / cm 3 The thickness of the deposited N-type GaN layer is preferably controlled to be 25 nm.

[0057] The n-type doped GaN layer serves as the main epitaxial layer that provides electrons. During GaN growth, SiH4 is introduced to provide Si elements, where Si is a tetravalent element and Ga is a trivalent element in GaN. When Si atoms replace Ga atoms, they provide electrons, thus forming the electron-providing n-type doped GaN layer.

[0058] Furthermore, in the preparation of Er a Al b Ga 1-a-b During the N-layer deposition process, the reaction chamber temperature needs to be reduced to 1050–1100℃, the pressure controlled at 100–500 torr, and the graphite substrate rotation speed controlled at 500–1200 rpm. NH3 is introduced at a flow rate of 120–160 slm as the N (nitrogen) source, and TMGa is introduced at a flow rate of 300–600 sccm as the Ga (gallium) source, with the Ga source flow rate gradually decreasing. TMAl is introduced at a flow rate of 100–500 sccm as the Al (aluminum) source, with the Al source flow rate gradually increasing. TRIPER is introduced at a flow rate of 100–600 sccm as the Er (erbium) source, with the Er source flow rate gradually increasing, and the deposited Er is controlled. a Alb Ga 1-a-b The thickness of the N-layer is 10–100 nm. In a preferred embodiment of the invention, the reaction chamber temperature is preferably 1070 °C, the pressure is preferably 150 torr, the graphite substrate rotation speed is preferably 800 rpm, the TMGa flow rate is preferably gradually decreasing from 500 sccm to 100 sccm, the TMAl flow rate is preferably gradually decreasing from 150 sccm to 300 sccm, and the TRIPER flow rate is preferably gradually decreasing from 100 sccm to 300 sccm. This ensures that the gallium source flow rate gradually decreases over time, while the Al and erbium source flow rates gradually increase over time. Furthermore, in this embodiment, the deposited Er... a Al b Ga 1-a-b The preferred thickness of the N layer is 50 nm.

[0059] Among them, the Er a Al b Ga 1-a-b The N-layer has a larger band gap than GaN and is placed on top of the n-type doped GaN layer. Electrons move from the n-type doped GaN layer to Er. a Al b Ga 1-a-b The N-layer needs to overcome a higher potential barrier height to effectively restrict electron movement, reduce electron overflow, improve the electron-hole distribution in the active layer, and increase the luminescence efficiency of electron-hole recombination in the active layer. Furthermore, by adjusting the composition of the ErAlGaN layer from Er... 0.1 Al 0.4 Ga 0.5 N to Er 0.2 Al 0.7 Ga 0.1 Nitrogen (N) can achieve a gradual change in the potential barrier and match the lattice constant of GaN, which can better improve the electron-hole distribution in the active layer without exacerbating the piezoelectric polarization effect, thus improving the luminescence efficiency under high current. Simultaneously, the addition of Er... a Al b Ga 1-a-b The formation of an N-layer superlattice structure can achieve better crystal quality, thereby reducing the dislocation density of the active layer, reducing non-radiative recombination centers and leakage channels, and enabling LED devices to have superior performance and reliability.

[0060] Step S04: Deposit an active layer on the n-type semiconductor layer;

[0061] In this embodiment of the invention, the active layer is formed by alternating growth of x periodically arranged quantum well layers and quantum barrier layers. Specifically, the quantum well layers are first arranged on an n-type semiconductor layer, and then the quantum barrier layers are arranged on top of the quantum well layers. The quantum well layers and quantum barrier layers are then periodically alternating to form the multi-quantum well layer. In this embodiment, the period x for alternating arrangement of the quantum well layers and quantum barrier layers ranges from 6 ≤ x ≤ 12. As a preferred embodiment, x can be 10, meaning the multi-quantum well layer is formed by 10 alternating arrangements of quantum well layers and quantum barrier layers. Further, the quantum well layer is an InGaN layer, and the quantum barrier layer is a GaN layer. As an example of the invention, the thickness of the quantum well layer is 1.5–5.5 nm, and the thickness of the quantum barrier layer 72 is 5–15 nm.

[0062] Specifically, during the growth of the quantum well layer, the reaction chamber growth temperature is 750℃~810℃, the pressure is 150~300 torr, the graphite substrate rotation speed is 400~700 rpm, NH3 is introduced at a flow rate of 150~200 slm as the N (nitrogen) source, TEGa is introduced at a flow rate of 250 sccm as the Ga (gallium) source, and TMIn is introduced at a flow rate of 2500 sccm as the In (indium) source. The thickness of the deposited InGaN quantum well layer is controlled to be 1.5~5.5 nm. In a preferred embodiment of the present invention, the thickness of the quantum well layer is 3 nm.

[0063] Furthermore, during the growth of the quantum barrier layer, the reaction chamber temperature is 850–900°C, the pressure is 150–300 torr, the rotation speed of the graphite substrate is 400–700 rpm, NH3 is introduced at a flow rate of 150–200 slm as the N (nitrogen) source, and TEGa is introduced at a flow rate of 1000 sccm as the Ga (gallium) source. The thickness of the deposited GaN quantum barrier layer is controlled to be 5 nm–15 nm. In a preferred embodiment of the present invention, the thickness of the quantum barrier layer is 10 nm. Furthermore, in one cycle, the total thickness of the quantum well layer and the quantum barrier layer is 6.5 nm–20 nm.

[0064] Step S05: Deposit a p-type semiconductor layer on the active layer.

[0065] It should be noted that the p-type GaN layer comprises a low-temperature p-type layer (first p-type layer), a p-type electron blocking layer, a high-temperature p-type layer (second p-type layer), and a p-type contact layer stacked sequentially. Therefore, the steps for depositing a p-type layer on the active layer are: sequentially depositing a low-temperature p-type layer, a p-type electron blocking layer, a high-temperature p-type layer, and a p-type contact layer on the active layer. The low-temperature p-type layer is directly deposited on the multi-quantum-well layer, that is, it is deposited on the last periodically alternating quantum barrier layer. Furthermore, the low-temperature p-type layer is a p-type GaN layer grown under low-temperature conditions, the p-type electron blocking layer is an AlGaN layer, the high-temperature p-type layer is a p-type GaN layer grown under high-temperature conditions, and the p-type contact layer is a heavily Mg-doped GaN layer.

[0066] The specific process for depositing the low-temperature p-type layer is as follows: the reaction chamber temperature is controlled at 700–800℃, the pressure is controlled at 100–400 torr, the rotation speed of the graphite disk supporting the substrate is controlled at 1000–1300 rpm, NH3 with a flow rate of 100–150 slm is introduced as the N (nitrogen) source, and TEGa with a flow rate of 1000–1600 sccm is introduced as the Ga (gallium) source. During GaN growth, Mg2+ (CP2Mg) is introduced as the p-type dopant, and the Mg (magnesium) doping concentration is 5 × E. 19 atoms / cm 3 ~2×E 20 atoms / cm 3 This allows for the growth of a Mg-doped p-type GaN layer, with the thickness of the deposited low-temperature p-type layer controlled to be 5 nm to 30 nm. In a preferred embodiment of the invention, the thickness of the low-temperature p-type layer is preferably 15 nm. CP2Mg provides Mg (magnesium) element, where Mg is a divalent element, while Ga in GaN is a trivalent element. When Mg atoms replace Ga atoms, they provide holes, thus forming a hole-providing p-type GaN layer. Simultaneously, by using an appropriate concentration of Mg doping, defects and vacancies in the GaN material can be effectively filled, dislocations repaired, and further dislocation propagation prevented.

[0067] Furthermore, the specific process for depositing a p-type electron blocking layer on a low-temperature p-type layer is as follows: the reaction chamber temperature is controlled at 900–1000°C, the pressure is controlled at 50–300 torr, the rotation speed of the graphite disk supporting the substrate is controlled at 800–1100 rpm, NH3 with a flow rate of 100–150 slm is introduced as the N (nitrogen) source, TEGa with a flow rate of 500–1200 sccm is introduced as the Ga (gallium) source, and TMAl with a flow rate of 10–100 sccm is introduced as the Al (aluminum) source, so that an AlGaN electron blocking layer is grown, and the thickness of the deposited p-type electron blocking layer is controlled at 10 nm–100 nm. In a preferred embodiment of the present invention, the thickness of the p-type electron blocking layer is preferably 20 nm.

[0068] Furthermore, the specific process for depositing a high-temperature p-type layer on a p-type electron blocking layer is as follows: the reaction chamber temperature is controlled at 900–1050 °C, the pressure is controlled at 100–600 torr, the rotation speed of the graphite disk supporting the substrate is controlled at 800–1100 rpm, NH3 with a flow rate of 100–150 slm is introduced as the N (nitrogen) source, and TEGa with a flow rate of 700–1000 sccm is introduced as the Ga (gallium) source. During GaN growth, magnesia-diocene (CP2Mg) is introduced as the p-type dopant, and the Mg (magnesium) doping concentration is 3 × E 18 atoms / cm 3 ~2×E 19 atoms / cm 3 This allows for the growth of a Mg-doped high-temperature p-type GaN layer, with the thickness of the deposited high-temperature p-type layer controlled to be 20 nm to 150 nm. In a preferred embodiment of the invention, the thickness of the high-temperature p-type layer is preferably 60 nm, and the Mg doping concentration in the high-temperature p-type layer is preferably 1 × E. 19 atoms / cm 3 .

[0069] Furthermore, the specific deposition process for depositing the p-type contact layer on the high-temperature p-type layer is as follows: the reaction chamber temperature is controlled at 700–900℃, the pressure is controlled at 100–400 torr, the rotation speed of the graphite disk supporting the substrate is controlled at 800–1100 rpm, NH3 with a flow rate of 100–150 slm is introduced as the N (nitrogen) source, and TEGa with a flow rate of 400–600 sccm is introduced as the Ga (gallium) source. During GaN growth, magnesia-diocene (CP2Mg) is introduced as the p-type dopant, and the Mg (magnesium) doping concentration is 2 × E 20 atoms / cm 3 ~1×E 22 atoms / cm 3 This allows for the growth of a heavily Mg-doped GaN layer, with the deposited p-type contact layer controlled to be 1 nm to 10 nm in thickness. In a preferred embodiment of the invention, the thickness of the p-type contact layer is preferably 5 nm, and the Mg doping concentration in the p-type contact layer is preferably 1 × E. 21 atoms / cm 3 .

[0070] Experimental Examples 1-4

[0071] Please refer to Table 1 below. Using the preparation method in the second embodiment, adjust Er... a Al b Ga 1-a-b With the ratio of erbium to aluminum in the N-layer remaining constant, and other processes unchanged, the specific experimental data obtained are as follows:

[0072] Table 1

[0073] Experimental example <![CDATA[Er a Al b Ga 1-a-b Initial proportions in layer N]]> <![CDATA[Er a Al b Ga 1-a-b The final proportions in layer N]]> Brightness / mW Voltage / V 1 a = 0.05, b = 0.2 a = 0.15, b = 0.5 193.9 3.21 2 a = 0.1, b = 0.25 a = 0.2, b = 0.55 195.2 3.18 3 a = 0.15, b = 0.3 a = 0.25, b = 0.6 195.4 3.17 4 a = 0.2, b = 0.35 a = 0.3, b = 0.65 193.1 3.12

[0074] Experimental Example 5-17

[0075] Please refer to Table 2 below. Using the preparation method in the second embodiment, the Si doping concentration in the n-type doped GaN layer was adjusted while other processes remained unchanged. The experimental data obtained are as follows:

[0076] Table 2

[0077] Experimental example Si doping concentration in n-type doped GaN layer Brightness / mW Voltage / V 5 <![CDATA[2×E 18 atoms / cm 3 ]]> 176.9 3.28 6 <![CDATA[3×E 18 atoms / cm 3 ]]> 181.0 3.26 7 <![CDATA[4×E 18 atoms / cm 3 ]]> 184.0 3.25 8 <![CDATA[5×E 18 atoms / cm 3 ]]> 186.4 3.24 9 <![CDATA[6×E 18 atoms / cm 3 ]]> 188.5 3.23 10 <![CDATA[7×E 18 atoms / cm 3 ]]> 190.0 3.23 11 <![CDATA[8×E 18 atoms / cm 3 ]]> 191.3 3.22 12 <![CDATA[9×E 18 atoms / cm 3 ]]> 192.3 3.21 13 <![CDATA[1×E 19 atoms / cm 3 ]]> 193.1 3.21 14 <![CDATA[2×E 19 atoms / cm 3 ]]> 195.2 3.18 15 <![CDATA[3×E 19 atoms / cm 3 ]]> 195.6 3.16 16 <![CDATA[4×E 19 atoms / cm 3 ]]> 195.3 3.15 17 <![CDATA[5×E 19 atoms / cm 3 ]]> 193.9 3.15

[0078] Experimental Examples 18-39

[0079] Please refer to Table 3 below. Using the preparation method in the second embodiment, the Mg doping concentrations of the first p-type layer, the second p-type layer, and the p-type contact layer were adjusted, while other processes remained unchanged. The experimental data obtained are as follows:

[0080] Table 3

[0081]

[0082]

[0083] Comparative Example 1

[0084] The difference between this comparative example and the experimental example is that Er is not set. a Al b Ga 1-a-b The N-layer, or n-type semiconductor layer, is simply an n-type GaN layer, and its fabrication method does not include Er. a Al b Ga 1-a-b The fabrication method for the N-layer, i.e., the fabrication method excluding the superlattice structure, is the same as that in Experiments 1-4. The operating voltage of the chip was measured to be 3.27V and the brightness was 189.2mW.

[0085] Comparative Example 2

[0086] The difference between this comparative example and the experimental example is that the p-type semiconductor layer is only a simple p-type GaN layer. All other steps are the same as in experimental examples 18-39. The measured chip voltage is 3.39V and the brightness is 189.7mW.

[0087] Analysis: Based on Experimental Examples 1-4 and Comparative Example 1, it can be seen that setting an n-type doped GaN layer / Er a Al b Ga 1-a-bN-layer superlattice structures can improve brightness by approximately 2.1%-3.3% and reduce operating voltage by 1.8%-4.6%. As shown in Experiment 5-17, chip brightness initially increases with increasing Si doping concentration in the n-type doped GaN layer. After reaching a relatively high level, the brightness begins to decrease. However, the chip's operating voltage consistently decreases with increasing Si doping concentration in the n-type doped GaN layer. The conventional Si doping concentration in n-type doped GaN layers is typically 1×E. 19 atoms / cm 3 The following describes how to set an n-type doped GaN layer / Er a Al b Ga 1-a-b The N-layer superlattice structure allows for a further increase in the Si doping concentration in the n-type doped GaN layer, thereby improving brightness and reducing operating voltage. As shown in Experimental Examples 18-39 and Comparative Example 2, by setting the p-type semiconductor layer as multiple sublayers and optimizing the Mg doping concentration in each layer, the chip brightness is increased by 0.4%-3.1%, and the operating voltage is reduced by 1.2%-7.1%.

[0088] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these modifications and improvements all fall within the scope of protection of the present invention. Therefore, the scope of protection of this patent should be determined by the appended claims.

Claims

1. An LED epitaxial structure, characterized in that, It includes a substrate and a buffer layer, a transition layer, an n-type semiconductor layer, an active layer, and a p-type semiconductor layer sequentially stacked on the substrate, wherein: The n-type semiconductor layer includes a predetermined period of n-type doped GaN layers / Er. a Al b Ga 1-a-b The N-layer superlattice structure has Er and Al component concentrations that gradually increase away from the transition layer in each superlattice structure. The n-type dopant of the n-type doped GaN layer is Si, and the Si doping concentration is 2×E. 19 atoms / cm 3 -5×E 19 atoms / cm 3 ; Among them, in the superlattice structure Er a Al b Ga 1-a-b In layer N: 0<a<0.4, 0<b<1, a+b≤1, a<b.

2. The LED epitaxial structure according to claim 1, characterized in that, The Er a Al b Ga 1-a-b The thickness of the N-layer is 10-100 nm, and the thickness of the n-type doped GaN layer is 5-50 nm.

3. The LED epitaxial structure according to claim 1, characterized in that, The p-type semiconductor layer comprises a first p-type layer, a p-type electron blocking layer, a second p-type layer, and a p-type contact layer stacked sequentially, wherein: The growth temperature of the first p-type layer is lower than that of the second p-type layer. Both the first p-type layer and the second p-type layer are Mg-doped p-type GaN layers. The p-type electron blocking layer is an AlGaN layer, and the p-type contact layer is a Mg-doped GaN layer.

4. The LED epitaxial structure according to claim 3, characterized in that, The doping concentration of Mg in the first p-type layer is 5×E. 19 atoms / cm 3 ~2×E 20 atoms / cm 3 The Mg doping concentration of the second p-type layer is 3×E. 18 atoms / cm 3 ~2×E 19 atoms / cm 3 The Mg doping concentration of the p-type contact layer is 2×E. 20 atoms / cm 3 ~1×E 22 atoms / cm 3 .

5. A method for preparing an LED epitaxial structure, used to prepare the LED epitaxial structure according to any one of claims 1-4, characterized in that, The preparation method includes: A substrate is provided, and a buffer layer is deposited on the substrate; A transition layer is deposited on the buffer layer; An n-type semiconductor layer is deposited on the transition layer, the n-type semiconductor layer comprising a predetermined number of n-type doped GaN layers / Er. a Al b Ga 1-a-b The N-layer superlattice structure has Er and Al component concentrations that gradually increase away from the transition layer in each superlattice structure. An active layer is deposited on the n-type semiconductor layer; A p-type semiconductor layer is deposited on the active layer.

6. The method for preparing an LED epitaxial structure according to claim 5, characterized in that, In the steps of preparing an n-type doped GaN layer with a superlattice structure: The growth temperature is 1090~1120℃, the growth pressure is 100-500 torr, the nitrogen source flow rate is 120~160 slm, and the gallium source flow rate is 1000~1500 sccm.

7. The method for preparing an LED epitaxial structure according to claim 5, characterized in that, Er in the preparation of superlattice structures a Al b Ga 1-a-b In the steps of layer N: The growth temperature is 1050~1100℃, the growth pressure is 100-500 torr, and the nitrogen source flow rate is 120~160 slm. The flow rate of the gallium source is 300~600 sccm, and the flow rate of the gallium source gradually decreases over time. The flow rate of the aluminum source is 100~500 sccm, and the flow rate of the Al source gradually increases over time. The flow rate of the erbium source is 100-600 sccm, and the flow rate of the erbium source gradually increases over time.

8. The method for preparing an LED epitaxial structure according to claim 5, characterized in that, In the step of preparing the p-type semiconductor layer: A first p-type layer, a p-type electron blocking layer, a second p-type layer, and a p-type contact layer are sequentially deposited on the active layer, wherein: The growth temperature of the first p-type layer is 700~800℃, and the growth temperature of the second p-type layer is 900~1050℃.

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