amplification device

Abstract

An amplification device includes an amplification unit, an impedance unit, and a logarithmic power detector. The amplification unit includes an input for receiving a radio frequency (RF) signal, an output for outputting an amplified RF signal, and a detection unit for outputting a detection signal related to the RF signal. The impedance unit provides an impedance, includes an input coupled to the detection unit for receiving the detection signal, and an output for outputting a power signal. The logarithmic power detector generates a power indication signal based on the power signal, includes an input coupled to the output of the impedance unit, and an output for outputting the power indication signal.

Description

Technical Field

[0001] This invention relates to an amplification device for reducing load effects, and more particularly to an amplification device that reduces load effects by providing appropriate impedance. Background Technology

[0002] To detect the power of the input signals of a group of power amplifiers, a coupler can be connected to the group of power amplifiers, and a logarithmic power detector can be connected to the coupler. Since the output signal of the logarithmic power detector is correlated with the input signals of the group of power amplifiers, its output signal can be used to indicate the power of the input signals of the group of power amplifiers. While this circuit structure is usable, the coupler increases insertion loss, which is detrimental to signal quality.

[0003] In another circuit configuration, a logarithmic power detector can be directly coupled to a group of power amplifiers, and the output signal of the logarithmic power detector can be used to indicate the power of the input signal of the group of power amplifiers. However, the loading effect induced by the logarithmic power detector reduces the linearity between the input signal of the group of power amplifiers and the output signal of the logarithmic power detector, making it difficult to determine the power of the input signal of the group of power amplifiers by measuring the output signal of the logarithmic power detector. Summary of the Invention

[0004] An embodiment provides an amplification device comprising an amplification unit, an impedance unit, and a logarithmic power detector. The amplification unit includes an input terminal for receiving a radio frequency (RF) signal, an output terminal for outputting an amplified RF signal, and a detection terminal for outputting a detection signal related to the RF signal. The impedance unit provides an impedance and includes an input terminal coupled to the detection terminal of the amplification unit for receiving the detection signal, and an output terminal for outputting a power signal. The logarithmic power detector generates a power indication signal based on the power signal and includes an input terminal coupled to the output terminal of the impedance unit, and an output terminal for outputting the power indication signal. The logarithmic power detector has a parallel configuration.

[0005] Another embodiment provides an amplification device including an amplification unit, an impedance unit, and a logarithmic power detector. The amplification unit includes an input for receiving a radio frequency (RF) signal, an output for outputting an amplified RF signal, and a detection unit for outputting a detection signal related to the RF signal. The impedance unit provides an impedance and includes an input coupled to the detection unit for receiving the detection signal, and an output for outputting a power signal. The logarithmic power detector generates a power indication signal based on the power signal and includes an input coupled to the output of the impedance unit, and an output for outputting the power indication signal. The logarithmic power detector has a cascaded structure. Attached Figure Description

[0006] Figure 1 This is a schematic diagram of the amplification device in the embodiment.

[0007] Figure 2 This is a schematic diagram of the amplification device in another embodiment.

[0008] Figure 3 This is a schematic diagram of the impedance unit in the embodiment.

[0009] Figure 4 This is a schematic diagram of an impedance unit in another embodiment.

[0010] Figure 5 This is a schematic diagram of an impedance unit in another embodiment.

[0011] Figure 6 This is a schematic diagram of an impedance unit in another embodiment.

[0012] Figure 7 This is a schematic diagram of an impedance unit in another embodiment.

[0013] Figure 8 This is a schematic diagram of an impedance unit in another embodiment.

[0014] Figure 9 The structure of the logarithmic power detector is shown in the embodiment.

[0015] Figure 10 for Figure 9 A partial schematic diagram of a logarithmic power detector.

[0016] Figure 11 In another embodiment, the structure of the logarithmic power detector is shown.

[0017] Figure 12 In the example, Figure 11 A partial schematic diagram of a logarithmic power detector.

[0018] Figure 13 This is a schematic diagram of the operation unit in the embodiment.

[0019] Figure 14 , Figure 15 and Figure 16 In the example, with Figure 2 The waveform of the signal processed by the impedance unit.

[0020] Figure 17 This is a schematic diagram of a curve with insufficient linearity in the embodiment.

[0021] Figure 18 This is a schematic diagram of a curve with sufficient linearity in the embodiment.

[0022] Symbol Explanation

[0023] 100, 200: Amplification devices

[0024] 110: Amplification Unit

[0025] 120: Impedance unit

[0026] 122, 322, 422: Phase shifters

[0027] 124, 324, 424, 524, 624, 824: Diodes

[0028] 130: Logarithmic Power Detector

[0029] 150: Matching circuit

[0030] 526, 626, 720: Amplifiers

[0031] A9, A11: Adders

[0032] AT1, AT2, AT3: Attenuation circuits

[0033] BB: Third end

[0034] Ca, Ca1, Ca2, C2, C91, C92, C93, C9R, C111, C112, C11R, C13: Capacitors

[0035] CV9, CV11: Current-to-voltage converters

[0036] GG: Fourth End

[0037] I4, I5: Current

[0038] IN: First end

[0039] IT: Result Signal

[0040] N9: Node

[0041] P1, P2, P3: Paths

[0042] PD4, PD131: Parasitic diodes

[0043] Q4, Q5, Q102, Q122, Q131, Q132: Transistors

[0044] R7, R1, R5, R10, R9, R90, R104, R111, R112, R113, R11A, R124, R131, R132, R133: Resistors

[0045] RA1, RA2, RA3, RA111, RA112, RA113: Operation Units

[0046] S1: Detection signal

[0047] Sd: Power signal

[0048] So: Amplify the radio frequency signal

[0049] Spd: Power indicator signal

[0050] SRFIN: Radio frequency signal

[0051] SRFOUT: Output signal

[0052] SS: Second end

[0053] V4, V5, V10, V12: Voltage

[0054] VREF0, VREF, VREF2, VREF3, VREF4, VREF5, VREF6: Reference voltage

[0055] Z1, Z2: Impedance Detailed Implementation

[0056] Figure 1 This is a schematic diagram of the amplification device 100 in an embodiment. The amplification device 100 includes an amplification unit 110 and a logarithmic power detector 130. Figure 1As shown, the amplification unit 110 includes an input terminal, an output terminal, and a detection terminal. The input terminal is used to receive the radio frequency signal SRFIN, the output terminal is used to output the amplified radio frequency signal S0, and the detection terminal is used to output a detection signal S1, which is related to the radio frequency signal SRFIN. A logarithmic power detector 130 is used to generate a power indication signal Spd based on the detection signal S1. The logarithmic power detector 130 includes an input terminal and an output terminal. The input terminal is coupled to the detection terminal of the amplification unit 110, and the output terminal is used to output the power indication signal Spd. In one embodiment, the input terminal of the logarithmic power detector 130 may be coupled to a resistor, but this resistor may be omitted to improve the resolution in the low-power region. In one embodiment, the amplification device 100 further includes a matching circuit 150 (e.g., a matching inductor) coupled to the output terminal of the amplification unit 110.

[0057] Figure 2 This is a schematic diagram of the amplification device 200 in another embodiment. The amplification device 200 is similar to... Figure 1 The amplification device 100 is included, but the amplification device 200 further includes an impedance unit 120. The impedance unit 120 is used to provide a predetermined impedance, such as... Figure 2 As shown, the impedance unit 120 includes an input terminal and an output terminal, wherein the input terminal is coupled to the detection terminal of the amplifier unit 110 to receive the detection signal S1, and the output terminal is used to output the power signal Sd to the input terminal of the logarithmic power detector 130. Figure 2 In this process, the logarithmic power detector 130 can generate a power indication signal Spd based on the power signal Sd.

[0058] In one embodiment, the impedance value of the impedance unit 120 may be 5 to 7 times the impedance value of the amplification unit 110.

[0059] Figure 2 In this process, the impedance Z1 obtained from the input terminal of the impedance unit 120 can be higher than the impedance Z2 obtained from the input terminal of the logarithmic power detector 130.

[0060] According to one embodiment, the logarithmic power detector 130 may have a parallel structure or a cascade structure. The parallel and cascade structures will be described later.

[0061] In one embodiment, if the logarithmic power detector 130 has a cascaded structure, the impedance obtained from the amplification unit 110 into the logarithmic power detector 130 will not be too low, therefore... Figure 1 As shown, impedance unit 120 may not be required.

[0062] In one embodiment, if the logarithmic power detector 130 has a parallel structure, the impedance seen from the amplification unit 110 into the logarithmic power detector 130 may be too low, which will cause a loading effect. Therefore, an impedance unit 120 can be set as shown in Figure 2 to reduce the loading effect. According to another embodiment, if the logarithmic power detector 130 has a cascaded structure, the impedance unit 120 can still be set as shown in Figure 2 to adjust the impedance.

[0063] As shown in Figure 1 and Figure 2 , a matching circuit 150 (for example, a matching inductor) can be coupled to the output end of the amplification unit 110 to output an output signal SRFOUT related to the radio frequency signal SRFIN. The output signal SRFOUT can be processed and analyzed to obtain the information carried by the radio frequency signal SRFIN. As shown in Figure 1 and Figure 2 , a set of capacitors Ca can be set to block the DC part of the signal. The set of capacitors Ca can be coupled to the output end of the matching circuit 150. In one embodiment, the set of capacitors Ca includes a first capacitor Ca1 and a second capacitor Ca2. The first capacitor Ca1 can be coupled to the matching circuit 150 and includes a first end to receive the output signal SRFOUT. The second capacitor Ca2 includes a first end for receiving a reference voltage VREF0 and a second end coupled to the matching circuit 150. The reference voltage VREF0 can be the ground voltage. However, the present invention is not limited thereto.

[0064] The amplification unit 110 may further include n amplifiers connected in series, where n is an integer greater than 1. In the amplification unit 110, the output end of the i-th amplifier can be coupled to the input end of the (i + 1)-th amplifier, where i is an integer and 0 < i < n. In the amplification unit 110, the input end of the first amplifier is the input end of the amplification unit 110, and the output end of the n-th amplifier is the output end of the amplification unit 110. One of the input end and the output end of the n-th amplifier can be the detection end of the amplification unit 110. In one embodiment, in the amplification unit 110, the output end of the last-stage amplifier or the output end of the penultimate-stage amplifier can be the detection end of the amplification unit 110. However, the present invention is not limited thereto.

[0065] Figure 2In this embodiment, the detection terminal of the amplification unit 110 can be directly electrically connected to the input terminal of the impedance unit 120 via a conductive path. The conductive path can be at least one of a wire, a metal path, or a conductive trace. The impedance unit 120 may include a diode. The impedance unit 120 may include a phase shifter, for example, which may include a set of passive components and / or a set of attenuators to adjust the phase in a Smith chart, thereby adjusting the impedance. By using the impedance unit 120, the impedance seen through the impedance unit 120 can be increased and adjusted, thereby improving the linearity relative to the amplification unit 110.

[0066] Figure 3 This is a schematic diagram of the impedance unit 120 in the embodiment. Figure 3 As shown, the impedance unit 120 may include a phase shifter 322 and a diode 324 connected in series. The input terminal of the phase shifter 322 may be coupled to the input terminal of the impedance unit 120, the output terminal of the phase shifter 322 may be coupled to the input terminal of the diode 322, and the output terminal of the diode 324 may be coupled to the output terminal of the impedance unit 120.

[0067] Figure 4 This is a schematic diagram of the impedance unit 120 in another embodiment. (See diagram below.) Figure 4 As shown, the impedance unit 120 may include a diode 424 and a phase shifter 422 connected in series. The input terminal of the diode 124 may be coupled to the input terminal of the impedance unit 120, the input terminal of the phase shifter 422 may be coupled to the output terminal of the diode 424, and the output terminal of the phase shifter 422 may be coupled to the output terminal of the impedance unit 120.

[0068] Figure 5 This is a schematic diagram of the impedance unit 120 in another embodiment. (See diagram below.) Figure 5 As shown, the impedance unit 120 may include an amplifier 526 and a diode 524 connected in series, wherein the input terminal of the amplifier 526 may be coupled to the input terminal of the impedance unit 120, and the output terminal of the amplifier 526 may be coupled to the input terminal of the diode 524, and the output terminal of the diode 524 may be coupled to the output terminal of the impedance unit 120.

[0069] Figure 6 This is a schematic diagram of the impedance unit 120 in another embodiment. (See diagram below.) Figure 6 As shown, the impedance unit 120 may include a diode 624 and an amplifier 626 connected in series, wherein the input terminal of the diode 624 may be coupled to the input terminal of the impedance unit 120, the input terminal of the amplifier 626 may be coupled to the output terminal of the diode 624, and the output terminal of the amplifier 626 may be coupled to the output terminal of the impedance unit 120.

[0070] Figure 7This is a schematic diagram of the impedance unit 120 in another embodiment. (See diagram below.) Figure 7 As shown, impedance unit 120 may include amplifier 720, wherein the input terminal of amplifier 720 may be coupled to the input terminal of impedance unit 120, and the output terminal of amplifier 720 may be coupled to the output terminal of impedance unit 120. In one embodiment, amplifier 720 may be a unity-gain amplifier used to operate as a buffer. However, the invention is not limited thereto.

[0071] Figure 8 This is a schematic diagram of the impedance unit 120 in another embodiment. (See diagram below.) Figure 8 As shown, impedance unit 120 may include diode 824, and diode 824 may include transistor Q4 and transistor Q5. Transistor Q5 includes a first terminal, a second terminal, and a control terminal, wherein the control terminal is coupled to the first terminal of transistor Q5. Transistor Q4 includes a first terminal, a second terminal, and a control terminal, wherein the control terminal is coupled to the control terminal of transistor Q5 and the input terminal of diode 824.

[0072] The output terminal of diode 824 in impedance unit 120 can be coupled to either the first or second terminal of transistor Q4. Figure 8 In the example, the output of diode 824 is coupled to the second terminal of transistor Q4, and the parasitic diode PD4 between the control terminal and the second terminal of transistor Q4 provides both diode and rectifier functions. Conversely, if the output of diode 824 is coupled to the first terminal of transistor Q4, the parasitic diode between the first terminal and the control terminal of transistor Q4 provides diode functions. Each of transistors Q4 and Q5 can be a bipolar transistor or a metal-oxide-semiconductor field-effect transistor.

[0073] like Figure 8As shown, the diode 824 in impedance unit 120 may further include resistors R1, R5, R10, R9, and capacitor C2, each of which may include a first terminal and a second terminal. The first terminal of resistor R1 is used to receive a reference voltage VREF, and its second terminal is coupled to the first terminal of transistor Q5. The first terminal of resistor R5 is coupled to the second terminal of transistor Q5, and its second terminal is used to receive a reference voltage VREF2. The reference voltage VREF2 may be ground. The first terminal of resistor R10 may be coupled to the first terminal of resistor R1, and its second terminal may be coupled to the first terminal of transistor Q4. The first terminal of resistor R9 may be coupled to the second terminal of transistor Q4, and its second terminal may be coupled to the second terminal of resistor R5. The first terminal of capacitor C2 may be coupled to the input terminal of diode 824, and its second terminal may be coupled to the control terminal of transistor Q4. Diode 824 may optionally include a resistor R7, which includes a first terminal and a second terminal, wherein the first terminal is coupled to the input terminal of diode 824, and the second terminal is coupled to the first terminal of capacitor C2. Each of diodes 324, 424, 524, and 624 mentioned above may have… Figure 8 The structure of the diode 824 is shown, but the present invention is not limited thereto.

[0074] about Figure 8 The impedance unit 120 can perform temperature compensation, thereby stabilizing the power signal Sd when the temperature changes. For example, in Figure 8 In this context, voltages V4 and V5 (e.g., the base-emitter voltages of transistors Q4 and Q5) can be equal, expressed as V4 = V5. As temperature rises, voltages V4 and V5 will decrease. The current I5 flowing through the first terminal of transistor Q5 can be expressed as I5 = (VREF - V5 - VREF2) ÷ (R1 + R5), where reference voltages VREF and VREF2 can be constants. Since transistors Q5 and Q4 form a current mirror, the current I4 flowing through the first terminal of transistor Q4 can be expressed as I4 = I5. Here, the currents at the control terminals of transistors Q5 and Q4 can be neglected for simplicity. Figure 8 As shown, the voltage level at the second terminal of transistor Q4 can be the product of the current I4 and the resistance value of resistor R9, which can be expressed as I4 × R9. When the current I4 increases, the voltage difference across resistor R9 increases, and the voltage level of the power signal Sd also increases accordingly. When the temperature rises, the voltage level of the power signal Sd increases, which can compensate for the decrease in the voltage level of the power signal Sd. In other words, when the temperature changes, temperature compensation can be performed, thereby stabilizing the power signal Sd. Since the impedance unit 120 can perform temperature compensation to stabilize the power signal Sd, it can also stabilize accordingly (e.g., Figure 2 (As shown) Power indication signal Spd.

[0075] Figure 9The structure of the logarithmic power detector 130 is shown in the embodiment. Figure 9 The structure is a parallel structure, which includes at least a first attenuation circuit AT1, a first operating unit RA1, a second attenuation circuit AT2, and a second operating unit RA2. In one embodiment, it may further include a third attenuation circuit AT3 and a third operating unit RA3, but the present invention is not limited thereto.

[0076] Each of the first attenuation circuit AT1 and the second attenuation circuit AT2 may include a first terminal and a second terminal. Each of the first operating unit RA1 and the second operating unit RA2 may include a first terminal IN, a second terminal SS, a third terminal BB, and a fourth terminal GG.

[0077] The first attenuation circuit AT1 can be used to attenuate the power signal Sd within a first power range, and the first terminal of the first attenuation circuit AT1 can be coupled to the input terminal of the logarithmic power detector 130.

[0078] The first terminal IN of the first operating unit RA1 can be coupled to the second terminal of the first attenuation circuit AT1.

[0079] The second attenuation circuit AT2 can be used to attenuate the power signal Sd within the second power range, and the first terminal of the second attenuation circuit AT2 can be coupled to the input terminal of the logarithmic power detector 130.

[0080] The first terminal IN of the second operating unit RA2 can be coupled to the second terminal of the second attenuation circuit AT2.

[0081] Multiple paths can be coupled between two nodes to form a parallel structure. In one embodiment, such as... Figure 9 As shown, path P1, relating to the first attenuation circuit AT1 and the first operating unit RA1, can be coupled between node N9 and adder A9. Similarly, path P2, relating to the second attenuation circuit AT2 and the second operating unit RA2, can also be coupled between node N9 and adder A9. Therefore, from the perspective of node N9, paths P1 and P2 can form a parallel structure. However, the present invention is not limited thereto.

[0082] In addition to the first attenuation circuit AT1, the second attenuation circuit AT2, the first operating unit RA1, and the second operating unit RA2, the parallel structure of the logarithmic power detector 130 can be expanded to include more attenuation circuits and operating units. For example... Figure 9 As shown, the logarithmic power detector 130 may further include a third attenuation circuit AT3 and a third operating unit RA3 to form path P3. Viewed from node N9, path P3 can form a parallel structure with paths P1 and P2. In addition to the first attenuation circuit AT1 and the second attenuation circuit AT2 being used to attenuate the power signal Sd as described above, the third attenuation circuit AT3 can be used to attenuate the power signal Sd within a third power range.

[0083] The aforementioned first power range, second power range, and third power range can form a power range when the radio frequency signal SRFIN (e.g., Figure 1 and Figure 2 If the power of the signal (as shown) is within this power range, the power of the radio frequency signal SRFIN can be detected based on the power indication signal Spd generated by the logarithmic power detector 130.

[0084] For example, the first power range can be 5 to 15 dBm (decibel-milliwatts), the second power range can be 15 to 20 dBm, and the third power range can be 20 to 30 dBm. Therefore, the power range formed by the first, second, and third power ranges can be 5 to 30 dBm. In this example, when the power of the RF signal SRFIN is within 5 to 30 dBm, the power of the RF signal SRFIN can be detected based on the power indication signal Spd generated by the logarithmic power detector 130. Within this power range (5 to 30 dBm), the level of the power indication signal Spd and the power of the RF signal SRFIN can be positively correlated and linearly correlated, as can be described below. Figure 18 As shown.

[0085] like Figure 9 As shown, resistor R90 can be selectively set and coupled to logarithmic power detector 130 and node N9 to adjust the signal strength. Capacitor C91 can be coupled to node N9 and the first attenuation circuit AT1 to block the DC portion of the signal. Similarly, capacitor C92 can be coupled to node N9 and the second attenuation circuit AT2 to block the DC portion of the signal, and capacitor C93 can be coupled to node N9 and the third attenuation circuit AT3 to block the DC portion of the signal.

[0086] In one embodiment, each of the first attenuation circuit AT1, the second attenuation circuit AT2, and the third attenuation circuit AT3 may include a resistor, the first and second ends of which may be coupled to the first and second ends of the corresponding attenuation circuit, respectively. However, the present invention is not limited thereto.

[0087] like Figure 9 As shown, resistor R91 may include a first terminal and a second terminal, wherein the first terminal may receive a reference voltage VREF3, and the second terminal may be coupled to the third terminal BB of the first operating unit RA1. Resistor R91 may be a bias resistor used to generate and provide a bias voltage to the first operating unit RA1.

[0088] Similarly, resistor R92 may include a first terminal and a second terminal, wherein the first terminal may receive the reference voltage VREF3, and the second terminal may be coupled to the third terminal BB of the second operating unit RA2. Resistor R92 may be a bias resistor used to generate and provide a bias voltage to the second operating unit RA2. Similarly, resistor R93 may receive the reference voltage VREF3 to generate and provide a bias voltage to the third terminal BB of the third operating unit RA3.

[0089] like Figure 9 As shown, the fourth terminal GG of each of the first operation unit RA1, the second operation unit RA2 and the third operation unit RA3 can be used to receive the reference voltage VREF4, which may be, for example, the ground voltage.

[0090] The operating unit of the logarithmic power detector 130 (e.g., Figure 9 The operating units RA1, RA2 and RA3 can form a rectifier amplifier circuit to rectify and amplify signals.

[0091] like Figure 9 As shown, the logarithmic power detector 130 may further include an adder A9 and a current-to-voltage circuit CV9.

[0092] Adder A9 may include a first terminal, a second terminal, and a control terminal. The first terminal can receive a supply voltage (e.g., a reference voltage VREF3), the second terminal can output a result signal IT, and the control terminal can be coupled to the second terminal SS of the first operation unit RA1 and the second operation unit RA2. In one embodiment, the control terminal of adder A9 can be coupled to the second terminal SS of the first operation unit RA1, the second operation unit RA2, and the third operation unit RA3.

[0093] The current-to-voltage circuit CV9 can generate a power indication signal Spd based on the result signal IT. The current-to-voltage circuit CV9 may include a first terminal and a second terminal, wherein the first terminal may be coupled to the second terminal of the adder A9 and the output terminal of the logarithmic power detector 130, and the second terminal may receive a reference voltage (e.g., reference voltage VREF4). The result signal IT may be a current signal, and the power indication signal Spd may be a voltage signal.

[0094] like Figure 9 As shown, the logarithmic power detector 130 may further include a capacitor C9R, which includes a first terminal and a second terminal. The first terminal is coupled to the output of the logarithmic power detector 130, and the second terminal is capable of receiving a reference voltage (e.g., reference voltage VREF4). The capacitor C9R may be a rectifier component.

[0095] Figure 10 In the example, Figure 9 A partial schematic diagram of the logarithmic power detector 130. Figure 10Further details are provided for adder A9 and current-to-voltage circuit CV9. For example... Figure 10 As shown, adder A9 may include transistor Q102, which may include a first terminal, a second terminal, and a control terminal, respectively coupled to the first terminal, the second terminal, and the control terminal of adder A9. Current-to-voltage circuit CV9 may include resistor R104, which may include a first terminal and a second terminal, respectively coupled to the first terminal and the second terminal of current-to-voltage circuit CV9.

[0096] about Figure 9 and Figure 10 The logarithmic power detector 130 can be temperature compensated to stabilize the power indication signal Spd in response to temperature changes. The resulting signal IT (e.g., a current signal) and Figure 10 The relationship between the voltage V10 (e.g., the base-emitter voltage of transistor Q102) and the current-voltage (IV) characteristic of a diode can be approximated. Therefore, as the temperature rises, the voltage V10 can decrease, and the resulting signal IT can increase accordingly. Since the voltage level of the power indication signal Spd (e.g., a voltage signal) can be approximated by the product of the current value of the resulting signal IT and the resistance value of resistor R104, a larger resulting signal IT will result in a larger voltage across resistor R104. Therefore, the increase in the voltage level of the power indication signal Spd as the temperature rises can compensate for the decrease in the voltage level of the power indication signal Spd. In other words, temperature compensation can be performed when the temperature changes, thereby stabilizing the power indication signal Spd.

[0097] Figure 11 In another embodiment, the structure of the logarithmic power detector 130 is shown. Figure 11 The structure is a cascade structure, which includes at least a first operating unit RA111, a first attenuation circuit AT111, and a second operating unit RA112. For example... Figure 11 As shown, the cascaded structure of the logarithmic power detector 130 may further include more attenuation circuits and operating units, such as the second attenuation circuit AT112 and the third operating unit RA113. However, the present invention is not limited thereto.

[0098] like Figure 11 As shown, each of the first attenuation circuit AT111 and the second attenuation circuit AT112 may include a first terminal and a second terminal. Each of the first operation unit RA111, the second operation unit RA112 and the third operation unit RA113 may include a first terminal IN, a second terminal SS, a third terminal BB and a fourth terminal GG.

[0099] like Figure 11As shown, the first terminal IN of the first operating unit RA111 can be coupled to the input terminal of the logarithmic power detector 130. The first terminal of the first attenuation circuit AT111 can be coupled to the third terminal BB of the first operating unit RA111. The first terminal IN of the second operating unit RA112 can be coupled to the second terminal of the first attenuation unit AT111. The first terminal of the second attenuation unit AT112 can be coupled to the third terminal BB of the second operating unit RA112. The first terminal IN of the third operating unit RA113 can be coupled to the second terminal of the second attenuation unit AT112.

[0100] like Figure 11 As shown, the logarithmic power detector 130 may further include resistors R111, R112, R113, and R11A. Regarding resistor R111, its first terminal can receive a reference voltage VREF5, and its second terminal can be coupled to the third terminal BB of the first operating unit RA111. Regarding resistor R112, its first terminal can receive a reference voltage VREF5, and its second terminal can be coupled to the third terminal BB of the second operating unit RA112. Regarding resistor R113, its first terminal can receive a reference voltage VREF5, and its second terminal can be coupled to the third terminal BB of the third operating unit RA113. Resistors R111, R112, and R113 can be bias resistors, used to generate and provide bias voltages to the first operating unit RA111, the second operating unit RA112, and the third operating unit RA113, respectively.

[0101] like Figure 11 As shown, the logarithmic power detector 130 may further include capacitors C111 and C112. Regarding capacitor C111, its first terminal may be coupled to the third terminal BB of the first operating unit RA111, and its second terminal may be coupled to the first terminal of the first attenuation circuit AT111. Regarding capacitor C112, its first terminal may be coupled to the third terminal BB of the second operating unit RA112, and its second terminal may be coupled to the first terminal of the second attenuation circuit AT112.

[0102] In one embodiment, each of the first attenuation circuit AT111 and the second attenuation circuit AT112 may include a resistor, which may include a first terminal and a second terminal, respectively coupled to the first terminal and the second terminal of the corresponding attenuation circuit. However, the present invention is not limited thereto.

[0103] like Figure 11As shown, the logarithmic power detector 130 may further include a resistor R11A, an adder A11, and a current-to-voltage conversion circuit CV11. Resistor R11A may include a first terminal and a second terminal, wherein the first terminal can receive a reference voltage VREF5, and the second terminal can be coupled to the second terminal SS of the third operating unit RA113 and the control terminal of the adder A11. Resistor R11A may be a bias resistor used to generate and provide a bias voltage to the adder A11. Adder A11 may include a first terminal, a second terminal, and a control terminal, wherein the first terminal can receive a supply voltage (e.g., a reference voltage VREF5), the second terminal can output a result signal IT, and the control terminal can be coupled to the second terminal SS of the first operating unit RA111, the second operating unit RA112, and the third operating unit RA113. The current-to-voltage circuit CV11 generates a power indication signal Spd based on the result signal IT. The current-to-voltage circuit CV11 may include a first terminal and a second terminal, wherein the first terminal may be coupled to the second terminal of adder A11 and the output terminal of logarithmic power detector 130, and the second terminal may receive a reference voltage VREF6. For example, the reference voltage VREF6 may be ground voltage. The result signal IT may be a current signal, and the power indication signal Spd may be a voltage signal.

[0104] like Figure 11 As shown, the logarithmic power detector 130 may further include a capacitor C11R, which includes a first terminal and a second terminal. The first terminal may be coupled to the output of the logarithmic power detector 130, and the second terminal may receive a reference voltage (e.g., reference voltage VREF6). The capacitor C11R may be a rectifier component.

[0105] Figure 12 In the example, Figure 11 A partial schematic diagram of the logarithmic power detector 130. (See attached diagram.) Figure 12 As shown, adder A11 may include transistor Q122, which may include a first terminal, a second terminal, and a control terminal, respectively coupled to the first terminal, the second terminal, and the control terminal of adder A11. Current-to-voltage circuit CV11 may include resistor R124, which may include a first terminal and a second terminal, respectively coupled to the first terminal and the second terminal of current-to-voltage circuit CV11.

[0106] about Figure 11 and Figure 12 The logarithmic power detector 130 can be temperature compensated. The resulting signal IT (e.g., current signal) and Figure 12The relationship between the voltage V12 (e.g., the base-emitter voltage of transistor Q122) and the current-voltage (IV) characteristic of a diode can be approximated. Therefore, as the temperature rises, the voltage V12 can decrease, and the resulting signal IT can increase accordingly. Since the voltage level of the power indication signal Spd (e.g., a voltage signal) can be approximated by the product of the current value of the resulting signal IT and the resistance value of resistor R124, a larger resulting signal IT will result in a larger voltage across resistor R124. Therefore, as the temperature rises, the increase in the voltage level of the power indication signal Spd can compensate for the decrease in the voltage level of the power indication signal Spd. In other words, temperature compensation can be performed when the temperature changes, thereby stabilizing the power indication signal Spd.

[0107] about Figure 9 The first operating unit RA1, the second operating unit RA2, and the third operating unit RA3 and Figure 11 The first operation unit RA111, the second operation unit RA112, and the third operation unit RA113, wherein the circuit of each operation unit (hereinafter referred to as RA) can be as follows: Figure 13 As shown. Figure 13 This is a schematic diagram of the operation unit RA in the embodiment. The operation unit RA may include resistors R131, R132, and R133, transistors Q131 and Q132, and capacitor C13. Transistor Q131 may include a first terminal, a second terminal, and a control terminal, wherein the second terminal may be coupled to the fourth terminal GG of the operation unit RA. Regarding resistor R131, its first terminal may be coupled to the first terminal IN of the operation unit RA, and its second terminal may be coupled to the first terminal of transistor Q131. Regarding resistor R132, its first terminal may be coupled to the third terminal BB of the operation unit RA, and its second terminal may be coupled to the control terminal of transistor Q131. Transistor Q132 may include a first terminal, a second terminal, and a control terminal, wherein its first terminal may be coupled to the second terminal SS of the operation unit RA, and its second terminal may be coupled to the fourth terminal GG of the operation unit RA. Regarding resistor R133, its first terminal may be coupled to the third terminal BB of the operation unit RA, and its second terminal may be coupled to the control terminal of transistor Q132. Regarding capacitor C13, its first terminal can be coupled to the control terminal of transistor Q132, and its second terminal can be coupled to the second terminal of transistor Q132. For example... Figure 13 As shown, a parasitic diode PD131 can be formed between the first terminal and the control terminal of transistor Q131, and the parasitic diode PD131 can provide rectifier functionality. Transistor Q131 can be used to provide a bias voltage to transistor Q132, and transistor Q132 can operate as an amplifier. Therefore, the operating unit RA can be a rectifier-amplifier circuit.

[0108] Figure 14 , Figure 15 and Figure 16 In the example, with Figure 2 The waveform of the signal processed by the impedance unit 120. The impedance unit 120 can be a rectifier and filter circuit. Figure 14 This can be the waveform of a radio frequency signal. After half-wave rectification, Figure 14 The waveform can be as follows Figure 15 As shown. If the signal is further filtered, then we can obtain... Figure 16 The envelope waveform shown.

[0109] Figure 17 This is a schematic diagram of a curve indicating insufficient linearity in an embodiment. Figure 17 and Figure 2 As shown, Figure 17 The horizontal axis represents the power of the radio frequency signal SRFIN, and Figure 17 The vertical axis represents the voltage level of the power signal Sd generated by impedance unit 120. For example... Figure 17 As shown, the curve has a higher curvature in the power range of 5dBm to 30dBm, making it more difficult to measure the power of the RF signal SRFIN by measuring the voltage level of the power signal Sd. Furthermore, as mentioned earlier, due to the current mirror (e.g., within the impedance unit 120) Figure 8 (As shown) Temperature compensation can be performed, therefore Figure 17 The two curves for 25℃ and 85℃ are close to each other.

[0110] Figure 18 This is a schematic diagram of a curve with sufficient linearity in the embodiment. For example... Figure 18 and Figure 2 As shown, Figure 18 The horizontal axis represents the power of the radio frequency signal SRFIN, and Figure 18 The vertical axis represents the voltage level of the power indication signal Spd generated by the logarithmic power detector 130. For example... Figure 18 As shown, the curve has a lower curvature in the power range of 5dBm to 30dBm, making it easier to measure the power of the RF signal SRFIN by measuring the voltage level of the power indicator signal Spd.

[0111] In summary, the amplification devices 100 and 200 provided in the embodiments can reduce problems caused by insertion loss, load effect and insufficient linearity by having a smaller size. By measuring the power indication signal Spd generated by the logarithmic power detector 130, the signal power of the input amplification unit 110 can be measured better.

[0112] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made within the scope of the claims of the present invention should be included in the scope of the present invention.

Claims

1. An amplification device, characterized in that, It includes: An amplification unit includes an input terminal for receiving a radio frequency signal, an output terminal for outputting an amplified radio frequency signal, and a detection terminal for outputting a detection signal, wherein the detection signal is related to the radio frequency signal. An impedance unit for providing an impedance includes an input terminal coupled to the detection terminal of the amplification unit for receiving the detection signal, and an output terminal for outputting a power signal. The impedance unit further includes: a diode with an input terminal and an output terminal; and A logarithmic power detector for generating a power indication signal based on the power signal, the logarithmic power detector including an input terminal coupled to the output terminal of the impedance unit, and an output terminal for outputting the power indication signal; The logarithmic power detector has a parallel structure.

2. The amplification device as described in claim 1, characterized in that, The amplification unit further includes n amplifiers connected in series. An input terminal of a first amplifier of these amplifiers is the input terminal of the amplification unit, and an output terminal of an nth amplifier of these amplifiers is the output terminal of the amplification unit. One of the input terminal and the output terminal of the nth amplifier of these amplifiers is the detection terminal of the amplification unit, where n is an integer greater than 1.

3. The amplification device as described in claim 1, characterized in that, The impedance unit further includes: A phase shifter includes an input terminal coupled to the input terminal of the impedance unit and an output terminal coupled to the input terminal of the diode.

4. The amplification device as described in claim 1, characterized in that, The impedance unit further includes: A phase shifter includes an input terminal coupled to the output terminal of the diode and an output terminal coupled to the output terminal of the impedance unit.

5. The amplification device as described in claim 1, characterized in that, The impedance unit further includes: An amplifier includes an input terminal coupled to the input terminal of the impedance unit and an output terminal coupled to the input terminal of the diode.

6. The amplification device as described in claim 1, characterized in that, The impedance unit further includes: An amplifier includes an input terminal coupled to the output terminal of the diode, and an output terminal coupled to the output terminal of the impedance unit.

7. The amplification device as claimed in claim 1, characterized in that, The diode in the impedance unit further includes: A first transistor includes a first terminal, a second terminal, and a control terminal coupled to the first terminal of the first transistor; and A second transistor includes a first terminal, a second terminal, and a control terminal coupled to the control terminal of the first transistor and the input terminal of the diode.

8. The amplification device as described in claim 7, characterized in that, Each of the first transistor and the second transistor is a bipolar transistor or a metal-oxide-semiconductor field-effect transistor.

9. The amplification device as described in claim 7, characterized in that, The output terminal of the diode is coupled to either the first terminal or the second terminal of the second transistor.

10. The amplification device as claimed in claim 7, characterized in that, The diode in the impedance unit further includes: A first resistor includes a first terminal and a second terminal coupled to the first terminal of the first transistor; A second resistor includes a first terminal coupled to the second terminal of the first transistor, and a second terminal; A third resistor includes a first terminal coupled to the first terminal of the first resistor and a second terminal coupled to the first terminal of the second transistor; A fourth resistor, comprising a first terminal coupled to the second terminal of the second transistor, and a second terminal; and A first capacitor includes a first terminal coupled to the input terminal of the diode and a second terminal coupled to the control terminal of the second transistor.

11. The amplification device as claimed in claim 10, characterized in that, The diode in the impedance unit further includes: A fifth resistor includes a first terminal coupled to the input terminal of the diode and a second terminal coupled to the first terminal of the first capacitor.

12. The amplification device as claimed in claim 1, characterized in that, The impedance unit also includes a unity-gain amplifier.

13. The amplification device as claimed in claim 1, characterized in that, The impedance value of one impedance unit is 5 to 7 times that of one impedance unit.

14. The amplification device as claimed in claim 1, characterized in that, The logarithmic power detector further includes: A first attenuation circuit for attenuating the power signal within a first power range, the first attenuation circuit including a first terminal coupled to the input terminal of the logarithmic power detector, and a second terminal; A first operating unit includes a first terminal coupled to the second terminal of the first attenuation circuit, and a second terminal; A second attenuation circuit for attenuating the power signal within a second power range, the second attenuation circuit including a first terminal coupled to the input terminal of the logarithmic power detector, and a second terminal; and A second operating unit includes a first terminal coupled to the second terminal of the second attenuation circuit, and a second terminal; The parallel structure of the logarithmic power detector includes at least the first attenuation circuit, the first operating unit, the second attenuation circuit, and the second operating unit.

15. The amplification device as claimed in claim 14, characterized in that, The logarithmic power detector further includes: An adder includes a first terminal, a second terminal for outputting a result signal, and a control terminal coupled to the second terminal of the first operation unit and the second terminal of the second operation unit; and A current-to-voltage circuit for generating a power indication signal based on the result signal, the current-to-voltage circuit includes a first terminal coupled to the second terminal of the adder and the output terminal of the logarithmic power detector, and a second terminal; The result signal is a current signal, and the power indication signal is a voltage signal.

16. The amplification device as claimed in claim 15, characterized in that, in: The adder includes a transistor with a first terminal coupled to the first terminal of the adder, a second terminal coupled to the second terminal of the adder, and a control terminal coupled to the control terminal of the adder; and The current-to-voltage circuit includes a resistor, with a first terminal coupled to the first terminal of the current-to-voltage circuit and a second terminal coupled to the second terminal of the current-to-voltage circuit.

17. The amplification device as claimed in claim 1, characterized in that, The first impedance obtained from the input terminal of the impedance unit is higher than the second impedance obtained from the input terminal of the logarithmic power detector.

18. The amplification device as claimed in claim 1, characterized in that, The detection terminal of the amplification unit is directly electrically connected to the input terminal of the impedance unit through a conductive path.

19. An amplification device, characterized in that, It includes: An amplification unit includes an input terminal for receiving a radio frequency signal, an output terminal for outputting an amplified radio frequency signal, and a detection terminal for outputting a detection signal, wherein the detection signal is related to the radio frequency signal. An impedance unit for providing an impedance includes an input terminal coupled to the detection terminal of the amplification unit for receiving the detection signal, and an output terminal for outputting a power signal. The impedance unit further includes: a diode with an input terminal and an output terminal; and A logarithmic power detector for generating a power indication signal based on the power signal, the logarithmic power detector including an input terminal coupled to the output terminal of the impedance unit, and an output terminal for outputting the power indication signal; The logarithmic power detector has a cascaded structure.

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