Filter element and design method and manufacturing method therefor, electronic device

Abstract

The application discloses a filter element, a design method and a manufacturing method thereof, and an electronic device. The filter element comprises an upper wafer, a lower wafer and a substrate, wherein the lower wafer is provided with a metal ground plane below the lower wafer, and the metal ground plane is connected with a ground plane of the substrate; the lower wafer is provided with a plurality of resonator elements above the lower wafer, and the plurality of resonator elements constitute a plurality of parallel filters. The technical scheme of the application can reduce parasitic inductance, improve insertion loss and realize miniaturization.

Description

Technical Field

[0001] This invention relates to the field of filter technology, and in particular to a filter element, its design and manufacturing methods, and electronic equipment. Background Technology

[0002] In high-power filter components (such as base station filters), to improve power capacity, multiple bare dies (i.e., unpackaged semiconductor structures on which resonators and other devices are formed through semiconductor processing, also called dies) are typically connected in parallel. Then, a matching network is used to match the input and output impedances to a specific impedance. Multiple dies are generally distributed on a substrate and connected in parallel using bonding wires or bumps. In this technology, each die has a parasitic inductance to ground, which degrades the filter's out-of-band rejection. When multiple dies are distributed on the substrate, each die's input and output must be connected via specific wiring, significantly limiting the matching method. Therefore, resistance and matching losses increase, and insertion loss deteriorates. Furthermore, the packaging path for multiple dies is complex, and due to the spacing requirements, the overall chip size is larger, increasing both packaging and manufacturing costs. Summary of the Invention

[0003] In view of this, the present invention proposes a filter element with reduced parasitic inductance, improved insertion loss and miniaturization, as well as a design method and manufacturing method thereof, and an electronic device.

[0004] The first aspect of the present invention provides a filter element, including an upper wafer, a lower wafer, and a substrate, wherein a metal ground plane is provided below the lower wafer and the metal ground plane is connected to the ground plane of the substrate; a plurality of resonator elements are provided above the lower wafer, wherein the plurality of resonator elements constitute a plurality of parallel filters.

[0005] Optionally, the upper wafer has a ground pad, an input pad, and an output pad, the input terminals of the plurality of parallel filters are connected to the input pad, and the output terminals of the plurality of parallel filters are connected to the output pad.

[0006] Optionally, the ground pad, input pad, and output pad are connected to the substrate via multiple bonding leads.

[0007] Optionally, the number of the plurality of filters connected in parallel is 2 to 4.

[0008] A second aspect of the present invention provides a design method for a filter element, the filter element comprising an upper wafer, a lower wafer, and a substrate. The design method comprises: setting a metal ground plane below the lower wafer, the metal ground plane being connected to the ground plane of the substrate, and setting a plurality of resonator elements above the lower wafer, wherein the plurality of resonator elements constitute a plurality of parallel filters to reduce parasitic inductance, improve insertion loss, and achieve miniaturization.

[0009] Optionally, it further includes: providing a ground pad, an input pad, and an output pad above the upper wafer, with the input terminals of the plurality of parallel filters connected to the input pad and the output terminals of the plurality of parallel filters connected to the output pad.

[0010] Optionally, it further includes: providing a plurality of ground vias in parallel in the upper wafer and the lower wafer, wherein the ground inductor in the filter element is connected to the metal ground plane through the ground vias in the lower wafer, or connected to the ground pad through the ground vias in the upper wafer.

[0011] Optionally, the distance between the top surface of the upper wafer and the bottom surface of the lower wafer is 50 to 300 micrometers, or 80 to 200 micrometers.

[0012] Optionally, it further includes connecting the ground pad, input pad, and output pad to the substrate via multiple bonding leads.

[0013] Optionally, the number of the plurality of filters connected in parallel is 2 to 4.

[0014] A third aspect of the present invention provides a method for manufacturing a filter element, the filter element comprising an upper wafer, a lower wafer, and a substrate. The manufacturing method includes: forming a metal ground plane below the lower wafer and forming a plurality of resonator elements above the lower wafer, wherein the metal ground plane is connected to the ground plane of the substrate, and the plurality of resonator elements constitute a plurality of parallel filters; forming a ground pad, an input pad, and an output pad above the upper wafer, wherein the input terminals of the plurality of parallel filters are connected to the input pad, and the output terminals of the plurality of parallel filters are connected to the output pad; and connecting the ground pad, the input pad, and the output pad to the substrate via a plurality of bonding leads.

[0015] Optionally, the number of the plurality of filters connected in parallel is 2 to 4.

[0016] A fourth aspect of the present invention provides an electronic device comprising any of the filter elements proposed in the present invention.

[0017] According to the technical solution of the present invention, merging multiple dies in parallel circuits has at least the following advantages: (1) The parasitic inductance after merging is reduced, the parasitic inductance is improved, and the out-of-band rejection is also improved; (2) In the prior art, multiple discrete filters have inductors for input and output respectively, while the present invention connects the merged dies at the input and output ends through only one inductor. The matching method of the present invention reduces resistance loss and matching loss, and improves insertion loss; (3) After merging multiple dies, the packaging process can be simplified. There is no need to attach multiple dies to the substrate separately and then perform more bonding wire connections. This can reduce the dicing process, save dicing channel space, facilitate device miniaturization, improve chip utilization, and reduce production costs; (4) It avoids the use of multiple discrete non-uniform dies at different positions on the wafer (due to manufacturing non-uniformity, the performance of multiple dies is not completely consistent), thereby avoiding the non-uniformity of overall power distribution and transmission characteristics, and thus avoiding the deterioration of power capacity, transmission insertion loss, echo and other indicators. Attached Figure Description

[0018] For illustrative and not limiting purposes, the invention will now be described with reference to preferred embodiments thereof, particularly the accompanying drawings, in which:

[0019] Figure 1 This is a topology diagram of existing filter elements;

[0020] Figure 2 for Figure 1 Topology diagram of filter1;

[0021] Figure 3 This is a schematic diagram of a package for a filter element containing two dies in the prior art;

[0022] Figure 4 for Figure 3 A cross-sectional view at point AA';

[0023] Figure 5 This is a schematic diagram of the package of a filter element that combines two dies according to an embodiment of the present invention;

[0024] Figure 6 This is the topology of a filter element with two discrete dies in the prior art;

[0025] Figure 7 The topology of a filter element with two merged dies is shown in an embodiment of the present invention;

[0026] Figure 8 This is a comparison diagram of out-of-band suppression between filter elements in existing technologies and embodiments of the present invention;

[0027] Figure 9A comparison diagram of insertion loss of filter elements in prior art and embodiments of the present invention;

[0028] Figure 10 This is a schematic diagram of the package of a filter element that combines three dies according to an embodiment of the present invention;

[0029] Figure 11 This is a schematic diagram of the package of a filter element that combines four dies according to an embodiment of the present invention. Detailed Implementation

[0030] In this embodiment of the invention, multiple discrete dies in the prior art are combined to improve device performance and simplify the manufacturing process, as will be explained in detail below.

[0031] Figure 1 This refers to the topology of filter elements in the prior art. In the prior art, multiple dies, such as N dies, are connected in parallel, with one filter fabricated on each die. The filters are then matched to a specific impedance value (e.g., 50 ohms) through a matching network. All dies are connected through input and output inductors, where N is greater than or equal to 2.

[0032] Figure 2 for Figure 1 The topology diagram of filter 1 is shown. All ground-to-ground inductors L1 to L4 are connected to ground through a common-ground parasitic inductor L5, which may be on the die, on the substrate, or both. It should be noted that the number and connection method of resonators and ground-to-ground inductors within the filter element of this embodiment are not limited. Figure 2 The structure shown.

[0033] Figure 3 This is a schematic diagram of a package for a prior art filter element containing two dies.

[0034] In the diagram above, the two dies are connected to the input and output terminals of the substrate via input and output inductors, respectively. Their ground terminals are connected to the substrate's ground terminal via bonding wires. Due to the bonding wires, a certain spacing is required between the two dies. The relatively long inductor connections between the input and output terminals increase resistance losses and necessitate an additional matching network to eliminate the inductor's effect, thus introducing additional matching losses.

[0035] Figure 4 for Figure 3 A cross-sectional view at point AA'. As shown, multiple vias to ground are connected in parallel on both the upper and lower wafers to reduce ground inductance. Specifically, the ground inductance in the filter element can be connected to the metal ground plane via the vias on the lower wafer, or to the ground pad via the vias on the upper wafer.

[0036] The thickness of the die also affects the size of the equivalent inductance of the ground via. In the filter element of the present invention, the distance between the top surface of the upper wafer and the bottom surface of the lower wafer (i.e., the thickness of the die) can be 50 to 300 micrometers, or 80 to 200 micrometers.

[0037] Figure 5 This is a schematic diagram of the package of a filter element according to an embodiment of the present invention. As shown in the figure, by... Figure 3 The two dies are merged to ensure they are connected in parallel in the circuit topology, meaning the input and output terminals of the two dies are converged to two separate nodes. Then, through the setting and allocation of pads on the top of the upper wafer, the ground-to-ground area above the upper wafer is connected to form a ground pad, which is connected to the overall metal ground plane below the lower wafer. The input and output pads of the upper wafer are connected to the substrate's IN and OUT terminals respectively via multiple bonding leads. Figure 5 As can be seen, on the one hand, this embodiment combines multiple dies, avoiding the dicing process between multiple discrete dies and simplifying the manufacturing process; on the other hand, multiple separate dies require each die to be separately glued to the substrate and then connected by numerous bonding wires, while this embodiment only requires one die to be glued to the substrate, and the connection of the bonding wires is also simplified. In addition, the area occupied by multiple discrete dies is larger, compared to the single-die solution in this embodiment, which at least increases the spacing between the dies (generally at least 50µm wide) and the area for setting the intermediate bonding wires. Therefore, this embodiment can achieve a smaller chip size.

[0038] Figure 6 This is a topology for a two-die filter element in the prior art. The input and output inductors are also included in the figure above. Figure 7 This is the topology of a filter element with two merged dies according to an embodiment of the present invention. From... Figure 6 and Figure 7 It can be seen that, on the one hand, Figure 7 The parasitic inductance to ground L5 is connected in parallel, which halves the parasitic inductance to ground. On the other hand, the input-output matching method changes. Figure 7 It uses two dies directly connected and then matched through an input / output inductor. Figure 6 Each die is connected via an inductor and then converges to a single node.

[0039] Figure 8 This diagram compares the out-of-band rejection of filter elements in existing technologies and embodiments of the present invention. The solid line represents the combined die scheme of the present invention, while the dashed line represents the discrete die scheme of the prior art. It can be seen that reducing parasitic inductance significantly improves out-of-band rejection.

[0040] Figure 9 This diagram compares the insertion loss of filter elements in existing technologies and embodiments of the present invention. The solid line represents the merging die scheme of the present invention, while the dashed line represents the discrete die scheme of the prior art. It can be seen that when the matching method changes due to merging dies, the insertion loss is also improved.

[0041] In other embodiments of the present invention, the filter element that combines multiple dies may contain three, four or more filters connected in parallel, and the principle of the invention remains the same. Figure 10 This is a schematic diagram of the package of a filter element that combines three dies according to an embodiment of the present invention;

[0042] Figure 11 This is a schematic diagram of the package of a filter element that combines four dies according to an embodiment of the present invention. The dashed lines represent the boundaries between the multiple dies.

[0043] According to an embodiment of the present invention, a filter element is designed, comprising an upper wafer, a lower wafer, and a substrate. The design method may include: setting a metal ground plane below the lower wafer, the metal ground plane being connected to a ground plane on the substrate; and setting a plurality of resonator elements above the lower wafer, wherein the plurality of resonator elements constitute a plurality of parallel filters to reduce parasitic inductance, improve insertion loss, and achieve miniaturization. The number of parallel filters is 2 to 4.

[0044] Optionally, it also includes: providing a ground pad, an input pad, and an output pad above the upper wafer, with the input terminals of multiple parallel filters connected to the input pad and the output terminals of multiple parallel filters connected to the output pad.

[0045] Optionally, it also includes connecting the ground pad, input pad, and output pad to the substrate via multiple bonding leads.

[0046] According to an embodiment of the present invention, a method for manufacturing a filter element includes an upper wafer, a lower wafer, and a substrate. The method includes: forming a metal ground plane below the lower wafer and forming a plurality of resonator elements above the lower wafer, wherein the metal ground plane is connected to the ground plane of the substrate, and the plurality of resonator elements constitute a plurality of parallel filters; forming a ground pad, an input pad, and an output pad above the upper wafer, wherein the input terminals of the plurality of parallel filters are connected to the input pad, and the output terminals of the plurality of parallel filters are connected to the output pad; and connecting the ground pad, the input pad, and the output pad to the substrate via a plurality of bonding leads. The number of parallel filters is 2 to 4.

[0047] In the embodiments of the present invention, multiple dies are combined in parallel and the pads on the wafer are rearranged, which has at least the following advantages: (1) The parasitic inductance after merging is reduced, the parasitic inductance is improved, and the out-of-band rejection is also improved; (2) In the prior art, multiple discrete filters have inductors for input and output respectively, while the present invention connects the merged dies at the input and output ends with only one inductor. The matching method of the present invention reduces resistance loss and matching loss, and improves insertion loss; (3) After merging multiple dies, the packaging process can be simplified. There is no need to attach multiple dies to the substrate separately and then perform more bonding wire connections. This can reduce the dicing process, save dicing channel space, facilitate device miniaturization, improve chip utilization, and reduce production costs; (4) It avoids the use of multiple discrete non-uniform dies at different positions on the wafer (due to manufacturing non-uniformity, the performance of multiple dies is not completely consistent), thereby avoiding the non-uniformity of overall power distribution and transmission characteristics, and thus avoiding the deterioration of indicators such as power capacity, transmission insertion loss, and echo.

[0048] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can occur depending on design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A filter element, comprising an upper wafer, a lower wafer, and a substrate, characterized in that, The lower wafer has a metal ground plane below it, which is connected to the ground plane of the substrate; the upper wafer has a ground pad, an input pad, and an output pad above it; the input terminals of multiple parallel filters are connected to the input pad, and the output terminals of the multiple parallel filters are connected to the output pad; the ground pad, input pad, and output pad are connected to the substrate through multiple bonding leads; The lower wafer has multiple resonator elements above it, which constitute multiple parallel filters.

2. The filter element according to claim 1, characterized in that, The number of the multiple parallel filters is 2 to 4.

3. A method for designing a filter element, the filter element comprising an upper wafer, a lower wafer, and a substrate, characterized in that, include: A metal ground plane is provided below the lower wafer, the metal ground plane is connected to the ground plane of the substrate, and a plurality of resonator elements are provided above the lower wafer, wherein the plurality of resonator elements constitute a plurality of parallel filters to reduce parasitic inductance, improve insertion loss and achieve miniaturization. Furthermore, a ground pad, an input pad, and an output pad are provided above the upper wafer, the input terminals of the plurality of parallel filters are connected to the input pad, and the output terminals of the plurality of parallel filters are connected to the output pad.

4. The design method for filter elements according to claim 3, characterized in that, Also includes: Multiple ground vias are connected in parallel in the upper wafer and the lower wafer. The ground inductor in the filter element is connected to the metal ground plane through the ground via in the lower wafer, or to the ground pad through the ground via in the upper wafer.

5. The design method for filter elements according to claim 3, characterized in that, The distance between the top surface of the upper wafer and the bottom surface of the lower wafer is 50 to 300 micrometers, or 80 to 200 micrometers.

6. The design method of the filter element according to claim 4, characterized in that, Also includes: The ground pad, input pad, and output pad are connected to the substrate via multiple bonding leads.

7. The design method for filter elements according to claim 4, characterized in that, The number of the multiple parallel filters is 2 to 4.

8. An electronic device, characterized in that, Includes the filter element according to any one of claims 1 to 2.

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