Fractionally stepped frequency divider and frequency divider comprising a fractionally stepped frequency divider

Abstract

The present invention relates to a half-integer step divider and a frequency divider comprising the same. The half-integer step divider according to an aspect of the present invention comprises a logic processing unit configured to operate in response to rising and falling edges of a clock signal to generate an output signal, wherein a minimum step of the output signal is half of a period of the clock signal and an output level of the output signal is generated with a predetermined logic; and a data delay unit configured to receive the output signal and store the output signal triggered by a rising edge of the clock signal and feed back the output signal to the logic processing unit triggered by a falling edge of the clock signal.

Description

Technical Field

[0001] This invention relates to the field of communication technology, and more specifically to a half-integer step divider and a divider including the half-integer step divider. Background Technology

[0002] Frequency dividers are essential components in many wireless radio frequency communication chips for processing radio frequency clock signals, such as clock generators and frequency synthesizers. Based on the division type, frequency dividers can be divided into integer dividers and fractional dividers.

[0003] With the development of wireless communication systems, higher demands are placed on the frequency accuracy and frequency switching time of frequency synthesizers. To achieve shorter setup times, phase-locked loops (PLLs) require wide loop bandwidth. For integer frequency dividers, since their frequency resolution can only be an integer multiple of the reference signal frequency, a smaller input reference signal frequency is generally chosen to achieve the required frequency resolution. However, considering loop stability, the loop bandwidth needs to be less than one-tenth of the reference frequency. However, the smaller loop bandwidth of integer frequency dividers leads to increased frequency switching time. Furthermore, a smaller reference signal frequency results in a larger division ratio, thus amplifying the input noise of the phase and frequency detector.

[0004] For fractional frequency dividers, since their output frequency can be a fraction of the reference frequency, they can use a higher reference frequency and a larger loop bandwidth, thereby reducing the frequency switching time while taking into account requirements such as phase noise, frequency accuracy, and locking speed.

[0005] Therefore, it is desirable to provide an improved fractional frequency divider. Summary of the Invention

[0006] To address or at least alleviate one or more of the above problems, the following technical solutions are provided.

[0007] According to a first aspect of the invention, a half-integer step divider is provided, the half-integer step divider comprising: a logic processing unit configured to operate in response to a rising edge and a falling edge of a clock signal to generate an output signal, wherein the minimum step size of the output signal is half the period of the clock signal and the output level of the output signal is generated according to predetermined logic; and a data delay unit configured to receive the output signal, and to store the output signal triggered by a rising edge of the clock signal and to feed the output signal back to the logic processing unit triggered by a falling edge of the clock signal.

[0008] According to an embodiment of the present invention, a half-integer step divider is provided, wherein the predetermined logic includes: during the first half-cycle of the clock signal, the output level of the output signal is high; during the second half-cycle of the clock signal, the output level of the output signal is low; and during the third half-cycle of the clock signal, the output level of the output signal is low.

[0009] According to one embodiment or any of the above embodiments of the present invention, the half-integer step divider, wherein the logic processing unit includes: a first data selector, which includes a first transmission gate and a third transmission gate connected in series in a first branch, and a second transmission gate and a fourth transmission gate connected in series in a second branch connected in parallel with the first branch; and a NOR gate, the input of which is connected to the output of the first data selector and the output of the data delay unit, and the output of which is connected to the input of the first data selector.

[0010] According to one or more embodiments of the present invention, a half-integer step divider is provided, wherein the clock signal includes a first clock signal and a second clock signal that is inversely phase to the first clock signal, and the first data selector is configured to: be triggered by the rising edge of the first clock signal and the falling edge of the second clock signal to turn on the second transmission gate and the third transmission gate and turn off the first transmission gate and the fourth transmission gate, such that the second transmission gate buffers the signal output by the NOR gate and the third transmission gate outputs the buffered signal output by the NOR gate as an output signal; and be triggered by the rising edge of the second clock signal and the falling edge of the first clock signal to turn on the first transmission gate and the fourth transmission gate and turn off the second transmission gate and the third transmission gate, such that the first transmission gate buffers the signal output by the NOR gate and the fourth transmission gate outputs the buffered signal output by the NOR gate as an output signal.

[0011] According to one or more embodiments of the present invention, the half-integer step divider, wherein the data delay unit comprises: a second data selector, which includes a first transmission gate and a third transmission gate connected in series in the first branch, and a second transmission gate and a fourth transmission gate connected in series in the second branch connected in parallel with the first branch; a first NAND gate, whose input is connected to the output of the logic processing unit and a mode control signal, and whose output is connected to the input of the second data selector; and a second NAND gate, whose input is connected to the output of the second data selector and an enable signal, and whose output is connected to the logic processing unit.

[0012] According to one embodiment or any of the above embodiments of the present invention, the half-integer step divider, wherein the clock signal includes a first clock signal and a second clock signal that is inversely phase to the first clock signal, and the second data selector is configured to: be triggered by the rising edge of the first clock signal and the falling edge of the second clock signal to turn on the second transmission gate and the third transmission gate and turn off the first transmission gate and the fourth transmission gate, such that the second transmission gate buffers the signal output of the first NAND gate and the third transmission gate inputs the buffered signal output of the first NAND gate into the second NAND gate; and be triggered by the rising edge of the second clock signal and the falling edge of the first clock signal to turn on the first transmission gate and the fourth transmission gate and turn off the second transmission gate and the third transmission gate, such that the first transmission gate buffers the signal output of the first NAND gate and the fourth transmission gate inputs the buffered signal output of the first NAND gate into the second NAND gate.

[0013] According to one embodiment or any of the above embodiments of the present invention, the half-integer step divider is configured to: when the mode control signal is at a low level, control the data delay unit to be turned on so that the half-integer step divider operates as a DIV1.5 divider; and when the mode control signal is at a high level, control the data delay unit to be turned off so that the half-integer step divider operates as a DIV1 divider.

[0014] According to one embodiment or any of the above embodiments of the present invention, the half-integer step divider is configured such that: when the enable signal is high, the data delay unit is turned on, causing the half-integer step divider to operate as a DIV1.5 divider; and when the enable signal is low, the data delay unit is turned off, causing the half-integer step divider to operate as a DIV1 divider.

[0015] According to one embodiment or any of the above embodiments of the present invention, the half-integer step divider, wherein the logic processing unit includes: a DIV2 divider configured to divide the clock signal by two to generate a divided signal with a frequency of 1 / 2 of the frequency of the clock signal; and a third data selector including a first path having a first NAND gate and a first transmission gate and a second path having a second NAND gate and a second transmission gate, wherein the inputs of the first NAND gate and the second NAND gate are connected to the divided signal generated by the DIV2 divider, the output of the first NAND gate is connected to the first transmission gate, and the output of the second NAND gate is connected to the second transmission gate.

[0016] According to an embodiment of the present invention or any of the above embodiments, the half-integer step divider, wherein the clock signal includes a first clock signal and a second clock signal that is inverted relative to the first clock signal, the DIV2 divider is further configured to divide the first clock signal and the second clock signal by two respectively to generate a first divided signal, a second divided signal, a third divided signal, and a fourth divided signal in the following manner: such that the first divided signal and the second divided signal are inverted; such that the third divided signal and the fourth divided signal are inverted; such that the phase difference between the first divided signal and the fourth divided signal is half a cycle of the clock signal; and such that the phase difference between the second divided signal and the third divided signal is half a cycle of the clock signal.

[0017] According to one embodiment or any of the above embodiments of the present invention, the input terminal of the first NAND gate is connected to the first frequency division signal and the fourth frequency division signal, and the input terminal of the second NAND gate is connected to the second frequency division signal and the third frequency division signal.

[0018] According to one embodiment or any of the above embodiments of the present invention, the third data selector is configured to: be triggered by the rising edge of the first clock signal and the falling edge of the second clock signal to turn on the second path and turn off the first path, so that the second NAND gate generates an output signal based on the second divided signal and the third divided signal; and be triggered by the rising edge of the second clock signal and the falling edge of the first clock signal to turn on the first path and turn off the second path, so that the first NAND gate generates an output signal based on the first divided signal and the fourth divided signal.

[0019] According to a second aspect of the present invention, a frequency divider is provided, the frequency divider comprising the half-integer step frequency divider according to the first aspect of the present invention.

[0020] According to an embodiment of the present invention, the frequency divider wherein the half-integer step-size frequency divider is cascaded as a first stage with the one or more integer frequency dividers.

[0021] The half-integer step divider according to one or more embodiments of the present invention has a simple and easy-to-implement structure, low cost, low transmission delay and low power consumption, and can be applied to various high-speed and low-power application scenarios. Attached Figure Description

[0022] The above and / or other aspects and advantages of the present invention will become clearer and more readily understood from the following description taken in conjunction with the accompanying drawings, in which the same or similar elements are denoted by the same reference numerals. In the drawings: Figure 1 A half-integer step divider according to one or more embodiments of the present invention is shown.

[0023] Figure 2 A transmission gate according to an embodiment of the present invention is shown.

[0024] Figure 3 A half-integer step divider according to one or more embodiments of the present invention is shown.

[0025] Figure 4 A half-integer step divider according to one or more embodiments of the present invention is shown.

[0026] Figure 5 A signal timing diagram of a half-integer step divider according to one or more embodiments of the present invention is shown.

[0027] Figure 6 A signal timing diagram of a half-integer step divider according to one or more embodiments of the present invention is shown.

[0028] Figure 7 A frequency divider according to one or more embodiments of the present invention is shown. Detailed Implementation

[0029] The following detailed description is merely exemplary in nature and is not intended to limit the disclosed technology or its application and use. Furthermore, it is not intended to be bound by any express or implied theory presented in the foregoing technical fields, background art, or the following detailed description.

[0030] In the following detailed description of the embodiments, numerous specific details are set forth in order to provide a more thorough understanding of the disclosed technology. However, it will be apparent to those skilled in the art that the disclosed technology can be practiced without these specific details. In other instances, well-known features have not been described in detail to avoid unnecessarily complicating the description.

[0031] Terms such as "comprising" and "including" indicate that, in addition to the units and steps that are directly and explicitly stated in the specification, the technical solution of the present invention does not exclude the presence of other units and steps that are not directly or explicitly stated. Terms such as "first" and "second" do not indicate the order of the units in terms of time, space, size, etc., but are merely used to distinguish the units.

[0032] In the following, various exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0033] Figure 1 A half-integer step divider according to one or more embodiments of the present invention is shown.

[0034] like Figure 1 As shown, the half-integer step divider 100 includes a logic processing unit 110 and a data delay unit 120. The logic processing unit 110 can be configured to operate in response to the rising and falling edges of a clock signal to generate an output signal, wherein the minimum step size of the output signal is half the period of the clock signal and the output level of the output signal is generated according to predetermined logic. The data delay unit 120 can be configured to receive the output signal from the logic processing unit 110, and to store the output signal triggered by the rising edge of the clock signal and to feed the output signal back to the logic processing unit 110 triggered by the falling edge of the clock signal.

[0035] Optionally, the predetermined logic may include: during the first half-cycle of the clock signal, the output level of the output signal is high; during the second half-cycle of the clock signal, the output level of the output signal is low; and during the third half-cycle of the clock signal, the output level of the output signal is low. As an example, when the clock signal is a square wave signal with a duty cycle of 1 / 2 and a period of T, the output signal generated by the logic processing unit 110 according to the predetermined logic is a square wave signal with a duty cycle of 1 / 3 and a period of 1.5T, which is a frequency divider signal.

[0036] Optionally, the logic processing unit 110 and the data delay unit 120 can be implemented using a combination of multiple transmission gates and logic gates. The following uses... Figure 2 To describe the structure and function of a single transmission gate.

[0037] Figure 2 A transmission gate according to an embodiment of the invention is shown. For example... Figure 2 As shown, CKP and CKN represent the input clock signals, where CKN = ~CKP, meaning CKP and CKN have the same amplitude but opposite phases, i.e., a phase difference of 180 degrees. D represents the input signal, and OUT represents the output signal. When CKN = 1 and CKP = 0, OUT = ~D; and when CKN = 0 and CKP = 1, OUT is in a high-impedance state, i.e., an open-circuit state. It can be understood that when CKN = 1 and CKP = 0, the transmission gate operates as an inverter; and when CKN = 0 and CKP = 1, the transmission gate is in an open-circuit state. For example, CKP and CKN can be square wave signals with the same amplitude but opposite phases. Figure 3 A half-integer step divider according to one or more embodiments of the present invention is shown.

[0038] like Figure 3 As shown, the half-integer step divider 300 includes a logic processing unit 310 and a data delay unit 320.

[0039] The logic processing unit 310 may include a first data selector 3101 and an NOR gate 3102. The first data selector 3101 includes a first transmission gate D1 and a third transmission gate D3 connected in series in the first branch, and a second transmission gate D2 and a fourth transmission gate D4 connected in series in the second branch connected in parallel with the first branch. The input terminal of the NOR gate 3102 is connected to the output terminal OUT of the first data selector 3101 and the output terminal MOD_F of the data delay unit 320. The output terminal NOR of the NOR gate 3102 is connected to the input terminal of the first data selector 3101.

[0040] like Figure 3 As shown, CIP and CIN represent the input clock signals to the respective transmission gates D1, D2, D3, and D4, where CIP = ~CIN, meaning CIP and CIN have the same amplitude but opposite phases, i.e., a phase difference of 180 degrees. VDDR and AVSS represent power supply and ground, respectively. In the following description, CIP is used as the first clock signal and CIN as the second clock signal.

[0041] Further as Figure 3 As shown, the first data selector 3101 can be configured to: be triggered by the rising edge of the first clock signal CIP and the falling edge of the second clock signal CIN to turn on the second transmission gate D2 and the third transmission gate D3 and turn off the first transmission gate D1 and the fourth transmission gate D4, so that the second transmission gate D2 buffers the signal NOR output by the NOR gate 3102 and the third transmission gate D3 outputs the buffered signal Q1 output by the NOR gate 3102 as the output signal OUT; and be triggered by the rising edge of the second clock signal CIN and the falling edge of the first clock signal CIP to turn on the first transmission gate D1 and the fourth transmission gate D4 and turn off the second transmission gate D2 and the third transmission gate D3, so that the first transmission gate D1 buffers the signal NOR output by the NOR gate 3102 and the fourth transmission gate D4 outputs the buffered signal Q2 output by the NOR gate 3102 as the output signal OUT. Understandably, the first data selector 3101 can split the NOR signal output by the NOR gate 3102 into two parts, which are then output as the output signal OUT via the first transmission gate D1 and the third transmission gate D3 connected in series in the first branch, and the second transmission gate D2 and the fourth transmission gate D4 connected in parallel with the first branch. The first branch acquires data on the falling edge of the first clock signal CIP and transmits data on the rising edge of the first clock signal CIP, while the second branch acquires data on the rising edge of the first clock signal CIP and transmits data on the falling edge of the first clock signal CIP. Therefore, the first data selector 3101 can reduce the minimum step size of the output signal OUT to half of the first clock signal CIP and / or the second clock signal CIN.

[0042] The data delay unit 320 may include a second data selector 3201, a first NAND gate 3202, and a second NAND gate 3203. The second data selector 3201 includes a first transmission gate D1 and a third transmission gate D3 connected in series in the first branch, and a second transmission gate D2 and a fourth transmission gate D4 connected in series in parallel with the first branch in the second branch. The input of the first NAND gate 3202 is connected to the output OUT of the logic processing unit 310 and the mode control signal MOQB. The output MOQ_IN of the first NAND gate 3202 is connected to the input of the second data selector 3201. The input of the second NAND gate 3203 is connected to the output MOQ_M of the second data selector 3201 and the enable signal CL. The output MOD_F of the second NAND gate 3203 is connected to the logic processing unit 310.

[0043] Further as Figure 3 As shown, the second data selector 3201 can be configured to: be triggered by the rising edge of the first clock signal CIP and the falling edge of the second clock signal CIN to turn on the second transmission gate D2 and the third transmission gate D3 and turn off the first transmission gate D1 and the fourth transmission gate D4, so that the second transmission gate D2 buffers the signal MOQ_IN output by the first NAND gate 3202 and the third transmission gate D3 inputs the buffered signal MOQ1 output by the first NAND gate to the second NAND gate 3203; and be triggered by the rising edge of the second clock signal CIN and the falling edge of the first clock signal CIP to turn on the first transmission gate D1 and the fourth transmission gate D4 and turn off the second transmission gate D2 and the third transmission gate D3, so that the first transmission gate D1 buffers the signal MOQ_IN output by the first NAND gate 3202 and the fourth transmission gate D4 inputs the buffered signal MOQ2 output by the first NAND gate 3202 to the second NAND gate 3203.

[0044] As the input signal to the first NAND gate 3202, the mode control signal MOQB can be configured such that: when the mode control signal MOQB is low, the control data delay unit 320 is turned on, causing the half-integer step divider 300 to operate as a DIV1.5 divider; and when the mode control signal MOQB is high, the control data delay unit 320 is turned off, causing the half-integer step divider 300 to operate as a DIV1 divider. It can be understood that when the mode control signal MOQB is high, the signal input to the first NAND gate 3202 through the NOT gate is low, causing the data delay unit 320 to be in an open-circuit state, thereby causing the first data selector 3101 in the half-integer step divider 300 to be in a working state, thus the half-integer step divider 300 operates as a DIV1 divider.

[0045] As the input signal to the second NAND gate 3203, the enable signal CL can be configured such that: when the enable signal CL is high, the data delay unit 320 is turned on, causing the half-integer step divider 300 to operate as a DIV1.5 divider; and when the enable signal CL is low, the data delay unit 320 is turned off, causing the half-integer step divider 300 to operate as a DIV1 divider. It can be understood that when the enable signal CL is low, the data delay unit 320 is in an open-circuit state, causing the first data selector 3101 in the half-integer step divider 300 to be active, thus the half-integer step divider 300 operates as a DIV1 divider.

[0046] like Figure 3 As shown, the logical relationship between the output signal (OUT) and the input signals (NOR, MOD_F) of the logic processing unit 310 is a NOR gate relationship, and its truth table is shown in Table 1 below. In Table 1, 1UI represents the first cycle of the first clock signal CIP and / or the second clock signal CIN, 2UI represents the second cycle of the first clock signal CIP and / or the second clock signal CIN, 3UI represents the third cycle of the first clock signal CIP and / or the second clock signal CIN, and so on. Rise represents the rising edge of the clock cycle and Fall represents the falling edge of the clock cycle.

[0047] Table 1. Logical relationship between output signal (OUT) and input signals (NOR, MOD_F) Table 1: Figure 4 A half-integer step divider according to one or more embodiments of the present invention is shown.

[0048] like Figure 4 As shown, the half-integer step divider 400 includes a logic processing unit 410 and a data delay unit 420.

[0049] The logic processing unit 410 may include a DIV2 divider 4101 and a third data selector 4102. The DIV2 divider 4101 can be configured to process pairs of clock signals ( Figure 4The clock signals CKN and CKP shown are divided by two to generate frequency-divided signals Q1, Q1B, Q2, and Q2B with frequencies equal to half the frequency of the clock signals. The third data selector 4102 may include a first path having a first NAND gate 4102A and a first transmission gate 4102B, and a second path having a second NAND gate 4102D and a second transmission gate 4102C. The inputs of the first NAND gate 4102A and the second NAND gate 4102D are connected to the frequency-divided signals Q1, Q2B and Q1B, Q2 generated by the DIV2 frequency divider 4101. The output of the first NAND gate 4102A is connected to the first transmission gate 4102B, and the output of the second NAND gate 4102D is connected to the second transmission gate 4102C. It should be noted that the first transmission gate 4102B and the second transmission gate 4102C of the third data selector 4102 can be connected by means of... Figure 2 This is achieved using a single transmission gate.

[0050] like Figure 4 As shown, the DIV2 divider 4101 can be further configured to divide the first clock signal CKN and the second clock signal CKP by two respectively to generate a first divided signal Q1, a second divided signal Q1B, a third divided signal Q2, and a fourth divided signal Q2B in the following manner: the first divided signal Q1 and the second divided signal Q1B are out of phase; the third divided signal Q2 and the fourth divided signal Q2B are out of phase; the phase difference between the first divided signal Q1 and the fourth divided signal Q2B is half a cycle of the clock signal (i.e., the first clock signal CKN and / or the second clock signal CKP); and the phase difference between the second divided signal Q1B and the third divided signal Q2 is half a cycle of the clock signal (i.e., the first clock signal CKN and / or the second clock signal CKP). The input of the first NAND gate 4102A is connected to the first frequency divider signal Q1 and the fourth frequency divider signal Q2B, and the input of the second NAND gate 4102D is connected to the second frequency divider signal Q1B and the third frequency divider signal Q2. The first clock signal CKN and the second clock signal CKP represent the input clock signals of the DIV2 frequency divider 4101, respectively, where CKN = ~CKP, that is, CKP and CKN have the same amplitude but opposite phase, i.e., a phase difference of 180 degrees. For example, CKP and CKN can be square wave signals with the same amplitude and opposite phase.

[0051] The third data selector 4102 can be configured to: be triggered by the rising edge of the first clock signal CKP and the falling edge of the second clock signal CKN to turn on the second path and turn off the first path, so that the second NAND gate 4102D generates the output signal CKO based on the second frequency divider signal Q1B and the third frequency divider signal Q2; and be triggered by the rising edge of the second clock signal CKN and the falling edge of the first clock signal CKP to turn on the first path and turn off the second path, so that the first NAND gate 4102A generates the output signal CKO based on the first frequency divider signal Q1 and the fourth frequency divider signal Q2B. It is understandable that the third data selector 4102 can be implemented as an inverter with switching function. It is triggered by the rising edge of the first clock signal CKP and the falling edge of the second clock signal CKN to open the second path with the second NAND gate 4102D and the second transmission gate 4102C, so that the second frequency divider signal Q1B and the third frequency divider signal Q2 generate the output signal CKO through the second NAND gate 4102D; and is triggered by the rising edge of the second clock signal CKN and the falling edge of the first clock signal CKP to open the first path with the first NAND gate 4102A and the first transmission gate 4102B, so that the first frequency divider signal Q1 and the fourth frequency divider signal Q2B generate the output signal CKO through the first NAND gate 4102A.

[0052] like Figure 4 As shown, in the data delay unit 420, CIP and CIN represent the input clock signals to each transmission gate D1, D2, D3, and D4, respectively, where CIP = ~CIN, meaning that CIP and CIN have the same amplitude but opposite phase, i.e., a phase difference of 180 degrees. VDDR and AVSS represent power supply and ground, respectively. It can be understood that the data delay unit 420 and... Figure 3 The data delay unit 320 described herein has a similar function and structure. Further, as... Figure 4 As shown, the output signal CKO of the third data selector 4102 serves as the input of the data delay unit 420, and the output signals of the data delay unit 420 are clock signals CKN and CKP, which can be used as the input signals of the DIV2 divider 4101.

[0053] The data delay unit 420 may include a fourth data selector 4201, a third NAND gate 4202, and a fourth NAND gate 4203. The fourth data selector 4201 includes a first transmission gate D1 and a third transmission gate D3 connected in series in the first branch, and a second transmission gate D2 and a fourth transmission gate D4 connected in series in parallel with the first branch in the second branch. The input of the third NAND gate 4202 is connected to the output of the logic processing unit 410, CKO, and the mode control signal MOQB. The output of the third NAND gate 4202, MOQ_IN, is connected to the input of the fourth data selector 4201. The input of the fourth NAND gate 4203 is connected to the output of the fourth data selector 4201 and the enable signal CL. The output of the fourth NAND gate 4203, CKN, is connected to the DIV2 divider 4101 as the input signal of the DIV2 divider 4101.

[0054] As the input signal of the third NAND gate 4202, the mode control signal MOQB can be configured such that: when the mode control signal MOQB is low, the control data delay unit 420 is turned on, causing the half-integer step divider 400 to operate as a DIV1.5 divider; and when the mode control signal MOQB is high, the control data delay unit 420 is turned off, causing the half-integer step divider 400 to operate as a DIV1 divider.

[0055] As the input signal of the fourth NAND gate 4203, the enable signal CL can be configured such that: when the enable signal CL is at a high level, the data delay unit 420 is turned on, causing the half-integer step divider 400 to operate as a DIV1.5 divider; and when the enable signal CL is at a low level, the data delay unit 420 is turned off, causing the half-integer step divider 400 to operate as a DIV1 divider.

[0056] The half-integer step divider according to one or more embodiments of the present invention has a simple and easy-to-implement structure, low cost, low transmission delay and low power consumption, and can be applied to various high-speed and low-power application scenarios.

[0057] Figure 5 A signal timing diagram of a half-integer step divider according to one or more embodiments of the present invention is shown.

[0058] Figure 5 As shown Figure 3 The following are logic simulation results of a half-integer step divider 300 according to one or more embodiments of the present invention. Figure 5 In the text, CIP and CIN respectively represent input to... Figure 3The input clock signals of each transmission gate D1, D2, D3, and D4 in the diagram are shown, where CIP = ~CIN, meaning that CIP and CIN have the same amplitude but opposite phases, i.e., a phase difference of 180 degrees. OUT1 represents the output signal generated when the mode control signal MOQB is low, and the half-integer step divider 300 operates as a DIV1.5 divider. OUT2 represents the output signal generated when the mode control signal MOQB is high, and the half-integer step divider 300 operates as a DIV1 divider.

[0059] Figure 6 A signal timing diagram of a half-integer step divider according to one or more embodiments of the present invention is shown.

[0060] Figure 6 As shown Figure 4 The following are logic simulation results of a half-integer step divider 400 according to one or more embodiments of the present invention. Figure 6 In Chinese, CIP indicates input to... Figure 4 The input clock signals of each transmission gate D1, D2, D3, and D4 in the data delay unit 420, Q1, Q1B, Q2, and Q2B respectively represent Figure 4 The DIV2 frequency divider 4101 in the middle is used for clock signals ( Figure 4 The clock signals CKN and CKP shown are divided by two to generate a frequency that is half the frequency of the clock signal. CKO represents the output signal generated when the mode control signal MOQB is low, and the half-integer step divider 400 operates as a DIV1.5 divider. Figure 6 As shown, the first frequency divider signal Q1 and the second frequency divider signal Q1B are out of phase, the third frequency divider signal Q2 and the fourth frequency divider signal Q2B are out of phase, the phase difference between the first frequency divider signal Q1 and the fourth frequency divider signal Q2B is half a cycle of the clock signal, and the phase difference between the second frequency divider signal Q1B and the third frequency divider signal Q2 is half a cycle of the clock signal.

[0061] Additionally, as described above, the present invention can also be implemented as a frequency divider comprising a half-integer step divider according to one aspect of the invention and one or more integer frequency dividers.

[0062] Figure 7 A frequency divider according to one or more embodiments of the present invention is shown.

[0063] like Figure 7 As shown, the frequency divider 700 includes a half-integer step divider 710 and an integer frequency divider 720 according to one aspect of the present invention. It should be noted that the half-integer step divider 710 can be combined with... Figure 3 and Figure 4The half-integer step divider 300 and half-integer step divider 400 are described as implementations. Although Figure 7 Only one integer frequency divider 720 is shown, but frequency divider 700 can include two or more integer frequency dividers, wherein a half-integer step-size frequency divider 710 can be cascaded as the first stage with one or more integer frequency dividers. By cascading the half-integer step-size frequency divider 710 as the first stage with one or more integer frequency dividers, various integer or half-integer step-size frequency dividers such as DIV1, DIV1.5, DIV2, DIV2.5, DIV3, and DIV3.5 can be obtained. This fills the gaps in the application scenarios of traditional integer and fractional frequency division, resulting in a wider frequency range for the input signal and meeting low power consumption requirements, making it applicable to various high-speed, low-power applications.

[0064] The embodiments and examples presented herein are provided to best illustrate embodiments of the invention and its particular applications, thereby enabling those skilled in the art to practice and use the invention. However, those skilled in the art will understand that the above description and examples are provided merely for ease of illustration and example. The descriptions presented are not intended to cover all aspects of the invention or to limit the invention to the precise forms disclosed.

Claims

1. A half-integer step-size frequency divider, characterized in that, The half-integer step-size frequency divider includes: A logic processing unit configured to operate in response to the rising and falling edges of a clock signal to generate an output signal, wherein the output level of the output signal is high during a first half-cycle of the clock signal, low during a second half-cycle of the clock signal, and low during a third half-cycle of the clock signal; and A data delay unit is configured to receive the output signal, store the output signal triggered by the rising edge of the clock signal, and feed the output signal back to the logic processing unit triggered by the falling edge of the clock signal. The logic processing unit includes: A first data selector includes a first transmission gate and a third transmission gate connected in series in a first branch, and a second transmission gate and a fourth transmission gate connected in series in parallel with the first branch in a second branch; and A NOR gate, whose input is connected to the output of the first data selector and the output of the data delay unit, and whose output is connected to the input of the first data selector. The clock signal includes a first clock signal and a second clock signal that is inverted by the first clock signal. Both the first clock signal and the second clock signal are input as input clock signals to the logic processing unit and the data delay unit. The first data selector is configured to: When the rising edge of the first clock signal and the falling edge of the second clock signal occur simultaneously, the second transmission gate and the third transmission gate are turned on, and the first transmission gate and the fourth transmission gate are turned off, so that the second transmission gate buffers the signal output by the NOR gate and the third transmission gate outputs the buffered signal output by the NOR gate as its output signal; and When the rising edge of the second clock signal and the falling edge of the first clock signal occur simultaneously, the first transmission gate and the fourth transmission gate are turned on and the second transmission gate and the third transmission gate are turned off, so that the first transmission gate buffers the signal output by the NOR gate and the fourth transmission gate outputs the buffered signal output by the NOR gate as an output signal.

2. The half-integer step divider according to claim 1, wherein the data delay unit comprises: The second data selector includes a first transmission gate and a third transmission gate connected in series in the first branch, and a second transmission gate and a fourth transmission gate connected in series in the second branch connected in parallel with the first branch. The first NAND gate has its input connected to the output of the logic processing unit and the mode control signal, and its output connected to the input of the second data selector. as well as The second NAND gate has its input connected to the output and enable signal of the second data selector, and its output connected to the logic processing unit.

3. The half-integer step divider according to claim 2, wherein the clock signal includes a first clock signal and a second clock signal that is inverted by the first clock signal, and the second data selector is configured to: When the rising edge of the first clock signal and the falling edge of the second clock signal occur simultaneously, the second transmission gate and the third transmission gate are turned on, and the first transmission gate and the fourth transmission gate are turned off, so that the second transmission gate buffers the signal output from the first NAND gate and the third transmission gate inputs the buffered signal output from the first NAND gate into the second NAND gate; and When the rising edge of the second clock signal and the falling edge of the first clock signal occur simultaneously, the first transmission gate and the fourth transmission gate are turned on and the second transmission gate and the third transmission gate are turned off, so that the first transmission gate buffers the signal output by the first NAND gate and the fourth transmission gate inputs the buffered signal output by the first NAND gate into the second NAND gate.

4. The half-integer step divider according to claim 2, wherein the mode control signal is configured to: When the mode control signal is low, the data delay unit is turned on, causing the half-integer step divider to operate as a DIV1.5 divider; and When the mode control signal is high, the data delay unit is disconnected, causing the half-integer step divider to operate as a DIV1 divider.

5. The half-integer step divider according to claim 2, wherein the enable signal is configured to: When the enable signal is high, the data delay unit is turned on, causing the half-integer step divider to operate as a DIV1.5 divider; and When the enable signal is low, the data delay unit is disconnected, causing the half-integer step divider to operate as a DIV1 divider.

6. A frequency divider, characterized in that, The frequency divider includes: The half-integer step divider according to any one of claims 1-5; and One or more integer frequency dividers.

7. The frequency divider according to claim 6, wherein the half-integer step divider is cascaded as a first stage with the one or more integer frequency dividers.

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