A continuous-time sigma-delta modulator structure

Abstract

This invention relates to the field of integrated circuit technology, specifically to a continuous-time sigma-delta modulator structure. It includes an integrator unit, an ADC unit, a decoding unit, and a low-pass filter current-steering DAC array unit. The output of the integrator unit is electrically connected to the input of the ADC unit, the output of the ADC unit is electrically connected to the input of the decoding unit, the output of the decoding unit is electrically connected to the input of the low-pass filter current-steering DAC array unit, and the output of the low-pass filter current-steering DAC array unit is electrically connected to the input of the integrator unit. The integrator unit is used to integrate and filter quantization noise of the input signal, the ADC unit is used to quantize the input signal, the decoding unit is used to decode the input signal, and the low-pass filter current-steering DAC array unit is used to perform level conversion and filtering of the input signal. This method improves modulator performance without increasing the complexity of modulator circuit design.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and specifically to a continuous-time sigma-delta modulator structure. Background Technology

[0002] Continuous-time sigma-delta modulators not only perform analog-to-digital conversion but also filtering; that is, they automatically filter the signal while performing data conversion. Due to their unique characteristics, this type of modulator is widely used in the design of fully integrated receiver chips. Since the filtering effect of this type of modulator is achieved through the combined action of the feedback loop DAC and integrator circuit, the performance of the DAC and integrator circuit in the feedback loop affects the overall performance of the modulator.

[0003] In a modulator, the function of a feedback DAC is to recover the quantized signal and complete the conversion from digital signal to analog signal. However, in communication receiver applications, the clock frequency is often very high, reaching several gigahertz, and the impact of clock jitter is very significant. Since the input of the DAC is a digital signal with the same frequency as the clock, the impact of clock jitter on the DAC performance is particularly obvious.

[0004] In existing modulators, two common methods to suppress clock jitter are increasing the number of bits in the quantizer or using an FIR-DAC. The core principle of these two methods is to increase the number of bits in the DAC, reduce the level of clock jitter, thereby reducing the energy of clock jitter within a certain time, and thus reducing the impact of clock jitter on the DAC output waveform. However, increasing the number of bits in the DAC will indirectly increase the design difficulty of the pre-stage quantizer. Summary of the Invention

[0005] The technical problem solved by this invention is to provide a continuous-time sigma-delta modulator structure that can improve modulator performance without increasing the difficulty of modulator circuit design.

[0006] The basic solution provided by this invention is a continuous-time sigma-delta modulator structure, including an integrator unit, an ADC unit, a decoding unit, and a low-pass filter current-steering DAC array unit. The output terminal of the integrator unit is electrically connected to the input terminal of the ADC unit, the output terminal of the ADC unit is electrically connected to the input terminal of the decoding unit, the output terminal of the decoding unit is electrically connected to the input terminal of the low-pass filter current-steering DAC array unit, and the output terminal of the low-pass filter current-steering DAC array unit is electrically connected to the input terminal of the integrator unit.

[0007] The integrator unit is used to integrate and filter the quantization noise of the input signal, the ADC unit is used to quantize the input signal, the decoding unit is used to decode the input signal, and the low-pass filter current-controlled DAC array unit is used to perform level conversion and filtering of the input signal.

[0008] The principle and advantages of this invention are as follows: The quantization noise of the input signal is integrated and filtered by an integrator unit. The output of the integrator unit serves as the input of an ADC unit, which quantizes the integrated input signal. The output of the ADC unit serves as the input of a decoding unit, which performs a base conversion on the input signal. A base-1 output codeword is generated at the output port of the decoding unit. This output codeword serves as the input signal of a low-pass filter current-steering DAC array unit, connected to the corresponding port. A digital-to-analog conversion is performed by the DAC. The low-pass filter current-steering DAC array unit performs level conversion and filtering on the input codeword, thereby optimizing the digital codeword and effectively suppressing clock jitter in the digital codeword, reducing clock jitter energy. The analog signal corresponding to the codeword in the low-pass filter current-steering DAC array unit and the input signal of the integrator unit produce a residual, i.e., quantization noise. Since clock jitter has been reduced, the generated quantization noise is cleaner, thus improving the overall performance of the modulator.

[0009] Furthermore, the integration unit includes a resistor R, a capacitor C, and an operational amplifier OPA. One end of the resistor R is electrically connected to the input signal, and the other end of the resistor R is electrically connected to the input terminal of the operational amplifier OPA. One end of the capacitor C is electrically connected to the input terminal of the operational amplifier OPA, and the other end of the capacitor C is electrically connected to the output terminal of the operational amplifier OPA.

[0010] An active RC integrator is constructed using a resistor R, a capacitor C, and an operational amplifier OPA.

[0011] Furthermore, the low-pass filter current-controlled DAC array unit includes several groups of DAC sub-units and a total current source, wherein the total current source is electrically connected to each group of DAC sub-units.

[0012] Furthermore, the decoding unit is a 3-8 decoder, and the low-pass filter current rudder array unit includes 8 DAC sub-units.

[0013] The 3-to-8 decoder has 8 output pins, with one set of DAC subunits corresponding to the output port of one decoder unit.

[0014] Furthermore, the DAC subunit includes transistors M0, M1, M2, M3, and M4, resistors R1 and R2, and capacitors C1 and C2;

[0015] The drain of M0 is connected to the source of M1 and M2 respectively. The drains of M1 and M2 are connected to the output nodes Vn and Vp respectively. The output nodes Vn and Vp are connected to the two input terminals of the operational amplifier OPA respectively.

[0016] The drain of M0 is also connected to the source of M3 and M4 respectively. The drain of M3 is connected to resistor R1 and capacitor C1 respectively, and the drain of M4 is connected to resistor R2 and capacitor C2 respectively.

[0017] A low-pass filter unit based on CML is constructed from M3, M4, R1, R2, C1, and C2 to perform level conversion and filtering of the input codeword, thereby reducing clock jitter energy. The analog signal corresponding to the codeword is output from nodes Vn and Vp. Nodes Vn and Vp are connected to the two input terminals of the operational amplifier OPA, generating a residual with the input signal to complete the subsequent integration.

[0018] Furthermore, M1 and M2 are high-threshold MOS transistors.

[0019] To avoid incorrect switching of transistors M1 and M2 when they are turned on at low levels, high threshold MOSFETs are selected for M1 and M2.

[0020] Furthermore, the total current source includes transistors M5 and M6, with the drains of M5 and M6 connected to the drains of M1 and M2, respectively.

[0021] Furthermore, the ADC unit is a 3-bit Sub-ADC. Attached Figure Description

[0022] Figure 1 This is a logic block diagram of an embodiment of a continuous sigma-delta modulator structure according to the present invention;

[0023] Figure 2 This is a schematic diagram of the low-pass filter current-rudder DAC array unit in an embodiment of a continuous sigma-delta modulator structure according to the present invention.

[0024] Figure 3 The output waveforms of the traditional current-rudder DAC array unit and the low-pass filter current-rudder DAC array unit are shown in the embodiment of a continuous sigma-delta modulator structure of the present invention. Detailed Implementation

[0025] The following detailed description illustrates the specific implementation method:

[0026] The basic implementation examples are as follows: Figure 1 As shown:

[0027] A continuous-time sigma-delta modulator structure includes an integrator unit, an ADC unit, a decoding unit, and a low-pass filter current-steering DAC array unit. The output terminal of the integrator unit is electrically connected to the input terminal of the ADC unit, the output terminal of the ADC unit is electrically connected to the input terminal of the decoding unit, and the output terminal of the low-pass filter current-steering DAC array unit is electrically connected to the input terminal of the integrator unit.

[0028] The integrator unit is used to filter the quantization noise of the input signal vin. Specifically, the integrator unit includes a resistor R, a capacitor C, and an operational amplifier OPA. One end of the resistor R is electrically connected to the input signal vin, and the other end of the resistor R is electrically connected to the input terminal of the operational amplifier. One end of the capacitor C is electrically connected to the input terminal of the operational amplifier OPA, and the other end of the capacitor C is electrically connected to the output terminal of the operational amplifier OPA, forming an active RC integrator.

[0029] The output of the integrator unit serves as the input of the ADC unit. In this embodiment, the ADC unit is specifically a 3-bit sub-ADC. The sub-ADC quantizes the output signal of the integrator unit in 3-bit form. Since the quantized codeword is in binary form, a decoding unit performs a binary conversion. Therefore, the output of the sub-ADC serves as the input signal of the decoding unit and is connected to the input port of the decoding unit. In this embodiment, the decoding unit is preferably a 3-8 thermometer decoder.

[0030] The decoder generates binary codewords D0-D7 at the output port, and D0-D7 are connected to the corresponding ports as input signals of the low-pass filtered current-controlled DAC array unit.

[0031] like Figure 2 As shown, the low-pass filter current-controlled DAC array unit includes several groups of DAC sub-units and a total current source. The total current source is connected to each DAC sub-unit. In this embodiment, there are 8 groups of DAC sub-units, and each of the digital codewords D0-D7 is connected to a group of DAC sub-units.

[0032] The DAC sub-unit includes transistors M0, M1, M2, M3, and M4, resistors R1 and R2, and capacitors C1 and C2. The drain of M0 is connected to the sources of M1 and M2, respectively. The drains of M1 and M2 are connected to output nodes Vn and Vp, respectively. Output nodes Vn and Vp are connected to the two input terminals of operational amplifier OPA. The drain of M0 is also connected to the sources of M3 and M4, respectively. The drain of M3 is connected to resistor R1 and capacitor C1, respectively, and the drain of M4 is connected to resistor R2 and capacitor C2, respectively. Vbias1 provides a bias voltage for M0. The total current source of the DAC array includes transistors M5 and M6. The drain of M5 is connected to the drain of M1 in each DAC unit, and the drain of M6 is connected to the drain of M2 in each DAC unit. Vbias2 provides a bias voltage for M5 and M6.

[0033] A low-pass filter unit based on the CML circuit is constructed from transistors M3 and M4, resistors R1 and R2, and capacitors C1 and C2. This unit performs level conversion and filtering on the input codewords D0-D7 of the DAC subunit, where D0_B to D7_B represent the inverse code of D0-D7. In 65nm CMOS technology, by properly setting the value of R1, the low-level output of CML can be maintained at 550mV. Therefore, to prevent M1 and M2 from conducting at low levels, high-threshold transistors are required for M1 and M2. By performing level conversion and filtering on the input codewords D0-D7 within the DAC subunit, the digital codewords are optimized. This process effectively suppresses clock jitter in the input codewords D0-D7, significantly reducing the energy of clock jitter.

[0034] Vn and Vp are the output nodes of the DAC subunit, and they are connected to the two input terminals of the operational amplifier (OPA). It is worth noting that the architecture described in this embodiment is a single-ended structure. In actual circuit design, a fully differential structure is typically used. In a fully differential structure, the DAC's output nodes Vn and Vp need to be connected to the two output terminals of the operational amplifier (OPA).

[0035] Simulation platforms for a traditional DAC array and the low-pass filter current-controlled DAC array of this application were built using a 65nm CMOS process. Simulations were performed on both DAC arrays with an input signal of 1.5MHz. Specific simulation results are shown below. Figure 3 As shown, the simulation results show that the output waveform of the DAC array in this application is significantly better than that of the traditional DAC array, which can effectively improve the performance of the modulator.

[0036] The above are merely embodiments of the present invention. Commonly known structures and characteristics are not described in detail here. Those skilled in the art are aware of all common technical knowledge in the field prior to the application date or priority date, are aware of all existing technologies in that field, and have the ability to apply conventional experimental methods prior to that date. Those skilled in the art can, under the guidance of this application, improve and implement this solution in combination with their own capabilities. Some typical known structures or methods should not be obstacles for those skilled in the art to implement this application. It should be noted that those skilled in the art can make several modifications and improvements without departing from the structure of the present invention. These should also be considered within the scope of protection of the present invention, and will not affect the effectiveness of the implementation of the present invention or the practicality of the patent. The scope of protection claimed in this application should be determined by the content of its claims, and the specific embodiments described in the specification can be used to interpret the content of the claims.

Claims

1. A continuous-time sigma-delta modulator structure, characterized in that: It includes an integrator unit, an ADC unit, a decoding unit, and a low-pass filter current-rudder DAC array unit. The output terminal of the integrator unit is electrically connected to the input terminal of the ADC unit, the output terminal of the ADC unit is electrically connected to the input terminal of the decoding unit, the output terminal of the decoding unit is electrically connected to the input terminal of the low-pass filter current-rudder DAC array unit, and the output terminal of the low-pass filter current-rudder DAC array unit is electrically connected to the input terminal of the integrator unit. The integration unit is used to integrate and filter the quantization noise of the input signal, the ADC unit is used to quantize the input signal, the decoding unit is used to decode the input signal, and the low-pass filter current-controlled DAC array unit is used to perform level conversion and filtering of the input signal. The low-pass filter current-controlled DAC array unit includes several groups of DAC sub-units and a total current source, wherein the total current source is electrically connected to each group of DAC sub-units. The decoding unit is a 3-8 decoder, and the low-pass filter current-controlled DAC array unit includes 8 groups of DAC sub-units; The DAC subunit includes transistors M0, M1, M2, M3, M4, resistors R1 and R2, and capacitors C1 and C2; The drain of M0 is connected to the source of M1 and M2 respectively. The drains of M1 and M2 are connected to the output nodes Vn and Vp respectively. The output nodes Vn and Vp are connected to the two input terminals of the operational amplifier OPA respectively. The drain of M0 is also connected to the source of M3 and M4 respectively. The drain of M3 is connected to resistor R1, capacitor C1 and gate of M1 respectively. The drain of M4 is connected to resistor R2, capacitor C2 and gate of M2 respectively. The other end of resistor R1 is connected to the power supply, the other end of capacitor C1 is grounded, the other end of resistor R2 is connected to the power supply, and the other end of capacitor C2 is grounded.

2. The continuous-time sigma-delta modulator structure according to claim 1, characterized in that: The integration unit includes a resistor R, a capacitor C, and an operational amplifier OPA. One end of the resistor R is electrically connected to the input signal, and the other end of the resistor R is electrically connected to the input terminal of the operational amplifier OPA. One end of the capacitor C is electrically connected to the input terminal of the operational amplifier OPA, and the other end of the capacitor C is electrically connected to the output terminal of the operational amplifier OPA.

3. The continuous-time sigma-delta modulator structure according to claim 1, characterized in that: M1 and M2 are high threshold MOS transistors.

4. The continuous-time sigma-delta modulator structure according to claim 1, characterized in that: The total current source includes transistors M5 and M6, with the drain of M5 connected to the drain of M1 and the drain of M6 connected to the drain of M2.

5. A continuous-time sigma-delta modulator structure according to claim 1, characterized in that: The ADC unit is a 3-bit Sub-ADC.

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