Communication method, secure chip, terminal device, and storage medium

Abstract

The application discloses a communication method, a security chip, a terminal device and a storage medium thereof. The communication method is used for the security chip, the security chip comprises a plurality of interfaces, the plurality of interfaces are connected with a master chip, each interface of the plurality of interfaces is configured with a corresponding chip selection signal, and the communication method comprises the following steps: based on a falling edge of a target chip selection signal, starting an interrupt processing to receive a starting identifier; in the case that the starting identifier comprises a command flag, receiving an instruction content sent by the master chip; based on a rising edge of the target chip selection signal, backing up the starting identifier in a memory and exiting the interrupt processing; executing the instruction content to obtain a processing result, and sending the processing result to a target interface. The application realizes the business distribution by jumping different instructions through different interfaces of the security chip, avoids affecting the business logic of the master chip, realizes the multiple business processing of a single security chip, and reduces the cost of the terminal device.

Description

Technical Field

[0001] This application relates to the field of communication technology, and in particular to a communication method, a security chip, a terminal device, and a storage medium. Background Technology

[0002] The intelligent converged terminal is an edge device in the "cloud-edge-device" architecture of the smart IoT system. It has information collection, IoT agent and edge computing functions to support marketing, power distribution and emerging businesses.

[0003] Currently, smart converged terminals use different security chips to handle marketing and power distribution services separately. However, with each security chip handling only one service, this inevitably leads to hardware waste. Summary of the Invention

[0004] This application aims to address at least one of the technical problems existing in the prior art. To this end, this application provides a communication method, a security chip, a terminal device, and a non-volatile computer-readable storage medium.

[0005] The communication method provided in this application is used for a security chip, the security chip including multiple interfaces, the security chip being connected to a main control chip through the multiple interfaces, each of the multiple interfaces being configured with a corresponding chip select signal, the communication method including:

[0006] Based on the falling edge of the target chip select signal, interrupt processing is initiated to receive the start flag;

[0007] If the starting identifier includes a command flag, the instruction content sent by the main control chip is received;

[0008] Based on the rising edge of the target chip select signal, the start identifier is backed up in memory and the interrupt processing is exited;

[0009] Execute the instructions to obtain the processing result;

[0010] Send the processing result to the target interface.

[0011] In some embodiments, the communication method further includes:

[0012] If the start identifier does not include the command flag, in response to the start identifier stored in the memory, the processing result is sent to the main control chip through the target interface.

[0013] In some implementations, when the start identifier does not include the command flag, sending the processing result to the main control chip via the target interface in response to the start identifier stored in the memory includes:

[0014] Restore the backed-up start identifier to the target random access register of the target interface;

[0015] Control the target interface to enable transmit / receive to exit interrupt handling;

[0016] The processing result is sent to the main control chip through the target interface according to the starting identifier.

[0017] In some implementations, controlling the target interface to perform transmit / receive enable and exit interrupt handling includes:

[0018] Control the target interface to perform transmit / receive enable to set the receive response flag and the target interface sequence number;

[0019] Enable the target chip select signal pull-down interrupt to exit interrupt processing.

[0020] In some implementations, sending the processing result to the main control chip via the target interface according to the starting identifier includes:

[0021] Query the status of the target chip select signal;

[0022] When the target chip select signal is a falling edge, the target interface initiates target direct memory access;

[0023] The processing result is sent to the main control chip according to the serial number of the target interface and the received response flag.

[0024] In some embodiments, the communication method further includes:

[0025] Based on the rising edge of the target chip select signal, disable the target direct memory access and set the data output pin of the target interface to general purpose input / output mode;

[0026] Enable transmit / receive on the target interface to clear the response flag;

[0027] Enable the pull-down interrupt for the target chip select signal.

[0028] In some implementations, the step of initiating interrupt processing to receive the start identifier based on the falling edge of the target chip select signal includes:

[0029] An interrupt is initiated after the duration of the falling edge of the target chip select signal exceeds a preset time.

[0030] Set the data output pin of the target interface to clock transmission mode to receive the start identifier through the target interface.

[0031] In some implementations, receiving the instruction content sent by the main control chip when the starting identifier includes a command flag includes:

[0032] Initiate target direct memory access of the target interface to receive the instruction content.

[0033] In some implementations, backing up the start identifier to memory and exiting interrupt processing based on the rising edge of the target chip select signal includes:

[0034] When the target chip select signal is on a rising edge, target direct memory access of the target interface is disabled and the data output pin of the target interface is set to general purpose input / output mode;

[0035] The starting identifier is backed up in the memory;

[0036] Control the target interface to set the command to complete receiving the flag and the sequence number of the target interface;

[0037] Enable the pull-down interrupt for the target chip select signal to exit interrupt handling.

[0038] In some implementations, executing the instruction content to obtain the processing result includes:

[0039] Clear the command reception completion flag;

[0040] The instruction content is parsed to obtain the command;

[0041] The command is processed to obtain the processing result.

[0042] In some implementations, the interface includes a first interface and a second interface, wherein the first interface is configured with a first chip select signal and the second interface is configured with a second chip select signal;

[0043] When the first chip select signal is a falling edge, the second chip select signal is a rising edge; or

[0044] When the second chip select signal is a falling edge, the first chip select signal is a rising edge.

[0045] The security chip provided in this application includes multiple interfaces and a processor. The security chip is connected to a main control chip through the multiple interfaces. Each of the multiple interfaces is configured with a corresponding chip select signal. The communication method includes:

[0046] Based on the falling edge of the target chip select signal, interrupt processing is initiated to receive the start flag;

[0047] If the starting identifier includes a command flag, the instruction content sent by the main control chip is received;

[0048] Based on the rising edge of the target chip select signal, the start identifier is backed up in memory and the interrupt processing is exited;

[0049] Execute the instructions to obtain the processing result;

[0050] Send the processing result to the target interface.

[0051] In some embodiments, the processor is further configured to:

[0052] If the start identifier does not include the command flag, in response to the start identifier stored in the memory, the processing result is sent to the main control chip through the target interface.

[0053] In some implementations, the processor is used to:

[0054] Restore the backed-up start identifier to the target random access register of the target interface;

[0055] Control the target interface to enable transmit / receive to exit interrupt handling;

[0056] The processing result is sent to the main control chip through the target interface according to the starting identifier.

[0057] In some implementations, the processor is used to:

[0058] Control the target interface to perform transmit / receive enable to set the receive response flag and the target interface sequence number;

[0059] Enable the pull-down interrupt for the target chip select signal to exit interrupt handling.

[0060] In some implementations, the processor is used to:

[0061] Query the status of the target chip select signal;

[0062] When the target chip select signal is a falling edge, the target interface initiates target direct memory access;

[0063] The processing result is sent to the main control chip according to the serial number of the target interface and the received response flag.

[0064] In some embodiments, the processor is further configured to:

[0065] Based on the rising edge of the target chip select signal, disable the target direct memory access and set the data output pin of the target interface to general purpose input / output mode;

[0066] Enable transmit / receive on the target interface to clear the response flag;

[0067] Enable the pull-down interrupt for the target chip select signal.

[0068] In some implementations, the processor is used to:

[0069] An interrupt is initiated after the duration of the falling edge of the target chip select signal exceeds a preset time.

[0070] Set the data output pin of the target interface to clock transmission mode to receive the start identifier through the target interface.

[0071] In some implementations, the processor is used to:

[0072] Initiate target direct memory access of the target interface to receive the instruction content.

[0073] In some implementations, the processor is used to:

[0074] When the target chip select signal is on a rising edge, target direct memory access of the target interface is disabled and the data output pin of the target interface is set to general purpose input / output mode;

[0075] The starting identifier is backed up in the memory;

[0076] Control the target interface to set the command to complete receiving the flag and the sequence number of the target interface;

[0077] Enable the pull-down interrupt for the target chip select signal to exit interrupt handling.

[0078] In some implementations, the processor is used to:

[0079] Clear the command reception completion flag;

[0080] The instruction content is parsed to obtain the command;

[0081] The command is processed to obtain the processing result.

[0082] In some implementations, the plurality of interfaces include a first interface and a second interface, wherein the first interface is configured with a first chip select signal and the second interface is configured with a second chip select signal;

[0083] When the first chip select signal is a falling edge, the second chip select signal is a rising edge; or

[0084] When the second chip select signal is a falling edge, the first chip select signal is a rising edge.

[0085] The terminal device provided in this application includes a security chip and a main control chip. The security chip includes multiple interfaces, which are connected to the main control chip. The main control chip is used to set the state of the target chip select signal of the target interface of the multiple interfaces to a falling edge and send instruction data to the security chip. The instruction data includes an initial identifier and instruction content.

[0086] The security chip is used to receive and determine whether the initial identifier includes a command flag when the target chip select signal is in a falling edge state; if the initial identifier includes a command flag, it receives and executes the instruction content to obtain a processing result; and if the initial identifier does not include a command flag, it sends the processing result to the main control chip through the target interface.

[0087] The non-volatile computer-readable storage medium provided in this application includes a computer program that, when processed by a processor, causes the processor to execute any of the communication methods described herein.

[0088] In the terminal device, security chip, communication method, and communication method of this application, the security chip initiates an interrupt processing flow when the target chip select signal falls, thereby receiving a start identifier and determining whether the start identifier includes a command flag. If the start identifier includes a command flag, the instruction content is determined to be a command, and the instruction content sent by the main control chip is received. After receiving the instruction content, the start identifier is backed up in memory after the target chip select signal rises, thereby exiting the interrupt processing. Then, the command content is executed to obtain the processing result of the command, and the processing result is sent to the target interface. Thus, when the start identifier of the main control chip does not include the command flag, the processing result can be sent to the main control chip. Therefore, the terminal device only needs to set up one security chip to handle multiple business functions, reducing the hardware cost of the terminal device, reducing the hardware circuit board area, and improving the business processing capability of the security chip. This allows the main control chip to continue sending other business instructions or handling its own non-security tasks through other interfaces while the security chip is processing business instructions.

[0089] Additional aspects and advantages of this application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this application. Attached Figure Description

[0090] The above and / or additional aspects and advantages of this application will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, wherein:

[0091] Figure 1 This is a schematic diagram of a terminal device in related technologies.

[0092] Figure 2 This is a timing diagram of the chip select signal according to an embodiment of this application.

[0093] Figure 3 This is a timing diagram of the chip select signal according to an embodiment of this application.

[0094] Figure 4 This is a timing diagram of the first chip select signal and the second chip select signal according to an embodiment of this application.

[0095] Figure 5 This is a flowchart illustrating the communication method according to an embodiment of this application.

[0096] Figure 6 This is a flowchart illustrating the communication method according to an embodiment of this application.

[0097] Figure 7 This is a flowchart illustrating the communication method according to an embodiment of this application.

[0098] Figure 8 This is a flowchart illustrating the communication method according to an embodiment of this application.

[0099] Figure 9 This is a flowchart illustrating the communication method according to an embodiment of this application.

[0100] Figure 10 This is a flowchart illustrating the communication method according to an embodiment of this application.

[0101] Figure 11 This is a flowchart illustrating the communication method according to an embodiment of this application.

[0102] Figure 12 This is a flowchart illustrating the communication method according to an embodiment of this application.

[0103] Figure 13 This is a flowchart illustrating the communication method according to an embodiment of this application. Detailed Implementation

[0104] The embodiments of this application are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application.

[0105] In the description of this application, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," and "counterclockwise," etc., indicating orientation or positional relationships based on the orientation or positional relationships shown in the accompanying drawings, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more of the stated features. In the description of this application, "a plurality of" means two or more, unless otherwise explicitly specified.

[0106] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection, an electrical connection, or a connection that allows communication between them; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication between two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0107] In this application, unless otherwise expressly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature being directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature being directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0108] The following disclosure provides many different embodiments or examples for implementing different structures of this application. To simplify the disclosure, specific examples of components and arrangements are described below. Of course, these are merely examples and are not intended to limit the scope of this application. Furthermore, reference numerals and / or letters may be repeated in different examples; such repetition is for simplification and clarity and does not in itself indicate a relationship between the various embodiments and / or arrangements discussed. In addition, various specific examples of processes and materials are provided in this application, but those skilled in the art will recognize the application of other processes and / or the use of other materials.

[0109] Intelligent converged terminals are edge devices within a smart IoT system architecture, possessing information collection, IoT agent, and edge computing capabilities to support marketing, power distribution, and emerging businesses. They employ a hardware platform-based, function-software-based, modular structure, hardware-software decoupling, and self-adaptive communication protocol design to meet the demands of high-performance concurrency, large-capacity storage, and multiple data collection objects. These intelligent converged terminal devices integrate functions such as power supply and consumption information collection in distribution substations, data collection from various terminals or energy meters, equipment status monitoring and communication networking, localized analysis and decision-making, and collaborative computing.

[0110] In related technologies, intelligent converged terminals typically include one main control chip and two security chips. The main control chip connects to the two security chips via two Serial Peripheral Interfaces (SPI). The two chips are used to handle marketing and power distribution operations, respectively. When processing marketing operations, the main control chip connects to the security chip handling marketing operations through one SPI interface. When processing power distribution operations, it connects to the security chip handling power distribution operations through the other SPI interface. The interfaces of the two security chips can be the same (both using SPI0) or different (one using SPI0, the other using SPI1), both serving as SPI protocol data read / write implementations (SPI slaves).

[0111] It should be noted that the Serial Peripheral Interface (SPI) bus system is a synchronous serial peripheral interface that enables the MCU to communicate with various peripheral devices in a serial manner to exchange information.

[0112] An SPI interface typically includes: a clock signal (SCK) generated by the master device, a master input / slave output data line (MISO), a master output / slave input data line (MOSI), and a chip select signal (SSN). When the chip is in operation, the port has two logic states: high and low. A low level indicates that the chip is enabled.

[0113] The SPI operating mode can be MODE3, with clock polarity (CPOL=1), the idle state of the serial synchronous clock is high level, and the clock phase (CPHA=1). Data is converted on the falling edge of the serial synchronous clock and sampled on the rising edge.

[0114] When the master device is sending data, the data output pin MISO must remain in receive mode. The SPI interface transmits and receives data sequentially in simplex mode. When the master device uses the MOSI pin to send data, the data on the MISO pin is invalid data, which the master device does not need to process and can simply discard or not receive.

[0115] However, this results in high overall hardware costs for intelligent converged terminals. Using only one interface to process one service inevitably leads to hardware waste. Furthermore, it is impossible to receive data from another interface while processing data from one interface. Data from another interface can only be received after the data from one interface has been processed, resulting in low processing efficiency.

[0116] In view of this, please combine Figure 1 This application discloses a terminal device 100, including a main control chip 10 and a security chip 20. The security chip 20 includes multiple interfaces, which are respectively connected to the main control chip 10.

[0117] The main control chip 10 is used to set the state of the target chip select signal of the target interface among multiple interfaces to the falling edge and send instruction data to the security chip 20. The instruction data includes the initial identifier and the instruction content.

[0118] The security chip 20 is used to receive and determine whether the initial identifier includes the command flag when the target chip select signal is in the falling edge state; if the initial identifier includes the command flag, it receives and executes the instruction content to obtain the processing result; and if the initial identifier does not include the command flag, it sends the processing result to the main control chip through the target interface.

[0119] The terminal device 100 of this application controls the target chip select signal of the target interface to fall on the target edge and sends instruction data to the security chip 20 through the main control chip. When the target chip select signal falls on the target edge, the security chip 20 starts the interrupt processing flow, thereby receiving the start identifier and determining whether the start identifier includes the command flag. If the start identifier includes the command flag, the instruction content is determined to be a command, and the instruction content sent by the main control chip 10 is received. After receiving the instruction content, the start identifier is backed up in the memory after the target chip select signal rises on the target edge, thereby exiting the interrupt processing, and then the command content is executed to obtain the command processing result. The processing result is then sent to the target interface. Thus, when the start identifier sent by the main control chip 10 does not include the command flag, the processing result can be sent to the main control chip 10. In this way, the terminal device 100 only needs to set up a security chip 20 to realize multiple service processing functions, improve the service processing capability of the security chip 20, reduce the hardware cost of the terminal device 100, and reduce the hardware circuit board area. In addition, compared with the existing technology, multiple security chips require multiple sets of key management methods, while this application can unify them into a single set of key management methods, reducing the software cost of terminal device 100.

[0120] Specifically, the interface can be a Serial Peripheral Interface (SPI). Each interface is configured with a corresponding Random Access Register (RAM), Direct Memory Access (DMA), Chip Select (SSN), and Data Output Pin (MISO). The MISO data output pin has two operating modes: General-purpose Input / Output (GPIO) mode and Clock Transfer (SPI) mode.

[0121] It should be noted that Direct Memory Access (DMA) enables data transfer between the interface and the specified system SRAM. When the interface receives data, the corresponding DMA channel is DMA Channel 0, and when the interface sends data, the corresponding DMA channel is DMA Channel 1. In addition to being controlled by the conventional DMA transfer length, DMA can also be stopped by a peripheral request for a transfer stop signal. This supports triggering a peripheral request for a transfer stop signal after the interface has finished receiving or sending data, requesting the DMA channel to terminate the transfer.

[0122] The state of the chip select signal SSN is controlled by the main control chip 10. That is, the main control chip 10 is used to control the state of the chip select signal SSN of each interface. When the main control chip 10 sets the chip select signal SSN low, that is, sets the state of the chip select signal SSN of the interface to a falling edge, it can send command data to the interface. After the data is sent, the chip select signal SSN is set high, that is, SSN=1.

[0123] The instruction data includes a start identifier and the instruction content. The start identifier is used to determine whether the instruction data is a command or a result of a command. If the start identifier includes a command flag, the instruction content is a command; if the start identifier does not include a command flag, the instruction content is a response to a command.

[0124] The start identifier can include a preset number of bytes, which is not limited in specific terms and can be one or more. For example, the start identifier can include one byte, two bytes, three bytes, four bytes, or even more bytes. In this application, the start identifier is four bytes. The command flag can be 0x55. That is, if the start identifier includes 0x55, it indicates that the instruction content includes a command. If the start identifier is not 0x55, it indicates that the instruction content is a response to fetching a command. The security chip also includes a memory that can be used to back up the start identifier.

[0125] In this application, there can be two interfaces, namely a first interface SPI0 and a second interface SPI1. The first interface SPI0 and the second interface SPI1 can be used to process marketing business and power distribution business. For example, the first interface SPI0 is configured to process marketing business and the second interface SPI1 is configured to process power distribution business, or the second interface SPI1 is configured to process marketing business and the first interface SPI0 is configured to process power distribution business.

[0126] In this application, the random access register (RAM) configured by the first interface SPI0 can be the first random access register RAM1, the chip select signal SSN configured by the first interface SPI0 can be the first chip select signal SSN1, the direct memory access (DMA) configured by the first interface SPI0 can be the first direct memory access (DMA1), and the data output pin MISO configured by the first interface SPI0 can be the first data output pin MISO1. The random access register (RAM) configured by the second interface SPI1 can be the second random access register RAM2, the chip select signal SSN configured by the second interface SPI1 can be the second chip select signal SSN2, the direct memory access (DMA) configured by the second interface SPI1 can be the second direct memory access (DMA2), and the data output pin MISO configured by the second interface SPI1 can be the second data output pin MISO2. The master control chip 10 can send commands or request the processing results of commands to the security chip 20 through the first interface SPI0 and / or the second interface SPI1.

[0127] The security chip 20 contains different instruction lists, corresponding to different business processes and file systems. For example, the instruction lists include a first instruction list and a second instruction list, where the first instruction list corresponds to marketing business processes and their file systems, and the second instruction list corresponds to power distribution business processes and their file systems. The security chip 20 does not restrict the content of the instruction lists, meaning that multiple lists are allowed to use the same instructions.

[0128] The security chip 20 includes an interrupt handling function and a main processing function. The security chip 20 implements marketing and power distribution operations by executing the interrupt handling function and the main processing function. The main processing function includes the following steps: initializing global variables, the first interface SPI0, the second interface SPI1 and their direct memory access DMA and file system, enabling interrupts by turning on the chip select signal SSN and pulling it low, and entering the main loop processing flow.

[0129] It should be noted that the interrupt handler has a higher priority than the main loop. That is, during the main loop processing of the security chip 20, the main loop can be interrupted and the interrupt handler can be executed first. After the interrupt handler finishes processing, the main loop processing flow can continue.

[0130] During the main function processing, the SSN (Single Select) interrupt enable signal must be placed after all initialization is complete and before entering the main loop. Enabling it too early, if an interrupt occurs before the initialization preparation is finished, can cause errors in the command processing. Furthermore, during the initialization of the first interface SPI0, the second interface SPI1, and their direct memory access (DMA), the transmit and receive interfaces must be separated, with independent transmit and receive addresses for each interface. For example, the transmit area of ​​the first interface SPI0 is 0x20002B00, and the receive area is 0x20002200; the transmit area of ​​the second interface SPI1 is 0x20001100, and the receive area is 0x20000000. In this way, the transmit or receive address can be used to determine whether to use the first interface SPI0 or the second interface SPI1 for data transmission and reception.

[0131] Please combine Figure 2 Additionally, it should be noted that for the target interface (first interface SPI0 or second interface SPI1), the command and the result of fetching the command must appear in pairs. For example, if the first interface SPI0 is the target interface, and the target chip select signal SSN is falling, if the command received by the target interface is command 1, the command received after command 1 is received must be the result of fetching command 1. If the command received by the target interface is command 2, the command received after command 2 is received must be the result of fetching command 2.

[0132] Please combine Figure 3 Furthermore, after the command is processed, an instruction message to retrieve the command result is executed. If retrieving the command result fails, the main control chip 10 can resend the instruction message to the security chip 20 to retrieve the command result again, thus allowing the main control chip 10 to retrieve the command result from the security chip 20 once more. For example, if a verification error occurs when retrieving the result of command 1 after command 1 is processed, the main control chip 10 is allowed to retrieve the result of command 1 from the security chip 20 again. Understandably, because the difficulty of commands varies, the time required to obtain the command result is uncertain. When the main control chip 10 sends an instruction to the security chip 20 to retrieve the command result, the result may not yet be available, and the main control chip 10 may not be able to respond.

[0133] Please combine Figure 4 The pull-down of the first chip select signal SSN1 and the second chip select signal SSN2 must be staggered on the time axis. That is, in the same time period, when the first chip select signal SSN1 is pulled down to the falling edge, the second chip select signal SSN2 must be in the rising edge stage, and when the state of the second chip select signal SSN2 is pulled down to the falling edge, the state of the first chip select signal SSN1 must be in the rising edge stage.

[0134] The interrupt handling process can be as follows:

[0135] When the target chip select signal SSN becomes a falling edge, delay for 10 microseconds to eliminate jitter, confirm that the target chip select signal SSN is a low-triggered interrupt, set the target data output pin MISO to clock transmission mode SPI, control the target interface to receive the start flag, and determine whether the start flag has a command flag.

[0136] If the start flag includes a command flag, the target direct memory access DMA is initiated to receive the remaining instruction content. The process waits for the chip select signal SSN to rise, and after SSN rises, the target direct memory access DMA is disabled, and the target data output pin MISO is set to general purpose input / output (GPIO) mode. The start flag is then backed up and stored in memory to prevent it from being overwritten when an interrupt is triggered again. Next, the target interface's transmit / receive enable is enabled, allowing it to receive or send data to the main control chip 10. The command reception completion flag and the target interface's serial number are set, and the pull-down interrupt enable for the chip select signal SSN is enabled, thus ending the interrupt handling process.

[0137] If the start flag does not have a command flag, it is considered that the main control chip 10 is receiving a response. The start flag backed up in the memory is restored, and the transmit / receive enable of the target interface is turned on, so that the target interface can receive or send data to the main control chip 10. The receive response flag and the serial number of the target interface are set, and the chip select signal SSN pull-down interrupt enable is turned on, thereby ending the interrupt handling process.

[0138] Please combine Figure 4 Additionally, if the target interface does not receive the start flag after the chip select signal SSN is pulled low, and it is confirmed that the target direct memory access DMA configuration is incorrect or the state of the chip select signal SSN becomes rising edge, then the data output pin MISO is set to general purpose input / output mode GPIO, the transmit / receive enable of the target interface is enabled, the serial number of the target interface is set, and the interrupt enable of the chip select signal SSN is enabled, thereby ending the interrupt handling process.

[0139] It should be noted that the above interrupt handling process can be either a marketing interrupt handling process or a power distribution interrupt handling process. For example, if the interrupt handling process is for marketing operations, then the chip select signal SSN is the first chip select signal SSN1, the target interface is the first interface SPI0, the target data output pin MISO is the first data output pin MISO1 of the first interface SPI0, and the target direct memory access DMA is the first direct memory access DMA1 of the first interface SPI0. If the interrupt handling process is for power distribution operations, then the chip select signal SSN is the second chip select signal SSN2, the target interface is the second interface SPI1, the target data output pin MISO is the second target data output pin MISO2 of the second interface SPI1, and the target direct memory access DMA is the second direct memory access DMA2 of the second interface SPI1.

[0140] In this way, the interrupt handling process described above avoids the main control chip from constantly querying command responses, allowing the main control chip to obtain command responses at any time during its idle time, thereby improving the business processing efficiency of the terminal device.

[0141] The main loop processing flow can be:

[0142] The system receives instruction data sent by the main control chip 10. After receiving the instruction data, it determines whether the start identifier includes the command flag.

[0143] If the start flag includes a command flag, determine that the instruction content includes a command, and clear the command reception completion flag. Determine whether the instruction data originates from the first interface SPI0 or the second interface SPI1. If the instruction data originates from the first interface SPI0, set the data transmit / receive pointer to the first random access register RAM1, parse the instruction content to obtain the command, process the command, and send the processing result to the first random access register RAM1. If the instruction data originates from the second interface SPI1, set the data transmit / receive pointer to the second random access register RAM2 dedicated to the second interface SPI1, parse the instruction content, process the command, and send the processing result to the second random access register RAM2. End the current main loop process and continue waiting for the next instruction data to be executed.

[0144] If the start identifier does not include the command flag, and the instruction content is determined to be the result of obtaining the command, then it is determined whether the instruction data comes from the first interface SPI0 or the second interface SPI1. If the instruction data comes from the first interface SPI0, the status of the first chip select signal SSN1 of the first interface SPI0 is queried. When the first chip select signal SSN1 is low, the first direct memory access DMA1 is started, and the first chip select signal SSN1 is pulled high. After the first chip select signal SSN1 is pulled high, the first direct memory access DMA1 is closed, and the first data output pin MISO1 of the first interface SPI0 is set to general purpose input / output mode GPIO. When the first chip select signal SSN1 is high, it is determined that the first chip select signal SSN1 is pulled high by the master control chip I0. The first interface SPI0 is enabled for transmit and receive, and the response flag is cleared. Then the pull-down interrupt enable of the first chip select signal SSN1 is turned on. When the instruction data originates from the second interface SPI1, the status of the second chip select signal SSN2 of the second interface SPI1 is queried. When the second chip select signal SSN2 is low, the second direct memory access DMA2 is started, and the second direct memory access DMA2 is turned off after the second chip select signal SSN2 is pulled high. The second data output pin MISO2 of the second interface SPI0 is set to general purpose input / output mode GPIO. When the second chip select signal SSN2 is high, it is determined that the second chip select signal SSN2 is pulled high by the master control chip 10. The second interface SPI1 is enabled for transmit and receive, and the response flag is cleared. Then the pull-down interrupt enable of the second chip select signal SSN2 is turned on. Finally, the main loop process of the current instruction data ends, and the main loop process of waiting to execute the next instruction data continues.

[0145] Please combine Figure 5 This application also provides a communication method for the aforementioned security chip 20, the communication method comprising:

[0146] 01. Based on the falling edge of the target chip select signal, initiate interrupt processing to receive the start flag;

[0147] 02. If the start identifier includes a command flag, receive the instruction content sent by the main control chip;

[0148] 03. Based on the rising edge of the target chip select signal, back up the start identifier to memory and exit interrupt handling;

[0149] 04. Execute the instructions to obtain the processing result;

[0150] 05. Send the processing result to the target interface.

[0151] In some implementations, the security chip 20 includes a processor for implementing the communication method described above. In other words, the processor is used to initiate interrupt processing based on the falling edge of the target chip select signal to receive a start flag; if the start flag includes a command flag, receive the instruction content sent by the main control chip 10; back up the start flag to memory based on the rising edge of the target chip select signal and exit the interrupt processing; execute the instruction content to obtain the processing result; and send the processing result to the target interface.

[0152] In the communication method and security chip 20 of this application, an interrupt processing procedure is initiated when the target chip select signal falls, thereby receiving the start identifier and determining whether the start identifier includes a command flag. If the start identifier includes a command flag, the instruction content is determined to be a command, and the instruction content sent by the main control chip 10 is received. After receiving the instruction content, the start identifier is backed up in the memory after the target chip select signal rises, thereby exiting the interrupt processing, avoiding the situation where the previous start identifier is overwritten when the target chip select signal falls again. Then, the command content is executed to obtain the command processing result, and the processing result is sent to the target interface. In this way, when the start identifier of the main control chip 10 does not include the command flag, the processing result can be sent to the main control chip 10. Thus, the terminal device 100 only needs to set up a security chip 20 to handle multiple business functions, which reduces the hardware cost of the terminal device 100, reduces the hardware circuit board area, and improves the business processing capability of the security chip 20. This allows the main control chip 10 to continue to send other business instructions or handle its own non-security tasks through other interfaces while the security chip 20 is processing business instructions.

[0153] In step 02, the target interface can be initiated to access the target direct memory, thereby receiving the instruction content sent by the main control chip 10.

[0154] Please combine Figure 6 In some implementations, the communication method further includes:

[0155] 06. In the case where the start identifier does not include the command flag, the processing result is sent to the main control chip via the target interface in response to the start identifier stored in the memory.

[0156] In some implementations, the processor is configured to send the processing result to the main control chip 10 via the target interface in response to a start identifier stored in memory, provided that the start identifier does not include a command flag.

[0157] Thus, if the start identifier does not include the command flag, it means that the instruction content is to retrieve the processing result of the command. The processing result can then be sent to the main control chip 10, so that the main control chip 10 can obtain the processing result of the command.

[0158] Please see Figure 7 In some implementations, step 06 includes:

[0159] 061, restore the backup start identifier to the target random access register of the target interface;

[0160] 062, Control the target interface to enable transmit / receive to exit interrupt handling;

[0161] 063, based on the starting identifier, the processing result is sent to the main control chip through the target interface.

[0162] In some implementations, the processor is used to restore the backup start identifier to the target random access register of the target interface, control the target interface to perform transmit / receive enable to exit interrupt processing, and send the processing result to the main control chip through the target interface according to the start identifier.

[0163] Please see Figure 8 In some implementations, sub-step 062 includes:

[0164] 0621, control the target interface to execute transmit / receive enable by setting the receive response flag and the target interface sequence number;

[0165] 0622, Enable the pull-down interrupt for the target chip select signal to exit interrupt handling.

[0166] In some implementations, the processor controls the target interface to perform transmit / receive enable to set the receive response flag and the target interface's serial number, and to enable the pull-down interrupt of the target chip select signal to exit interrupt handling.

[0167] Please combine Figure 9 In some implementations, sub-step 063 includes:

[0168] 0631, query the status of the target chip select signal;

[0169] 0632, when the target chip select signal is on a falling edge, initiate target direct memory access of the target interface;

[0170] 0633, based on the target interface's serial number and the received response flag, send the processing result to the main control chip 10.

[0171] In some implementations, the processor is used to query the status of the target chip select signal, initiate target direct memory access of the target interface when the target chip select signal is on a falling edge, and send the processing result to the main control chip according to the target interface serial number and receive response flag.

[0172] In this way, the main control chip can receive the processing results of the commands sent by the target interface.

[0173] Please combine Figure 10 In some implementations, the communication method further includes:

[0174] 07. Based on the rising edge of the target chip select signal, disable the target direct memory access and set the data output pin of the target interface to general purpose input / output mode;

[0175] 08. Enable send and receive on the target interface to clear the response flag;

[0176] 09. Enable the pull-down interrupt for the target chip select signal.

[0177] In some implementations, the processor is configured to disable target direct memory access based on the rising edge of the target chip select signal, set the data output pin of the target interface to general purpose input / output mode, enable transmit / receive on the target interface to clear the response flag, and enable pull-down interrupt enable on the target chip select signal.

[0178] Please see Figure 11 In some implementations, step 01 includes:

[0179] 011. If the duration of the falling edge of the target chip select signal exceeds a preset time, interrupt processing will be initiated.

[0180] 012, Set the data output pin of the target interface to clock transmission mode to receive the start flag through the target interface.

[0181] In some implementations, the processor is configured to initiate interrupt processing after the falling edge duration of the target chip select signal exceeds a preset time, and to set the data output pin of the target interface to clock transmission mode so as to receive the start flag through the target interface.

[0182] The preset time can be 10 microseconds. That is, the interrupt processing will be started after the duration of the falling edge of the target chip select signal is greater than 10 microseconds. This can avoid the interrupt processing being triggered by the target chip select signal due to oscillation.

[0183] Please see Figure 12 In some implementations, step 03 includes:

[0184] 031. When the target chip select signal is on a rising edge, disable the target interface's direct memory access and set the target interface's data output pin to general purpose input / output mode.

[0185] 032, back up the starting identifier to memory;

[0186] 033, the target interface set command reception completion flag and the target interface sequence number;

[0187] 034. Enable the pull-down interrupt for the target chip select signal to exit interrupt handling.

[0188] In some implementations, the processor is configured to disable target direct memory access of the target interface and set the data output pin of the target interface to general purpose input / output mode when the target chip select signal is on a rising edge, back up the start flag to memory, control the target interface set command reception completion flag and the target interface serial number, and enable pull-down interrupt enable of the target chip select signal to exit interrupt processing.

[0189] It should be noted that, in this embodiment, the rising edge duration of the target chip select signal needs to be greater than 15 microseconds to ensure that the above steps can be executed.

[0190] Please see Figure 13 In some implementations, step 04 includes:

[0191] 041, Clear the command reception completed flag;

[0192] 042, parse the instruction content to obtain the command;

[0193] 043, process the command to obtain the processing result.

[0194] In some implementations, the processor is used to clear the initial identifier, parse the instruction content to obtain the command, and process the command to obtain the processing result.

[0195] Thus, when the processing result of the acquisition command received from the main control chip is obtained, the processing result can be sent to the main control chip through the target interface.

[0196] This application also provides a non-volatile computer-readable storage medium, which includes a computer program that, when processed by a processor, causes the processor to execute any of the above-described communication methods.

[0197] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with the described embodiment or example, which are included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0198] Although embodiments of this application have been shown and described, those skilled in the art will understand that various changes, modifications, substitutions and variations can be made to these embodiments without departing from the principles and spirit of this application, the scope of which is defined by the claims and their equivalents.

Claims

1. A communication method for a security chip, characterized in that, The security chip includes multiple interfaces, all of which are SPI interfaces. The security chip connects to the main control chip through these multiple interfaces. Each of the multiple interfaces is configured with a corresponding chip select signal. The communication method includes: Based on the falling edge of the target chip select signal, interrupt processing is initiated to receive the start flag; If the starting identifier includes a command flag, the instruction content sent by the main control chip is received; Based on the rising edge of the target chip select signal, the start identifier is backed up in memory and the interrupt processing is exited; Execute the instructions to obtain the processing result; Send the processing result to the target interface; If the start identifier does not include the command flag, in response to the start identifier stored in the memory, the processing result is sent to the main control chip through the target interface; The plurality of interfaces includes a first interface and a second interface, wherein the first interface is configured with a first chip select signal and the second interface is configured with a second chip select signal; When the first chip select signal is a falling edge, the second chip select signal is a rising edge; or When the second chip select signal is a falling edge, the first chip select signal is a rising edge; The step of initiating interrupt processing based on the falling edge of the target chip select signal to receive the start identifier includes: After the falling edge duration of the target chip select signal exceeds a preset time, interrupt processing is initiated; the data output pin of the target interface is set to clock transmission mode to receive the start identifier through the target interface.

2. The communication method according to claim 1, characterized in that, In the case where the starting identifier does not include the command flag, in response to the starting identifier stored in the memory, sending the processing result to the main control chip through the target interface includes: Restore the backed-up start identifier to the target random access register of the target interface; Control the target interface to enable transmit / receive to exit interrupt handling; The processing result is sent to the main control chip through the target interface according to the starting identifier.

3. The communication method according to claim 2, characterized in that, The control of the target interface to enable transmit and receive and exit interrupt handling includes: Control the target interface to perform transmit / receive enable to set the receive response flag and the target interface sequence number; Enable the pull-down interrupt for the target chip select signal to exit interrupt handling.

4. The communication method according to claim 3, characterized in that, The step of sending the processing result to the main control chip through the target interface according to the starting identifier includes: Query the status of the target chip select signal; When the target chip select signal is a falling edge, the target interface initiates target direct memory access; The processing result is sent to the main control chip according to the serial number of the target interface and the received response flag.

5. The communication method according to claim 4, characterized in that, The communication method further includes: Based on the rising edge of the target chip select signal, disable the target direct memory access and set the data output pin of the target interface to general purpose input / output mode; Enable transmit / receive on the target interface to clear the response flag; Enable the pull-down interrupt for the target chip select signal.

6. The communication method according to claim 1, characterized in that, When the starting identifier includes a command flag, receiving the instruction content sent by the main control chip includes: Initiate target direct memory access of the target interface to receive the instruction content.

7. The communication method according to claim 1, characterized in that, The step of backing up the start identifier to memory and exiting interrupt processing based on the rising edge of the target chip select signal includes: When the target chip select signal is on a rising edge, disable target direct memory access of the target interface and set the data output pin of the target interface to general purpose input / output mode; The starting identifier is backed up in the memory; Control the target interface to set the command to complete receiving the flag and the sequence number of the target interface; Enable the pull-down interrupt for the target chip select signal to exit interrupt handling.

8. The communication method according to claim 7, characterized in that, The execution of the instruction content to obtain the processing result includes: Clear the command reception completion flag; The instruction content is parsed to obtain the command; The command is processed to obtain the processing result.

9. A security chip, characterized in that, The security chip includes multiple interfaces and a processor. The security chip is connected to the main control chip through the multiple interfaces, which are SPI interfaces. Each of the multiple interfaces is configured with a corresponding chip select signal. The processor is used for: Based on the falling edge of the target chip select signal, interrupt processing is initiated to receive the start flag; If the starting identifier includes a command flag, the instruction content sent by the main control chip is received; Based on the rising edge of the target chip select signal, the start identifier is backed up in memory and the interrupt processing is exited; Execute the instructions to obtain the processing result; Send the processing result to the target interface; If the start identifier does not include the command flag, in response to the start identifier stored in the memory, the processing result is sent to the main control chip through the target interface; The plurality of interfaces include a first interface and a second interface, wherein the first interface is configured with a first chip select signal and the second interface is configured with a second chip select signal; when the first chip select signal is a falling edge, the second chip select signal is a rising edge; or when the second chip select signal is a falling edge, the first chip select signal is a rising edge. Specifically, the processor is used to initiate interrupt processing after the falling edge duration of the target chip select signal exceeds a preset time; and to set the data output pin of the target interface to clock transmission mode so as to receive the start identifier through the target interface.

10. The security chip according to claim 9, characterized in that, The processor is used for: Restore the backed-up start identifier to the target random access register of the target interface; Control the target interface to enable transmit / receive to exit interrupt handling; The processing result is sent to the main control chip through the target interface according to the starting identifier.

11. The security chip according to claim 10, characterized in that, The processor is used for: Control the target interface to perform transmit / receive enable to set the receive response flag and the target interface sequence number; Enable the pull-down interrupt for the target chip select signal to exit interrupt handling.

12. The security chip according to claim 11, characterized in that, The processor is used for: Query the status of the target chip select signal; When the target chip select signal is a falling edge, the target interface initiates target direct memory access; The processing result is sent to the main control chip according to the serial number of the target interface and the received response flag.

13. The security chip according to claim 12, characterized in that, The processor is also used for: Based on the rising edge of the target chip select signal, disable the target direct memory access and set the data output pin of the target interface to general purpose input / output mode; Enable transmit / receive on the target interface to clear the response flag; Enable the pull-down interrupt for the target chip select signal.

14. The security chip according to claim 9, characterized in that, The processor is used for: Initiate target direct memory access of the target interface to receive the instruction content.

15. The security chip according to claim 9, characterized in that, The processor is used for: When the target chip select signal is on a rising edge, disable target direct memory access of the target interface and set the data output pin of the target interface to general purpose input / output mode; The starting identifier is backed up in the memory; Control the target interface to set the command to complete receiving the flag and the sequence number of the target interface; Enable the pull-down interrupt for the target chip select signal to exit interrupt handling.

16. The security chip according to claim 15, characterized in that, The processor is used for: Clear the command reception completion flag; The instruction content is parsed to obtain the command; The command is processed to obtain the processing result.

17. A terminal device, characterized in that, The system includes a security chip and a main control chip. The security chip includes multiple interfaces, all of which are SPI interfaces. These multiple interfaces are connected to the main control chip. The main control chip is used to set the state of the target chip select signal of the target interface among the multiple interfaces to a falling edge and send instruction data to the security chip. The instruction data includes a start identifier and instruction content. The security chip is configured to receive and determine whether the start identifier includes a command flag when the target chip select signal is in a falling edge state; if the start identifier includes a command flag, receive and execute the instruction content to obtain a processing result; and if the start identifier does not include a command flag, respond to the start identifier stored in the memory to send the processing result to the main control chip through the target interface. Specifically, the security chip is configured to receive and determine whether the start identifier includes a command flag when the duration of the falling edge of the target chip select signal is greater than a preset time, and set the data output pin of the target interface to clock transmission mode to receive the start identifier through the target interface. The plurality of interfaces include a first interface and a second interface, wherein the first interface is configured with a first chip select signal and the second interface is configured with a second chip select signal; when the first chip select signal is a falling edge, the second chip select signal is a rising edge; or when the second chip select signal is a falling edge, the first chip select signal is a rising edge.

18. A non-volatile computer-readable storage medium comprising a computer program, characterized in that, When the computer program is executed by a processor, the processor performs the communication method according to any one of claims 1-8.

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