Core control method and device, processing core, system, electronic equipment and medium

Abstract

The disclosure provides a core control method for a many-core system, the many-core system comprising at least one core cluster, each core cluster comprising at least one second processing core, the core control method comprising: for any one core cluster, performing load detection on the core cluster to obtain load data corresponding to the core cluster; determining a load state of the core cluster according to the load data corresponding to the core cluster; and performing regulation and control processing on the core cluster according to the load state of the core cluster; the regulation and control processing comprising one of the following regulation and control modes: regulating the number of second processing cores in the core cluster that can currently perform a job; regulating the working voltage and working frequency of the second processing cores in the core cluster that can currently perform a job; and inserting a blank frame into a buffer corresponding to the core cluster. The disclosure also provides a core control device, a processing core, a many-core system, an electronic device and a computer readable medium.

Description

Technical Field

[0001] This disclosure relates to the field of computer technology, and in particular to a core control method and apparatus for many-core systems, a processing core, a many-core system, an electronic device, a computer-readable medium, and a computer program product. Background Technology

[0002] With the development of artificial intelligence technology, the demand for data processing speed is increasing, leading to the widespread application of many-core systems. Many-core systems typically have numerous cores (also called processing cores). A core is the smallest computing unit in a many-core system that can be independently scheduled and possesses complete computing capabilities. Cores have certain storage and computing resources. The cores of a many-core system can independently execute program instructions, leveraging parallel computing capabilities to accelerate program execution and provide multitasking capabilities.

[0003] In related technologies, the core storage input devices of a many-core system store input data, the arithmetic unit performs calculations based on the input data, stores the calculation results in the memory, and finally notifies the output device to receive the output results. The input devices and output devices can be external devices or core components of the many-core system. Summary of the Invention

[0004] This disclosure provides a core control method and apparatus for a many-core system, a processing core, a many-core system, an electronic device, a computer-readable medium, and a computer program product.

[0005] In a first aspect, this disclosure provides a core control method for a many-core system, the many-core system including at least one core cluster, each core cluster including at least one second processing core, the core control method including: for any one of the core clusters, performing load detection on the core cluster to obtain load data corresponding to the core cluster; determining the load state of the core cluster based on the load data corresponding to the core cluster; and performing regulation processing on the core cluster based on the load state of the core cluster; wherein the regulation processing includes one of the following regulation methods: regulating the number of second processing cores currently capable of performing tasks in the core cluster; regulating the operating voltage and operating frequency of the second processing cores currently capable of performing tasks in the core cluster; and inserting blank frames into the buffer corresponding to the core cluster.

[0006] In some embodiments, each core cluster is provided with a corresponding cache, which is used to cache task data of the tasks to be processed by the corresponding core cluster; the load detection of the core cluster and the acquisition of the load data corresponding to the core cluster includes: monitoring the real-time memory space utilization of the cache corresponding to the core cluster; monitoring the comparison result of the real-time memory space utilization of the cache corresponding to the core cluster with a first preset threshold; recording the duration for which the real-time memory space utilization is continuously greater than or equal to the first preset threshold, and recording it as a first duration, wherein the load data corresponding to the core cluster includes the first duration.

[0007] In some embodiments, determining the load status of the core cluster based on the load data corresponding to the core cluster includes: determining whether the first duration is greater than or equal to a first preset duration; and determining that the load status of the core cluster is busy if the first duration is greater than or equal to the first preset duration.

[0008] In some embodiments, the step of performing load detection on the core cluster and obtaining load data corresponding to the core cluster further includes: monitoring the comparison result between the real-time memory space utilization rate of the cache corresponding to the core cluster and a second preset threshold, wherein the second preset threshold is greater than 0 and less than the first preset threshold; recording the duration for which the real-time memory space utilization rate is continuously less than or equal to the second preset threshold, and recording it as the second duration, wherein the load data corresponding to the core cluster includes the second duration.

[0009] In some embodiments, determining the load state of the core cluster based on the load data corresponding to the core cluster includes: determining whether the second duration is greater than or equal to a second preset duration; and determining that the load state of the core cluster is a low load state if the second duration is greater than or equal to the second preset duration.

[0010] In some embodiments, each core cluster is provided with a corresponding cache, which is used to cache task data of the tasks to be processed by the corresponding core cluster; the load detection of the core cluster and the acquisition of the load data corresponding to the core cluster includes: acquiring the memory space usage growth rate of the cache corresponding to the core cluster, wherein the load data corresponding to the core cluster includes the memory space usage growth rate of the corresponding cache.

[0011] In some embodiments, determining the load status of the core cluster based on the load data corresponding to the core cluster includes: determining whether the memory space usage growth rate is greater than or equal to a first preset growth rate value; and if the memory space usage growth rate is greater than or equal to the first preset growth rate value, determining that the load status of the core cluster is a busy state.

[0012] In some embodiments, the load data corresponding to the core cluster also includes the real-time memory space utilization rate of the corresponding cache. Determining the load status of the core cluster based on the load data includes: if the real-time memory space utilization rate of the cache corresponding to the core cluster is less than or equal to a preset utilization rate, determining whether the memory space utilization growth rate is less than or equal to a second preset growth rate value, wherein the second preset growth rate value is negative; if the memory space utilization growth rate is less than or equal to the second preset growth rate value, determining that the load status of the core cluster is a low load status.

[0013] In some embodiments, the buffer is a FIFO buffer.

[0014] In some embodiments, the step of performing load detection on the core cluster and obtaining load data corresponding to the core cluster includes: real-time monitoring of the task processing time required for the core cluster to process tasks, wherein the load data corresponding to the core cluster includes the task processing time.

[0015] In some embodiments, determining the load status of the core cluster based on the load data corresponding to the core cluster includes: determining whether the task processing time required for the core cluster to process the task is greater than or equal to a first preset processing time; and determining that the load status of the core cluster is busy if the task processing time required for the core cluster to process the task is greater than or equal to the first preset processing time.

[0016] In some embodiments, determining the load state of the core cluster based on the load data corresponding to the core cluster includes: determining whether the task processing time required for the core cluster to process the task is less than or equal to a second preset processing time; if the task processing time required for the core cluster to process the task is less than or equal to the second preset processing time, determining that the load state of the core cluster is a low load state.

[0017] In some embodiments, the many-core system includes a plurality of core clusters, which perform task processing based on a synchronization period, wherein the synchronization period is the longest task processing time required by each core cluster to process the task.

[0018] The step of determining the load status of the core cluster based on the load data of the core cluster includes: counting the frequency of the task processing time of the core cluster as the synchronization cycle within a preset monitoring time period; and determining the load status of the core cluster as a busy state when the frequency of the task processing time of the core cluster as the synchronization cycle is greater than or equal to a first preset number.

[0019] In some embodiments, the many-core system includes a plurality of core clusters, which perform task processing based on a synchronization period, wherein the synchronization period is the longest task processing time required by each core cluster to process the task.

[0020] The step of determining the load status of the core cluster based on the load data of the core cluster includes: counting the frequency of the task processing time corresponding to the core cluster as the synchronization cycle within a preset monitoring time period; calculating the ratio of the frequency of the task processing time corresponding to the core cluster as the synchronization cycle to the number of synchronization cycles within the preset monitoring time period; and determining that the load status of the core cluster is busy if the ratio is greater than or equal to a first preset ratio.

[0021] In some embodiments, the step of adjusting the core cluster according to its load state includes: when the load state of the core cluster is busy, determining whether the core cluster has adjustable voltage and frequency domains; if the core cluster has adjustable voltage and frequency domains, increasing the operating voltage and operating frequency of the second processing cores corresponding to the adjustable voltage and frequency domains in the currently operable second processing cores of the core cluster; if the core cluster does not have adjustable voltage and frequency domains, increasing the number of currently operable second processing cores in the core cluster.

[0022] In some embodiments, the step of adjusting the core cluster according to its load state includes: when the load state of the core cluster is low, determining whether the core cluster has an adjustable voltage domain and frequency domain; if the core cluster has an adjustable voltage domain and frequency domain, lowering the operating voltage and operating frequency of the second processing cores corresponding to the adjustable voltage domain and frequency domain in the currently operable second processing cores of the core cluster; if the core cluster does not have an adjustable voltage domain and frequency domain, reducing the number of currently operable second processing cores in the core cluster.

[0023] In some embodiments, increasing the number of second processing cores currently available for work in the core cluster includes adding one or more idle second processing cores outside the core cluster in the many-core system to the core cluster as second processing cores currently available for work in the core cluster.

[0024] In some embodiments, increasing the number of second processing cores currently capable of performing tasks in the core cluster includes: waking up one or more second processing cores in the core cluster that are in a closed state, so as to serve as second processing cores currently capable of performing tasks in the core cluster.

[0025] In some embodiments, reducing the number of second processing cores currently capable of performing jobs in the core cluster includes: removing at least one second processing core currently capable of performing jobs from the core cluster.

[0026] In some embodiments, reducing the number of second processing cores currently capable of performing tasks in the core cluster includes: controlling at least one second processing core currently capable of performing tasks in the core cluster to be in a closed state.

[0027] In some embodiments, each core cluster of the many-core system corresponds to a task in a processing task pipeline. Each core cluster includes multiple sub-clusters, and each sub-cluster includes at least one second processing core that is currently capable of performing a task. These multiple sub-clusters are used to process the task corresponding to their respective core cluster in parallel. The method further includes: constructing a new sub-cluster of the core cluster based on the newly added second processing cores that are currently capable of performing a task in the core cluster and obtaining the configuration information of the new sub-cluster. The new sub-cluster includes one or more newly added second processing cores that are currently capable of performing a task. The configuration information includes the number of second processing cores in the new sub-cluster and the address information of each second processing core; sending the task to the target processing core in the predecessor core cluster of the core cluster. The configuration information of the new sub-cluster; sending the configuration information of the new sub-cluster to the target processing core in the successor core cluster of the core cluster; wherein, the successor core cluster is the core cluster preceding the core cluster in the task pipeline, and the target processing core in the successor core cluster is used to establish the input branch of the new sub-cluster according to the configuration information of the new sub-cluster of the core cluster, and the input branch is the path for the output data from the successor core cluster to the new sub-cluster; the successor core cluster is the core cluster following the core cluster in the task pipeline, and the target processing core in the successor core cluster is used to establish the output branch of the new sub-cluster according to the configuration information of the new sub-cluster of the core cluster, and the output branch is the path for the output data from the new sub-cluster to the successor core cluster.

[0028] In some embodiments, if the real-time memory space utilization rate is 0, and the second duration that is continuously 0 is greater than or equal to the second preset duration and less than the third preset duration, then the load state of the core cluster is determined to be idle, and the idle state level is the first level; if the real-time memory space utilization rate is 0, and the second duration that is continuously 0 is greater than or equal to the third preset duration, then the load state of the core cluster is determined to be idle, and the idle state level is the second level.

[0029] In some embodiments, the step of adjusting the core cluster according to its load state includes: inserting blank frames into the buffer corresponding to the core cluster when the load state of the core cluster is a first-level idle state; and when the load state of the core cluster is a second-level idle state, lowering the operating voltage and operating frequency of the second processing cores corresponding to the adjustable voltage and frequency domains of the currently operable second processing cores of the core cluster, or reducing the number of currently operable second processing cores in the core cluster.

[0030] In some embodiments, after inserting a blank frame into the buffer corresponding to the core cluster, the method further includes: turning off the gated clock corresponding to each second processing core in the core cluster, wherein the gated clock is used to output a clock signal to the corresponding second processing core in the core cluster to drive the corresponding second processing core to work or not work based on the clock signal.

[0031] In some embodiments, the many-core system includes multiple core clusters. When multiple core clusters are processing the same task and the load status of the multiple core clusters is all at the first level of idle state, after inserting blank frames into the buffers corresponding to the multiple core clusters, the core control method further includes: pausing the transmission of synchronization signals to the multiple core clusters, wherein the synchronization signals are used to drive the multiple core clusters to process tasks based on a synchronization period.

[0032] Secondly, this disclosure provides a core control device applied to a many-core system, the many-core system including at least one core cluster, each core cluster including at least one second processing core, the core control device including: a load data detection module configured to perform load detection on a corresponding core cluster and obtain load data corresponding to the core cluster; a load status detection module configured to determine the load status of the core cluster based on the load data corresponding to the core cluster; and a core regulation module configured to perform regulation processing on the core cluster based on the load status of the core cluster; wherein the regulation processing includes one of the following regulation methods: regulating the number of second processing cores currently capable of performing operations in the core cluster; regulating the operating voltage and operating frequency of the second processing cores currently capable of performing operations in the core cluster; and inserting blank frames into the buffer corresponding to the core cluster.

[0033] Thirdly, this disclosure provides a processing core that includes the aforementioned core control device.

[0034] Fourthly, this disclosure provides a many-core system comprising multiple processing cores, including a first processing core and multiple second processing cores. Some or all of the multiple second processing cores are divided into at least one core cluster. Each core cluster includes at least one second processing core and has a master processing core, wherein the master processing core of the core cluster is a designated second processing core within that core cluster. The first processing core employs the processing core provided in the third aspect, and / or, at least some of the master processing cores of the core clusters employ the processing core provided in the third aspect.

[0035] Fifthly, this disclosure provides an electronic device comprising: a plurality of processing cores; and an on-chip network configured to interact with data between the plurality of processing cores and external data; wherein one or more of the processing cores store one or more instructions, and the one or more instructions are executed by the one or more processing cores to enable the one or more processing cores to perform the core control method described above.

[0036] Sixthly, this disclosure provides a computer-readable medium having a computer program stored thereon, wherein the computer program, when executed by a processing core, implements the aforementioned core control method.

[0037] In a seventh aspect, this disclosure provides a computer program product comprising a computer program that, when executed by a processing core, implements the aforementioned core control method.

[0038] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of this disclosure, nor is it intended to limit the scope of this disclosure. Other features of this disclosure will become readily apparent from the following description. Attached Figure Description

[0039] The accompanying drawings are provided to further illustrate the present disclosure and form part of the specification. They are used together with the embodiments of the present disclosure to explain the disclosure and do not constitute a limitation thereof. The above and other features and advantages will become more apparent to those skilled in the art from the detailed description of exemplary embodiments with reference to the accompanying drawings, in which:

[0040] Figure 1 A flowchart of a core control method for a many-core system provided in this disclosure embodiment;

[0041] Figure 2 A block diagram of a many-core system provided in this disclosure embodiment;

[0042] Figure 3 for Figure 1A flowchart of a specific implementation of step S1;

[0043] Figure 4 for Figure 1 A flowchart of another specific implementation of step S1;

[0044] Figure 5 for Figure 1 A flowchart of a specific implementation of step S2;

[0045] Figure 6 for Figure 1 A flowchart of another specific implementation of step S2;

[0046] Figure 7 for Figure 1 A flowchart of another specific implementation of step S2;

[0047] Figure 8 for Figure 1 A flowchart of another specific implementation of step S2;

[0048] Figure 9 for Figure 1 A flowchart of another specific implementation of step S2;

[0049] Figure 10 for Figure 1 A flowchart of another specific implementation of step S2;

[0050] Figure 11 for Figure 1 A flowchart of another specific implementation of step S2;

[0051] Figure 12 for Figure 1 A flowchart of another specific implementation of step S2;

[0052] Figure 13 for Figure 1 A flowchart of a specific implementation of step S3;

[0053] Figure 14 for Figure 1 A flowchart of another specific implementation of step S3;

[0054] Figure 15 This is a schematic diagram illustrating an application scenario for a many-core system.

[0055] Figure 16 for Figure 15 A block diagram of the core cluster in the diagram;

[0056] Figure 17 A block diagram showing the composition of the core cluster after the new subclusters are formed;

[0057] Figure 18 A block diagram of a core control device provided in an embodiment of this disclosure;

[0058] Figure 19 This is a block diagram of an electronic device provided in an embodiment of the present disclosure. Detailed Implementation

[0059] To enable those skilled in the art to better understand the technical solutions of this disclosure, exemplary embodiments of this disclosure are described below with reference to the accompanying drawings, including various details of the embodiments of this disclosure to aid understanding. These should be considered merely exemplary. Therefore, those skilled in the art should recognize that various changes and modifications can be made to the embodiments described herein without departing from the scope and spirit of this disclosure. Similarly, for clarity and conciseness, descriptions of well-known functions and structures are omitted in the following description.

[0060] Where there is no conflict, the various embodiments of this disclosure and the features thereof in the embodiments may be combined with each other.

[0061] As used herein, the term “and / or” includes any and all combinations of one or more related enumerated entries.

[0062] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. As used herein, the singular forms “a” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will also be understood that when the terms “comprising” and / or “made of” are used in this specification, the presence of the stated feature, integral, step, operation, element, and / or component is specified, but the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof is not excluded. Words such as “connected” or “linked” are not limited to physical or mechanical connections but can include electrical connections, whether direct or indirect.

[0063] Unless otherwise specified, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art. It will also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and this disclosure, and will not be interpreted as having an idealized or overly formal meaning, unless expressly so defined herein.

[0064] In this embodiment, the many-core system includes at least one core cluster, and each core cluster includes at least one second processing core. Each core cluster is used to execute a corresponding computing task. During the execution of tasks by each core cluster, especially in scenarios where each core cluster executes tasks in a task pipeline, there are high requirements for the task execution efficiency of each core cluster. Therefore, how to effectively improve the task execution efficiency of the core cluster has become a pressing technical problem to be solved in the core cluster scenario of a many-core system.

[0065] Figure 1 A flowchart of a core control method for a many-core system provided in an embodiment of this disclosure.

[0066] Reference Figure 1 This disclosure provides a core control method for a many-core system, wherein the many-core system includes at least one core cluster, each core cluster including at least one second processing core. The method can be executed by a core control device, which can be implemented in software and / or hardware. The core control method includes:

[0067] Step S1: For any core cluster, perform load detection on the core cluster and obtain the load data corresponding to the core cluster.

[0068] Step S2: Determine the load status of the core cluster based on the load data corresponding to the core cluster.

[0069] Step S3: Adjust the core cluster according to its load status.

[0070] The control processing includes one of the following control methods: controlling the number of second processing cores that can currently perform operations in the core cluster; controlling the operating voltage and operating frequency of the second processing cores that can currently perform operations in the core cluster; and inserting blank frames into the buffer corresponding to the core cluster.

[0071] In this embodiment of the disclosure, the load status of the core cluster can be obtained in real time, and the core cluster can be adjusted and processed in real time, so that the core cluster can handle tasks flexibly, improve the efficiency of task processing, and reduce the power consumption of the many-core system.

[0072] The core control method for many-core systems provided in this disclosure detects the load status of each core cluster and adjusts and processes each core cluster, thereby enabling flexible control and management of each core cluster in the many-core system, effectively improving the efficiency of each core cluster in executing tasks, and enhancing the flexibility of the many-core system in task processing.

[0073] Figure 2 A block diagram of a many-core system provided in this disclosure embodiment is shown. See also: Figure 2The many-core system includes multiple processing cores, comprising a first processing core and multiple second processing cores. Some or all of the second processing cores are pre-divided into at least one core cluster. Each core cluster has a master processing core, which is a pre-designated second processing core from among the at least one second processing core in that core cluster. The first processing core can handle tasks of the many-core system and perform task allocation and management. The master processing core of each core cluster can handle tasks within its cluster and perform task allocation and management within the cluster.

[0074] The core control method of this disclosure can be applied to the main processing core of any core cluster in a many-core system. That is, the core control method of this disclosure is implemented based on the main processing core of any core cluster. The main processing core of any core cluster can control and manage the second processing core of its core cluster through the core control method of this disclosure.

[0075] The core control method of this disclosure embodiment can also be applied to the first processing core of the many-core system. That is, the core control method of this disclosure embodiment is implemented based on the first processing core of the many-core system. The first processing core can control and manage all core clusters of the many-core system through the core control method of this disclosure embodiment.

[0076] In some embodiments, each core cluster is provided with a corresponding buffer, which is used to cache the task data of the tasks to be processed by the corresponding core cluster. Therefore, the memory state of the buffer can characterize the load of the core cluster. The buffer is a FIFO (First Input First Output) buffer.

[0077] In some embodiments, the load data of the core cluster can be obtained by monitoring the real-time memory space utilization of the cache corresponding to the core cluster. Figure 3 for Figure 1 A flowchart of a specific implementation of step S1 is shown below. Figure 3 As shown, step S1 may further include steps S11a to S13a.

[0078] Step S11a: Monitor the real-time memory space usage of the cache corresponding to the core cluster.

[0079] Among them, real-time memory space utilization rate (real-time memory space utilization ratio) refers to the ratio of the real-time used memory space to the total memory space.

[0080] Step S12a: Monitor the comparison result between the real-time memory space utilization rate of the cache corresponding to the core cluster and the first preset threshold.

[0081] The first preset threshold can be set according to actual needs. For example, the first preset threshold can be set to a value greater than or equal to 60% and less than 100%, such as 70%.

[0082] Step S13a: Record the duration for which the real-time memory space utilization rate is continuously greater than or equal to the first preset threshold, and record it as the first duration. The load data corresponding to the core cluster includes the first duration.

[0083] It is understandable that the real-time memory space utilization of the cache changes over time. Therefore, the duration for which the real-time memory space utilization is continuously greater than or equal to the first preset threshold refers to the duration for which the real-time memory space utilization is continuously greater than or equal to the first preset threshold. This can characterize the current load state of the cache, that is, the current load state of the core cluster.

[0084] Figure 4 for Figure 1 A flowchart of another specific implementation of step S1, as shown below. Figure 4 As shown, step S1 may further include steps S11b to S13b.

[0085] Step S11b: Monitor the real-time memory space usage of the cache corresponding to the core cluster.

[0086] Step S12b: Monitor the comparison result between the real-time memory space utilization rate of the cache corresponding to the core cluster and the second preset threshold.

[0087] The second preset threshold is greater than 0 and less than the first preset threshold. The second preset threshold can be set according to actual needs. For example, the second preset threshold can be set to a value less than or equal to 40%, such as 10% or 5%.

[0088] Step S13b: Record the duration for which the real-time memory space utilization rate is continuously less than or equal to the second preset threshold, and record it as the second duration. The load data corresponding to the core cluster includes the second duration.

[0089] It is understandable that the real-time memory space utilization of the cache changes over time. Therefore, the duration for which the real-time memory space utilization is continuously less than or equal to the second preset threshold refers to the duration for which the real-time memory space utilization is continuously in a state of less than or equal to the second preset threshold. This can characterize the current load state of the cache, that is, the current load state of the core cluster.

[0090] Figure 5 for Figure 1The flowchart shows a specific implementation of step S2. In some embodiments, when the load data corresponding to the core cluster includes the first duration mentioned above, step S2 may further include steps S21a and S22a.

[0091] Step S21a: Determine whether the first duration is greater than or equal to the first preset duration. If yes, proceed to step S22a. If no, no further processing is performed.

[0092] Step S22a: If the first duration is greater than or equal to the first preset duration, determine that the load status of the core cluster is busy.

[0093] In some embodiments, when the real-time memory space utilization rate of the cache corresponding to the core cluster is continuously greater than or equal to a first preset threshold, and the duration (first duration) is greater than or equal to the first preset duration, it indicates that the core cluster is in an overloaded state, i.e., a busy state.

[0094] If the duration (first duration) is less than the first preset duration, it indicates that the core cluster is not in a busy state, so no further processing is required.

[0095] The first preset duration can be set according to the actual situation, such as 15 minutes, half an hour or 1 hour.

[0096] Figure 6 for Figure 1 The flowchart of another specific implementation of step S2 is shown below. In some embodiments, when the load data corresponding to the core cluster includes the second duration mentioned above, step S2 may further include steps S21b and S22b.

[0097] Step S21b: Determine whether the second duration is greater than or equal to the second preset duration. If yes, proceed to step S22b; otherwise, no further processing is performed.

[0098] Step S22b: If the second duration is greater than or equal to the second preset duration, determine that the load state of the core cluster is a low load state.

[0099] In some embodiments, when the real-time memory space utilization rate of the cache corresponding to the core cluster is continuously less than or equal to a second preset threshold, and the duration (second duration) is greater than or equal to the second preset duration, it indicates that the core cluster is in a state of resource surplus, i.e., a low load state.

[0100] If the duration (second duration) is less than the second preset duration, it indicates that the core cluster is not in a low-load state, so no further processing is required.

[0101] The second preset duration can be set according to the actual situation. The second preset duration can be equal to the first preset duration, for example, it can be set to 15 minutes, half an hour or 1 hour.

[0102] In some embodiments, the real-time memory space utilization of the cache corresponding to the core cluster is monitored. The load data of the core cluster includes the real-time memory space utilization of the cache corresponding to the core cluster. If the real-time memory space utilization of the cache is continuously greater than or equal to a first preset threshold and the duration (first duration) is greater than or equal to the first preset duration, then the load state of the core cluster is determined to be busy. If the real-time memory space utilization of the cache is continuously less than or equal to a second preset threshold and the duration (second duration) is greater than or equal to the second preset duration, then the load state of the core cluster is determined to be low. If the real-time memory space utilization of the cache is continuously between the second preset threshold and the first preset threshold, or the duration of the state of being greater than or equal to the first preset threshold is less than the first preset duration and the duration of the state of being greater than or equal to the second preset threshold is less than the second preset duration, then the core cluster is neither busy nor idle, and the load state of the core cluster is an intermediate state, which is a state between the low load state and the busy state, so no further processing is required.

[0103] In some embodiments, the load data of a core cluster can be obtained by monitoring the memory space usage growth rate of the cache corresponding to the core cluster. Specifically, step S1 may further include: obtaining the memory space usage growth rate of the cache corresponding to the core cluster, wherein the load data corresponding to the core cluster includes the memory space usage growth rate of the corresponding cache.

[0104] The memory usage growth rate refers to the rate at which the cache's memory usage increases within a preset time period (e.g., 5 minutes, 10 minutes, or 15 minutes). Specifically, it's the ratio of the difference between the current memory usage rate and the historical memory usage rate to the historical memory usage rate. The preset time period is the time span from the historical time to the current time.

[0105] Figure 7 for Figure 1 The flowchart illustrates another specific implementation of step S2. In some embodiments, when core cluster load data is obtained by monitoring the memory space usage growth rate of the cache corresponding to the core cluster, such as... Figure 7 As shown, step S2 may further include steps S21c to S22c.

[0106] Step S21c: Determine whether the memory space usage growth rate of the cache corresponding to the core cluster is greater than or equal to the first preset growth rate value. If yes, proceed to step S22c; otherwise, no further processing is performed.

[0107] The first preset growth rate is a positive value, which can be set according to actual needs. For example, the first preset growth rate can be a value between 60% and 90%, such as 70%.

[0108] Step S22c: If the memory space usage growth rate is greater than or equal to the first preset growth rate value, determine that the load status of the core cluster is busy, and jump to step S3.

[0109] If the memory usage growth rate of the cache corresponding to the core cluster is greater than or equal to the first preset growth rate value, it indicates that the cache is in an overloaded state, which means that the core cluster is in an overloaded state, i.e., a busy state.

[0110] In some embodiments, if the memory space usage growth rate of the cache corresponding to the core cluster is less than the first preset growth rate value, it indicates that the cache is not in an overloaded state, that is, the core cluster is not in an overloaded state, i.e., not in a busy state. Therefore, no further processing is required, or step S21d can be further executed to determine whether the core cluster is in a low-load state.

[0111] Figure 8 for Figure 1 The flowchart of another specific implementation of step S2 shows that, in some embodiments, when the load data of the core cluster is obtained by monitoring the memory space usage growth rate and real-time memory space utilization rate of the corresponding cache, the load data of the core cluster includes the memory space usage growth rate and real-time memory space utilization rate of the corresponding cache. Figure 8 As shown, step S2 may further include steps S20d to S22d.

[0112] Step S20d: Determine whether the real-time memory space utilization rate of the cache corresponding to the core cluster is less than or equal to the preset utilization rate. If yes, proceed to step S21d; otherwise, no further processing is performed.

[0113] The preset usage rate can be set according to actual needs, for example, it can be set to 10%, 20% or 30%.

[0114] Step S21d: Determine whether the memory space usage growth rate is less than or equal to the second preset growth rate value. If yes, proceed to step S22d; otherwise, no further processing is performed.

[0115] The second preset growth rate value is a negative value that is greater than -1 and less than 0. The specific value of the second preset growth rate value can be set according to actual needs. For example, the second preset growth rate value can be a value between -90% and -50%, such as -60%.

[0116] If the real-time memory space utilization rate of the cache corresponding to the core cluster is less than or equal to the preset utilization rate, it is further determined whether the memory space utilization growth rate is less than or equal to the second preset growth rate value, thereby determining the load status of the core cluster.

[0117] Step S22d: If the memory space usage growth rate is less than or equal to the second preset growth rate value, determine that the load state of the core cluster is a low load state, and jump to step S3.

[0118] If the real-time memory space utilization rate of the cache corresponding to the core cluster is less than or equal to the preset utilization rate, and the memory space utilization growth rate of the cache corresponding to the core cluster is less than or equal to the second preset growth rate value, it indicates that the real-time memory space utilization rate of the cache corresponding to the core cluster is small, and the memory space utilization of the cache shows a significant negative growth, that is, it is in a state of resource surplus, which also indicates that the core cluster is in a state of resource surplus, or a low-load state.

[0119] In some embodiments, if the memory usage growth rate of the cache corresponding to the core cluster is less than a first preset growth rate value and greater than a second preset growth rate value, it indicates that the core cluster is neither busy nor idle, and the load state of the core cluster is an intermediate state, which is a state between a low load state and a busy state, so no further processing is required.

[0120] In some embodiments, the load data of a core cluster can also be obtained by monitoring the task processing status of the core cluster. Specifically, step S1 may further include: real-time monitoring of the task processing time required for the core cluster to process the task, wherein the load data corresponding to the core cluster includes the task processing time. It is understood that the task processing time refers to the time spent by the core cluster processing the task.

[0121] Figure 9 for Figure 1 A flowchart of another specific implementation of step S2 is shown below. Figure 9 As shown, in some embodiments, when the load data corresponding to the core cluster includes the task processing time, step S2 may further include steps S21e to S22e.

[0122] Step S21e: Determine whether the processing time required for the core cluster to process the task is greater than or equal to the first preset processing time. If yes, proceed to step S22e; otherwise, no further processing is performed.

[0123] The first preset processing time can be set according to actual needs.

[0124] Step S22e: If the processing time required for the core cluster to process the task is greater than or equal to the first preset processing time, determine that the load status of the core cluster is busy, and proceed to step S3.

[0125] If the processing time of the task corresponding to the core cluster is greater than or equal to the first preset processing time, it indicates that the core cluster takes a long time to process the task, and therefore it can be determined that the core cluster is in an overloaded state, i.e., a busy state.

[0126] In some embodiments, if the processing time of the task corresponding to the core cluster is less than the first preset processing time, it indicates that the core cluster is not in an overloaded state, that is, it is not in a busy state. Therefore, no further processing is required, or step S21f can be further executed to determine whether the core cluster is in a low-load state.

[0127] Figure 10 for Figure 1 A flowchart of another specific implementation of step S2 is provided. In some embodiments, when the load data corresponding to the core cluster includes task processing time, such as... Figure 10 As shown, step S2 may further include steps S21f to S22f.

[0128] Step S21f: Determine whether the processing time required for the core cluster to process the task is less than or equal to the second preset processing time. If yes, proceed to step S22f; otherwise, no further processing is performed.

[0129] The second preset processing time is shorter than the first preset processing time, and the second preset processing time can be set according to actual needs.

[0130] Step S22f: If the processing time required for the core cluster to process the task is less than or equal to the second preset processing time, determine that the load state of the core cluster is low load state, and jump to step S3.

[0131] If the processing time of the task corresponding to the core cluster is less than or equal to the second preset processing time, it indicates that the core cluster takes less time to process the task. Therefore, it can be determined that the core cluster is in a state of resource surplus, i.e., a low load state.

[0132] In some embodiments, if the processing time of the task corresponding to the core cluster is greater than the second preset processing time and less than the first preset processing time, it indicates that the core cluster is neither busy nor idle, and the load state of the core cluster is an intermediate state, which is a state between a low load state and a busy state, so no further processing is required.

[0133] In some embodiments, the many-core system includes multiple core clusters that process tasks based on a synchronization period, which is the longest processing time among all core clusters required to process the task. For example, the current task is face recognition of a video to be synthesized. This face recognition task includes multiple subtasks, such as video stream decoding, face detection, face feature recognition, feature extraction, and feature matching. Each core cluster is responsible for its corresponding subtask, and these subtasks constitute a task pipeline. That is, the result of the subtask processed by the previous core cluster needs to be sent to the next core cluster for processing. During the task pipeline processing, the multiple core clusters share a unified synchronization period, which is the longest processing time among all core clusters required to process their respective subtasks. After the synchronization period ends, the multiple core clusters can proceed to the next task, such as audio recognition and video synthesis of the video to be synthesized.

[0134] Figure 11 for Figure 1 A flowchart of another specific implementation of step S2 is shown below. Figure 11 As shown, in some embodiments, if the load data of each core cluster is monitored to include the task processing time of each core cluster, step S2 may further include steps S21g to S23g.

[0135] Step S21g: Calculate the task processing time corresponding to the core cluster within the preset monitoring time period and use it as the frequency of the synchronization cycle.

[0136] The preset monitoring time period can be any preset time period. In step S22e, the task processing time corresponding to the core cluster within the preset monitoring time period is counted as the number of synchronization cycles, i.e., the frequency.

[0137] Step S22g: Determine whether the frequency of the task processing time corresponding to the core cluster as the synchronization cycle within the preset monitoring time period is greater than or equal to the first preset number. If yes, proceed to step S23g; otherwise, no further processing is performed.

[0138] The first preset number of times can be set according to actual needs.

[0139] Step S23g: Determine that the load status of the core cluster is busy, and proceed to step S3.

[0140] If the frequency of the synchronization cycle corresponding to the task processing time of the core cluster is greater than or equal to a first preset number, it indicates that the task processing time of the core cluster is frequently at its maximum among all core clusters. Therefore, it can be determined that the core cluster is in an overloaded state, i.e., a busy state. If the frequency of the synchronization cycle corresponding to the task processing time of the core cluster is less than the first preset number, it indicates that the core cluster is not in an overloaded state, i.e., not in a busy state, and therefore no further processing is required.

[0141] Figure 12 for Figure 1 A flowchart of another specific implementation of step S2 is shown below. Figure 12 As shown, in some embodiments, if the load data of each core cluster is monitored to include the task processing time of each core cluster, step S2 may further include steps S21h to S24h.

[0142] Step S21h: Calculate the task processing time corresponding to the core cluster within the preset monitoring time period and use it as the frequency of the synchronization cycle.

[0143] For a description of step S21h, please refer to the description of step S21g above, which will not be repeated here.

[0144] Step S22h: Calculate the ratio of the frequency of the task processing time corresponding to the core cluster as the synchronization cycle to the number of synchronization cycles within the preset monitoring time period.

[0145] It is understandable that the number of synchronization cycles within the preset monitoring period is the same as the number of tasks processed by multiple core clusters within the preset monitoring period.

[0146] Step S23h: Determine whether the ratio is greater than or equal to the first preset ratio. If so, proceed to step S24h; otherwise, no further processing is performed.

[0147] The first preset ratio can be set according to actual needs.

[0148] Step S24h: Determine that the load status of the core cluster is busy, and proceed to step S3.

[0149] If the ratio is greater than or equal to the first preset ratio, it indicates that the task processing time of this core cluster is frequently at its maximum among all core clusters, thus confirming that the core cluster is in an overloaded state, i.e., a busy state. If the ratio is less than the first preset ratio, it indicates that the core cluster is not in an overloaded state, i.e., not a busy state, and therefore no further processing is required.

[0150] In some embodiments, if the load state of the core cluster is determined to be busy, step S3 may further include: increasing the number of second processing cores in the core cluster that are currently available for work.

[0151] Figure 13 for Figure 1 A flowchart of a specific implementation of step S3 is provided. In some embodiments, when the load state of the core cluster is determined to be busy, such as... Figure 13 As shown, step S3 may further include: steps S31a to S33a.

[0152] Step S31a: If the load state of the core cluster is busy, determine whether the core cluster has an adjustable voltage domain and frequency domain. If yes, proceed to step S32a; otherwise, proceed to step S33a.

[0153] Specifically, when the load status of the core cluster is busy, it checks whether there are multiple second processing cores in the core cluster that are currently capable of operation and have the same operating voltage and frequency, and whose operating voltage and frequency are adjustable. If so, it is determined that the core cluster has an adjustable voltage domain and frequency domain; otherwise, it is determined that the core cluster does not have an adjustable voltage domain and frequency domain. Here, having an adjustable voltage domain means that multiple second processing cores in the core cluster correspond to one operating voltage and the operating voltage is adjustable, and all corresponding second processing cores share the same operating voltage setting within the same adjustable voltage domain. Having an adjustable frequency domain means that multiple second processing cores in the core cluster correspond to one operating frequency and the operating frequency is adjustable, and all corresponding second processing cores share the same operating frequency setting within the same adjustable frequency domain. In other words, if there are multiple second processing cores in the core cluster operating at the same operating voltage, then the core cluster has a voltage domain. Furthermore, when the operating voltage is adjustable, it means that the voltage domain is an adjustable voltage domain. Correspondingly, the operating voltage and the operating frequency are linearly related, so the core cluster has an adjustable frequency domain.

[0154] Step S32a: Increase the operating voltage and operating frequency of the second processing core corresponding to the adjustable voltage and frequency domains in the currently operable second processing core of the core cluster, and end the process.

[0155] When the load state of the core cluster is busy, the operating voltage and operating frequency of some or all of the second processing cores corresponding to the adjustable voltage and frequency domains in the core cluster can be increased, thereby improving the operating efficiency of some or all of the second processing cores, thus improving the efficiency of the task processing of some or all of the second processing cores, and consequently improving the overall task processing efficiency of the core cluster.

[0156] As an example, if the load state of the core cluster is determined to be busy based on the comparison result of the first duration and the first preset duration, the voltage adjustment range corresponding to the first duration can be determined according to the preset correspondence between the duration and voltage adjustment range in the busy state, and the frequency adjustment range corresponding to the first duration can be determined according to the preset correspondence between the duration and frequency adjustment range in the busy state. Further, based on the voltage adjustment range corresponding to the first duration, the operating voltage of the second processing core corresponding to the adjustable voltage and frequency domains is increased to the corresponding voltage, so that the second processing core operates based on the adjusted operating voltage; and based on the frequency adjustment range corresponding to the first duration, the operating frequency of the second processing core corresponding to the adjustable voltage and frequency domains is increased to the corresponding frequency, so that the second processing core operates based on the adjusted operating frequency.

[0157] In busy conditions, the correspondence between duration and voltage adjustment range, as well as the correspondence between duration and frequency adjustment range, can be set according to actual needs. For example, assuming the first preset duration is 10 minutes, the voltage adjustment range corresponding to a duration of 10 to 20 minutes can be set to 10%, the voltage adjustment range corresponding to a duration of 20 to 40 minutes to 15%, the voltage adjustment range corresponding to a duration of 40 to 50 minutes to 20%, and so on. Similarly, the correspondence between duration and frequency adjustment range can be set, which will not be elaborated here.

[0158] As an example, if the first duration is 15 minutes and the first preset duration is 10 minutes, and according to the correspondence between the duration and voltage adjustment range in the preset busy state, it is found that the voltage adjustment range corresponding to the first duration is 10%, then the working voltage of the second processing core corresponding to the adjustable voltage domain and frequency domain is increased by 10%. The adjustment of the working frequency is similar and will not be elaborated here.

[0159] As an example, if the load state of the core cluster is determined to be busy based on the comparison result of the memory usage growth rate and the first preset growth rate value, the voltage adjustment range corresponding to the memory usage growth rate of the core cluster can be determined according to the preset correspondence between the memory usage growth rate and the voltage adjustment range under busy conditions. Similarly, the frequency adjustment range corresponding to the memory usage growth rate of the core cluster can be determined according to the preset correspondence between the memory usage growth rate and the frequency adjustment range under busy conditions. Further, based on the voltage adjustment range corresponding to the memory usage growth rate of the core cluster, the operating voltage of the second processing core corresponding to the adjustable voltage and frequency domains is increased to the corresponding voltage, so that the second processing core operates based on the adjusted operating voltage. And, based on the frequency adjustment range corresponding to the memory usage growth rate of the core cluster, the operating frequency of the second processing core corresponding to the adjustable voltage and frequency domains is increased to the corresponding frequency, so that the second processing core operates based on the adjusted operating frequency.

[0160] In particular, the correspondence between the increase in memory usage and the voltage adjustment range, as well as the correspondence between the increase in memory usage and the frequency adjustment range under busy conditions, can be set according to actual needs. For details, please refer to the above explanation of the correspondence between the duration and voltage adjustment range and the duration and frequency adjustment range under busy conditions, which will not be repeated here.

[0161] As an example, if the load state of the core cluster is determined to be busy based on the comparison result between the task processing time of the core cluster and the first preset processing time, the voltage adjustment range corresponding to the task processing time of the core cluster can be determined according to the preset correspondence between the task processing time and the voltage adjustment range under busy conditions. Similarly, the frequency adjustment range corresponding to the task processing time of the core cluster can be determined according to the preset correspondence between the task processing time and the frequency adjustment range under busy conditions. Further, based on the voltage adjustment range corresponding to the task processing time of the core cluster, the operating voltage of the second processing core corresponding to the adjustable voltage and frequency domains is increased to the corresponding voltage, so that the second processing core operates based on the adjusted operating voltage. And, based on the frequency adjustment range corresponding to the task processing time of the core cluster, the operating frequency of the second processing core corresponding to the adjustable voltage and frequency domains is increased to the corresponding frequency, so that the second processing core operates based on the adjusted operating frequency.

[0162] In the case of busy conditions, the correspondence between task processing time and voltage adjustment range, as well as the correspondence between task processing time and frequency adjustment range, can be set according to actual needs. For details, please refer to the above explanation of the correspondence between time and voltage adjustment range and the correspondence between time and frequency adjustment range in busy conditions, which will not be repeated here.

[0163] As an example, if the load state of the core cluster is determined to be busy based on the comparison result between the frequency corresponding to the core cluster and the first preset number of times, the voltage adjustment range corresponding to the frequency of the core cluster can be determined according to the preset correspondence between the frequency and the voltage adjustment range in the busy state, and the frequency adjustment range corresponding to the frequency of the core cluster can be determined according to the preset correspondence between the frequency and the frequency adjustment range in the busy state. Further, based on the voltage adjustment range corresponding to the frequency of the core cluster, the operating voltage of the second processing core corresponding to the adjustable voltage and frequency domains is increased to the corresponding voltage, so that the second processing core operates based on the adjusted operating voltage; and based on the frequency adjustment range corresponding to the frequency of the core cluster, the operating frequency of the second processing core corresponding to the adjustable voltage and frequency domains is increased to the corresponding frequency, so that the second processing core operates based on the adjusted operating frequency.

[0164] In the busy state, the correspondence between frequency and voltage adjustment amplitude, as well as the correspondence between frequency and frequency adjustment amplitude, can be set according to actual needs. For details, please refer to the above explanation of the correspondence between duration and voltage adjustment amplitude and duration and frequency adjustment amplitude in the busy state, which will not be repeated here.

[0165] Step S33a: Increase the number of second processing cores that can currently perform jobs in the core cluster, and end the process.

[0166] When the core cluster is in a busy state, the overall processing efficiency of the core cluster can be improved by increasing the number of second processing cores that are currently available for work.

[0167] In some embodiments, the number of additional currently available second processing cores required to perform tasks can be determined based on the busyness of the core cluster, which can be characterized, for example, by the first duration, the growth rate of memory space usage, the task processing duration, or the frequency.

[0168] As an example, a correspondence between the duration of a busy state and the number of cores to be added can be preset. If the load state of the core cluster is determined to be busy based on the comparison result between the first duration and the first preset duration, the number of cores to be added corresponding to the first duration can be determined based on the preset correspondence between the duration of the busy state and the number of cores to be added, so as to add a corresponding number of currently available second processing cores to the core cluster.

[0169] Similarly, the number of second processing cores that need to be added for currently available jobs can be determined by pre-setting the correspondence between the growth rate of memory space usage under busy conditions and the number of cores required, the correspondence between the task processing time under busy conditions and the number of cores required, or the correspondence between the frequency under busy conditions and the number of cores required.

[0170] In some embodiments, the step of increasing the number of second processing cores currently available for work in the core cluster may further include: adding one or more idle second processing cores outside the core cluster in the many-core system to the core cluster as second processing cores currently available for work in the core cluster.

[0171] In some embodiments, the step of increasing the number of second processing cores currently capable of performing tasks in the core cluster may further include: waking up one or more second processing cores in the core cluster that are in a shutdown state, so as to serve as second processing cores currently capable of performing tasks in the core cluster.

[0172] Specifically, each second processing core has a controller for controlling the second processing core to turn off or wake up (turn on). The second processing core can be woken up by sending a wake-up command to the controller of the second processing core, and the second processing core can be turned off by sending a shutdown command to the controller of the second processing core.

[0173] In some embodiments, when the load state of the core cluster is determined to be low, step S3 may further include: reducing the number of second processing cores in the core cluster that are currently available for work.

[0174] Figure 14 for Figure 1 The flowchart shows another specific implementation of step S3. In some embodiments, when the load state of the core cluster is determined to be low, such as... Figure 14 As shown, step S3 may further include: steps S31b to S33b.

[0175] Step S31b: When the load state of the core cluster is low load, determine whether the core cluster has adjustable voltage and frequency domains. If yes, proceed to step S32b; otherwise, proceed to step S33b.

[0176] Specifically, when the load state of the core cluster is low load, check whether there are multiple second processing cores that have the same operating voltage and operating frequency and whose voltage and frequency are adjustable among all the second processing cores that can currently perform operations in the core cluster. If they exist, it is determined that the core cluster has an adjustable voltage domain and frequency domain; otherwise, it is determined that the core cluster does not have an adjustable voltage domain and frequency domain.

[0177] Step S32b: Lower the operating voltage and / or operating frequency of the second processing core in the currently operable second processing core of the core cluster, corresponding to the adjustable voltage and frequency domains, and end the process.

[0178] When the load state of the core cluster is low, the operating voltage and operating frequency of some or all of the second processing cores corresponding to the adjustable voltage and frequency domains in the core cluster can be reduced, thereby reducing the operating efficiency of some or all of the second processing cores, effectively saving the power consumption of the core cluster, reducing the power consumption of the many-core system, and conserving resources.

[0179] As an example, if the load state of the core cluster is determined to be a low-load state based on the comparison result of the second duration and the second preset duration, the voltage adjustment range corresponding to the second duration can be determined according to the preset correspondence between the duration and voltage adjustment range under the low-load state, and the frequency adjustment range corresponding to the second duration can be determined according to the preset correspondence between the duration and frequency adjustment range under the low-load state. Further, based on the voltage adjustment range corresponding to the second duration, the operating voltage of the second processing core corresponding to the adjustable voltage and frequency domains is lowered to the corresponding voltage, so that the second processing core operates based on the adjusted operating voltage; and based on the frequency adjustment range corresponding to the second duration, the operating frequency of the second processing core corresponding to the adjustable voltage and frequency domains is lowered to the corresponding frequency, so that the second processing core operates based on the adjusted operating frequency.

[0180] The correspondence between duration and voltage adjustment, as well as the correspondence between duration and frequency adjustment, under low load conditions can be set according to actual needs. For example, assuming the second preset duration is 10 minutes, the voltage adjustment range corresponding to a duration of 10 to 20 minutes can be set to 10%, the range to 20 to 40 minutes to 15%, the range to 40 to 50 minutes to 20%, and so on. Similarly, the correspondence between duration and frequency adjustment under low load conditions can be set, which will not be elaborated here.

[0181] As an example, if the second duration is 15 minutes and the second preset duration is 10 minutes, and according to the preset correspondence between duration and voltage adjustment range under low load conditions, the voltage adjustment range corresponding to the second duration is found to be 10%, then the operating voltage of the second processing core with voltage and frequency domains will be reduced by 10%. The adjustment of the operating frequency is similar and will not be elaborated here.

[0182] As an example, if the load state of the core cluster is determined to be low load based on the comparison result between the memory usage growth rate and the second preset growth rate value, the voltage adjustment range corresponding to the memory usage growth rate of the core cluster can be determined according to the preset correspondence between the memory usage growth rate and the voltage adjustment range under low load conditions. Similarly, the frequency adjustment range corresponding to the memory usage growth rate of the core cluster can be determined according to the preset correspondence between the memory usage growth rate and the frequency adjustment range under low load conditions. Further, based on the voltage adjustment range corresponding to the memory usage growth rate of the core cluster, the operating voltage of the second processing core corresponding to the adjustable voltage and frequency domains is lowered to the corresponding voltage, so that the second processing core operates based on the adjusted operating voltage. And, based on the frequency adjustment range corresponding to the memory usage growth rate of the core cluster, the operating frequency of the second processing core corresponding to the adjustable voltage and frequency domains is lowered to the corresponding frequency, so that the second processing core operates based on the adjusted operating frequency.

[0183] The relationships between memory usage growth rate and voltage adjustment magnitude, and between memory usage growth rate and frequency adjustment magnitude under low load conditions, can be set according to actual needs. For details, please refer to the above explanation of the relationships between duration and voltage adjustment magnitude and duration and frequency adjustment magnitude under low load conditions, which will not be repeated here.

[0184] As an example, if the load state of the core cluster is determined to be low load based on the comparison result between the task processing time of the core cluster and the second preset processing time, the voltage adjustment range corresponding to the task processing time of the core cluster can be determined according to the preset correspondence between the task processing time and the voltage adjustment range under low load conditions. Similarly, the frequency adjustment range corresponding to the task processing time of the core cluster can be determined according to the preset correspondence between the task processing time and the frequency adjustment range under low load conditions. Further, based on the voltage adjustment range corresponding to the task processing time of the core cluster, the operating voltage of the second processing core corresponding to the adjustable voltage and frequency domains is lowered to the corresponding voltage, so that the second processing core operates based on the adjusted operating voltage. And, based on the frequency adjustment range corresponding to the task processing time of the core cluster, the operating frequency of the second processing core corresponding to the adjustable voltage and frequency domains is lowered to the corresponding frequency, so that the second processing core operates based on the adjusted operating frequency.

[0185] In particular, the correspondence between task processing time and voltage adjustment range, and the correspondence between task processing time and frequency adjustment range under low load conditions can be set according to actual needs. For details, please refer to the above explanation of the correspondence between time and voltage adjustment range and the correspondence between time and frequency adjustment range under low load conditions, which will not be repeated here.

[0186] Step S33b: Reduce the number of second processing cores currently capable of performing jobs in the core cluster, and end the process.

[0187] When the load state of the core cluster is low, the power consumption of the core cluster can be reduced by decreasing the number of second processing cores that are currently available for operation in the core cluster, thereby reducing the power consumption of the many-core system and conserving resources.

[0188] In some embodiments, the number of second processing cores that need to be reduced from currently available jobs can be determined based on the low load level of the core cluster, which can be characterized, for example, by the second duration, the task processing duration, or the frequency.

[0189] As an example, a correspondence between the duration of low load and the required reduction in the number of cores can be preset. If the load state of the core cluster is determined to be low load based on the comparison result of the second duration and the second preset duration, the required reduction in the number of cores corresponding to the second duration can be determined based on the preset correspondence between the duration of low load and the required reduction in the number of cores, so as to reduce the corresponding number of currently available second processing cores in the core cluster.

[0190] Similarly, the number of second processing cores that need to be reduced can be determined by pre-setting the correspondence between the memory space usage growth rate under low load conditions and the number of cores to be reduced, the correspondence between the task processing time under low load conditions and the number of cores to be reduced, or the correspondence between the frequency under low load conditions and the number of cores to be reduced.

[0191] In some embodiments, the step of reducing the number of second processing cores currently capable of performing tasks in the core cluster may further include: removing at least one second processing core currently capable of performing tasks from the core cluster.

[0192] In some embodiments, the step of reducing the number of second processing cores currently capable of performing tasks in the core cluster may further include: controlling at least one second processing core currently capable of performing tasks in the core cluster to be in a turned-off state.

[0193] Figure 15 This is a schematic diagram of an application scenario for a many-core system. In one application scenario, such as... Figure 15 As shown, the many-core system can be used to process various tasks in the business pipeline. For example, the business is a face recognition business. The various tasks in the face recognition business pipeline may include video stream decoding, face detection, face feature recognition, face feature extraction, and face feature matching tasks that need to be executed sequentially.

[0194] In this many-core system, each core cluster can correspond to and process a task in the task pipeline. Each core cluster processes its corresponding task sequentially according to the pipeline's job order. Within the task pipeline, for each core cluster, the task data after processing its corresponding task can be sent to a cache corresponding to the core cluster following it in the pipeline for caching. This allows the subsequent core clusters to read the data as needed and begin running their corresponding tasks. The cache can also buffer data transmitted from other external devices.

[0195] For any core cluster, the data processing logic within that core cluster may include data parallel processing logic. Figure 16 for Figure 15 A block diagram of the core cluster in the image, as shown below. Figure 16As shown, each core cluster contains multiple sub-clusters, and each sub-cluster contains at least one second processing core that can currently perform tasks. These multiple sub-clusters are used to process the task corresponding to their respective core cluster in parallel. For example, if the task corresponding to a core cluster is face recognition, after acquiring multiple frames of image data, each of the multiple sub-clusters of that core cluster can be responsible for performing face recognition based on one or more frames of image data. Assuming there are three sub-clusters and three frames of images, then each of the three sub-clusters can process one frame of image data respectively.

[0196] In such Figure 16 In the scenario shown, when the load state of the core cluster is busy and the number of second processing cores that can currently perform jobs in the core cluster is increased, after the step of increasing the number of second processing cores that can currently perform jobs in the core cluster, the core control method may further include: steps S4a to S6a.

[0197] Step S4a: Based on the newly added second processing core that can currently perform operations in the core cluster, construct a new sub-cluster of the core cluster and obtain the configuration information of the new sub-cluster.

[0198] Figure 17 The block diagram showing the composition of the core cluster after the new subclusters are formed is as follows: Figure 17 As shown, in step S4a, one or more newly added currently executable second processing cores can be designated as new subclusters of the core cluster, and the configuration information of the new subclusters can be obtained. The new subclusters can process the tasks corresponding to the core cluster in parallel with other subclusters. The new subclusters include one or more newly added currently executable second processing cores, and the configuration information includes, but is not limited to, the number of second processing cores in the new subclusters and the address information of each second processing core.

[0199] Step S5a: Send the configuration information of the new sub-cluster to the target processing core in the predecessor core cluster of the core cluster, so that the target processing core in the predecessor core cluster can establish the input distribution of the new sub-cluster according to the configuration information of the new sub-cluster of the core cluster.

[0200] In some embodiments, in step S5a, the main processing core of the core cluster sends the configuration information of the new sub-cluster to the target processing core in the predecessor core cluster of the core cluster.

[0201] In this context, the predecessor core cluster is the core cluster preceding the current core cluster in the task pipeline. The target processing core in the predecessor core cluster is used to establish the input routing for the new sub-cluster based on its configuration information. The input routing is the path from the predecessor core cluster to the new sub-cluster for output data. The target processing core in the predecessor core cluster can be either the main processing core or the second processing core responsible for data output.

[0202] Specifically, the successor core cluster may include a task scheduler, which can be configured in the second processing core responsible for data output in the successor core cluster, or in the main processing core of the successor core cluster. The task scheduler maintains a successor task list, which indicates information such as the number of sub-clusters of the next core cluster in the task pipeline of the successor core cluster, the number of second processing cores included in each sub-cluster, and the address of each sub-cluster.

[0203] In this context, each sub-cluster of the core cluster marked in the predecessor task list is assigned a flag bit. The value of the flag bit represents the status of the corresponding sub-cluster. For example, when the flag bit is valid, it means that the corresponding sub-cluster is currently available, while when the flag bit is invalid, it means that the corresponding sub-cluster is unavailable.

[0204] A predecessor core cluster can allocate tasks to its subclusters based on its maintained predecessor task list. Specifically, a predecessor core cluster can update its maintained predecessor task list based on updates received from a subsequent and adjacent core cluster in the task pipeline. For example, after a core cluster adds a new subcluster, the core cluster's main processing core can send the configuration information of the new subcluster to its predecessor core cluster. This allows the predecessor core cluster's target processing core to write the configuration information into its predecessor task list and set the flag corresponding to the newly added subcluster to a valid value.

[0205] Step S6a: Send the configuration information of the new sub-cluster to the target processing core in the successor core cluster of the core cluster, so that the target processing core in the successor core cluster can establish the output distribution of the new sub-cluster according to the configuration information of the new sub-cluster of the core cluster.

[0206] In some embodiments, in step S6a, the main processing core of the core cluster sends the configuration information of the new sub-cluster to the target processing core in the successor core cluster of the core cluster.

[0207] In this context, the successor core cluster is the next core cluster in the task pipeline. The target processing core within the successor core cluster is used to establish the output routing for the new sub-cluster based on its configuration information. This output routing is the path from the new sub-cluster to the successor core cluster. The target processing core in the successor core cluster can be either the main processing core or the second processing core responsible for data output.

[0208] In some embodiments, the target processing core of the successor core cluster may maintain a successor task list as needed. The successor task list is marked with information such as the number of sub-clusters of the previous core cluster in the task pipeline where the successor core cluster is located, the number of second processing cores included in each sub-cluster, and the address of each sub-cluster.

[0209] Successor core clusters can update their maintained list of successor tasks based on updates passed from a preceding and adjacent core cluster in the task pipeline. For example, after a core cluster adds a new sub-cluster, the core cluster's main processing core can send the configuration information of the new sub-cluster to its successor core cluster, so that the target processing core of the successor core cluster can write the configuration information into its list of successor tasks.

[0210] In some embodiments, the step of reducing the number of second processing cores currently capable of performing jobs in the core cluster may include: reducing the number of subclusters currently capable of performing jobs in the core cluster, or reducing the number of second processing cores in any one or more subclusters of the core cluster. After reducing the number of subclusters currently capable of performing jobs in the core cluster or reducing the number of second processing cores in any one or more subclusters of the core cluster, the main processing core of the core cluster may send update information of the core cluster to the predecessor core cluster and the successor core cluster, so that the predecessor core cluster updates its maintained predecessor task list, updates the flag bits corresponding to the subclusters, and deletes the corresponding input streams, and the successor core cluster updates its maintained successor task list and deletes the corresponding output streams.

[0211] In some embodiments, during the monitoring of the real-time memory space utilization of the cache corresponding to the core cluster, if the real-time memory space utilization is 0, and the second duration of the utilization being 0 is greater than or equal to a second preset duration and less than a third preset duration, then the load state of the core cluster is determined to be an idle state, and the idle state level is the first level. Here, the idle state can be understood as an underloaded state or a zero-load state, which is a low-load state under special circumstances.

[0212] The third preset duration is longer than the second preset duration, and the third preset duration can be set according to actual needs.

[0213] In some embodiments, during the process of monitoring the real-time memory space utilization of the cache corresponding to the core cluster, if the real-time memory space utilization is 0 and the second duration of the utilization is greater than or equal to the third preset duration, then the load state of the core cluster is determined to be idle, and the idle state level is the second level.

[0214] In some embodiments, when the load state of the core cluster is determined to be idle and the idle state level is the first level, the step of regulating the core cluster according to the load state of the core cluster includes: when the load state of the core cluster is the first level idle state, inserting blank frames into the buffer corresponding to the core cluster, wherein the blank frames can be preset frame images, thereby maintaining the working state of the core cluster and ensuring that the core cluster outputs the processed data.

[0215] In some embodiments, for each second processing core in each core cluster, a corresponding gated clock can be set to control whether the corresponding second processing core is working or not.

[0216] In some embodiments, when the load state of the core cluster is determined to be idle, and the idle state level is the first level, after inserting a blank frame into the buffer corresponding to the core cluster and waiting for the core cluster to output the processed data, the gated clocks corresponding to each second processing core in the core cluster are turned off, so that each second processing core in the core cluster is in a non-working state. This can save resources of the many-core system, achieve power saving effect, and reduce the power consumption of the many-core system. The gated clock is used to output clock signals to the multiple core clusters to drive the multiple core clusters to work or not work based on the clock signal.

[0217] In some embodiments, the many-core system includes multiple core clusters, and the core control method is implemented by a first processing core, which uniformly monitors and manages the load of each core cluster. When multiple core clusters are processing the same task, and the monitored load states of these multiple core clusters are all in a first-level idle state, after inserting blank frames into the buffers corresponding to these multiple core clusters, the core control method further includes: pausing the transmission of synchronization signals to these multiple core clusters, so that these multiple core clusters can pause synchronous updates, thereby saving resources of the many-core system, achieving power saving, and reducing the power consumption of the many-core system. The synchronization signal is used to control the multiple core clusters to process tasks based on a synchronization cycle.

[0218] Specifically, the same task processed by multiple core clusters can be, for example, a face recognition task in a video to be synthesized. When the load status of the multiple core clusters is monitored to be at the first level of idle state, blank frames are first inserted into the buffers of each core cluster to maintain the working state of the multiple core clusters. After the multiple core clusters output all the processed data, after the multiple core clusters have no data input and no data output, the sending of synchronization signals to the multiple core clusters is paused, or the door control clocks corresponding to the multiple core clusters are turned off at the same time.

[0219] In some embodiments, when it is determined that the load state of the core cluster is idle and the idle state level is second level, the step of adjusting the core cluster according to the load state of the core cluster includes: when the load state of the core cluster is the second level idle state, lowering the operating voltage and operating frequency of the second processing cores corresponding to the adjustable voltage and frequency domains of the currently operable second processing cores of the core cluster, or reducing the number of currently operable second processing cores in the core cluster.

[0220] Figure 18 This is a block diagram of a core control device provided in an embodiment of the present disclosure.

[0221] Reference Figure 18 This disclosure provides a core control device 300, which is applied to a many-core system. The many-core system includes at least one core cluster, and each core cluster includes at least one second processing core. The core control device 300 includes: a load data detection module 301, a load status detection module 302, and a core regulation module 303.

[0222] The load data detection module 301 is configured to perform load detection on the corresponding core cluster and obtain the load data corresponding to the core cluster; the load status detection module 302 is configured to determine the load status of the core cluster based on the load data corresponding to the core cluster; the core control module 303 is configured to perform control processing on the core cluster based on the load status of the core cluster; wherein the control processing includes one of the following control methods: controlling the number of second processing cores that can currently perform operations in the core cluster; controlling the operating voltage and operating frequency of the second processing cores that can currently perform operations in the core cluster; inserting blank frames into the buffer corresponding to the core cluster.

[0223] Furthermore, the core control device 300 provided in this embodiment is used to implement the core control method described above. Other descriptions of the core control device 300 can be found in the description of the core control method described above, and will not be repeated here.

[0224] This disclosure also provides a processing core, which includes the core control device described above.

[0225] This disclosure also provides a many-core system, which includes multiple processing cores, including a first processing core and multiple second processing cores. Some or all of the multiple second processing cores are divided into at least one core cluster. Each core cluster includes at least one second processing core and each core cluster has a master processing core, which is a designated second processing core in the core cluster.

[0226] In the many-core system, the first processing core adopts a processing core that includes the aforementioned core control device, and / or, at least a portion of the core clusters' main processing cores adopt the aforementioned processing core that includes the aforementioned core control device.

[0227] Figure 19 This is a block diagram of an electronic device provided in an embodiment of the present disclosure.

[0228] Reference Figure 19This disclosure provides an electronic device that includes multiple processing cores 701 and an on-chip network 702. The multiple processing cores 701 are all connected to the on-chip network 702, which is used to exchange data between the multiple processing cores and external data.

[0229] One or more processing cores 701 store one or more instructions, and the one or more instructions are executed by one or more processing cores 701 to enable one or more processing cores 701 to execute the core control method described above.

[0230] Furthermore, this disclosure also provides a computer-readable medium having a computer program stored thereon, wherein the computer program implements the aforementioned core control method when executed by a processing core.

[0231] This disclosure also provides a computer program product, which includes a computer program that implements the above-described core control method when executed by a processing core.

[0232] It will be understood by those skilled in the art that all or some of the steps, systems, or apparatuses disclosed above, and their functional modules / units, can be implemented as software, firmware, hardware, or suitable combinations thereof. In hardware implementations, the division between functional modules / units mentioned in the above description does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be performed collaboratively by several physical components. Some or all physical components may be implemented as software executed by a processor, such as a central processing unit, digital signal processor, or microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit (ASIC). Such software may be distributed on a computer-readable medium, which may include computer storage media (or non-transitory media) and communication media (or transient media). As is known to those skilled in the art, the term computer storage media includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technologies, CD-ROM, digital versatile disc (DVD) or other optical disc storage, magnetic cartridges, magnetic tape, disk storage or other magnetic storage devices, or any other medium that can be used to store desired information and can be accessed by a computer. Furthermore, it is well known to those skilled in the art that communication media typically contain computer-readable instructions, data structures, program modules, or other data in modulated data signals such as carrier waves or other transmission mechanisms, and may include any information delivery medium.

[0233] Example embodiments have been disclosed herein, and while specific terminology has been used, it is for illustrative purposes only and should be construed as such, and is not intended to be limiting. In some instances, it will be apparent to those skilled in the art that features, characteristics, and / or elements described in connection with particular embodiments may be used alone, or in combination with features, characteristics, and / or elements described in connection with other embodiments, unless otherwise expressly indicated. Therefore, those skilled in the art will understand that various changes in form and detail may be made without departing from the scope of this disclosure as set forth by the appended claims.

Claims

1. A core control method for a many-core system, the many-core system comprising at least one core cluster, each core cluster comprising at least one second processing core, the core control method comprising: For any one of the core clusters, perform load detection on the core cluster and obtain the load data corresponding to the core cluster. Based on the load data corresponding to the core cluster, determine the load status of the core cluster; Based on the load status of the core cluster, adjust and process the core cluster accordingly; Each of the core clusters is provided with a corresponding buffer, which is used to cache the task data of the task to be processed by the corresponding core cluster; The process of performing load detection on the core cluster and obtaining the load data corresponding to the core cluster includes: The comparison result between the real-time memory space utilization rate of the cache corresponding to the core cluster and the second preset threshold is monitored, wherein the second preset threshold is greater than 0 and less than the first preset threshold; The duration during which the real-time memory space utilization rate is continuously less than or equal to the second preset threshold is recorded and recorded as the second duration. The load data corresponding to the core cluster includes the second duration. Based on the load data corresponding to the core cluster, determine the load status of the core cluster, including: If the real-time memory space utilization rate is 0, and the second duration that is continuously 0 is greater than or equal to the second preset duration and less than the third preset duration, then the load state of the core cluster is determined to be idle, and the idle state level is the first level. If the real-time memory space utilization rate is 0, and the second duration of the continuous 0 is greater than or equal to the third preset duration, then the load state of the core cluster is determined to be idle, and the idle state level is the second level. The process of adjusting the core cluster based on its load status includes: When the load state of the core cluster is at the first level of idle state, insert blank frames into the buffer corresponding to the core cluster; When the load state of the core cluster is the second level of idle state, the operating voltage and operating frequency of the second processing core corresponding to the adjustable voltage and frequency domains of the currently operable second processing core of the core cluster are reduced, or the number of currently operable second processing cores in the core cluster is reduced.

2. The core control method according to claim 1, The step of performing load detection on the core cluster and obtaining the load data corresponding to the core cluster includes: Monitor the real-time memory space utilization of the cache corresponding to the core cluster; The comparison result between the real-time memory space utilization rate of the cache corresponding to the core cluster and the first preset threshold is monitored; The duration during which the real-time memory space utilization rate is continuously greater than or equal to the first preset threshold is recorded and recorded as the first duration. The load data corresponding to the core cluster includes the first duration.

3. The core control method according to claim 2, wherein determining the load state of the core cluster based on the load data corresponding to the core cluster includes: Determine whether the first duration is greater than or equal to the first preset duration; If the first duration is greater than or equal to the first preset duration, the load status of the core cluster is determined to be busy.

4. The core control method according to claim 1, wherein determining the load state of the core cluster based on the load data corresponding to the core cluster includes: Determine whether the second duration is greater than or equal to the second preset duration; If the second duration is greater than or equal to the second preset duration, the load state of the core cluster is determined to be a low load state.

5. The core control method according to claim 1, wherein each core cluster is provided with a corresponding buffer, the buffer being used to cache task data of the task to be processed by the corresponding core cluster; The step of performing load detection on the core cluster and obtaining the load data corresponding to the core cluster includes: Obtain the memory space usage growth rate of the cache corresponding to the core cluster. The load data corresponding to the core cluster includes the memory space usage growth rate of the corresponding cache.

6. The core control method according to claim 5, wherein determining the load state of the core cluster based on the load data corresponding to the core cluster includes: Determine whether the growth rate of memory space usage is greater than or equal to a first preset growth rate value; If the memory space usage growth rate is greater than or equal to a first preset growth rate value, the load status of the core cluster is determined to be busy.

7. The core control method according to claim 5, wherein, The load data corresponding to the core cluster also includes the real-time memory space utilization rate of the corresponding cache. Determining the load status of the core cluster based on the load data includes: If the real-time memory space utilization rate of the cache corresponding to the core cluster is less than or equal to a preset utilization rate, it is determined whether the memory space utilization growth rate is less than or equal to a second preset growth rate value, where the second preset growth rate value is negative. If the growth rate of memory space usage is less than or equal to the second preset growth rate value, the load state of the core cluster is determined to be a low load state.

8. The core control method according to any one of claims 1-7, wherein the buffer is a FIFO buffer.

9. The core control method according to claim 1, wherein performing load detection on the core cluster and obtaining load data corresponding to the core cluster includes: The task processing time required for the core cluster to process tasks is monitored in real time, and the load data corresponding to the core cluster includes the task processing time.

10. The core control method according to claim 9, wherein determining the load state of the core cluster based on the load data corresponding to the core cluster includes: Determine whether the processing time required for the core cluster to process the task is greater than or equal to the first preset processing time; If the processing time required for the core cluster to process a task is greater than or equal to a first preset processing time, the load status of the core cluster is determined to be busy.

11. The core control method according to claim 9, wherein determining the load state of the core cluster based on the load data corresponding to the core cluster includes: Determine whether the processing time required for the core cluster to process the task is less than or equal to the second preset processing time; If the processing time required for the core cluster to process a task is less than or equal to the second preset processing time, the load state of the core cluster is determined to be a low load state.

12. The core control method according to claim 9, wherein the many-core system includes a plurality of core clusters, the plurality of core clusters performing task processing based on a synchronization period, wherein the synchronization period is the longest task processing time among the task processing times required by each core cluster to process the task; Determining the load status of the core cluster based on the load data corresponding to the core cluster includes: The frequency of the synchronization cycle is determined by the processing time of the task corresponding to the core cluster within the preset monitoring period. If the frequency of the synchronization cycle, which is the processing time of the task corresponding to the core cluster, is greater than or equal to the first preset number, the load status of the core cluster is determined to be busy.

13. The core control method according to claim 9, wherein the many-core system includes a plurality of core clusters, the plurality of core clusters performing task processing based on a synchronization period, wherein the synchronization period is the longest task processing time among the task processing times required by each core cluster to process the task; Determining the load status of the core cluster based on the load data corresponding to the core cluster includes: The frequency of the synchronization cycle is determined by the processing time of the task corresponding to the core cluster within the preset monitoring period. The processing time of the task corresponding to the core cluster is calculated as the frequency of the synchronization cycle, and the ratio of the number of synchronization cycles within the preset monitoring time period. If the ratio is greater than or equal to the first preset ratio, the load status of the core cluster is determined to be busy.

14. The core control method according to claim 1, wherein regulating the core cluster according to its load state includes: When the load state of the core cluster is busy, determine whether the core cluster has adjustable voltage and frequency domains. If it is determined that the core cluster has adjustable voltage and frequency domains, the operating voltage and operating frequency of the second processing core corresponding to the adjustable voltage and frequency domains in the currently operable second processing core of the core cluster are increased. If it is determined that the core cluster does not have an adjustable voltage and frequency domain, the number of the second processing cores currently capable of performing operations in the core cluster is increased.

15. The core control method according to claim 1, wherein regulating the core cluster according to its load state includes: Under the condition that the load state of the core cluster is low load, determine whether the core cluster has adjustable voltage and frequency domains. If it is determined that the core cluster has adjustable voltage and frequency domains, the operating voltage and operating frequency of the second processing core corresponding to the adjustable voltage and frequency domains in the currently operable second processing core of the core cluster are reduced. If it is determined that the core cluster does not have an adjustable voltage and frequency domain, the number of second processing cores currently capable of performing operations in the core cluster is reduced.

16. The core control method according to claim 14, wherein increasing the number of second processing cores currently capable of performing tasks in the core cluster comprises: One or more idle second processing cores outside the core cluster in the many-core system are added to the core cluster to serve as the second processing cores that can currently perform tasks in the core cluster.

17. The core control method according to claim 14, wherein increasing the number of second processing cores currently capable of performing tasks in the core cluster comprises: One or more second processing cores in the core cluster that are in a shutdown state are woken up to serve as the second processing cores that are currently available for operation in the core cluster.

18. The core control method of claim 15, wherein reducing the number of second processing cores currently capable of performing tasks in the core cluster comprises: Remove at least one second processing core that is currently capable of performing operations from the core cluster.

19. The core control method of claim 15, wherein reducing the number of second processing cores currently capable of performing tasks in the core cluster comprises: Control at least one of the second processing cores in the core cluster that is currently capable of performing operations to be shut down.

20. The core control method according to claim 16 or 17, wherein each core cluster of the many-core system corresponds to a task in the processing task pipeline, each core cluster contains multiple sub-clusters, each sub-cluster contains at least one second processing core that can currently perform the job, and the multiple sub-clusters are used to process the task corresponding to the core cluster in parallel. The method further includes: Based on the newly added second processing cores that are currently capable of performing tasks in the core cluster, a new sub-cluster of the core cluster is constructed and the configuration information of the new sub-cluster is obtained. The new sub-cluster includes one or more newly added second processing cores that are currently capable of performing tasks. The configuration information includes the number of second processing cores in the new sub-cluster and the address information of each second processing core. Send the configuration information of the new sub-cluster to the target processing core in the predecessor core cluster of the core cluster; Send the configuration information of the new sub-cluster to the target processing core in the successor core cluster of the core cluster; Wherein, the predecessor core cluster is the core cluster preceding the core cluster in the task pipeline, and the target processing core in the predecessor core cluster is used to establish the input branch of the new sub-cluster according to the configuration information of the new sub-cluster of the core cluster. The input branch is the path from the predecessor core cluster to the new sub-cluster for output data. The successor core cluster is the next core cluster in the task pipeline. The target processing core in the successor core cluster is used to establish the output routing of the new sub-cluster according to the configuration information of the new sub-cluster of the core cluster. The output routing is the path for the new sub-cluster to output data to the successor core cluster.

21. The core control method according to claim 1, wherein after inserting a blank frame into the buffer corresponding to the core cluster, it further includes: The gated clocks corresponding to each second processing core in the core cluster are turned off. The gated clocks are used to output clock signals to the corresponding second processing core in the core cluster to drive the corresponding second processing core to work or not work based on the clock signal.

22. The core control method according to claim 1, wherein the many-core system includes multiple core clusters, and when multiple core clusters correspond to processing the same task, and the load state of the multiple core clusters is all at the first level of idle state, after inserting blank frames into the buffers corresponding to the multiple core clusters, the core control method further includes: Pause the transmission of synchronization signals to the multiple core clusters, which are used to control the multiple core clusters to perform task processing based on a synchronization cycle.

23. A core control device applied to a many-core system, characterized in that, For executing the core control method according to any one of claims 1-22, the many-core system includes at least one core cluster, each core cluster including at least one second processing core, the core control device comprising: The load data detection module is configured to perform load detection on the corresponding core cluster and obtain the load data corresponding to that core cluster. The load status detection module is configured to determine the load status of the core cluster based on the load data corresponding to the core cluster. The core control module is configured to control the core cluster based on its load status. The control process includes one of the following control methods: Adjust the number of second processing cores that are currently available for operation within the core cluster; The operating voltage and frequency of the second processing core that is currently capable of performing operations in the core cluster are adjusted. Insert blank frames into the buffer corresponding to the core cluster.

24. A processing core, comprising the core control device as described in claim 23.

25. A many-core system, comprising a plurality of processing cores, the plurality of processing cores including a first processing core and a plurality of second processing cores, some or all of the plurality of second processing cores being divided into at least one core cluster, each core cluster including at least one second processing core, each core cluster having a master processing core, the master processing core of the core cluster being a designated second processing core in the core cluster. in, The first processing core adopts the processing core described in claim 24, and / or, at least a portion of the main processing cores of the core cluster adopt the processing core described in claim 24.

26. An electronic device, comprising: Multiple processing cores; as well as The on-chip network is configured to interact with data between the multiple processing cores and external data; One or more of the processing cores store one or more instructions, and the one or more of the instructions are executed by one or more of the processing cores to enable the one or more of the processing cores to perform the core control method of any one of claims 1-22.

27. A computer-readable medium having a computer program stored thereon, wherein, The computer program, when executed by the processing core, implements the core control method as described in any one of claims 1-22.

28. A computer program product comprising a computer program that, when executed by a processing core, implements the core control method according to any one of claims 1-22.

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