High speed peripheral component interconnect interface device and method of operation thereof

Abstract

The present disclosure relates to a Peripheral Component Interconnect Express (PCIe) interface device and an operating method thereof. The PCIe interface device is coupled to an external device through a link including a plurality of lanes, the PCIe interface device including an EQ controller that controls the PCIe interface device to perform an equalization operation for determining a transmitter setting or a receiver setting of each of the plurality of lanes, and an EQ information storage device that stores log information indicating a number of attempts of the equalization operation for each of a plurality of EQ coefficients including a transmitter coefficient or a receiver coefficient, and error information about an error occurring in an L0 state for each of the plurality of EQ coefficients, wherein the EQ controller determines a final EQ coefficient using the log information and the error information.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2021-0067203, filed with the Korean Intellectual Property Office on May 25, 2021, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] The various embodiments generally relate to an electronic device, and more particularly, to a high-speed peripheral component interconnect (PCIe) interface device and a method of operating thereof. Background Technology

[0004] High-speed peripheral component interconnect (PCIe) involves a serially configurable interface for data communication. PCIe-based storage devices can support multiple ports and multiple functions. PCIe-based storage devices can be virtualized or non-virtualized and implement Quality of Service (QoS) for host I / O commands through at least one PCIe function.

[0005] Storage devices can store data under the control of a host device such as a computer or smartphone. A storage device may include a memory device for storing data and a memory controller for controlling the memory device. Memory devices can be classified as volatile memory devices and non-volatile memory devices.

[0006] Volatile memory devices retain data as long as power is supplied, but may lose stored data when power is unavailable. Types of volatile memory devices include static random access memory (SRAM), dynamic random access memory (DRAM), etc.

[0007] Non-volatile memory devices do not lose data even when there is no power supply. Types of non-volatile memory devices can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), flash memory, etc. Summary of the Invention

[0008] The various embodiments of this disclosure relate to a PCIe interface device and its operating method capable of performing improved PCIe balancing operations.

[0009] According to an embodiment, a high-speed peripheral component interconnect (PCIe) interface device is connected to an external device via a link including multiple paths. The PCIe interface device may include: an equalizer controller (EQ) controller that controls the PCIe interface device to perform equalization operations, the equalization operations being used to determine transmitter settings or receiver settings for each of the multiple paths; and an EQ information storage device that stores log information and error information, the log information indicating the number of attempts at equalization operations for each of the multiple EQ coefficients, and the error information relating to errors occurring in the L0 state for each of the multiple EQ coefficients, including transmitter coefficients or receiver coefficients, wherein the EQ controller uses the log information and error information to determine the final EQ coefficients.

[0010] According to an embodiment, a method for operating a PCIe interface device, the PCIe interface device being connected to an external device via a link including multiple paths, may include: determining whether log information exists, the log information indicating the number of times a leveling operation is tested on the multiple paths for each of a plurality of EQ coefficients; when the log information exists, using the log information to determine the EQ coefficients to test the leveling operation; performing link connection based on the determined EQ coefficients; and storing log information corresponding to the determined EQ coefficients and error information regarding errors occurring during the link connection state. Attached Figure Description

[0011] Figure 1 This is a diagram illustrating a PCIe computing system according to an embodiment of the present disclosure.

[0012] Figure 2 This is a diagram illustrating a PCIe device according to an embodiment of the present disclosure.

[0013] Figure 3 This is a diagram illustrating a PCIe interface according to an embodiment of the present disclosure.

[0014] Figure 4 This is a diagram illustrating a transmitter, receiver, and path according to an embodiment of the present disclosure.

[0015] Figure 5 This is a diagram illustrating a port according to an embodiment of the present disclosure.

[0016] Figure 6 This is a diagram illustrating the link status of a PCIe device according to an embodiment of the present disclosure.

[0017] Figure 7 This is a diagram illustrating the equalization operation according to an embodiment of the present disclosure.

[0018] Figure 8This is a diagram illustrating the changes in link state during equalization operation according to an embodiment of the present disclosure.

[0019] Figure 9 This is a diagram illustrating the EQ coefficients according to an embodiment of the present disclosure.

[0020] Figure 10 This is a diagram illustrating a method for performing load balancing operations on a PCIe interface based on relevant technologies.

[0021] Figure 11 This is a diagram illustrating a method for performing load balancing operations on a PCIe interface according to an embodiment of the present disclosure.

[0022] Figure 12 This is a diagram illustrating an EQ coefficient table according to an embodiment of the present disclosure.

[0023] Figure 13 This is a diagram illustrating the configuration of a PCIe interface according to an embodiment of the present disclosure.

[0024] Figure 14 This is a diagram illustrating a method of operating a PCIe interface according to an embodiment of the present disclosure.

[0025] Figure 15 This is a diagram illustrating how an EQ coefficient is determined based on stored log information according to an embodiment of the present disclosure. Detailed Implementation

[0026] The specific structural or functional descriptions of examples of embodiments of the concept disclosed in this specification are for illustrative purposes only. Examples of embodiments of the concept can be implemented in various forms. However, implementation is not limited to the examples of embodiments described in this specification.

[0027] Various modifications and changes can be made to the examples of the embodiments based on this concept, so that examples of the embodiments are shown in the drawings and described in the specification. However, embodiments based on this concept are not to be construed as limited to the specific disclosure and include all changes, equivalents, or alternatives without departing from the spirit and technical scope of this disclosure. In describing those embodiments, descriptions of techniques well-known in the art to which this disclosure pertains and not directly related to this disclosure will be omitted. This is intended to make the gist of the disclosure clearer by omitting unnecessary descriptions.

[0028] In the following, exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0029] Figure 1 This is a diagram illustrating a PCIe computing system according to an embodiment of the present disclosure.

[0030] Reference Figure 1 The PCIe computing system 100 may include a central processing unit (CPU) 110, a root complex 120, a memory 130, a switch 140, PCIe endpoints 150_1 to 150_3, legacy endpoints 160_1 and 160_2, and a PCIe to PCI / PCI-X bridge 170.

[0031] PCIe computing system 100 can be an electronic device that supports communication using a PCIe interface. PCIe computing system 100 can be a personal computer (PC), a laptop computer, or a mobile computing device. PCIe computing system 100 may include expansion cards, expansion boards, adapter cards, plug-in cards, or auxiliary cards. Additionally, PCIe computing system 100 may include a printed circuit board (PCB) that can be inserted into an electronic connector or expansion slot on the motherboard of PCIe computing system 100 to provide additional functionality to PCIe computing system 100 via an expansion bus. Furthermore, PCIe computing system 100 may include storage devices such as solid-state drives (SSDs) and may include graphics cards, network cards, or USB cards.

[0032] The CPU 110 can be electrically connected to each component of the PCIe computing system 100 and can control the corresponding operations of the PCIe computing system 100. More specifically, the CPU 110 can drive an operating system or application to control the hardware or software components connected to the CPU 110, and can perform various types of data processing and operations. In addition, the CPU 110 can execute software or applications for controlling the operation of the PCIe computing system 100.

[0033] Root union 120 can be a root hub, controller hub, or root controller in a PCIe interconnect architecture. For example, root union 120 may include a chipset, memory controller hub (MCH), northbridge, interconnect controller hub (ICH), southbridge, and root controller / hub. Additionally, root union 120 can connect CPU 110 and memory 130 to the I / O layer. Root union 120 can support point-to-point (P2P) routing. Root union 120 may include at least one host bridge and a root port. Root union 120 can support at least one PCIe port.

[0034] The memory 130 can store data, commands, or program code required for the operation of the PCIe computing system 100. According to an embodiment, the memory 1030 can store program code operable to run one or more operating systems (OS) and virtual machines (VMs), as well as program code for running a virtualization intermediary (VI) for managing virtual machines (VMs). Additionally, the memory 130 can be implemented as a volatile memory device such as DRAM or SRAM.

[0035] Switch 140 can route packets or messages upstream or downstream. More specifically, switch 140 can route packets or messages from a PCIe endpoint (e.g., 150_1) up one level to root union 120. However, alternatively, switch 140 can route packets or messages from root union 120 down one level to PCIe endpoint (e.g., 150_2).

[0036] Switch 140 may be referred to as a logical component of multiple virtual PCI to PCI bridge devices. Examples of devices connected to switch 140 may include any internal or external devices or components connected to an electronic system, such as I / O devices, network interface controllers (NICs), expansion cards, audio processors, network processors, hard disk drives, storage devices, CD / DVD ROMs, monitors, printers, mice, keyboards, routers, portable storage devices, FireWire devices, Universal Serial Bus (USB) devices, scanners, and other input / output devices.

[0037] Each of PCIe endpoints 150_1 to 150_3 and traditional endpoints 160_1 and 160_2 can be used as a requester or completer for PCIe transactions. Transaction layer packets (TLPs) sent or received by PCIe endpoints 150_1 to 150_3 and traditional endpoints 160_1 and 160_2 may provide a configuration space header. Additionally, each of PCIe endpoints 150_1 to 150_3 and traditional endpoints 160_1 and 160_2, acting as a completer, may provide a configuration request. Under certain conditions, transaction layer packets (TLPs) sent or received by PCIe endpoints 150_1 to 150_3 and traditional endpoints 160_1 and 160_2 must provide a configuration space header. Furthermore, each of PCIe endpoints 150_1 to 150_3 and traditional endpoints 160_1 and 160_2, acting as a completer, must provide a configuration request.

[0038] PCIe endpoints 150_1 to 150_3 and traditional endpoints 160_1 and 160_2 can be classified according to the possible size of memory transactions. For example, when a memory transaction may exceed 4GB, the endpoints can be PCIe endpoints (150_1 to 150_3). On the other hand, when a memory transaction is unlikely to exceed 4GB, the endpoints can be traditional endpoints (160_1 and 160_2). Although PCIe endpoints 150_1 to 150_3 are not allowed to generate I / O requests, traditional endpoints 160_1 and 160_2 can provide or generate I / O requests. Additionally, PCIe endpoint 150_3 can send TLPs to or receive TLPs from root union 120. Furthermore, PCI / PCI-X can send TLPs to or receive TLPs from root union 120 via PCIe to PCI / PCI-X bridge 170. In addition, PCIe endpoints 150_1 and 150_2 and traditional endpoints 160_1 and 160_2 can send TLPs to or receive TLPs from switch 140.

[0039] Figure 2 This is a diagram illustrating a PCIe device according to an embodiment of the present invention.

[0040] Reference Figure 2 A PCIe device may include a PCIe interface and is an electronic device that supports sending and receiving using a PCIe interface. For example, the first PCIe device 200-1 or the second PCIe device 200-2 may include... Figure 1 The root union 120, switch 140, PCIe endpoints 150_1 to 150_3, legacy endpoints 160_1 and 160_2, and one of the PCIe to PCI / PCI-X bridges 170 are shown.

[0041] Furthermore, the first PCIe device 200-1 or the second PCIe device 200-2 can perform communication using the first PCIe interface 210-1 or the second PCIe interface 210-2, respectively. More specifically, the first PCIe device 200-1 can use the first PCIe interface 210-1 to convert data to be sent from the second PCIe device 200-2 into a protocol suitable for communication. Additionally, the first PCIe device 200-1 and the second PCIe device 200-2 can form a link. The first PCIe device 200-1 and the second PCIe device 200-2 can perform communication through the link. For example, the first PCIe device 200-1 or the second PCIe device 200-2 can send or receive data packets through the link.

[0042] Figure 3 This is a diagram illustrating a PCIe interface according to an embodiment of the present disclosure.

[0043] Figure 3 Show Figure 2 The first PCIe interface 210-1 and the second PCIe interface 210-2. The first PCIe interface 210-1 and the second PCIe interface 210-2 can have the same structure. Therefore, the following description of the first PCIe interface 210-1 can also be applied to the second PCIe interface 210-2.

[0044] The PCIe layers included in the first PCIe interface 210-1 may include three discrete logical layers. For example, the first PCIe interface 210-1 may include a PCIe core 211, a transaction layer 212, a data link layer 213, and a physical layer 214. Each layer (212, 213, and 214) may include two segments. More specifically, one segment TX can handle outbound information (or information to be sent), while the other segment RX can handle inbound information (or received information). Additionally, the first PCIe interface 210-1 can communicate with other PCIe interfaces using data packets.

[0045] PCIe core 211 can control the entire first PCIe interface 210-1. More specifically, PCIe core 211 may include a software layer for operating the interface. Additionally, PCIe core 211 can transmit addresses, transaction types, and data to transaction layer 212, or receive addresses, transaction types, and data from transaction layer 212.

[0046] Transaction layer 212 can be an upper layer in the PCIe interface architecture. Transaction layer 212 can assemble or disassemble Transaction Layer Packets (TLPs). Additionally, transaction layer 212 can implement split transactions, i.e., transactions that allow other traffic to be transmitted to the link while the target system assembles data for a response. For example, transaction layer 212 can implement transactions where requests and responses are temporarily separated. According to embodiments, the four transaction address spaces can consist of a configuration address space, a memory address space, an input / output address space, and a message address space. Memory space transactions can include at least one of a read request and a write request, where a read request is used to transfer data from a memory-mapped location / a write request is used to transfer data to a memory-mapped location. According to embodiments, memory space transactions can use two different address formats, such as a short address format like a 32-bit address or a long address format like a 64-bit address. Configuration space transactions can be used to access the configuration space of a PCIe device. Transactions targeting the configuration space can include read requests and write requests. Message space transactions (or messages) can be defined to support in-band communication between PCIe devices.

[0047] Transaction layer 212 can store link configuration information received from PCIe core 211. In addition, transaction layer 212 can generate TLPs requested by PCIe core 211, or can convert received TLPs into payloads or status information.

[0048] In the PCIe interface architecture, the intermediate layer can be the data link layer 213. The data link layer 213 can serve as an intermediate stage between the transaction layer 212 and the physical layer 214. The main functions of the data link layer 213 can include link management and data integrity, including error detection and correction. More specifically, the sending side of the data link layer 213 can receive the TLP (Transaction Protection Token) collected by the transaction layer 212, apply the data protection code, or calculate the TLP sequence number. Additionally, the sending side of the data link layer 213 can send the data protection code and the TLP sequence number to the physical layer 214. The receiving side of the data link layer 213 can check the integrity of the TLP received from the physical layer 214 and send the TLP to the transaction layer 212 for further processing.

[0049] Physical layer 214 may include circuitry for interface operation. Physical layer 214 may include drivers, input buffers, serial-to-parallel conversion circuitry, parallel-to-serial conversion circuitry, phase-locked loops (PLLs), and impedance matching circuitry.

[0050] Additionally, physical layer 214 may include logical and electrical sub-blocks for physically sending data packets to external PCIe devices. The logical sub-blocks may be used to perform the "digital" functions of physical layer 214. More specifically, the logical sub-blocks may include: a transmit segment, which prepares information for transmission via the physical sub-blocks; and a receive segment, which identifies and prepares received information before passing it to data link layer 213. Physical layer 214 may include a transmitter Tx and a receiver Rx. The transmitter Tx may receive symbols serialized by the transmitter and sent to external devices by the logical sub-blocks. Additionally, the receiver Rx may receive serialized symbols from external devices and convert the received signals into a bit stream. The bit stream may be deserialized and supplied to the logical sub-blocks. In other words, physical layer 214 may convert TLPs received from data link layer 213 into a serialized format and data packets received from external devices into a deserialized format. Furthermore, physical layer 214 may include logic functions related to interface initialization and maintenance.

[0051] Figure 3 The architectures of the first PCIe interface 210-1 and the second PCIe interface 210-2 are illustrated. However, the architectures of the PCIe interfaces in other embodiments may include any architecture such as a fast path interconnect architecture, a next-generation high-performance computing interconnect architecture, or other hierarchical architectures.

[0052] Figure 4 This is a diagram illustrating a transmitter, receiver, and path according to an embodiment of the present disclosure.

[0053] Figure 4 A first transmitter TX1, a second transmitter TX2, a first receiver RX1, and a second receiver RX2 are shown. A path may include a path comprising differential drive signal pairs, such as a transmit path pair configured for transmitting and a receive path pair configured for receiving. A PCIe device may include transmit logic for transmitting data to another PCIe device and receive logic for receiving data from another PCIe device. For example, a PCIe device may include two transmit paths coupled to the first transmitter TX1 and two receive paths coupled to the first receiver RX1.

[0054] The transmitting path can refer to any path used for data transmission, such as a transmission line, copper wire, wireless communication channel, infrared communication link, or one or more other communication paths. Furthermore, the receiving path can be implemented in the same way as the transmitting path, and the receiving path can be configured for receiving data.

[0055] Two PCIe devices (e.g., Figure 2 The connection between the first PCIe device 200-1 and the second PCIe device 200-2 shown can be referred to as a link. A link can support at least one path. Additionally, each path can be indicated by a set of differential signal pairs (one pair for transmitting and another for receiving). A differential signal pair can refer to two signals with the same frequency and amplitude but opposite phases. For example, while the first signal has a rising edge switching from 0 to a voltage level V+, the second signal can have a falling edge switching from 0 to a voltage level V-. For example, PCIe devices can utilize signal integrity (such as cross-connection, voltage overshoot / undershoot, and ringing electrical characteristics) and can control the transmission frequency more quickly by utilizing differential signals. Furthermore, PCIe devices can include multiple paths to control bandwidth. For example, two PCIe devices can form a link consisting of 1, 2, 4, 8, 12, 16, or 64 paths.

[0056] Figure 5 This is a diagram illustrating a port according to an embodiment of the present disclosure.

[0057] like Figure 5As shown, downstream port 215-1 and upstream port 215-2 can be included in the first PCIe device 200-1 and the second PCIe device 200-2, respectively. According to an embodiment, the first PCIe device 200-1 can be the upper layer compared to the second PCIe device 200-2. Data movement and transmission to the upper layer can be referred to as "upstream." On the other hand, data movement and transmission to the lower layer can be referred to as "downstream." For example, refer to... Figure 1 Switch 140 can support both downstream and upstream routing. More specifically, upstream can refer to routing up one level from a PCIe endpoint (e.g., 150_1) to the root union 120, and downstream can refer to routing down one level away from the root union 120 to a PCIe endpoint (e.g., 150_2).

[0058] Each of the downstream port 215-1 and the upstream port 215-2 may include a transmitter Tx, a receiver Rx, and a phase-locked loop (PLL) circuit. The PLL circuit can generate a clock signal to be supplied to the transmitter Tx or receiver Rx by multiplying a signal provided from a clock signal generator CLK GEN. The PLL circuit can also multiply a signal received from the clock signal generator CLK GEN to generate a clock signal with a changed frequency. For example, the PLL circuit can multiply a reference clock signal REFCLK with a frequency of 100 MHz to generate a clock signal with a frequency of 2.5 GHz. The transmitter Tx can convert a parallel data signal into a serial data signal using the output signal of the PLL circuit, and can send the serial data signal to an external device, such as an external PCIe device. The receiver Rx can receive a serial data signal sent from an external device to generate a clock signal for recovering the received serial data signal and a clock signal for converting the recovered serial data signal into a parallel data signal using the output signal of the PLL circuit. The clock signal generator CLK GEN can generate the reference clock signal REFCLK used in the operation of the PCIe interface. The operation of the PCIe interface can correspond to communication with external PCIe devices.

[0059] Figure 6 This is a diagram illustrating the link status of a PCIe device according to an embodiment of the present disclosure.

[0060] like Figure 6 As shown, the link status of a PCIe device can include detection, polling, configuration, hot reset, disabled, and L0 status.

[0061] The detection state can refer to the initial state after power-on or reset. The detection state can be entered from states described below. For example, the detection state can be entered from the configuration state, hot reset state, disabled state, L2 state, loopback state, and recovery state. In the detection state, all logic, ports, and registers can be reset, and the links connected to the PCIe interface can be detected. In other words, a PCIe device in the detection state can search for physically connected paths.

[0062] In polling mode, it's possible to distinguish between channels with enabled data communication and detected channels. For example, in polling mode, the clocks at both ends of the PCIe interface can be synchronized, and the polarity of the channel (D+ or D-) can be confirmed. Additionally, the data transfer rate available for the channel can be checked. In other words, polarity reversal can be checked in polling mode. Furthermore, a link in polling mode can enter either detection or configuration mode.

[0063] In configuration mode, the connection status of the path can be checked. More specifically, in configuration mode, the path width for enabling data communication can be determined. Additionally, in configuration mode, path reversal can be checked. Configuration mode can be entered from polling mode. However, optionally, after entering L0 mode, configuration mode can be entered if the path width is reduced or increased.

[0064] The recovery state can be used to reconfigure link bandwidth. In recovery state, the link bandwidth can be changed, and bit locking, symbol locking, and lane-to-lane de-skew can be reset. Recovery state can be entered when an error occurs in L0 state. After recovering from the error in recovery state, the state can be changed back to L0 state. Additionally, according to an embodiment, link equalization operations can be performed in recovery state.

[0065] The L0 state can be the normal operational state for sending and receiving data and data packets via the link. More specifically, the L0 state can be the operational state of the physical bus interface for sending and receiving data and control data packets. The L0 state can also be a fully active state.

[0066] L0s state refers to the state in which the physical bus interface can quickly enter from a power-saving state and recover from a power-saving state without going through a recovery state. L0s state can be a power-saving state. L0s state can also refer to the idle or standby state of some functions within the interface.

[0067] L1 state can be a power-saving state. L1 state can refer to a power-saving state that allows for even greater power consumption than L0s state. L1 state can also be a low-power standby state.

[0068] L2 state can be a power-saving state that significantly conserves power. Most transmitters and receivers can be turned off. While main power and clock are not guaranteed, auxiliary power can be provided. L2 state can also be a low-power sleep state that does not supply power to most functions.

[0069] Loopback states can be designed for testing and fault isolation. Loopback states can operate on a per-path basis, and the loopback receive path must be selected and configured.

[0070] A disabled state can be a state that allows the configuration link to be disabled until indicated. A hot reset state can only be triggered by a downstream port. The downstream port can use a training sequence (e.g., TS1 or TS2) to propagate a hot reset. The training sequence TS can consist of an ordered set used to initialize bit alignment, sign alignment, and for physical layer parameter exchange.

[0071] Figure 7 This is a diagram illustrating the equalization operation according to an embodiment of the present disclosure.

[0072] Equalization operations can be performed to adjust the transmitter and receiver settings of each path to improve the quality of transmitted and received signals and meet specific requirements. In other words, equalization operations can be performed on each path associated with the Link Training and State Machine (LTSSM). Furthermore, equalization operations can be performed autonomously by the PCIe interface or controlled by the host. Equalization operations can be performed at a lower data rate and then at a higher data rate. However, equalization operations can be skipped at specific data rates, and upstream and downstream ports can announce the specific data rate at which equalization operations can be skipped using TS1 or TS2.

[0073] Reference Figure 7 The upstream and downstream ports can perform a load balancing operation consisting of up to four phases. The load balancing operation can consist of Phase 0 through Phase 3. Alternatively, the load balancing operation can be performed by the physical layer.

[0074] Phase 0 can refer to the phase performed when the data rate for performing equalization operations is determined. For example, when the data rate is determined to change from 2.5 GT / s to 8.0 GT / s, the downstream and upstream ports can send and receive TS2 ordered sets (OS). More specifically, the downstream port can transmit transmitter and receiver presets for each path, encoded in 8b / 10b or 128b / 130b, to the upstream port using the TS2 OS in Recovery.RcvrCfg. For example, when performing equalization operations at 8.0 GT / s, the TS2 OS can include information about the 8.0 GT / s transmitter and receiver presets for the upstream port of each path. Additionally, the upstream port can send a TS1 OS with the received presets. When performing equalization operations, phase information indicating the phase of equalization can be sent using the equalization control (EC) field of the TS1 OS. For example, in Phase 0, phase information can be exchanged by exchanging TS1 OSs with the EC field set to "00".

[0075] In Phase 1, the downstream and upstream ports can exchange TS1 OS to perform fine-tuning of the transmitter / receiver pair. In other words, the downstream and upstream ports can exchange TS1 OS to set up the operational link. More specifically, the downstream port can initialize Phase 1 by sending a TS1 OS with the EC field set to "01". After adjusting the receiver, the upstream port can receive the TS1 OS and transition to Phase 1 if needed. Alternatively, the upstream port can send a TS1 OS with the EC field set to "01". When the downstream port receives a TS1 OS with the EC field set to "01" from the upstream port before entering Phase 2, the downstream port can ensure that it can reliably receive the bit stream from the upstream port to continue through the remaining phases.

[0076] In Phase 2, the upstream port can adjust the transmitter settings and receiver settings of the downstream port. In other words, the upstream port can request the downstream port to adjust the transmitter coefficients and preset settings to ensure that the upstream port can reliably receive bit streams that meet specific requirements. For example, the upstream port can adjust its receiver settings and request the downstream port's transmitter settings to ensure that the bit error rate (BER) for each path is less than 10. -12 .

[0077] The downstream port can initialize the second phase by sending a TS1 OS with the EC field set to "10" to the upstream port. The downstream port can provide the upstream port with information about its transmitter coefficients and preset settings. Conversely, the upstream port can receive information about the downstream port's transmitter coefficients and preset settings from the downstream port and can request changes to the downstream port's transmitter coefficients or preset settings. Furthermore, the upstream port can continue to evaluate each setting until it reaches the optimal setting for operating the downstream path within a finite timeframe. After completing the second phase, the upstream port can proceed to the third phase by sending a TS1 OS with the EC field set to "11" to the downstream port.

[0078] In Phase 3, the downstream port can adjust the transmitter settings of the upstream port. In other words, the downstream port can request the upstream port to set the transmitter coefficients and preset settings so that the incoming link meets specific requirements.

[0079] The downstream port can receive information about the transmitter coefficients and preset settings of the upstream port, and can request the transmitter coefficients or preset settings from the upstream port. Furthermore, the downstream port can continue to evaluate each setting until it reaches the optimal setting for operating the upstream path within a finite time. Additionally, after completing the third phase, the downstream port can send a TS1 OS with the EC field set to "00" to the upstream port to notify that the load balancing operation has terminated.

[0080] After the load balancing operation is complete, the link state can transition from Recovery.RcvrLock, Recovery.RcvrCfg, and Recovery.Idle to L0 state. (Refer to...) Figure 8 This will be described in detail.

[0081] Figure 8 This is a diagram illustrating the changes in link state during equalization operation according to an embodiment of the present disclosure.

[0082] Figure 8 This illustrates the link state transitioning from Gen1 L0 to Gen3 L0. Gen1 and Gen3 can each be individual modes operating on either the upstream or downstream port and can include different data rates. (See above for reference.) Figure 7As described above, equalization operations can be performed in response to changes in data rate. The link state of upstream and downstream ports can be entered into recovery state by sending a TS1 OS from the Gen1 L0 state to the Gen1 Recovery.Lock state to the peer port. Gen1 L0 can refer to the state of normally sending or receiving data and control packets. Therefore, a port receiving a TS1 OS in the Gen1 Recovery.Lock state can be considered to have achieved block alignment after the final data stream ends. Then, it can enter the Gen1 Recovery.CFG state. In the Gen1 Recovery.CFG state, receivers on all paths of the configured link can sequentially receive eight TS1 OSs or TS2 OSs. Additionally, when a speed change bit indicating a data rate change is set in a TS1 OS or TS2 OS received in the Gen1 Recovery.CFG state, the downstream and upstream ports can change the data rate in the Recovery.Speed ​​state. Figure 8 This demonstrates the data rate change from Gen1 to Gen3. However, it can also be applied to changes from Gen3 to Gen4 or from Gen1 to Gen5. Additionally, the link state can enter Gen3 Recovery.Lock and Gen3 Recovery.EQ phase0,1. The Gen3 Recovery.EQ phase0,1 state can be... Figure 7 The zero-phase Phase 0 shown is the same as the first-phase Phase 1. In Gen3Recovery.EQ phase 0, 1 states, the downstream and upstream ports can swap full swing (FS) and low frequency (LF). Additionally, the downstream and upstream ports can sweep the EQ coefficients based on the FS and LF values ​​in Gen3 Recovery.EQ Phase 2 and Gen3 Recovery.EQ Phase 3 states. The Gen3 Recovery.EQ Phase 2 state can be maintained for a maximum of 24ms. A limited time of 24ms may be insufficient to meet the requirements of a 10... -12 The following are examples of bit error rates.

[0083] Figure 9 This is a diagram illustrating the EQ coefficients according to an embodiment of the present disclosure.

[0084] Figure 9 The graph shows the EQ coefficients including the pre-cursor, cursor, and post-cursor. Figure 9In this equation, C-1 and C+1 can be coefficients used in the FIR equations, representing the preamble and suffix, respectively. The preamble and suffix values ​​communicated in the TS1 OS can represent their absolute values. Additionally, C0 can represent the primary coefficient setting and can have a positive value. Furthermore, the sum of the absolute values ​​of the coefficients defines FS. In other words, FS can satisfy [Equation 2] below. Additionally, FS can be sent to the link partner (e.g., the peer port) in the first phase. Furthermore, FS can have values ​​from 24 to 63 for full-swing mode and from 12 to 63 for reduced-swing mode. The transmitter can advertise the LF value during the first phase. The LF value can correspond to the minimum differential voltage generated by the transmitter, which is obtained by multiplying LF / FS by the transmitter's maximum differential voltage. The transmitter can satisfy V TX-EIEOS-FS and V TX-EIEOS-RS Specific requirements. The transmitter must ensure that V satisfies the following condition when [Equation 3] below equals LF. TX-EIEOS-FS and V TX-EIEOS-RS Specific requirements. A transmitter can request a set of coefficients from a link partner (e.g., a peer port) transmitter. Additionally, the following equations can be satisfied before requesting a set of coefficients from a link partner (e.g., a peer port) transmitter. Upon receiving an update request for TX coefficient settings, the port can verify whether the update request satisfies the following equations, and reject the update request if any equation is not satisfied:

[0085] [Equation 1]

[0086] |C-1| ≤ Floor (FS / 4)

[0087] [Equation 2]

[0088] |C-1|+C0+|C+1| = FS

[0089] [Equation 3]

[0090] C0 -|C-1|-|C+1| ≥ LF

[0091] According to the embodiment, the values ​​of the prefix, subject, and postscript can be obtained by multiplying them by the prefix coefficient, subject coefficient, and postscript coefficient, respectively. Figure 9 The EQ coefficients are shown below. During output, the suffix can be used to obtain the following values: Figure 9 The "de-emphasis" effect shown is significant in differential signals. Furthermore, at output, by connecting a preamble, a result such as... Figure 9 The "pre-shoot" effect shown can exhibit a significant voltage change when the voltage is reduced.

[0092] Figure 10 This is a diagram illustrating a method for performing load balancing operations on a PCIe interface based on relevant technologies.

[0093] Figure 10 The balancing operation performed over time is shown. (See above reference.) Figure 7 and Figure 8 The link states of the upstream and downstream ports during the equalization operation can include Rcvr.Speed, EQ Phase 2, and EQ Phase 3 states. Furthermore, because the data rate has been changed, the Rcvr.Speed ​​state may be unstable. Therefore, the reliability of the equalization operation in the Rcvr.Speed ​​state may be reduced. Additionally, in the EQ Phase 2 state, the upstream port can determine the TX coefficient of the downstream port over a duration of up to 24ms. More specifically, the upstream port can be a PCIe endpoint connected to the PCIe computing system. From the perspective of the PCIe endpoint, physical characteristics, including channel length, can vary between platforms or between slots. Furthermore, the equalization operation can involve a process of finding a suitable equalization operation and determining the EQ coefficient. Even if the optimal EQ coefficient is determined, if the link is reset (e.g., hot reset, cold reset, or warm reset), the EQ coefficient can still be searched and determined again. In other words, each executed equalization operation can be performed discontinuously from previous equalization operations. Therefore, even if the link is connected to a previous EQ coefficient, the optimal EQ coefficient may not be guaranteed in subsequent equalization operations. The EQ coefficient can include the TX coefficient and the RX coefficient.

[0094] In EQ Phase 3, the TX coefficients of the PCIe endpoints connected to the PCIe computing system can be set. Because the PCIe computing system is aware of its physical characteristics, including channel characteristics, the equalization operation in Phase 3 may not be important.

[0095] Figure 11 This is a diagram illustrating a method for performing load balancing operations on a PCIe interface according to an embodiment of the present disclosure.

[0096] Figure 11The diagram illustrates the load balancing operation performed over time. The PCIe interface can store error information and EQ coefficients corresponding to each of the multiple paths in an EQ coefficient table. Assuming the load balancing operation is first performed at time t1, it's not necessary to store the error information and EQ coefficients corresponding to each of the multiple paths in the EQ coefficient table at time t1. Additionally, at time t2, information about errors occurring in the L0 state or link-on state, or information about errors occurring during the load balancing operation, can be stored in the EQ coefficient table. Similar to time t2, error information can be stored at times t3 and t4.

[0097] Because the leveling operation is repeated, the PCIe interface can identify the optimal EQ coefficient information. More specifically, the PCIe interface can determine the final optimal EQ coefficient based on log information and error information, where the log information indicates the number of leveling operations attempted and the error information per path and EQ coefficient, relating to errors occurring in the L0 state or link-on state. The PCIe interface can determine the effective final EQ coefficient by performing leveling using the EQ coefficients adjacent to the EQ coefficient in the EQ coefficient table that include the minimum error information. According to embodiments of this disclosure, the PCIe interface can determine and maintain the final EQ coefficient even during link resets.

[0098] Figure 12 This is a diagram illustrating an EQ coefficient table according to an embodiment of the present disclosure.

[0099] Figure 12 An EQ coefficient table is shown, arranged according to the EQ coefficients. The EQ coefficient table can include values ​​for the prefix, major, and subscript. More specifically, EQ coefficients can be composed of combinations of prefix, major, and subscript. The EQ coefficient table can include values ​​for the prefix, major, and subscript that satisfy [Equation 1], [Equation 2], and [Equation 3]. Figure 12 This is a diagram showing an example with a full swing (FS) value of 32 and a low frequency (LF) value of 10. However, the FS and LF values ​​can be changed during implementation.

[0100] The EQ coefficient table can store error information based on each of the multiple paths connected to the PCIe system device. More specifically, the EQ coefficient table can accumulate and store errors occurring in the L0 state or link-on state. Errors can include at least one of training sequence errors, ordered set (OS) errors, receiver (RX) errors, decoding errors, synchronization header errors, and framing errors. Additionally, the EQ coefficient table can store margin information indicating the path margin calculated based on each of the multiple paths. More specifically, margins regarding the height and width of the receiver Rx can be stored. According to an embodiment, the PCIe system device can record the margin of the receiver Rx using an error sampler.

[0101] According to an embodiment, the EQ coefficient table can effectively determine the final EQ coefficients by using the stored error information. More specifically, the PCIe interface device can use the error information to understand information about errors that occurred in the L0 state or link-on state based on each EQ coefficient. Additionally, the PCIe interface device can perform equalization by using the EQ coefficients adjacent to the EQ coefficient in the EQ coefficient table that include the least error information to determine the effective final EQ coefficients.

[0102] Figure 13 This is a diagram illustrating the configuration of a PCIe interface according to an embodiment of the present disclosure.

[0103] Figure 13 A PCIe interface device 1000 and an external device 200 are shown. For example, the external device 200 may be as follows: Figure 1 The diagram shows one of the root union 120, switch 140, PCIe endpoints 150_1 to 150_3, legacy endpoints 160_1 and 160_2, and PCIe to PCI / PCI-X bridge 170. Downstream port 215 may be included in external device 200. External device 200 and PCIe interface device 1000 can communicate using a PCIe interface that supports the PCIe protocol. More specifically, external device 200 and PCIe interface device 1000 can form a link and communicate through that link. For example, external device 200 and PCIe interface device 1000 can send or receive data packets through the link. The link may include multiple paths.

[0104] PCIe interface device 1000 may include EQ information storage device 1100, EQ controller 1200 and upstream port 1300.

[0105] The EQ information storage device 1100 may include log information and error information. The log information may indicate the number of equalization attempts made for each of the EQ coefficients, including transmitter coefficients or receiver coefficients. According to an embodiment, the EQ information storage device 1100 may store error information about errors occurring in each of the multiple paths. Errors may include at least one of training sequence errors, ordered set (OS) errors, receiver (RX) errors, decoding errors, synchronization header errors, and framing errors.

[0106] According to an embodiment, the EQ information storage device 1100 can be implemented as a non-volatile memory device that stores log information or error information in the event of a link reset (e.g., a cold reset, a warm reset, or a hot reset). Additionally, according to an embodiment, the EQ information storage device 1100 can store a preset combination of EQ coefficients.

[0107] According to an embodiment, the EQ information storage device 1100 may store margin information indicating the path margin calculated based on each of a plurality of paths. According to an embodiment, the EQ information storage device 1100 may store port information including full swing (FS) value or low frequency (LF) value.

[0108] The EQ controller 1200 can control the general operation of the PCIe interface device 1000 to perform equalization operations that determine the transmitter or receiver settings for each of a plurality of paths. According to an embodiment, the EQ controller 1200 can determine the final EQ coefficient based on log information and error information. According to an embodiment, when the number of attempts at equalization operations for a pre-set preset combination exceeds a first threshold number, the EQ controller 1200 can determine one of the EQ coefficients as the final EQ coefficient. According to an embodiment, when the number of attempts at equalization operations for a pre-set preset combination exceeds a second threshold number, the EQ controller 1200 can determine the final EQ coefficient based on error information. According to an embodiment, when the number of attempts at equalization operations corresponding to each of the three EQ coefficients that caused the fewest errors per unit time in the L0 state exceeds a third threshold number, the EQ controller 1200 can determine one of the three EQ coefficients as the final EQ coefficient.

[0109] According to an embodiment, when a link connected to a PCIe interface device is reset, the EQ controller 1200 can determine, based on port information including FS or LF values, whether a leveling operation for an external device has been performed before the link is reset. According to an embodiment, when the number of errors occurring per unit time in the L0 state exceeds a threshold error value, the EQ controller 1200 can control the PCIe interface device to perform a re-leveling operation to reset the transmitter or receiver settings of each of the multiple paths.

[0110] Figure 14 This is a diagram illustrating a method of operating a PCIe interface according to an embodiment of the present disclosure.

[0111] exist Figure 14 The diagram illustrates a method for operating a PCIe interface. More specifically, the PCIe interface can be connected to an external device via a link comprising multiple paths. Furthermore, the PCIe interface can perform a balancing operation to determine the transmitter or receiver settings for each of the multiple paths. When the balancing operation is entered in step S1410, the PCIe interface can determine whether the physically connected link is connected to a new port. In other words, it can determine whether a balancing operation has previously been performed on the external device connected to the PCIe interface. The PCIe interface can determine whether the external device is the first to be connected to the new port of the PCIe interface based on port information including configuration read / write address order, full swing (FS) value, low frequency (LF) value, presence of a re-timer, number of re-timers, and bus number.

[0112] Additionally, when an external device is first connected to a new port of the PCIe interface (yes in step S1410), information about the port connected to the PCIe interface can be changed in step S1415. More specifically, the PCIe interface can manage log information or error rate (ER) based on port information. According to an embodiment, when an external device connected to the PCIe interface is determined to be a new port, existing recorded port information can be deleted.

[0113] Additionally, when the external device is not connected to a new port of the PCIe interface (No in step S1410), the PCIe interface can determine whether to store log information based on the port information in step S1420. Furthermore, the log information can indicate the number of equalization operations performed on multiple paths for each of the EQ coefficients.

[0114] When no log information is stored in the PCIe interface (No in step S1420), the PCIe interface can determine the EQ coefficients to a preset combination in step S1425. The EQ coefficients can be composed of a combination of preamble, main index, and postscript. Additionally, in step S1440, the PCIe interface can perform link connection based on the preset combination.

[0115] When log information is stored in the PCIe interface (yes in step S1420), the PCIe interface can determine the EQ coefficients or combinations based on the log information stored in the PCIe interface in step S1430 to test the equalization operation. See below for further details. Figure 15 Describe in detail the methods for determining EQ coefficients or combinations.

[0116] Additionally, in step S1440, the PCIe interface can perform link establishment based on the determined EQ coefficients or combinations. In step S1450, the PCIe interface can store log information corresponding to the determined EQ coefficients, as well as information about errors that occurred during the link establishment state. Errors may include at least one of training sequence errors, ordered set (OS) errors, receiver (RX) errors, decoding errors, synchronization header errors, and framing errors. Furthermore, the PCIe interface can store error information about errors that occurred in each of the multiple paths.

[0117] According to an embodiment, the PCIe interface can store margin information indicating the path margin calculated based on each of a plurality of paths. According to an embodiment, the PCIe interface can determine the final EQ coefficient based on log information and error information. According to an embodiment, when the number of tests for balancing operations against a pre-set preset combination exceeds a first threshold number, the PCIe interface can determine one of the EQ coefficients as the final EQ coefficient. The first threshold number can be 10 (+) and is appropriately calculated through repeated experiments. According to an embodiment, when the number of tests for balancing operations against all EQ coefficients exceeds a second threshold number, the PCIe interface can determine the final EQ coefficient based on error information. The second threshold number can be 10 (+) and is appropriately calculated through repeated experiments. According to an embodiment, when the number of tests for balancing operations corresponding to each of the three EQ coefficients that caused the fewest errors per unit time in the link-on state exceeds a third threshold number, the PCIe interface can determine one of the three EQ coefficients as the final EQ coefficient. The third threshold number can be between 20 (20) and 30 (30) and is appropriately calculated through repeated experiments.

[0118] In step S1460, the PCIe interface can determine whether the number of errors occurring per unit time during the link-on state exceeds a threshold error value. Furthermore, when the number of errors occurring per unit time exceeds the threshold error value (yes in step S1460), a rebalancing operation to reset the EQ coefficients can be performed in step S1470.

[0119] Figure 15 This is a diagram illustrating how an EQ coefficient is determined based on stored log information according to an embodiment of the present disclosure.

[0120] Reference Figure 15 When log information is stored in the PCIe interface ( Figure 14 (In step S1420, if yes), the PCIe interface can determine the EQ coefficients or combinations based on the log information stored in the PCIe interface to test the equalization operation.

[0121] More specifically, when log information is stored in the PCIe interface, the PCIe interface can, in step S1421, determine the number n of attempts at balancing operations for a preset combination of EQ coefficients or combinations. preset Does it exceed the first threshold number n? th1 .

[0122] In addition, when the number of attempts to perform equalization operations on the preset combination does not exceed the first threshold number (no in step S1421), the PCIe interface can determine the preset combination among the EQ coefficients as the combination to attempt equalization operations in step S1422.

[0123] Furthermore, when the number of attempts at balancing operations for a pre-defined preset combination exceeds a first threshold number (yes in step S1421), the PCIe interface can determine the number of attempts n for balancing operations for all EQ coefficients in step S1423. coef Does it exceed the second threshold number n? th2 .

[0124] When the number of attempts n for balancing operations across all EQ coefficients coef The number of items not exceeding the second threshold n th2 When (step S1423 is "No"), the PCIe interface can prepare or determine in step S1424 the combination of EQ coefficients with fewer or less frequent attempts at balancing operations as EQ coefficients for performing balancing operations.

[0125] Additionally, when the number of attempts n for balancing operations across all EQ coefficients coef The number of times n exceeds the second threshold th2 When (yes in step S1423), the PCIe interface can determine in step S1425 the number of attempts n for balancing operations for each of the three EQ coefficients with the minimum error rate. m_ER Does it exceed the third threshold number n? th3 .

[0126] The number of attempts n for balancing operations for each of the three EQ coefficients with the lowest error rate m_ER The number of items not exceeding the third threshold n th3 If (step S1425 is "No"), the PCIe interface can prepare in step S1426 a combination of three EQ coefficients with the minimum error rate to perform equalization operation on the EQ coefficients and the combination.

[0127] On the other hand, the number of attempts n for balancing operations for each of the three EQ coefficients with the lowest error rate m_ER The number of times n exceeds the third threshold th3When (yes in step S1425), the PCIe interface can prepare an EQ coefficient with the minimum error rate as a combination to perform equalization operation in step S1427.

[0128] According to an embodiment, the PCIe interface can determine the optimal EQ coefficient that satisfies all steps S1421, S1423, and S1425 as the final EQ coefficient.

[0129] According to this disclosure, a PCIe interface for performing improved PCIe balancing operations and a method thereof can be provided.

[0130] In the above embodiments, all steps may be selectively performed or skipped. Additionally, the steps in each embodiment may not always be performed in a regular order. Furthermore, the embodiments disclosed in this specification and accompanying drawings are intended to help those skilled in the art to better understand this disclosure, and are not intended to limit the scope of this disclosure. In other words, those skilled in the art will readily understand that various modifications can be made based on the technical scope of this disclosure. It will be apparent to those skilled in the art that various modifications can be made to the above exemplary embodiments of this disclosure without departing from the spirit or scope of the invention. Therefore, this disclosure is intended to cover all such modifications, provided they fall within the scope of the appended claims and their equivalents.

Claims

1. A high-speed peripheral component interconnect interface device, namely a PCIe interface device, wherein the PCIe interface device is connected to an external device via a link, the link including multiple paths, and the PCIe interface device includes: The equalizer controller, or EQ controller, controls the PCIe interface device to perform equalization operations, which are used to determine the transmitter settings or receiver settings for each of the plurality of paths. as well as An EQ information storage device stores log information and error information. The log information indicates the number of equalization attempts for each of a plurality of EQ coefficients, and the error information pertains to errors occurring in the L0 state for each of the plurality of EQ coefficients, including transmitter coefficients or receiver coefficients. The EQ controller uses the log information and the error information to determine the final EQ coefficient.

2. The PCIe interface device according to claim 1, wherein the error includes at least one of training sequence error, ordered set error (OS error), receiver error (RX error), decoding error, synchronization header error, and framing error.

3. The PCIe interface device according to claim 2, wherein the EQ information storage device stores error information about errors occurring in each of the plurality of paths.

4. The PCIe interface device of claim 1, wherein the EQ information storage device stores margin information indicating the calculated path margin for each of the plurality of paths.

5. The PCIe interface device according to claim 1, wherein each of the plurality of EQ coefficients comprises a combination of a prescript, a major index, and a postscript.

6. The PCIe interface device of claim 1, wherein when the number of attempts at equalization operations for a preset combination exceeds a first threshold number for the plurality of EQ coefficients, the EQ controller uses the log information to determine the final EQ coefficients.

7. The PCIe interface device of claim 1, wherein when the number of attempts at equalization operation for the plurality of EQ coefficients exceeds a second threshold number, the EQ controller uses the error information to determine the final EQ coefficient.

8. The PCIe interface device of claim 1, wherein when the number of attempts at equalization operation corresponding to each of the three EQ coefficients exceeds a third threshold number, the EQ controller determines one of the three EQ coefficients as the final EQ coefficient from among the plurality of EQ coefficients that have the fewest errors per unit time in the L0 state.

9. The PCIe interface device of claim 1, wherein when the link connected to the PCIe interface device is reset, the EQ controller uses port information to determine whether the equalization operation was performed on the external device before the link was reset, the port information including a full swing value (FS value) or a low frequency value (LF value).

10. The PCIe interface device of claim 1, wherein when the number of errors occurring per unit time in the L0 state exceeds a threshold error value, the EQ controller controls the PCIe interface device to perform a rebalancing operation, the rebalancing operation being used to reset the transmitter settings or receiver settings of each of the plurality of paths.

11. A method for operating a high-speed peripheral component interconnect interface device, i.e., a method for operating a PCIe interface device, the PCIe interface device being connected to an external device via a link including multiple paths, the method comprising: Determine if log information exists, the log information indicating the number of times the equalization operation was tested on the multiple channels for each of the multiple equalizer coefficients, i.e., multiple EQ coefficients. When the log information exists, the log information is used to determine the EQ coefficient to test the equalization operation; Link connection is established based on the determined EQ coefficient; and Store log information corresponding to the determined EQ coefficients, as well as error information about errors that occur while the link is connected.

12. The method of claim 11, wherein the error includes at least one of training sequence error, ordered set error (OS error), receiver error (RX error), decoding error, synchronization header error, and framing error.

13. The method of claim 12, wherein storing the error information comprises: Store error information about errors that occurred in each of the plurality of paths.

14. The method of claim 11, further comprising: The storage indicates the margin information of the calculated path margin for each of the plurality of paths.

15. The method of claim 11, wherein the EQ coefficient comprises a combination of a prefix, a major term, and a suffix.

16. The method of claim 11, further comprising: The log information and the error information are used to determine the final EQ coefficient.

17. The method of claim 16, wherein determining the final EQ coefficient comprises: Select at least one of the plurality of EQ coefficients from which the log information indicates that the number of times the equalization operation is tested for a preset combination exceeds a first threshold number.

18. The method of claim 16, wherein determining the final EQ coefficient comprises: When the number of times the equalization operation is tested for the multiple EQ coefficients exceeds a second threshold number, the error information is used to select the final EQ coefficient.

19. The method of claim 16, wherein determining the final EQ coefficient comprises: When the number of tests for the equalization operation corresponding to each of the three EQ coefficients exceeds a third threshold number, one of the three EQ coefficients is determined as the final EQ coefficient from among the plurality of EQ coefficients that have the fewest errors per unit time in the link-on state.

20. The method of claim 11, further comprising: When the number of errors occurring per unit time during the link-connected state exceeds the threshold error value, the plurality of EQ coefficients are reset.

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