Display device

Abstract

A display apparatus includes a display panel including a pixel coupled to a first scan line and a data line, a power supply supplying a voltage, a scan driver providing a first scan signal to the first scan line a plurality of times within a first frame period (FFP), a data driver supplying a data signal to the data line, and a timing controller controlling driving of components. The FFP includes a first active period (FAP) in which the data signal is supplied and a first blanking period (FBP) in which the data signal is not supplied. The power supply provides a turn-on bias power having a first voltage level (FVL) in the FAP and a turn-on bias power having a second voltage level (SVL) in the FBP. The FBP following the FAP includes a first dimming period in which the turn-on bias power is gradually changed from the FVL to the SVL.

Description

[0001] Cross-references to related applications

[0002] This application claims priority and benefit to Korean Patent Application No. 10-2021-0059497, filed on May 7, 2021, which is incorporated herein by reference for all purposes as fully set forth herein. Technical Field

[0003] Various embodiments generally relate to a display device. Background Technology

[0004] A display device includes a display panel (or pixel assembly) comprising multiple pixels and a driver for driving the display panel. The display device displays images on the display panel using image signals received from a graphics processor, such as an external graphics processor. The graphics processor generates image signals by rendering source data, and the rendering time spent generating image signals corresponding to a single frame can vary depending on the type or characteristics of the image. The driver can change its driving frequency (or frame rate) in response to the rendering time.

[0005] A pixel may include pixel circuitry and a light-emitting element. The pixel circuitry includes multiple transistors and capacitors. When a scan signal is supplied from a scan line, the pixel circuitry may be supplied with a data voltage from the data line, and the current of the driving transistor, set based on the data voltage, may be supplied to the light-emitting element. The light-emitting element may emit light with an intensity corresponding to the current of the driving transistor.

[0006] When a display device is driven at a low drive frequency, a single frame may include an active period for writing data signals and a blanking period for not writing data signals. Due to the leakage current and / or hysteresis characteristics of the driving transistor, the brightness of the display device may increase during the blanking period compared to the active period. To address this issue, the display device may supply a turn-on bias voltage (or initialization voltage) to the driving transistor multiple times (e.g., twice) in each of the active and blanking periods. Here, the amplitude of the turn-on bias voltage (or initialization voltage) supplied during the active period may be set to be different from the amplitude of the turn-on bias voltage (or initialization voltage) supplied during the blanking period.

[0007] However, when the on-bias voltage (or initialization voltage) is supplied multiple times (e.g., twice) in each of the active and blanking cycles, the timing of the supply of the on-bias voltage (or initialization voltage) in a particular cycle (e.g., the active cycle) can overlap with that in a subsequent particular cycle (e.g., the blanking cycle). Therefore, during a single frame, both the on-bias voltage (or initialization voltage) of the active cycle and the on-bias voltage (or initialization voltage) of the blanking cycle can be applied to an area starting from a specific location on the display panel (e.g., from the middle pixel row), creating a brightness difference across the boundary at that specific location on the display panel.

[0008] The information disclosed in this section is only for understanding the background of the inventive concept and may therefore contain information that does not constitute prior art. Summary of the Invention

[0009] Various embodiments relate to a display device capable of preventing display quality degradation caused by changes in leakage current and / or hysteresis characteristics of the driving transistor.

[0010] Additional aspects will be set forth in the following detailed description, and will be partially apparent from this disclosure, or may be learned by practicing the inventive concept.

[0011] According to an embodiment, a display device includes: a display panel, a power supply, a scan driver, a data driver, and a timing controller. The display panel includes pixels coupled to a first scan line and a data line. The power supply is configured to supply a driving power supply voltage, a conduction bias power supply voltage, a first initialization power supply voltage, and a second initialization power supply voltage to the display panel. The scan driver is configured to provide a first scan signal multiple times to the first scan line within a first frame period. The data driver is configured to supply a data signal to the data line. The timing controller is configured to control the driving of the power supply, the scan driver, and the data driver. The first frame period includes: a first active period, in which the data signal is supplied to the display panel; and a first blanking period, in which the data signal is not supplied to the display panel. The power supply is configured to: provide a conduction bias power supply having a first voltage level during the first active period; and provide a conduction bias power supply having a second voltage level different from the first voltage level during the first blanking period. The first blanking cycle following the first active cycle includes a first dimming cycle, in which the conduction bias power supply gradually changes from the first voltage level to the second voltage level.

[0012] The foregoing general description and the following detailed description are exemplary and illustrative, and are intended to provide further explanation of the claimed subject matter. Attached Figure Description

[0013] The accompanying drawings are included to provide a further understanding of the inventive concept, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the inventive concept and, together with the description, serve to illustrate the principles of the inventive concept.

[0014] Figure 1 This is a block diagram illustrating a display device according to an embodiment.

[0015] Figure 2 It is shown that, according to the embodiment, it is included Figure 1 A view of an example of a scan driver in a display device.

[0016] Figure 3 It is shown that, according to the embodiment, it is included Figure 1 A circuit diagram of an example pixel in a display device.

[0017] Figure 4 This illustrates the supply to, according to an embodiment Figure 3 A timing diagram of an example of the signal of a pixel.

[0018] Figure 5 This illustrates the supply within a single frame period according to an embodiment. Figure 3 A timing diagram of an example of the signal of a pixel.

[0019] Figure 6A This illustrates the supply to, according to an embodiment Figure 3 A timing diagram of an example of the pixel's on-bias power supply voltage and the second initialization power supply voltage.

[0020] Figure 6B This is for explanation based on the embodiments. Figure 6A Timing diagram of the on-bias power supply voltage and the second initialization power supply voltage.

[0021] Figure 6C Part (a) and Figure 6C Part (b) is a view illustrating the changes in brightness of a display device according to some embodiments to explain the effects of dimming cycles including those for turning on the bias power supply and the second initialization power supply.

[0022] Figure 7A This illustrates the supply to, according to an embodiment Figure 3 A timing diagram of an example of the pixel's on-bias power supply voltage and the second initialization power supply voltage.

[0023] Figure 7B This is for explanation based on the embodiments. Figure 7A Timing diagram of the on-bias power supply voltage and the second initialization power supply voltage.

[0024] Figure 8A This illustrates the supply to, according to an embodiment Figure 3 A timing diagram of an example of the pixel's on-bias power supply voltage and the second initialization power supply voltage.

[0025] Figure 8B This is for explanation based on the embodiments. Figure 8A Timing diagram of the on-bias power supply voltage and the second initialization power supply voltage.

[0026] Figure 8C Part (a) and Figure 8C Part (b) is a view illustrating the changes in brightness of a display device according to some embodiments to explain the effects of dimming cycles including those for turning on the bias power supply and the second initialization power supply.

[0027] Figure 9A This illustrates the supply to, according to an embodiment Figure 3 A timing diagram of an example of the pixel's on-bias power supply voltage and the second initialization power supply voltage.

[0028] Figure 9B This is for explanation based on the embodiments. Figure 9A Timing diagram of the on-bias power supply voltage and the second initialization power supply voltage.

[0029] Figure 10 This illustrates the supply to, according to an embodiment Figure 3 A timing diagram of an example of the signal of a pixel.

[0030] Figure 11 This illustrates the supply to, according to an embodiment Figure 3 A timing diagram of an example of the signal of a pixel.

[0031] Figure 12 It is shown that, according to the embodiment, it is included Figure 1 A circuit diagram of an example pixel in a display device. Detailed Implementation

[0032] In the following description, numerous specific details are set forth for purposes of explanation to provide a full understanding of the various embodiments. As used herein, the terms “embodiment” and “implementation” are used interchangeably and are non-limiting examples employing one or more inventive concepts disclosed herein. However, it will be apparent that various embodiments may be practiced without these specific details or by one or more equivalent arrangements. In other instances, well-known structures and arrangements are shown in block diagram form to avoid unnecessarily obscuring the various embodiments. Furthermore, the various embodiments may be different but are not necessarily exclusive. For example, the specific shape, configuration, and characteristics of an embodiment may be used or implemented in another embodiment without departing from the inventive concept.

[0033] Unless otherwise stated, the embodiments shown are to be understood as exemplary features providing different details of some embodiments. Therefore, unless otherwise stated, features, components, modules, layers, films, panels, areas, aspects, etc. of various views (hereinafter individually or collectively referred to as “elements” or “multiple elements”) may be combined, separated, interchanged and / or rearranged in other ways without departing from the inventive concept.

[0034] The use of crosshairs and / or shading in the accompanying drawings is generally provided to clearly define the boundaries between adjacent elements. Thus, unless otherwise stated, the presence or absence of crosshairs or shading does not convey or indicate any preference or requirement for the specific material, material properties, size, proportions, commonalities between the elements shown, or any other characteristics, properties, performance, etc., of the elements. Furthermore, the dimensions and relative dimensions of elements may be exaggerated in the drawings for clarity and / or descriptive purposes. Thus, the dimensions and relative dimensions of individual elements are not necessarily limited to those shown in the drawings. When embodiments can be implemented differently, the specific process sequence may be performed differently from the order described. For example, two consecutively described processes may be performed substantially simultaneously or in the reverse order of their description. Moreover, the same reference numerals refer to the same elements.

[0035] When an element, such as a layer, is referred to as being "on" another element, "connected to," or "coupled to" another element, the element may be directly on, directly connected to, or directly coupled to the other element, or an intermediary element may be present. However, when an element is referred to as being "directly on" another element, "directly connected to," or "directly coupled to" another element, an intermediary element is not present. Other terms and / or phrases used to describe the relationship between elements should be interpreted in a similar manner, such as "between" versus "directly between," "adjacent" versus "directly adjacent," "on" versus "directly on," etc. Furthermore, the term "connection" can refer to a physical connection, an electrical connection, and / or a fluid connection. For the purposes of this disclosure, "at least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" can be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z, such as XYZ, XYY, YZ, and ZZ. As used herein, the term “and / or” includes any and all combinations of one or more of the relevant listed items.

[0036] Although the terms “first,” “second,” etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. Therefore, without departing from the teachings of this disclosure, the first element discussed below may be referred to as the second element.

[0037] For descriptive purposes, spatial relative terms such as “below,” “under,” “below,” “down,” “above,” “above,” “higher,” and “side” (e.g., as in “sidewall”) may be used herein to describe the relationship of one element to another (or more elements) as shown in the accompanying drawings. In addition to the orientations depicted in the drawings, the spatial relative terms are also intended to cover different orientations of the device during use, operation, and / or manufacture. For example, if the device in the drawings is flipped, an element described as “below” or “under” other elements or features will subsequently be oriented “above” other elements or features. Thus, the term “below” can cover both above and below orientations. Furthermore, the device may be otherwise oriented (e.g., rotated 90 degrees or in other orientations), and thus, the spatial relative descriptive terms used herein shall be interpreted accordingly.

[0038] The terminology used herein is for the purpose of describing some embodiments and is not intended to be limiting. As used herein, unless the context clearly indicates otherwise, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well. Furthermore, when the terms “comprising,” “including,” “containing,” and / or “having” are used in this specification, they indicate the presence of the stated features, integrals, steps, operations, elements, components, and / or groups thereof, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof. It should also be noted that, as used herein, the terms “substantially,” “about,” and other similar terms are used as approximate terms rather than terms of degree, and thus, the terms “substantially,” “about,” and other similar terms are used to explain the inherent biases of measured, calculated, and / or provided values ​​that will be recognized by those skilled in the art.

[0039] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. Unless expressly defined herein, terms (such as those defined in a general dictionary) shall be interpreted as having a meaning consistent with their meaning in the context of the relevant field, and shall not be interpreted in an idealized or overly formalized sense.

[0040] As is customary in the art, some embodiments are described and illustrated in the accompanying drawings in the form of functional blocks, units, and / or modules. Those skilled in the art will understand that these blocks, units, and / or modules are physically implemented by electronic (or optical) circuitry such as logic circuits, discrete components, microprocessors, hardwired circuitry, storage elements, and wiring connections, which can be formed using semiconductor-based fabrication techniques or other manufacturing techniques. Where blocks, units, and / or modules are implemented by microprocessors or other similar hardware, they can be programmed and controlled using software (e.g., microcode) to perform the various functions discussed herein, and optionally, they can be driven by firmware and / or software. It is also considered that each block, unit, and / or module can be implemented by dedicated hardware, or as a combination of dedicated hardware for performing some functions and a processor (e.g., one or more programmed microprocessors and associated circuitry) for performing other functions. Furthermore, without departing from the inventive concept, each block, unit, and / or module of some embodiments can be physically divided into two or more interactive and discrete blocks, units, and / or modules. Furthermore, without departing from the concept of the present invention, blocks, units and / or modules of some embodiments can be physically combined into more complex blocks, units and / or modules.

[0041] In the following text, various embodiments will be explained in detail with reference to the accompanying drawings.

[0042] Figure 1 This is a block diagram illustrating a display device according to an embodiment.

[0043] Reference Figure 1 The display device 1000 may include a display panel 100, a scan driver 200, a transmit driver 300, a data driver 400, a power supply 500, and a timing controller 600.

[0044] The display device 1000 can display images at any of a variety of frame frequencies (e.g., refresh rate, drive frequency, or screen refresh rate) depending on the driving conditions. Frame frequency is the number of times per second that data voltage is actually written to the drive transistors of a pixel PX. For example, frame frequency is called screen scan rate or screen refresh rate, and represents the number of times the display screen refreshes per second.

[0045] In an embodiment, the output frequency of the fourth scan signal supplied to the fourth scan line S4i for the data driver 400 and / or for supplying data signals can vary in response to the frame rate. For example, the frame rate for playing video can be equal to or greater than approximately 60 Hz (e.g., 120 Hz). In this case, the fourth scan signal can be supplied to each horizontal line (each pixel row) 60 times per second.

[0046] In an embodiment, the display device 1000 can adjust the output frequencies of the scan driver 200 and the transmit driver 300 according to driving conditions, and can adjust the output frequency of the data driver 400 in response to the output frequencies. For example, the display device 1000 can display an image in response to any of a variety of frame frequencies, for example, in the range of 1 Hz to 120 Hz. However, this is merely an example, and the display device 1000 can also display images at frame frequencies equal to or greater than 120 Hz (e.g., 240 Hz, 480 Hz, etc.).

[0047] The display device 1000 can operate at any of various frame rates. When driven at low frequencies, image defects such as flickering may occur due to current leakage in the pixels. Furthermore, when the display device 1000 is driven at various frame rates, changes in the response speed may occur due to variations in the bias state of the driving transistors and shifts in the threshold voltage of the driving transistors based on changes in hysteresis characteristics, which may result in residual images, such as image blurring.

[0048] To improve image quality, a single frame period for a pixel PX can include a single active period and at least one blank period, depending on the frame frequency. (See reference...) Figure 4 and Figure 5 A more detailed description of the operation of the active cycle and the hidden cycle.

[0049] Display panel 100 may include scan lines S11 to S1n, S21 to S2n, S31 to S3n and S41 to S4n, transmit control lines E1 to En, data lines D1 to Dm, and pixels PX coupled to scan lines S11 to S1n, S21 to S2n, S31 to S3n and S41 to S4n, transmit control lines E1 to En and data lines D1 to Dm (m and n are integers greater than 1). Each pixel PX may include a driving transistor and a plurality of switching transistors. Pixel PX may be supplied with voltages (e.g., power supplies) from power supply 500, such as a first driving power supply VDD, a second driving power supply VSS, a conduction bias power supply Vobs, and an initialization power supply Vint.

[0050] In an embodiment, the signal lines coupled to the pixel PX can be configured differently in response to the circuit structure of the pixel PX.

[0051] The timing controller 600 can be supplied with input image data IRGB and control signals Sync and DE from a host system such as an application processor (AP) through a predetermined interface.

[0052] The timing controller 600 can generate a first control signal SCS, a second control signal ECS, a third control signal DCS, and a fourth control signal PCS based on input image data IRGB, a synchronization signal Sync (e.g., a vertical synchronization signal and / or a horizontal synchronization signal), a data enable signal DE, and / or a clock signal. The first control signal SCS can be supplied to the scan driver 200, the second control signal ECS to the transmit driver 300, the third control signal DCS to the data driver 400, and the fourth control signal PCS to the power supply 500. The timing controller 600 can rearrange (e.g., process) the input image data IRGB and supply the image data RGB to the data driver 400.

[0053] The scan driver 200 can receive a first control signal SCS from the timing controller 600, and can supply a first scan signal, a second scan signal, a third scan signal and a fourth scan signal to the first scan lines S11 to S1n, the second scan lines S21 to S2n, the third scan lines S31 to S3n and the fourth scan lines S41 to S4n respectively based on the first control signal SCS.

[0054] The first through fourth scan signals can be configured to have gate on-state voltages (e.g., low voltages) corresponding to the type of transistor to which the corresponding scan signal is supplied. When a scan signal is supplied to a transistor receiving the scan signal, the receiving transistor can be turned on. For example, the gate on-state voltage of a scan signal supplied to a P-channel metal-oxide-semiconductor (PMOS) transistor can be logic low, and the gate on-state voltage of a scan signal supplied to an N-channel metal-oxide-semiconductor (NMOS) transistor can be logic high. Hereinafter, “supplying a scan signal” can be understood as supplying a scan signal having a logic level that turns on the transistor thereby controlled.

[0055] The transmit driver 300 can supply transmit control signals to transmit control lines E1 to En based on the second control signal ECS. For example, the transmit control signals can be supplied sequentially to transmit control lines E1 to En.

[0056] The transmit control signal can be configured to have a gate cutoff voltage (e.g., a high voltage). When the transmit control signal is supplied to a transistor that receives the transmit control signal, the transistor receiving the transmit control signal can be turned off, and in other cases can be turned on. In the following text, "supplying a transmit control signal" can be understood as supplying a transmit control signal having a logic level that turns off the transistor thereby controlling it.

[0057] exist Figure 1 For ease of description, the scan driver 200 and the transmit driver 300 are shown as separate components, but the embodiment is not limited thereto. By design, the scan driver 200 may include a plurality of scan drivers, each of which supplies at least one of a first scan signal to a fourth scan signal. Furthermore, at least a portion of the scan driver 200 and the transmit driver 300 may be integrated into a drive circuit or module, etc.

[0058] The data driver 400 can receive a third control signal DCS and image data RGB from the timing controller 600. The data driver 400 can convert the digital image data RGB into an analog data signal (data voltage). The data driver 400 can supply data signals to data lines D1 to Dm in response to the third control signal DCS. Here, the data signals supplied to data lines D1 to Dm can be synchronized with the fourth scan signals supplied to the fourth scan lines S41 to S4n.

[0059] The power supply 500 can supply the voltage of the first driving power supply VDD and the voltage of the second driving power supply VSS to the display panel 100 to drive the pixels PX. The voltage level of the second driving power supply VSS can be lower than the voltage level of the first driving power supply VDD. For example, the voltage of the first driving power supply VDD can be a positive voltage and the voltage of the second driving power supply VSS can be a negative voltage, but the embodiment is not limited to this.

[0060] Power supply 500 can supply the voltage of the conduction bias power supply Vobs and the voltage of the initialization power supply Vint to the display panel 100. The initialization power supply Vint may include initialization power supplies output at different voltage levels (e.g., ...). Figure 3 Vint1 and Vint2).

[0061] The on-bias power supply Vobs can be a power supply used to supply a predetermined bias voltage to the source and / or drain electrodes of the driving transistor included in the pixel PX. The voltage level of the on-bias power supply Vobs can be a positive voltage. However, the voltage level of the on-bias power supply Vobs is not limited to this, and the voltage level of the on-bias power supply Vobs can be a negative voltage.

[0062] The initialization power supply Vint can be a power supply used to initialize a pixel PX. For example, the voltage of the initialization power supply Vint can be used to initialize the driving transistors and / or light-emitting elements included in the pixel PX. The voltage level of the initialization power supply Vint can be a negative voltage.

[0063] In an embodiment, the power supply 500 can change the voltage level of at least one of the conduction bias power supply Vobs and the initialization power supply Vint, and supply said voltage level to the display panel 100 within a single frame period. Therefore, the bias state of the driving transistors included in the pixel PX can be controlled.

[0064] Figure 2 It is shown that, according to the embodiment, it is included Figure 1 A view of an example of a scan driver in a display device.

[0065] Reference Figure 1 and Figure 2 The scan driver 200 may include a first scan driver 220, a second scan driver 240, a third scan driver 260, and a fourth scan driver 280.

[0066] The first control signal SCS may include the first scan start signal FLM1 to the fourth scan start signal FLM4. The first scan start signal FLM1 to the fourth scan start signal FLM4 may be supplied to the first scan driver 220, the second scan driver 240, the third scan driver 260 and the fourth scan driver 280 respectively.

[0067] The widths and supply timings of the first scan start signals FLM1 to the fourth scan start signals FLM4 can be set according to the driving conditions and frame rate of the pixel PX. The first scan signals to the fourth scan signals can be output based on the first scan start signals FLM1 to the fourth scan start signals FLM4, respectively. For example, the signal width of at least one of the first scan signals to the fourth scan signals can be different from the signal widths of the other signals (e.g., the signal widths of the other signals in the first scan signals to the fourth scan signals).

[0068] The first scan driver 220 can sequentially supply a first scan signal to the first scan lines S11 to S1n in response to the first scan start signal FLM1. The second scan driver 240 can sequentially supply a second scan signal to the second scan lines S21 to S2n in response to the second scan start signal FLM2. The third scan driver 260 can sequentially supply a third scan signal to the third scan lines S31 to S3n in response to the third scan start signal FLM3. The fourth scan driver 280 can sequentially supply a fourth scan signal to the fourth scan lines S41 to S4n in response to the fourth scan start signal FLM4.

[0069] Figure 3 It is shown that, according to the embodiment, it is included Figure 1 A circuit diagram of an example pixel in a display device.

[0070] exist Figure 3 For ease of description, pixel PX1 (where i and j are positive integers) located in the i-th horizontal line (or the i-th pixel row) and coupled to the j-th data line Dj is shown. Figure 3 The pixel PX1 shown can be with Figure 1 The pixel PX values ​​are basically the same.

[0071] Reference Figure 1 and Figure 3 Pixel PX1 may include a light-emitting element LD, a first transistor M1 to an eighth transistor M8, and a storage capacitor Cst.

[0072] The first electrode (e.g., anode or cathode) of the light-emitting element LD can be coupled to the sixth transistor M6 (or the fourth node N4), and the second electrode (e.g., cathode or anode) of the light-emitting element LD can be coupled to the second driving power supply VSS. The light-emitting element LD can generate light of a predetermined brightness in response to the amount of current (e.g., driving current) supplied from the first transistor M1.

[0073] In one embodiment, the light-emitting element LD can be an organic light-emitting diode including an organic light-emitting layer. In another embodiment, the light-emitting element LD can be an inorganic light-emitting element formed of inorganic materials. In yet another embodiment, the light-emitting element LD can be a light-emitting element formed of a combination of inorganic and organic materials. Alternatively, the light-emitting element LD can be in the form where a plurality of inorganic light-emitting elements are connected in parallel and / or in series with each other between the second driving power supply VSS and the sixth transistor M6.

[0074] The first electrode of the first transistor M1 (or driving transistor) can be coupled to the first node N1, and the second electrode of the first transistor M1 can be coupled to the second node N2. The gate electrode of the first transistor M1 can be coupled to the third node N3. The first transistor M1 can control the amount of current flowing from the first driving power supply VDD to the second driving power supply VSS via the light-emitting element LD in response to the voltage of the third node N3. For this purpose, the first driving power supply VDD can be set to a voltage higher than that of the second driving power supply VSS.

[0075] The second transistor M2 can be coupled between the j-th data line Dj (hereinafter referred to as data line Dj) and the first node N1. The gate electrode of the second transistor M2 can be coupled to the i-th fourth scan line S4i (hereinafter referred to as fourth scan line S4i). The second transistor M2 is turned on in response to the fourth scan signal supplied to the fourth scan line S4i, thereby electrically connecting the data line Dj to the first node N1.

[0076] The third transistor M3 can be coupled between the second electrode (or second node N2) of the first transistor M1 and the gate electrode (or third node N3) of the first transistor M1. The gate electrode of the third transistor M3 can be coupled to the i-th second scan line S2i (hereinafter referred to as the second scan line S2i). The third transistor M3 is turned on in response to a second scan signal supplied to the second scan line S2i, thereby electrically connecting the second electrode of the first transistor M1 to the gate electrode of the first transistor M1 (or electrically connecting the second node N2 to the third node N3). For example, the timing of connecting the second electrode (e.g., the drain electrode) of the first transistor M1 to the gate electrode of the first transistor M1 can be controlled by the second scan signal. In response to the third transistor M3 being turned on, the first transistor M1 can be coupled in a diode manner.

[0077] The fourth transistor M4 is turned on in response to a first scan signal supplied to the i-th first scan line S1i (hereinafter referred to as the first scan line S1i), thereby supplying the voltage of the conduction bias power supply Vobs to the first transistor M1. In an embodiment, the fourth transistor M4 may be coupled between the first node N1 (or the first electrode of the first transistor M1) and the conduction bias power supply Vobs. Here, the timing of supplying the voltage of the conduction bias power supply Vobs to the first node N1 may be controlled by the first scan signal.

[0078] The gate electrode of the fourth transistor M4 can be coupled to the first scan line S1i. In response to the fourth transistor M4 being turned on, the voltage of the turn-on bias power supply Vobs can be supplied to the first node N1. In an embodiment, the voltage of the turn-on bias power supply Vobs can have a level similar to the data voltage of a black grayscale level. For example, the voltage of the turn-on bias power supply Vobs can be approximately 5V to approximately 7V.

[0079] In response to the fourth transistor M4 being turned on, a predetermined high voltage can be applied to the first electrode (e.g., the source electrode) of the first transistor M1. Here, if the third transistor M3 is in the off state, the first transistor M1 can have a conduction bias state (e.g., the state in which the first transistor M1 can conduct).

[0080] In this embodiment, the voltage level of the on-bias power supply Vobs can change within a single frame period. For example, the on-bias power supply Vobs can have a first voltage level during the active period of a single frame period and a second voltage level during the blanking period of a single frame period. Alternatively, the on-bias power supply Vobs can have different voltage levels during the active and blanking periods. Here, the second voltage level can be higher than the first voltage level. In this example, when a single frame period includes a single active period and multiple blanking periods, the on-bias power supply Vobs can have a first voltage level during the single active period, a second voltage level during the first blanking period within the blanking periods, and a third voltage level during the second blanking period within the blanking periods. For example, the on-bias power supply Vobs can have different voltage levels during the active and blanking periods, and can also have different voltage levels during the first and second blanking periods within the blanking periods. Here, the third voltage level can be higher than the second voltage level. Therefore, in a low-frequency drive state with an increased length of a single frame period, the voltage level of the on-bias power supply Vobs used to apply the on-bias voltage to the first electrode (e.g., the source electrode) changes, thereby improving the display quality degradation caused by the change in the hysteresis characteristics of the first transistor M1.

[0081] In some embodiments, the voltage level of the on-bias power supply Vobs may differ in the active periods included in multiple frame periods. For example, when the first frame period includes only active periods, the active period of the second frame period following the first frame period may immediately follow the active period of the first frame period. Here, the voltage level of the on-bias power supply Vobs in the active period of the first frame period may differ from the voltage level of the on-bias power supply Vobs in the active period of the second frame period. For example, the voltage level of the on-bias power supply Vobs may be a first voltage level in the active period of the first frame period, but may be a second voltage level in the active period of the second frame period following the first frame period.

[0082] The fifth transistor M5 can be coupled between the first drive power supply VDD and the first node N1. The gate electrode of the fifth transistor M5 can be coupled to the i-th emitter control line Ei (hereinafter referred to as emitter control line Ei). The fifth transistor M5 is turned off in response to the emitter control signal supplied to the emitter control line Ei, and is turned on under other conditions.

[0083] The sixth transistor M6 can be coupled between the second electrode (or second node N2) of the first transistor M1 and the first electrode (or fourth node N4) of the light-emitting element LD. The gate electrode of the sixth transistor M6 can be coupled to the emission control line Ei. The sixth transistor M6 can be controlled in essentially the same way as the fifth transistor M5.

[0084] exist Figure 3 In the diagram, the fifth transistor M5 and the sixth transistor M6 are shown as being coupled to the same emitter control line Ei, but this is merely an example. The fifth transistor M5 and the sixth transistor M6 can be coupled to separate emitter control lines supplied with different emitter control signals.

[0085] A seventh transistor M7 can be coupled between the third node N3 and the first initialization power supply Vint1. The gate electrode of the seventh transistor M7 can be coupled to the i-th third scan line S3i (hereinafter referred to as the third scan line S3i). The seventh transistor M7 is turned on in response to the third scan signal supplied to the third scan line S3i, thereby supplying the voltage of the first initialization power supply Vint1 to the third node N3. Here, the voltage of the first initialization power supply Vint1 can be set to be lower than the voltage of the data signal supplied to the data line Dj. Therefore, the gate voltage of the first transistor M1 can be initialized to the voltage of the first initialization power supply Vint1 by turning on the seventh transistor M7.

[0086] The eighth transistor M8 can be coupled between the first electrode (or fourth node N4) of the light-emitting element LD and the second initialization power supply Vint2. In an embodiment, the gate electrode of the eighth transistor M8 can be coupled to the first scan line S1i. The eighth transistor M8 is turned on in response to a first scan signal supplied to the first scan line S1i, thereby supplying the voltage of the second initialization power supply Vint2 to the first electrode of the light-emitting element LD.

[0087] When the voltage of the second initialization power supply Vint2 is supplied to the first electrode of the light-emitting element LD, the parasitic capacitor of the light-emitting element LD can be discharged. Discharging the parasitic capacitor (e.g., eliminating residual voltage in the parasitic capacitor) prevents unintended light emission (e.g., slight emission). In this way, the ability of pixel PX1 to represent black can be improved.

[0088] In this embodiment, the voltage level of the second initialization power supply Vint2 can be changed within a single frame period. For example, the second initialization power supply Vint2 can have a third voltage level (VI1, see example) during the active period of a single frame period. Figure 6A Furthermore, a fourth voltage level (VI2, see example) can be present during the blanking period of a single frame period. Figure 6A For example, the second initialization power supply Vint2 can have different voltage levels in the active period and the blanking period. Here, the fourth voltage level can be lower than the third voltage level. In the example, when a single frame period includes a single active period and multiple blanking periods, the second initialization power supply Vint2 can have a third voltage level in the single active period, a fourth voltage level in the first blanking period within the blanking period, and a sixth voltage level (VI3, see example) in the second blanking period within the blanking period. Figure 7A For example, the second initialization power supply Vint2 can have different voltage levels during the active and blanking cycles, and can also have different voltage levels during the first and second blanking cycles within the blanking cycle. Here, the sixth voltage level can be lower than the fourth voltage level. Therefore, in a low-frequency drive state with an increased length of a single frame cycle, the voltage level of the second initialization power supply Vint2 applied to the first electrode (e.g., the anode electrode) of the light-emitting element LD changes, thereby changing the initialization amount of the parasitic capacitor used for the light-emitting element LD. In this way, brightness fluctuations caused by changes in the hysteresis characteristics of the first transistor M1 are prevented, thereby improving display quality degradation.

[0089] In some embodiments, the voltage level of the second initialization power supply Vint2 may differ in the active periods included in multiple frame periods. For example, when the first frame period includes only active periods, the active period of the second frame period following the first frame period may immediately follow the active period of the first frame period. Here, the voltage level of the second initialization power supply Vint2 in the active period of the first frame period may differ from the voltage level of the second initialization power supply Vint2 in the active period of the second frame period. For example, the voltage level of the second initialization power supply Vint2 may be a third voltage level in the active period of the first frame period, and may be a third voltage level (VI1_1, see example) in the active period of the second frame period following the first frame period. Figure 9A ).

[0090] The first initialization power supply Vint1 and the second initialization power supply Vint2 can have different voltages. For example, the voltage used to initialize the third node N3 and the voltage used to initialize the fourth node N4 can be set differently from each other.

[0091] In a low-frequency drive state with an increased length of a single frame cycle, when the voltage of the first initialization power supply Vint1 supplied to the third node N3 is too low, a strong conduction bias voltage is applied to the first transistor M1, thereby shifting the threshold voltage of the first transistor M1 in the corresponding single frame cycle. This hysteresis characteristic may cause flickering in the low-frequency drive state. Therefore, in a display device driven at a low frequency, the voltage of the first initialization power supply Vint1 can be higher than the voltage of the second drive power supply VSS.

[0092] However, when the voltage of the second initialization power supply Vint2 supplied to the fourth node N4 becomes higher than a predetermined reference value, the parasitic capacitor of the light-emitting element LD can be charged instead of discharged. Therefore, the voltage of the second initialization power supply Vint2 should be low enough to discharge the parasitic capacitor of the light-emitting element LD (e.g., low enough to eliminate the voltage of the parasitic capacitor). For example, considering the threshold voltage of the light-emitting element LD, the voltage of the second initialization power supply Vint2 can be set such that the voltage of the second initialization power supply Vint2 is lower than the sum of the threshold voltage of the light-emitting element LD and the voltage of the second driving power supply VSS.

[0093] However, this is merely an example, and the voltages of the first initialization power supply Vint1 and the second initialization power supply Vint2 can be set differently. For instance, the voltages of the first initialization power supply Vint1 and the second initialization power supply Vint2 can be substantially equal.

[0094] The storage capacitor Cst is coupled between the first drive power supply VDD and the third node N3. The storage capacitor Cst can store the voltage applied to the third node N3.

[0095] According to some embodiments, the first transistor M1, the second transistor M2, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, and the eighth transistor M8 can be formed of polysilicon semiconductor transistors. For example, the first transistor M1, the second transistor M2, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, and the eighth transistor M8 may include a polysilicon semiconductor layer as an active layer (or channel), which is formed using a low-temperature polysilicon (LTPS) process. Furthermore, the first transistor M1, the second transistor M2, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, and the eighth transistor M8 can be P-type transistors (e.g., PMOS transistors). Therefore, the gate on-state voltage for turning on the first transistor M1, the second transistor M2, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, and the eighth transistor M8 can have a logic low level. Because polysilicon semiconductor transistors have the advantage of fast response time, they can be used in switching elements that achieve fast switching.

[0096] The third transistor M3 and the seventh transistor M7 can be formed of oxide semiconductor transistors. For example, the third transistor M3 and the seventh transistor M7 can be N-type oxide semiconductor transistors (e.g., NMOS transistors) and can include an oxide semiconductor layer as an active layer. Therefore, the gate on-state voltage used to turn on the third transistor M3 and the seventh transistor M7 can have a logic high level.

[0097] Oxide-semiconductor (OSB) transistors can be fabricated using low-temperature processes and exhibit lower charge mobility compared to polysilicon (PSB) transistors. For example, OSB transistors possess superior cutoff current characteristics. When the third transistor M3 and the seventh transistor M7 are formed using OSB transistors, leakage current caused by low-frequency driving can be minimized, thereby improving display quality.

[0098] However, the first transistor M1 to the eighth transistor M8 are not limited to the above description, and at least one of the first transistor M1, the second transistor M2, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6 and the eighth transistor M8 may be formed by an oxide semiconductor transistor, and / or at least one of the third transistor M3 and the seventh transistor M7 may be formed by a polysilicon semiconductor transistor.

[0099] Figure 4 This illustrates the supply to, according to an embodiment Figure 3A timing diagram of an example of the signal of a pixel. Figure 5 This illustrates the supply within a single frame period according to an embodiment. Figure 3 A timing diagram of an example of the signal of a pixel.

[0100] Reference Figures 3 to 5 In the case of frequency conversion drive used to control frame frequency, a single frame period FP can include an active period ACTP and a blanking period BLKP.

[0101] The active period ACTP can include a first non-emit period NEP1 and a first emit period EP1. The blanking period BLKP can include a second non-emit period NEP2 and a second emit period EP2. Figure 4 Non-emission periodic NEP and emission periodic EP can be respectively Figure 5 The first non-emission cycle NEP1 and the first emission cycle EP1.

[0102] The Active Cycle (ACTP) can include the period during which data signals corresponding to the actual output image are written. For example, when driving the display of a still image at a low frequency, data signals can be written for each Active Cycle (ACTP).

[0103] like Figure 5 As shown, the transmit control signal EMi can be supplied to the transmit control line Ei at a first frequency greater than the frame frequency. The third scan signal GIi and the fourth scan signal GWi can be supplied at a second frequency lower than the first frequency. For example, the first frequency can be 240Hz and the second frequency can be 60Hz. Here, the frequencies of the third scan signal GIi and the fourth scan signal GWi can be substantially equal to the frame frequency.

[0104] However, this is merely an example, and the second frequency can be equal to or lower than 60Hz. Due to the lower second frequency or the greater difference between the first and second frequencies, the number of repetitions of the blanking period BLKP in the frame period FP (e.g., the number of blanking periods BLKP) may increase. For example, depending on the frame frequency, the frame period FP may include a single active period ACTP and multiple consecutive blanking periods BLKP.

[0105] In this embodiment, the second scan signal GCI may be supplied only during the first non-emission cycle NEP1. The second scan signal GCI may be supplied to the second scan line S2i multiple times during the first non-emission cycle NEP1.

[0106] In this embodiment, the first scan signal GBi can be supplied during the first non-emission period NEP1 and the second non-emission period NEP2. The first scan signal GBi can be supplied to the first scan line S1i multiple times during the first non-emission period NEP1. Furthermore, the first scan signal GBi can be supplied to the first scan line S1i multiple times during the second non-emission period NEP2.

[0107] The first scan signal GBi can be a signal used to control the first transistor M1 to be in a biased state. For example, when the fourth transistor M4 is turned on in response to the first scan signal GBi, the voltage of the bias power supply Vobs can be supplied to the first node N1. Furthermore, the first scan signal GBi can be a signal used to initialize the light-emitting element LD. For example, when the eighth transistor M8 is turned on in response to the first scan signal GBi, the voltage of the second initialization power supply Vint2 can be supplied to the fourth node N4.

[0108] According to some embodiments, the display device may use a fourth transistor M4 to periodically apply a voltage of a conduction bias power supply Vobs to the first electrode (or source electrode) of a first transistor M1. In response to the voltage of the conduction bias power supply Vobs supplied to the source electrode of the first transistor M1, the first transistor M1 can be set to a conduction bias state, and the threshold voltage characteristic of the first transistor M1 can be changed. Therefore, in low-frequency driving states, degradation caused by the characteristics of the first transistor M1 being fixed in a specific state can be prevented.

[0109] In an embodiment, the voltage level of the on-bias power supply Vobs may differ during the active period ACTP and the blanking period BLKP of a single frame period FP. Here, the voltage level of the on-bias power supply Vobs may gradually change in response to transitions between the same type of period or between different types of periods within the active period ACTP and the blanking period BLKP. For example, regarding the transition from the active period ACTP to the blanking period BLKP, the blanking period BLKP may include a dimming period that begins at the start point of the blanking period BLKP and ends at a preset point, during which the voltage level of the on-bias power supply Vobs gradually increases. Therefore, the display quality degradation caused by changes in the hysteresis characteristics of the first transistor M1 can be improved.

[0110] According to some embodiments, the display device may use an eighth transistor M8 to periodically apply the voltage of a second initialization power supply Vint2 to the first electrode (or anode electrode) of the light-emitting element LD. When the voltage of the second initialization power supply Vint2 is supplied to the first electrode of the light-emitting element LD, the parasitic capacitor of the light-emitting element LD, which is charged with residual voltage, is discharged (e.g., residual voltage is eliminated), and unintended slight luminescence can be prevented.

[0111] In this embodiment, the voltage level of the second initialization power supply Vint2 may differ during the active period ACTP and the blanking period BLKP of a single frame period FP. Here, the voltage level of the second initialization power supply Vint2 may gradually change in response to transitions between periods of the same type or between different types within the active period ACTP and the blanking period BLKP. For example, regarding the transition from the active period ACTP to the blanking period BLKP, the blanking period BLKP may include a dimming period that begins at the start point of the blanking period BLKP and ends at a preset point, during which the voltage level of the second initialization power supply Vint2 gradually decreases. Therefore, the display quality degradation caused by residual voltage in the parasitic capacitors of the light-emitting element LD can be improved.

[0112] exist Figure 5 In this embodiment, the first scan signal GBi is shown as being supplied in each of the non-transmission cycles NEP1 and NEP2, but the embodiment is not limited to this. The first scan signal GBi may be supplied only in a portion of the second non-transmission cycle NEP2. For example, it may be supplied only in... Figure 5 During the active period ACTP and the second blanking period BLKP, the first scan signal GBi is supplied to the first scan line S1i.

[0113] The transmit control signal EMi has a logic low level during the transmit cycles EP, EP1, and EP2, and the other cycles besides the transmit cycles EP, EP1, and EP2 can be non-transmit cycles NEP, NEP1, and NEP2.

[0114] The gate on-state voltages of the second scan signal GCi and the third scan signal GIi, which are respectively supplied to the third transistor M3 and the seventh transistor M7 (which are N-type transistors), are logic high. The gate on-state voltage of the fourth scan signal GWi, which is supplied to the second transistor M2 (which is a P-type transistor), and the gate on-state voltage of the first scan signal GBi, which is supplied to the fourth transistor M4 and the eighth transistor M8 (which are P-type transistors), are logic low.

[0115] like Figure 5As shown, in the second non-emission cycle NEP2, which is the blanking cycle BLKP, the first scan signal GBi can be supplied to the first scan line S1i. Therefore, in the second non-emission cycle NEP2, the voltage of the conduction bias power supply Vobs can be supplied to the first electrode of the first transistor M1. For example, the conduction bias voltage can be periodically applied to the first transistor M1 regardless of the frame frequency. Moreover, in order to maintain a stable conduction bias state, the first scan signal GBi can be supplied to the first scan line S1i multiple times in the second non-emission cycle NEP2. Therefore, the brightness variation of the display device caused by the first transistor M1 in the frame cycle FP during the low-frequency drive state can be minimized or at least reduced. Even in the active cycle ACTP, the first scan signal GBi can be supplied to the first scan line S1i multiple times to drive the scan driver 200 and simplify the configuration of the display device 1000.

[0116] In the following text, reference will be made to Figure 3 and Figure 4 The operation of the scan signals GBi, GCI, GIi, and GWi, as well as the pixel PX1, supplied during the active cycle ACTP is described in more detail.

[0117] During the non-emit cycle (NEP), the transmit control signal EMi can be supplied to the transmit control line Ei. Therefore, the fifth transistor M5 and the sixth transistor M6 can be turned off during the non-emit cycle (NEP). The non-emit cycle (NEP) can include the first cycle P1 to the fifth cycle P5.

[0118] In the first cycle P1, the scan driver 200 (see...) Figure 1 The second scan signal GCI can be supplied to the second scan line S2i, and the first scan signal GBi can be supplied to the first scan line S1i. In an embodiment, the first scan signal GBi can be supplied after the second scan signal GCI. Therefore, in the first cycle P1, the fourth transistor M4 can be turned on after the third transistor M3 is turned on.

[0119] When only the fourth transistor M4 is turned on without the second scan signal GCI being supplied, the voltage of the turn-on bias power supply Vobs can be supplied to the first node N1 (and thus to the source electrode of the first transistor M1). Here, a high voltage of the turn-on bias power supply Vobs is applied to the first node N1, thereby allowing the first transistor M1 to have a turn-on bias state. For example, when the voltage of the turn-on bias power supply Vobs is equal to or higher than approximately 5V, the first transistor M1 has a source voltage and drain voltage equal to or higher than approximately 5V, and the absolute value of the gate-source voltage of the first transistor M1 can be increased.

[0120] In this state, when the data signal is supplied through the fourth scan signal GWi, the drive current changes unexpectedly due to the bias state of the first transistor M1, and the image brightness may fluctuate (e.g., increase).

[0121] To address this issue, the scan driver 200 can supply the second scan signal GCI in the first cycle P1 before the first scan signal GBi is supplied. Therefore, the third transistor M3 can be turned on before the fourth transistor M4 is turned on. With the third transistor M3 on, the second node N2 and the third node N3 can conduct electricity to each other. Subsequently, when the fourth transistor M4 is turned on, the voltage of the turn-on bias power supply Vobs can be transferred to the third node N3 via the first node N1. For example, the voltage difference between the first node N1 and the third node N3 can be reduced to the level of the threshold voltage of the first transistor M1. Therefore, in the first cycle P1, the amplitude of the gate-source voltage of the first transistor M1 can become very low. For example, the first transistor M1 can be set to a cut-off bias state.

[0122] As described above, in order to prevent an unexpected increase in brightness caused by the supply of voltage from the bias power supply Vobs before the data signal is written in the first cycle P1, the supply of the first scan signal GBi and the second scan signal GCI can be controlled so that the fourth transistor M4 is turned on while the third transistor M3 is turned on.

[0123] In this embodiment, during the first period P1, the width W1 of the second scan signal GCI can be greater than the width W2 of the first scan signal GBi. For example, during the first period P1, the third transistor M3 can be turned on before the fourth transistor M4 is turned on, and can be turned off after the fourth transistor M4 is turned off.

[0124] However, this is just an example, and the third transistor M3 can be turned off before the fourth transistor M4 is turned off.

[0125] In response to the first scan signal GBi, the eighth transistor M8 can be turned on, and the voltage of the second initialization power supply Vint2 can be supplied to the first electrode (or the fourth node N4) of the light-emitting element LD.

[0126] Subsequently, in the second cycle P2, the scan driver 200 (see...) Figure 1The third scan signal GIi can be supplied to the third scan line S3i. The seventh transistor M7 can be turned on in response to the third scan signal GIi. When the seventh transistor M7 is turned on, the voltage of the first initialization power supply Vint1 can be supplied to the gate electrode of the first transistor M1. For example, in the second cycle P2, the gate voltage of the first transistor M1 can be initialized based on the voltage of the first initialization power supply Vint1. Therefore, a strong on-bias voltage is applied to the first transistor M1, and the hysteresis characteristics may change (the threshold voltage of the first transistor M1 is shifted).

[0127] Subsequently, scan drive 200 (see Figure 1 In the third cycle P3, the second scan signal GCI can be supplied to the second scan line S2i. In response to the second scan signal GCI, the third transistor M3 can be turned on again. In the third cycle P3, the scan driver 200 can supply a fourth scan signal GWi to the fourth scan line S4i so that it overlaps with a portion of the second scan signal GCI. The second transistor M2 can be turned on in response to the fourth scan signal GWi, and a data signal can be provided to the first node N1.

[0128] Here, the first transistor M1 is diode-coupled via the conducting third transistor M3, and data signal writing and threshold voltage compensation can be performed. Because the supply of the second scan signal GCI is maintained even after the supply of the fourth scan signal GWi is stopped, the threshold voltage of the first transistor M1 can be compensated for a sufficient period of time.

[0129] Subsequently, scan drive 200 (see Figure 1 The first scan signal GBi can be supplied to the first scan line S1i again in the fourth cycle P4. Therefore, the fourth transistor M4 and the eighth transistor M8 can be turned on. The fourth transistor M4 is turned on, thereby supplying the voltage of the conduction bias power supply Vobs to the first node N1.

[0130] The effects of the strong on-bias voltage applied in the second cycle P2 can be eliminated by writing data signals and compensating for the threshold voltage. For example, compensation for the threshold voltage in the third cycle P3 may cause a significant reduction in the voltage difference between the gate and source (and drain) voltages of the first transistor M1. As a result, the characteristics of the first transistor M1 change again, and the drive current in the emit cycle EP may increase, or fluctuations in the black-gray level may occur.

[0131] To prevent this characteristic change, the fourth transistor M4 can be turned on in the fourth cycle P4. Therefore, in the fourth cycle P4, the voltage of the conduction bias power supply Vobs is supplied to the source electrode of the first transistor M1, thereby setting the first transistor M1 to the conduction bias state.

[0132] In order to set the first transistor M1 to a stable on-biased state before emission based on the operation in the fourth cycle P4, sufficient idle time is used between the fourth cycle P4 and the emission cycle EP. Therefore, a fifth cycle P5 can be inserted between the fourth cycle P4 and the emission cycle EP, in which none of the scan signals GBi, GCI, GIi, and GWi are supplied.

[0133] In an embodiment, the length of the fifth cycle P5 can be equal to or longer than four horizontal cycles. For example, the length of the fifth cycle P5 can be equal to or longer than approximately 10 μs. Therefore, the first transistor M1 can have a stable on-bias state before the emitt cycle EP. Thus, even when repeated with... Figure 5 The same frame period FP shown can also stably maintain the luminous brightness.

[0134] In an embodiment, it can be obtained from Figure 2 The first scan driver 220, the second scan driver 240, the third scan driver 260 and the fourth scan driver 280 respectively supply the first scan signal GBi, the second scan signal GCI, the third scan signal GIi and the fourth scan signal GWi.

[0135] Figure 6A This illustrates the supply to, according to an embodiment Figure 3 A timing diagram of an example of the pixel's on-bias power supply voltage and the second initialization power supply voltage. Figure 6B This is for explanation based on the embodiments. Figure 6A Timing diagram of the on-bias power supply voltage and the second initialization power supply voltage. Figure 6C Part (a) and Figure 6C Part (b) is a view illustrating the variation in brightness of a display device according to some embodiments to explain the effect of a dimming cycle including a bias power supply and a second initialization power supply. Here, for ease of description, it is assumed that the display device 1000 has ten pixel rows; however, the number of pixel rows in the display device 1000 is not limited to this. For example, when the resolution of the display device 1000 is Full High Definition (FHD), the number of pixel rows may be 1080, and when the resolution of the display device 1000 is Ultra High Definition (UHD), the number of pixel rows may be 2160.

[0136] Reference Figure 1 , Figure 4 , Figure 6Aand Figure 6C According to the embodiment, the first frame period FP1 may include a first active period ACTP1 and a first blanking period BLKP1. During the first active period ACTP1, data signals are supplied to the display panel 100, and during the first blanking period BLKP1, data signals are not supplied to the display panel 100.

[0137] For example, during the first active period ACTP1 of supplying the data enable signal DE, the scan driver 200 can supply the first scan signal GBi through the first scan line S1i and the fourth scan signal GWi through the fourth scan line S4i. For example, the scan driver 200 can sequentially supply the first scan signals GB1 to GB10 (i.e., GB1, GB2, GB3, GB4, GB5, GB6, GB7, GB8, GB9, and GB10) to each pixel row twice during the first active period ACTP1, and can sequentially supply the fourth scan signals GW1 to GW10 (i.e., GW1, GW2, GW3, GW4, GW5, GW6, GW7, GW8, GW9, and GW10) to each pixel row once during the first active period ACTP1. Here, the timing of the first supply of the first scan signals GB1 to GB10, provided twice in the first active cycle ACTP1, does not overlap with the subsequent first blanking cycle BLKP1. However, the timing of the second supply of the first scan signals GB1 to GB10 can partially overlap with the first blanking cycle BLKP1. Thus, the timing of the second supply of the first scan signals GB6 to GB10, which are supplied to the sixth to tenth pixel rows, can overlap with the first blanking cycle BLKP1.

[0138] During the first blanking period BLKP1 when the data enable signal DE is not provided, the scan driver 200 can supply the first scan signal GBi through the first scan line S1i, but may not supply the fourth scan signal GWi. For example, the scan driver 200 may sequentially supply the first scan signals GB1 to GB10 to each pixel row twice during the first blanking period BLKP1, but may not supply the fourth scan signals GW1 to GW10 during the first blanking period BLKP1.

[0139] Power supply 500 can provide a conduction bias power supply Vobs with a first voltage level Vob1 during the first active cycle ACTP1, and can provide a voltage level Vobs different from the first voltage level Vob1 during the first blanking cycle BLKP1 (e.g., ...). Figure 6AAs shown, the conduction bias power supply Vobs is a second voltage level Vob2 that is higher than the first voltage level Vob1. Here, the first blanking period BLKP1 after the first active period ACTP1 may include a first dimming period DIMP1, in which the conduction bias power supply Vobs is gradually changed from the first voltage level Vob1 to the second voltage level Vob2 (e.g., gradually or otherwise progressively changed).

[0140] Furthermore, the power supply 500 can provide a second initialization power supply Vint2 with a third voltage level VI1 during the first active cycle ACTP1, and can provide a power supply with a voltage level different from the third voltage level VI1 during the first blanking cycle BLKP1 (e.g., as...). Figure 6A As shown, the second initialization power supply Vint2 is at a fourth voltage level VI2, which is lower than the third voltage level VI1. The first blanking cycle BLKP1 after the first active cycle ACTP1 may include a first dimming cycle DIMP1_1, in which the second initialization power supply Vint2 is gradually changed from the third voltage level VI1 to the fourth voltage level VI2 (e.g., gradually or otherwise progressively changed).

[0141] Reference Figure 3 and Figure 6B According to the embodiment, the second voltage level Vob2 of the on-bias power supply Vobs can be higher than the first voltage level Vob1 of the on-bias power supply Vobs. Furthermore, the fourth voltage level VI2 of the second initialization power supply Vint2 can be lower than the third voltage level VI1 of the second initialization power supply Vint2.

[0142] In some embodiments, the lower the drive frequency, the longer the length of a single frame period (e.g., FP1). In other words, the number of blanking periods (e.g., BLKP1) included in a single frame (e.g., FP1) may increase. In this case, the degree of unintended variation in the drive current may increase due to the influence of the bias state of the first transistor M1. As a result, the brightness of the displayed image may fluctuate (e.g., brightness increases). In this case, as... Figure 6B As shown, in the first blanking cycle BLKP1, a conduction bias power supply Vobs with a voltage level (e.g., a second voltage level Vob2) higher than the voltage level in the first active cycle ACTP1 is supplied to pixel PX1, thereby effectively preventing fluctuations in image brightness during the blanking cycle (e.g., BLKP1).

[0143] Furthermore, during the first blanking cycle BLKP1, a second initialization power supply Vint2, having a voltage level lower than that in the first active cycle ACTP1 (e.g., a fourth voltage level VI2), is supplied to the light-emitting element LD included in the pixel PX1. This allows the initialization amount of the parasitic capacitor for the light-emitting element LD to increase in response to a decrease in the voltage level of the second initialization power supply Vint2 applied to the light-emitting element LD. Therefore, by controlling the increase in image brightness and the decrease in the brightness of the displayed image, fluctuations in image brightness can be improved.

[0144] However, as Figure 6C As shown in section (a), when the voltage of the conduction bias power supply Vobs and / or the voltage of the second initialization power supply Vint2 change rapidly without a dimming cycle (e.g., DIMP1 or DIMP1_1), a brightness difference (or half-mura) can be visually identified in the middle of a pixel row included in the display panel 100 (e.g., the sixth pixel row out of ten pixel rows). This is because, as referenced above... Figure 6A The timing of the second supply of the first scan signals GB1 to GB10, which are supplied twice in the first active cycle ACTP1, partially overlaps with the first blanking cycle BLKP1.

[0145] For example, since the timing of the first and second supplies of the first scan signals (e.g., GB1 to GB5) for the first to fifth pixel rows out of ten pixel rows corresponds to the first active cycle ACTP1, a conduction bias power supply Vobs with a first voltage level Vob1 and a second initialization power supply Vint2 with a third voltage level VI1 can be supplied uniformly. Therefore, the display panel 100 can display at a first brightness L1.

[0146] On the other hand, since the timing of the first supply of the first scan signal (e.g., GB6 to GB10) to the sixth to tenth pixel rows out of ten pixel rows corresponds to the first active period ACTP1, a conduction bias power supply Vobs with a first voltage level Vob1 and a second initialization power supply Vint2 with a third voltage level VI1 can be supplied; however, since the timing of the second supply of the first scan signal (e.g., GB6 to GB10) corresponds to the first blanking period BLKP1, a conduction bias power supply Vobs with a second voltage level Vob2 and a second initialization power supply Vint2 with a fourth voltage level VI2 can be supplied. Therefore, the display panel 100 can display at a second brightness L2 that is darker than the first brightness L1. Therefore, a brightness difference (or half-spot) can be visually identified in the middle of the pixel rows included in the display panel 100 (e.g., the sixth pixel row out of ten pixel rows).

[0147] To reduce the brightness difference, the display device 1000 according to the embodiment may include dimming cycles DIMP1 and DIMP1_1. In the dimming cycles DIMP1 and DIMP1_1, when the first active cycle ACTP1 changes to the first blanking cycle BLKP1 (or as the first active cycle ACTP1 changes to the first blanking cycle BLKP1), the voltage of the conduction bias power supply Vobs and the voltage of the second initialization power supply Vint2 are gradually changed.

[0148] like Figure 6B As shown, the voltage level of the bias power supply Vobs can be gradually increased from a first voltage level Vob1 to a second voltage level Vob2 within the first dimming cycle DIMP1. For example, the bias power supply Vobs can include a second-level voltage level Vob2_1, a second-level voltage level Vob2_2, a second-level voltage level Vob2_3, a second-level voltage level Vob2_4, and a second-level voltage level Vob2_5 within the first dimming cycle DIMP1. Here, the second-level voltage level Vob2_1, the second-level voltage level Vob2_2, the second-level voltage level Vob2_3, the second-level voltage level Vob2_4, and the second-level voltage level Vob2_5 can be increased in the order they are listed.

[0149] According to the embodiment, the first dimming cycle DIMP1 can correspond to half of the first blanking cycle BLKP1 (e.g., half the length of the first blanking cycle BLKP1), and the voltage level of the on-bias power supply Vobs can be increased based on a preset voltage width W and a preset voltage amplitude Vstp. For example, the voltage width W can be set by using a horizontal cycle 1H as the basic unit (e.g., 1H, 2H, and 3H, etc.), and the voltage amplitude Vstp can be set based on the following equation (1):

[0150] Vstp=(Vob2-Vob1) / (L_BLKP / (2×W)+1) Equation (1)

[0151] Where Vstp represents the voltage amplitude, Vob1 represents the first voltage level, Vob2 represents the second voltage level, L_BLKP represents the length of the blanking period, and W represents the voltage width.

[0152] Furthermore, the voltage level of the second initialization power supply Vint2 can be gradually decreased from the third voltage level VI1 to the fourth voltage level VI2 within the first dimming cycle DIMP1_1. For example, the second initialization power supply Vint2 can include voltage levels VI2_1, VI2_2, VI2_3, VI2_4, and VI2_5 within the first dimming cycle DIMP1_1. Here, voltage levels VI2_1, VI2_2, VI2_3, VI2_4, and VI2_5 can be decreased in the order they are listed.

[0153] According to the embodiment, the first dimming cycle DIMP1_1 can correspond to half of the first blanking cycle BLKP1 (e.g., half the length of the first blanking cycle BLKP1), and the voltage level of the second initialization power supply Vint2 can be reduced based on a preset voltage width W' and a preset voltage amplitude Vstp'. For example, the voltage width W' can be set by using a horizontal cycle 1H as the basic unit (e.g., 1H, 2H, and 3H, etc.), and the voltage amplitude Vstp' can be set based on the following equation (2):

[0154] Vstp'=(VI1-VI2) / (L_BLKP / (2×W')+1) Equation (2)

[0155] Where Vstp' represents the voltage amplitude, VI1 represents the third voltage level, VI2 represents the fourth voltage level, L_BLKP represents the length of the blanking period, and W' represents the voltage width.

[0156] Therefore, as Figure 6C As shown in part (b), the brightness difference (or half-spot) gradually changes from the middle of the pixel row included in the display panel 100 (e.g., from the sixth pixel row out of ten pixel rows), thereby preventing the brightness difference from being visually identified.

[0157] For example, since the timing of the first and second supplies of the first scan signals (e.g., GB1 to GB5) for the first to fifth pixel rows out of ten pixel rows corresponds to the first active cycle ACTP1, a conduction bias power supply Vobs with a first voltage level Vob1 and a second initialization power supply Vint2 with a third voltage level VI1 can be supplied. Therefore, the display panel 100 can display at a first brightness L1.

[0158] Furthermore, since the timing of the first supply of the first scan signal (e.g., GB6 to GB10) to the sixth to tenth pixel rows of the ten pixel rows corresponds to the first activity cycle ACTP1, a conduction bias power supply Vobs with a first voltage level Vob1 and a second initialization power supply Vint2 with a third voltage level VI1 can be supplied. However, it should be noted that the timing of the second supply of the first scan signal (e.g., GB6 to GB10) corresponds to the dimming cycle DIMP1 or DIMP1_1. Therefore, in the case of the sixth pixel row, by supplying the conduction bias power supply Vobs with a second voltage level Vob2_1 and the second initialization power supply Vint2 with a fourth voltage level VI2_1 to the sixth pixel row, the display panel 100 can display in the sixth pixel row at a second brightness L2_1 that is darker than the first brightness L1. In the case of the seventh pixel row, a conduction bias power supply Vobs having a voltage level of 2_2 Vob2_2 and a second initialization power supply Vint2 having a voltage level of 4_2 VI2_2 are supplied to the seventh pixel row, and the display panel 100 can display in the seventh pixel row at a brightness level of 2_2 L2_2 that is darker than the brightness level of 2_1 L2_1. In the case of the eighth pixel row, a conduction bias power supply Vobs having a voltage level of 2_3 Vob2_3 and a second initialization power supply Vint2 having a voltage level of 4_3 VI2_3 are supplied to the eighth pixel row, and the display panel 100 can display in the eighth pixel row at a brightness level of 2_3 L2_3 that is darker than the brightness level of 2_2 L2_2. In the case of the ninth pixel row, a conduction bias power supply Vobs having a 2_4 voltage level Vob2_4 and a second initialization power supply Vint2 having a 4_4 voltage level VI2_4 are supplied to the ninth pixel row, and the display panel 100 can display in the ninth pixel row at a 2_4 brightness L2_4 that is darker than the 2_3 brightness L2_3. In the case of the tenth pixel row, a conduction bias power supply Vobs having a 2_5 voltage level Vob2_5 and a second initialization power supply Vint2 having a 4_5 voltage level VI2_5 are supplied to the tenth pixel row, and the display panel 100 can display in the tenth pixel row at a 2_5 brightness L2_5 that is darker than the 2_4 brightness L2_4.

[0159] As described above, starting from the middle of the pixel row included in the display panel 100 (e.g., starting from the sixth pixel row out of ten pixel rows), the brightness gradually changes (e.g., decreases) from the 2_1 brightness L2_1 to the 2_5 brightness L2_5, thereby preventing brightness differences (or half-spots) from being visually identified. Figure 6CIn section (b), for ease of description, it is assumed that the display panel 100 comprises ten pixel rows. However, as stated above, as the resolution of the display device 1000 increases, the display panel 100 may include more pixel rows. Moreover, this disclosure is not limited thereto. In response to this, the voltage of the conduction bias power supply Vobs included in the dimming cycles DIMP1 and DIMP1_1 and the voltage of the second initialization power supply Vint2 can be divided into levels with smaller level differences, thereby further reducing the brightness difference between pixel rows.

[0160] Figure 7A This illustrates the supply to, according to an embodiment Figure 3 A timing diagram of an example of the on-bias power supply voltage and the second initialization power supply voltage for a pixel. Figure 7B This is for explanation based on the embodiments. Figure 7A The timing diagram shows the on-bias power supply voltage and the second initialization power supply voltage. For ease of description, it is assumed that the display device 1000 has ten pixel rows. However, the number of pixel rows in the display device 1000 is not limited to this. For example, when the resolution of the display device 1000 is Full HD (FHD), the number of pixel rows may be 1080, and when the resolution of the display device 1000 is Ultra HD (UHD), the number of pixel rows may be 2160.

[0161] Combination Figure 7A and Figure 7B The described embodiments relate to when combined with Figure 6A and Figure 6B Compared to the embodiment described, which involves the change in the voltage of the bias power supply Vobs and the change in the voltage of the second initialization power supply Vint2 during the transition from the first active period ACTP1 to the second blanking period BLKP1 in the first frame period FP1, the changes in the voltage of the bias power supply Vobs and the voltage of the second initialization power supply Vint2 during the transition from the first blanking period BLKP1 to the second blanking period BLKP2 in the first frame period FP1 are described.

[0162] Reference Figure 1 , Figure 4 , Figure 6A and Figure 7A According to the embodiment, the first frame period FP1 includes a first active period ACTP1 and a first blanking period BLKP1. In the first active period ACTP1, the data signal is supplied to the display panel 100. In the first blanking period BLKP1, the data signal is not supplied to the display panel 100. The first frame period FP1 may also include a second blanking period BLKP2 after the first blanking period BLKP1.

[0163] Even within the blanking cycles BLKP1 and BLKP2, the degree of change in drive current can increase as the frame period FP1 (or display period) becomes longer. For example, the degree of change in drive current in the second blanking cycle BLKP2 can be greater than that in the first blanking cycle BLKP1. To prevent this effect, the voltage of the on-bias power supply Vobs can have a first voltage level Vob1 in the active cycle ACTP1, a second voltage level Vob2 higher than the first voltage level Vob1 in the first blanking cycle BLKP1, and a fifth voltage level Vob3 higher than the second voltage level Vob2 in the second blanking cycle BLKP2. Furthermore, the second initialization power supply Vint2 can have a third voltage level VI1 in the active cycle ACTP1, a fourth voltage level VI2 lower than the third voltage level VI1 in the first blanking cycle BLKP1, and a sixth voltage level VI3 lower than the fourth voltage level VI2 in the second blanking cycle BLKP2.

[0164] For example, during the first blanking period BLKP1 and the second blanking period BLKP2, the scan driver 200 can supply the first scan signal GBi through the first scan line S1i, and may not supply the fourth scan signal GWi. For example, the scan driver 200 may sequentially supply the first scan signals GB1 to GB10 to each pixel row twice during the first blanking period BLKP1. Here, the timing of the first supply of the first scan signals GB1 to GB10 provided twice during the first blanking period BLKP1 does not overlap with the subsequent second blanking period BLKP2, but the timing of the second supply of the first scan signals GB1 to GB10 may partially overlap with the second blanking period BLKP2. For example, the timing of the second supply of the first scan signals GB6 to GB10 from the first scan signals GB1 to GB10 to the sixth to tenth pixel rows may overlap with the second blanking period BLKP2.

[0165] Power supply 500 can provide a conduction bias power supply Vobs with a second voltage level Vob2 during the first blanking cycle BLKP1, and can provide a voltage level Vobs different from the second voltage level Vob2 during the second blanking cycle BLKP2 (e.g., as shown in the image). Figure 7A As shown, the conduction bias power supply Vobs is a fifth voltage level Vob3, which is higher than the second voltage level Vob2. Here, the second blanking period BLKP2 after the first blanking period BLKP1 may include a first dimming period DIMP1_2, in which the conduction bias power supply Vobs gradually changes from the second voltage level Vob2 to the fifth voltage level Vob3.

[0166] Furthermore, the power supply 500 can provide a second initialization power supply with a fourth voltage level VI2 during the first blanking cycle BLKP1, and can provide a power supply with a voltage level different from the fourth voltage level VI2 during the second blanking cycle BLKP2 (e.g., as...). Figure 7A As shown, the second initialization power supply Vint2 is at the sixth voltage level VI3, which is lower than the fourth voltage level VI2. The second blanking period BLKP2, which follows the first blanking period BLKP1, may include the first dimming period DIMP1_3, in which the second initialization power supply Vint2 gradually changes from the fourth voltage level VI2 to the sixth voltage level VI3.

[0167] Reference Figure 3 and Figure 7B According to the embodiment, the fifth voltage level Vob3 of the on-bias power supply Vobs can be higher than the second voltage level Vob2 of the on-bias power supply Vobs. Furthermore, the sixth voltage level VI3 of the second initialization power supply Vint2 can be lower than the fourth voltage level VI2 of the second initialization power supply Vint2.

[0168] In the second blanking cycle BLKP2, a bias power supply Vobs with a voltage level higher than that in the first blanking cycle BLKP1 (e.g., the fifth voltage level Vob3) is supplied to pixel PX1, thereby effectively preventing image brightness fluctuations in the second blanking cycle BLKP2. Furthermore, in the second blanking cycle BLKP2, a second initialization power supply Vint2 with a voltage level lower than that in the first blanking cycle BLKP1 (e.g., the sixth voltage level VI3) is supplied to the light-emitting element LD included in pixel PX1. This allows the initialization amount of the parasitic capacitor for the light-emitting element LD to increase as the voltage level of the second initialization power supply Vint2 applied to the light-emitting element LD decreases (or as the voltage level of the second initialization power supply Vint2 applied to the light-emitting element LD decreases). Therefore, by controlling the increase in image brightness and the decrease in the brightness of the displayed image, image brightness fluctuations can be improved.

[0169] However, when transitioning from the first blanking cycle BLKP1 to the second blanking cycle BLKP2, the voltage of the on-bias supply Vobs and / or the voltage of the second initialization supply Vint2 change rapidly without a dimming cycle (e.g., DIMP1_2 or DIMP1_3), similar to... Figure 6C As shown in part (a), a brightness difference (or half-spot) can be visually identified in the middle of a row of pixels included in the display panel 100 (e.g., the sixth row of ten pixel rows).

[0170] This is because, as mentioned above... Figure 7A The timing of the first supply of the first scan signals GB1 to GB10 provided twice in the first blanking period BLKP1 does not overlap with the timing of the second blanking period BLKP2, but the timing of the second supply of the first scan signals GB1 to GB10 partially overlaps with the timing of the second blanking period BLKP2.

[0171] To reduce the brightness difference, the display device 1000 according to the embodiment may include dimming cycles DIMP1_2 and DIMP1_3. In the dimming cycles DIMP1_2 and DIMP1_3, when the first blanking cycle BLKP1 changes to the second blanking cycle BLKP2, the voltage of the conduction bias power supply Vobs and the voltage of the second initialization power supply Vint2 are gradually changed.

[0172] like Figure 7B As shown, the voltage level of the bias power supply Vobs can gradually increase from the second voltage level Vob2 to the fifth voltage level Vob3 within the first and second dimming cycles DIMP1_2. For example, the bias power supply Vobs can include voltage levels 5_1 Vob3_1, 5_2 Vob3_2, 5_3 Vob3_3, 5_4 Vob3_4, and 5_5 Vob3_5 within the first and second dimming cycles DIMP1_2. Here, voltage levels 5_1 Vob3_1, 5_2 Vob3_2, 5_3 Vob3_3, 5_4 Vob3_4, and 5_5 Vob3_5 can be increased in the order they are listed.

[0173] According to the embodiment, the first dimming cycle DIMP1_2 can correspond to half of the second blanking cycle BLKP2 (e.g., half the length of the second blanking cycle BLKP2), and the voltage level of the conduction bias power supply Vobs can be increased based on a preset voltage width W and a preset voltage amplitude Vstp. For example, the voltage width W can be set by using a horizontal cycle 1H as the basic unit (e.g., 1H, 2H, and 3H, etc.), and the voltage amplitude Vstp can be set based on the following equation (3):

[0174] Vstp=(Vob3-Vob2) / (L_BLKP / (2×W)+1) Equation (3)

[0175] Where Vstp represents the voltage amplitude, Vob2 represents the second voltage level, Vob3 represents the fifth voltage level, L_BLKP represents the length of the blanking period, and W represents the voltage width.

[0176] Furthermore, the voltage level of the second initialization power supply Vint2 can gradually decrease from the fourth voltage level VI2 to the sixth voltage level VI3 within the first and third dimming cycles DIMP1_3. For example, the second initialization power supply Vint2 can include voltage levels VI3_1 (6_1), VI3_2 (6_2), VI3_3 (6_3), VI3_4 (6_4), and VI3_5 (6_5) within the first and third dimming cycles DIMP1_3. Here, voltage levels VI3_1 (6_1), VI3_2 (6_2), VI3_3 (6_3), VI3_4 (6_4), and VI3_5 (6_5) can decrease in the order they are listed.

[0177] According to the embodiment, the first dimming cycle DIMP1_3 can correspond to half of the second blanking cycle BLKP2 (e.g., half the length of the second blanking cycle BLKP2), and the voltage level of the second initialization power supply Vint2 can be reduced based on a preset voltage width W' and a preset voltage amplitude Vstp'. For example, the voltage width W' can be set by using a horizontal cycle 1H as the basic unit (e.g., 1H, 2H, and 3H, etc.), and the voltage amplitude Vstp' can be set based on the following equation (4):

[0178] Vstp'=(VI2-VI3) / (L_BLKP / (2×W')+1) Equation (4)

[0179] Where Vstp' represents the voltage amplitude, VI2 represents the fourth voltage level, VI3 represents the sixth voltage level, L_BLKP represents the length of the blanking period, and W' represents the voltage width.

[0180] Therefore, similar to Figure 6C As shown in part (b), the brightness difference (or half-spot) gradually changes from the middle of the pixel row included in the display panel 100 (e.g., from the sixth pixel row out of ten pixel rows), thereby preventing the brightness difference from being visually recognized.

[0181] Figure 8A This illustrates the supply to, according to an embodiment Figure 3 A timing diagram of an example of the on-bias power supply voltage and the second initialization power supply voltage for a pixel. Figure 8B This is for explanation based on the embodiments. Figure 8A Timing diagram of the on-bias power supply voltage and the second initialization power supply voltage. Figure 8C Part (a) and Figure 8CPart (b) is a view illustrating the changes in brightness of a display device according to some embodiments to explain the effects of dimming cycles including those for turning on the bias power supply and the second initialization power supply. Here, for ease of description, it is assumed that the display device 1000 has ten pixel rows. However, the number of pixel rows in the display device 1000 is not limited to this. For example, when the resolution of the display device 1000 is Full High Definition (FHD), the number of pixel rows may be 1080, and when the resolution of the display device 1000 is Ultra High Definition (UHD), the number of pixel rows may be 2160.

[0182] Reference Figure 1 , Figure 4 , Figure 6A , Figure 8A and Figure 8C When combined with Figure 6A , Figure 6B , Figure 6C Part (a) and Figure 6C Compared to the embodiments described in part (b) which illustrate the transition from the first active period ACTP1 of the first frame period FP1 to the first blanking period BLKP1 of the first frame period FP1, the various embodiments described will involve the transition from the first blanking period BLKP1 of the first frame period FP1 to the second active period ACTP2 of the second frame period FP2.

[0183] Each of the first frame period FP1 and the second frame period FP2 according to the embodiment may include an active period ACTP1 or ACTP2 and a first blanking period BLKP1, during which a data signal is supplied to the display panel 100, and during the first blanking period BLKP1, no data signal is supplied to the display panel 100. In this case, the second active period ACTP2 of the second frame period FP2 may be after the first blanking period BLKP1 of the first frame period FP1.

[0184] For example, the scan driver 200 can supply the first scan signal GBi through the first scan line S1i within the first blanking period BLKP1. For example, the scan driver 200 can sequentially supply the first scan signals GB1 to GB10 to each pixel row twice within the first blanking period BLKP1. Here, the timing of the first supply of the first scan signals GB1 to GB10 provided twice in the first blanking period BLKP1 does not overlap with the subsequent second active period ACTP2, but the timing of the second supply of the first scan signals GB1 to GB10 can partially overlap with the second active period ACTP2. For example, the timing of the second supply of the first scan signals GB6 to GB10 from the first scan signals GB1 to GB10 to the sixth to tenth pixel rows can overlap with the second active period ACTP2.

[0185] In some embodiments, during the second active period ACTP2 that provides the data enable signal DE, the scan driver 200 can supply the first scan signal GBi via the first scan line S1i and the fourth scan signal GWi via the fourth scan line S4i. For example, the scan driver 200 can sequentially supply the first scan signals GB1 to GB10 to each pixel row twice during the second active period ACTP2, and can supply the fourth scan signals GW1 to GW10 to each pixel row once during the second active period ACTP2.

[0186] Power supply 500 can provide a conduction bias power supply Vobs with a second voltage level Vob2 during the first blanking cycle BLKP1, and can provide a voltage level Vobs different from the second voltage level Vob2 during the second active cycle ACTP2 (e.g., as shown in the image). Figure 8A As shown, the conduction bias power supply is the first voltage level Vob1_1, which is lower than the second voltage level Vob2. Here, the second active cycle ACTP2 after the first blanking cycle BLKP1 may include a second dimming cycle DIMP2, in which the conduction bias power supply Vobs gradually changes from the second voltage level Vob2 to the first voltage level Vob1_1.

[0187] Furthermore, the power supply 500 can provide a second initialization power supply Vint2 with a fourth voltage level VI2 during the first blanking cycle BLKP1, and can provide a power supply with a voltage level different from the fourth voltage level VI2 during the second active cycle ACTP2 (e.g., as...). Figure 8A As shown, the second initialization power supply Vint2 is the third_1 voltage level VI1_1, which is higher than the fourth voltage level VI2. The second active cycle ACTP2 after the first blanking cycle BLKP1 may include the second_1 dimming cycle DIMP2_1, in which the second initialization power supply Vint2 gradually changes from the fourth voltage level VI2 to the third_1 voltage level VI1_1.

[0188] Reference Figure 3 and Figure 8B According to the embodiment, the first voltage level Vob1_1 of the on-bias power supply Vobs can be lower than the second voltage level Vob2 of the on-bias power supply Vobs. Moreover, the third voltage level VI1_1 of the second initialization power supply Vint2 can be higher than the fourth voltage level VI2 of the second initialization power supply Vint2.

[0189] When the voltage of the on-bias supply Vobs and / or the voltage of the second initialization supply Vint2 change rapidly without a dimming cycle (e.g., DIMP2 or DIMP2_1) during the transition from the first blanking cycle BLKP1 to the second active cycle ACTP2, as... Figure 8C As shown in part (a), a brightness difference (or half-spot) can be visually identified in the middle of a row of pixels included in the display panel 100 (e.g., the sixth row of ten pixels).

[0190] This is because, as mentioned above... Figure 8A The timing of the first supply of the first scan signals GB1 to GB10 provided twice in the first blanking period BLKP1 does not overlap with the timing of the second active period ACTP2, but the timing of the second supply of the first scan signals GB1 to GB10 partially overlaps with the timing of the second active period ACTP2.

[0191] For example, since the timing of the first and second supplies of the first scan signals (e.g., GB1 to GB5) for the first to fifth pixel rows out of ten pixel rows corresponds to the first blanking period BLKP1, a conduction bias power supply Vobs with a second voltage level Vob2 and a second initialization power supply Vint2 with a fourth voltage level VI2 can be supplied. Therefore, the display panel 100 can display at a third brightness L3.

[0192] On the other hand, since the timing of the first supply of the first scan signal (e.g., GB6 to GB10) to the sixth to tenth pixel rows out of ten pixel rows corresponds to the first blanking period BLKP1, a conduction bias power supply Vobs with a second voltage level Vob2 and a second initialization power supply Vint2 with a fourth voltage level VI2 can be supplied. However, since the timing of the second supply of the first scan signal (e.g., GB6 to GB10) corresponds to the second activity period ACTP2, a conduction bias power supply Vobs with a first voltage level Vob1_1 and a second initialization power supply Vint2 with a third voltage level VI1_1 can be supplied. Therefore, the display panel 100 can display at a fourth brightness L4 that is brighter than the third brightness L3. Therefore, a brightness difference (or half-spot) can be visually identified in the middle of the pixel rows included in the display panel 100 (e.g., the sixth pixel row out of ten pixel rows).

[0193] To reduce the brightness difference, the display device 1000 according to the embodiment may include dimming cycles DIMP2 and DIMP2_1. In the dimming cycles DIMP2 and DIMP2_1, when the first blanking cycle BLKP1 changes to the second active cycle ACTP2, the voltage of the conduction bias power supply Vobs and the voltage of the second initialization power supply Vint2 are gradually changed.

[0194] like Figure 8B As shown, the voltage level of the bias power supply Vobs can gradually decrease from the second voltage level Vob2 to the first voltage level Vob1_1 within the second dimming cycle DIMP2. For example, the bias power supply Vobs can include voltage levels Vob1_11, Vob1_12, Vob1_13, Vob1_14, and Vob1_15 within the second dimming cycle DIMP2. Here, the voltage levels Vob1_11, Vob1_12, Vob1_13, Vob1_14, and Vob1_15 can decrease in the order they are listed.

[0195] According to the embodiment, the second dimming cycle DIMP2 can correspond to half of the second active cycle ACTP2 (e.g., half the length of the second active cycle ACTP2), and the voltage level of the on-bias power supply Vobs can be reduced based on a preset voltage width W and a preset voltage amplitude Vstp. For example, the voltage width W can be set by using a horizontal cycle 1H as the basic unit (e.g., 1H, 2H, and 3H, etc.), and the voltage amplitude Vstp can be set based on the following equation (5):

[0196] Vstp=(Vob2-Vob1_1) / (L_ACTP / (2×W)+1) Equation (5)

[0197] Where Vstp represents the voltage amplitude, Vob1_1 represents the first voltage level, Vob2 represents the second voltage level, L_ACTP represents the length of the active cycle, and W represents the voltage width.

[0198] Furthermore, the voltage level of the second initialization power supply Vint2 can be gradually increased from the fourth voltage level VI2 to the third voltage level VI1_1 within the second dimming cycle DIMP2_1. For example, the second initialization power supply Vint2 can include voltage levels VI1_11, VI1_12, VI1_13, VI1_14, and VI1_15 within the second dimming cycle DIMP2_1. Here, voltage levels VI1_11, VI1_12, VI1_13, VI1_14, and VI1_15 can be increased in the order they are listed.

[0199] According to the embodiment, the 2_1 dimming cycle DIMP2_1 can correspond to half of the second active cycle ACTP2 (e.g., half the length of the second active cycle ACTP2), and the voltage level of the second initialization power supply Vint2 can be increased based on a preset voltage width W' and a preset voltage amplitude Vstp'. For example, the voltage width W' can be set by using a horizontal cycle 1H as the basic unit (e.g., 1H, 2H, and 3H, etc.), and the voltage amplitude Vstp' can be set based on the following equation (6):

[0200] Vstp'=(VI1_1-VI2) / (L_ACTP / (2×W')+1) Equation (6)

[0201] Where Vstp' represents the voltage amplitude, VI1_1 represents the 3rd voltage level, VI2 represents the fourth voltage level, L_ACTP represents the length of the active cycle, and W' represents the voltage width.

[0202] Therefore, as Figure 8C As shown in part (b), the brightness difference (or half-spot) gradually changes from the middle of the pixel row included in the display panel 100 (e.g., from the sixth pixel row out of ten pixel rows), thereby preventing the brightness difference from being visually identified.

[0203] For example, since the timing of the first and second supplies of the first scan signals (e.g., GB1 to GB5) for the first to fifth pixel rows out of ten pixel rows corresponds to the first blanking period BLKP1, a conduction bias power supply Vobs with a second voltage level Vob2 and a second initialization power supply Vint2 with a fourth voltage level VI2 can be supplied. Therefore, the display panel 100 can display at a third brightness L3.

[0204] In some embodiments, since the timing of the first supply of the first scan signal (e.g., GB6 to GB10) to the sixth to tenth pixel rows of the ten pixel rows corresponds to the first blanking period BLKP1, a conduction bias power supply Vobs with a second voltage level Vob2 and a second initialization power supply Vint2 with a fourth voltage level VI2 can be supplied. However, the timing of the second supply of the first scan signal (e.g., GB6 to GB10) corresponds to the dimming periods DIMP2 and DIMP2_1. Therefore, in the case of the sixth pixel row, by supplying the conduction bias power supply Vobs with a first voltage level Vob1_11 and the second initialization power supply Vint2 with a third voltage level VI1_11 to the sixth pixel row, the display panel 100 can display in the sixth pixel row at a fourth brightness L4_1 that is brighter than the third brightness L3. In the case of the seventh pixel row, a conduction bias power supply Vobs with a voltage level of 1_12 Vob1_12 and a second initialization power supply Vint2 with a voltage level of 3_12 VI1_12 are supplied to the seventh pixel row, and the display panel 100 can display in the seventh pixel row at a brightness of 4_2 that is brighter than the brightness of 4_1 L4_1. In the case of the eighth pixel row, a conduction bias power supply Vobs with a voltage level of 1_13 Vob1_13 and a second initialization power supply Vint2 with a voltage level of 3_13 VI1_13 are supplied to the eighth pixel row, and the display panel 100 can display in the eighth pixel row at a brightness of 4_3 that is brighter than the brightness of 4_2 L4_2. In the case of the ninth pixel row, a conduction bias power supply Vobs with a voltage level of 1_14 Vob1_14 and a second initialization power supply Vint2 with a voltage level of 3_14 VI1_14 can be supplied to the ninth pixel row, and the display panel 100 can display in the ninth pixel row at a brightness of 4_4 L4_4, which is brighter than the brightness of 4_3 L4_3. In the case of the tenth pixel row, a conduction bias power supply Vobs with a voltage level of 1_15 Vob1_15 and a second initialization power supply Vint2 with a voltage level of 3_15 VI1_15 can be supplied to the tenth pixel row, and the display panel 100 can display in the tenth pixel row at a brightness of 4_5 L4_5, which is brighter than the brightness of 4_4 L4_4.

[0205] As described above, starting from the middle of the pixel row included in the display panel 100 (e.g., starting from the sixth pixel row out of ten), the brightness gradually changes (e.g., increases) from the 4_1 brightness L4_1 to the 4_5 brightness L4_5, thereby preventing brightness differences (or half-spots) from being visually identified. Figure 8CIn section (b), for ease of description, it is assumed that the display panel 100 comprises ten pixel rows. However, as stated above, as the resolution of the display device 1000 increases, the display panel 100 comprises more pixel rows. Moreover, this disclosure is not limited thereto. In response to this, the voltage of the conduction bias power supply Vobs included in the dimming cycles DIMP2 and DIMP2_1 and the voltage of the second initialization power supply Vint2 can be divided into levels with smaller level differences, thereby further reducing the brightness difference between pixel rows.

[0206] Figure 9A This illustrates the supply to, according to an embodiment Figure 3 A timing diagram of an example of the on-bias power supply voltage and the second initialization power supply voltage for a pixel. Figure 9B This is for explanation based on the embodiments. Figure 9A The timing diagram shows the on-bias power supply voltage and the second initialization power supply voltage. For ease of description, it is assumed that the display device 1000 has ten pixel rows. However, the number of pixel rows in the display device 1000 is not limited to this. For example, when the resolution of the display device 1000 is Full HD (FHD), the number of pixel rows may be 1080, and when the resolution of the display device 1000 is Ultra HD (UHD), the number of pixel rows may be 2160.

[0207] When combined with Figure 8A and Figure 8B When comparing the described embodiment involving the change in the voltage of the bias power supply Vobs during the transition from the first blanking period BLKP1 of the first frame period FP1 to the second active period ACTP2 of the second frame period FP2, in conjunction with the embodiment involving the change in the voltage of the second initialization power supply Vint2, Figure 9A and Figure 9B The described embodiments involve the change in voltage of the bias power supply Vobs and the change in voltage of the second initialization power supply Vint2 during the transition from the first active period ACTP1 of the first frame period FP1 to the second active period ACTP2 of the second frame period FP2.

[0208] Reference Figure 1 , Figure 4 , Figure 8A and Figure 9A According to the embodiment, the first frame period FP1 may only include a first active period ACTP1 that supplies data signals to the display panel 100. In this case, the first active period ACTP1 of the first frame period FP1 can be connected to the second active period ACTP2 of the subsequent second frame period FP2.

[0209] For example, in each of the first active cycle ACTP1 and the second active cycle ACTP2, the scan driver 200 can supply a first scan signal GBi via a first scan line S1i and a fourth scan signal GWi via a fourth scan line S4i. For example, the scan driver 200 can sequentially supply the first scan signals GB1 to GB10 to each pixel row twice within each of the first active cycle ACTP1 and the second active cycle ACTP2, and can sequentially supply the fourth scan signals GW1 to GW10 to each pixel row once within each of the first active cycle ACTP1 and the second active cycle ACTP2. Here, the timing of the first supply of the first scan signals GB1 to GB10 provided twice in the first active cycle ACTP1 does not overlap with the subsequent second active cycle ACTP2, but the timing of the second supply of the first scan signals GB1 to GB10 can partially overlap with the second active cycle ACTP2. For example, the timing of the second supply of the first scan signals GB6 to GB10 from the first scan signals GB1 to GB10 to the sixth to tenth pixel rows can overlap with the second active cycle ACTP2.

[0210] Power supply 500 can provide a conduction bias power supply Vobs with a first voltage level Vob1 in the first active cycle ACTP1, and can provide a voltage level Vobs different from the first voltage level Vob1 in the second active cycle ACTP2 (e.g., ...). Figure 9A As shown, the on-bias power supply Vobs is the first voltage level Vob1_1, which is lower than the first voltage level Vob1. Here, the second activity cycle ACTP2 after the first activity cycle ACTP1 may include the second dimming cycle DIMP2_2, in which the on-bias power supply Vobs gradually changes from the first voltage level Vob1 to the first voltage level Vob1_1.

[0211] Furthermore, the power supply 500 can provide a second initialization power supply Vint2 with a third voltage level VI1 in the first active cycle ACTP1, and can provide a power supply with a voltage level different from the third voltage level VI1 in the second active cycle ACTP2 (e.g., as...). Figure 9A As shown, the second initialization power supply Vint2 is at a voltage level VI1_1 (3_1) higher than the third voltage level VI1. The second activity cycle ACTP2, following the first activity cycle ACTP1, may include a second dimming cycle DIMP2_3, in which the second initialization power supply Vint2 gradually changes from the third voltage level VI1 to the third voltage level VI1_1.

[0212] Reference Figure 3 and Figure 9B According to the embodiment, the first voltage level Vob1_1 of the on-bias power supply Vobs can be lower than the first voltage level Vob1 of the on-bias power supply Vobs. Furthermore, the third voltage level VI1_1 of the second initialization power supply Vint2 can be higher than the third voltage level VI1 of the second initialization power supply Vint2. However, it is not limited to this; according to the embodiment, the first voltage level Vob1_1 of the on-bias power supply Vobs can be higher than the first voltage level Vob1 of the on-bias power supply Vobs, and the third voltage level VI1_1 of the second initialization power supply Vint2 can be lower than the third voltage level VI1 of the second initialization power supply Vint2.

[0213] When transitioning from the first active cycle ACTP1 to the second active cycle ACTP2, the voltage of the on-bias supply Vobs and / or the voltage of the second initialization supply Vint2 change rapidly without a dimming cycle (e.g., DIMP2_2 or DIMP2_3), similar to... Figure 8C As shown in part (a), a brightness difference (or half-spot) can be visually identified in the middle of a row of pixels included in the display panel 100 (e.g., the sixth row of ten pixel rows).

[0214] This is because, as mentioned above... Figure 9A The timing of the first supply of the first scan signals GB1 to GB10 provided twice in the first active cycle ACTP1 does not overlap with the timing of the second supply of the first scan signals GB1 to GB10 in the second active cycle ACTP2, but the timing of the second supply of the first scan signals GB1 to GB10 partially overlaps with the timing of the second active cycle ACTP2.

[0215] To reduce the brightness difference, the display device 1000 according to the embodiment may include dimming cycles DIMP2_2 and DIMP2_3. In the dimming cycles DIMP2_2 and DIMP2_3, when the first active cycle ACTP1 changes to the second active cycle ACTP2, the voltage of the conduction bias power supply Vobs and the voltage of the second initialization power supply Vint2 are gradually changed.

[0216] like Figure 9BAs shown, the voltage level of the bias power supply Vobs can gradually decrease from the first voltage level Vob1 to the first voltage level Vob1_1 within the second dimming cycle DIMP2_2. For example, the bias power supply Vobs can include the first voltage level Vob1_111, the first voltage level Vob1_112, the first voltage level Vob1_113, the first voltage level Vob1_114, and the first voltage level Vob1_115 within the second dimming cycle DIMP2_2. Here, the voltage levels Vob1_111 (1st voltage level), Vob1_112 (1st voltage level), Vob1_113 (1st voltage level), Vob1_114 (1st voltage level), and Vob1_115 (1st voltage level) can be decreased in the order they are listed.

[0217] According to the embodiment, the second dimming cycle DIMP2_2 can correspond to half of the second active cycle ACTP2 (e.g., half the length of the second active cycle ACTP2), and the voltage level of the bias power supply Vobs can be reduced based on a preset voltage width W and a preset voltage amplitude Vstp. For example, the voltage width W can be set by using a horizontal cycle 1H as the basic unit (e.g., 1H, 2H, and 3H, etc.), and the voltage amplitude Vstp can be set based on the following equation (7):

[0218] Vstp=(Vob1-Vob1_1) / (L_ACTP / (2×W)+1) Equation (7)

[0219] Where Vstp represents the voltage amplitude, Vob1 represents the first voltage level, Vob1_1 represents the 1_1th voltage level, L_ACTP represents the length of the active cycle, and W represents the voltage width.

[0220] Furthermore, the voltage level of the second initialization power supply Vint2 can be gradually increased from the third voltage level VI1 to the third voltage level VI1_1 within the second-third dimming cycle DIMP2_3. For example, the second initialization power supply Vint2 may include voltage levels VI1_111, VI1_112, VI1_113, VI1_114, and VI1_115 within the second-third dimming cycle DIMP2_3. Here, the voltage levels VI1_111, VI1_112, VI1_113, VI1_114, and VI1_115 can be increased in the order they are listed.

[0221] According to the embodiment, the second dimming cycle DIMP2_3 can correspond to half of the second active cycle ACTP2 (e.g., half the length of the second active cycle ACTP2), and the voltage level of the second initialization power supply Vint2 can be increased based on a preset voltage width W' and a preset voltage amplitude Vstp'. For example, the voltage width W' can be set by using a horizontal cycle 1H as the basic unit (e.g., 1H, 2H, and 3H, etc.), and the voltage amplitude Vstp' can be set based on the following equation (8):

[0222] Vstp'=(VI1_1-VI1) / (L_ACTP / (2×W')+1) Equation (8)

[0223] Where Vstp' represents the voltage amplitude, VI1 represents the third voltage level, VI1_1 represents the 3_1st voltage level, L_ACTP represents the length of the active cycle, and W' represents the voltage width.

[0224] Therefore, similar to Figure 8C As shown in part (b), the brightness difference (or half-spot) gradually changes from the middle of the pixel row included in the display panel 100 (e.g., from the sixth pixel row out of ten pixel rows), thereby preventing the brightness difference from being visually recognized.

[0225] Figure 10 This illustrates the supply to, according to an embodiment Figure 3 A timing diagram of an example of the signal of a pixel. Figure 11 This illustrates the supply to, according to an embodiment Figure 3 A timing diagram of an example of the signal of a pixel.

[0226] Apart from the width of some scan signals and the timing of the supply of some scan signals, Figure 10 and Figure 11 The timing diagram and Figure 4 The timing diagrams are the same or similar. Therefore, the same reference numerals are used to denote the same or corresponding components, and repeated descriptions will be omitted.

[0227] Reference Figure 3 , Figure 10 and Figure 11 The non-emission cycle NEP of the active cycle can include the first cycle P1 to the fifth cycle P5.

[0228] In an embodiment, such as Figure 10 As shown, the second cycle P2 and the third cycle P3 can partially overlap. For example, when the seventh transistor M7 is turned on in response to the third scan signal GIi, the third transistor M3 can be turned on in response to the second scan signal GCI. Because the third node N3 is in a state where the voltage of the first initialization power supply Vint1 has been supplied to the third node N3, and because the first transistor M1 is in a biased state, therefore... Figure 10 The characteristics of the first transistor M1 caused by the supply of the signal can be similar to those caused by... Figure 4 The characteristics of the first transistor M1 caused by the operation in the second cycle P2 and the third cycle P3.

[0229] In an embodiment, such as Figure 11 As shown, after stopping the supply of the second scan signal GCI in the first cycle P1, the supply of the first scan signal GBi can be stopped. In the first cycle P1, the fourth transistor M4 can turn on after the third transistor M3 turns on, and the fourth transistor M4 can turn off after the third transistor M3 turns off. In this case, because a voltage with a level similar to the voltage of the on-bias power supply Vobs is supplied to the second node N2, therefore... Figure 11 The characteristics of the first transistor M1 in the first cycle P1 can be similar to those in... Figure 4 The characteristics of the first transistor M1 in the first cycle P1.

[0230] As described above, it can be based on the supply to the scan driver ( Figure 1 The waveform of the clock signal (200) and included in the scan driver ( Figure 1 The output characteristics of the circuit in (200) are such that some scanning signals are output with a predetermined margin.

[0231] Figure 12 It is shown that, according to the embodiment, it is included Figure 1 A circuit diagram of an example pixel in a display device.

[0232] because Figure 12 The pixel PX2 has the same characteristics as the reference. Figure 3 The configuration and operation of the described pixel PX1 are the same, so except for the fourth transistor M4, the same reference numerals are used to indicate the same or corresponding components, and repeated descriptions will be omitted.

[0233] Reference Figure 12 The pixel PX2 may include a light-emitting element LD, a first transistor M1 to an eighth transistor M8, and a storage capacitor Cst.

[0234] In this embodiment, one electrode of the fourth transistor M4 may be coupled to the second node N2, and the other electrode of the fourth transistor M4 may be coupled to the on-bias power supply Vobs. The fourth transistor M4 may supply the voltage of the on-bias power supply Vobs to the second node N2 in response to a first scan signal supplied to the first scan line S1i. As described above, it is irrelevant which of the source and drain electrodes of the first transistor M1 is supplied with the voltage for on-biasing (e.g., Figure 3 Pixel PX1 is configured such that a voltage used for conduction bias is supplied to the source electrode of the first transistor M1, but Figure 12 Pixel PX2 is configured such that a voltage for conduction bias is supplied to the drain electrode of the first transistor M1.

[0235] The display device according to various embodiments gradually changes the on-bias voltage (or initialization voltage) of the first specific cycle (e.g., the active cycle) to the on-bias voltage (or initialization voltage) of the second specific cycle (e.g., the blanking cycle) by arranging a dimming cycle at the beginning of the second specific cycle when the first specific cycle transitions to the second specific cycle (or as the first specific cycle transitions to the second specific cycle). This prevents display quality degradation caused by changes in the leakage current and / or hysteresis characteristics of the driving transistor. However, the effects are not limited to those described above, and various extensions can be made without departing from the spirit and scope of this disclosure.

[0236] Although certain embodiments and implementations have been described herein, other embodiments and modifications will be apparent from this description. Therefore, the inventive concept is not limited to such embodiments, but rather to the broader scope of the appended claims and various obvious modifications and equivalent arrangements that will be apparent to those skilled in the art.

Claims

1. A display device, wherein, The display device includes: The display panel includes pixels coupled to the first scan line and the data line; A power supply is configured to supply the voltage of a drive power supply, the voltage of a conduction bias power supply, the voltage of a first initialization power supply, and the voltage of a second initialization power supply to the display panel. A scan driver configured to provide a first scan signal to the first scan line multiple times during a first frame period; A data driver, configured to supply data signals to the data line; and A timing controller is configured to control the driving of the power supply, the scan driver, and the data driver. The first frame period includes: In the first activity cycle, the data signal is supplied to the display panel; and During the first blanking cycle, the data signal is not supplied to the display panel. The power supply is configured as follows: A conduction bias power supply with a first voltage level is provided during the first active cycle; and During the first blanking cycle, a conduction bias power supply with a second voltage level different from the first voltage level is provided, and The first blanking cycle following the first active cycle includes a first dimming cycle, in which the conduction bias power supply gradually changes from the first voltage level to the second voltage level.

2. The display device according to claim 1, wherein, The first scan signal is configured to control the timing of supplying the voltage of the conduction bias power supply and the voltage of the second initialization power supply to the display panel.

3. The display device according to claim 1, wherein: The first scan signal is provided twice in each of the first active cycle and the first blanking cycle; and The timing of the second supply of the first scan signal provided twice during the first active cycle partially overlaps with the first blanking cycle following the first active cycle.

4. The display device according to claim 1, wherein: The first voltage level is lower than the second voltage level; and The voltage level of the bias power supply gradually increases from the first voltage level to the second voltage level during the first dimming cycle.

5. The display device according to claim 4, wherein: The first dimming cycle corresponds to half of the first blanking cycle; and The voltage level of the bias power supply is reduced based on a preset voltage width and a preset voltage amplitude.

6. The display device according to claim 5, wherein: The voltage width is set by using a horizontal period as the basic unit; and The voltage amplitude is set based on the following equation (1): Vstp=(Vob2-Vob1) / (L_BLKP / (2×W)+1) Equation (1) Wherein, Vstp represents the voltage amplitude, Vob1 represents the first voltage level, Vob2 represents the second voltage level, L_BLKP represents the length of the first blanking period, and W represents the voltage width.

7. The display device according to claim 1, wherein: The power supply is configured as follows: A second initialization power supply with a third voltage level is provided during the first activity cycle; and During the first blanking cycle, a second initialization power supply with a fourth voltage level different from the third voltage level is provided; and The first blanking cycle following the first active cycle includes a first dimming cycle, in which the second initialization power supply gradually changes from the third voltage level to the fourth voltage level.

8. The display device according to claim 7, wherein: The third voltage level is higher than the fourth voltage level; and The voltage level of the second initialization power supply gradually decreases from the third voltage level to the fourth voltage level during the first dimming cycle.

9. The display device according to claim 8, wherein: The first dimming cycle corresponds to half of the first blanking cycle; and The voltage level of the second initialization power supply is reduced based on a preset voltage width and a preset voltage amplitude.

10. The display device according to claim 9, wherein: The voltage width is set by using a horizontal period as the basic unit; and The voltage amplitude is set based on the following equation (2): Vstp=(VI1–VI2) / (L_BLKP / (2×W)+1) Equation (2) Wherein, Vstp represents the voltage amplitude, VI1 represents the third voltage level, VI2 represents the fourth voltage level, L_BLKP represents the length of the first blanking period, and W represents the voltage width.

11. The display device according to claim 1, wherein: The second frame period following the first frame period includes a second activity period, in which the data signal is supplied to the display panel; The power supply is configured to provide a conduction bias power supply with a first voltage level (1_1) during the second active cycle; and The second active cycle following the first blanking cycle includes a second dimming cycle in which the on-bias power supply is gradually changed from the second voltage level to the first voltage level.

12. The display device according to claim 11, wherein: The first scan signal is provided twice in each of the second active cycle and the first blanking cycle; and The timing of the second supply of the first scan signal provided twice during the first blanking period partially overlaps with the second active period following the first frame period.

13. The display device according to claim 11, wherein: The first voltage level is lower than the second voltage level; and The voltage level of the bias power supply gradually decreases from the second voltage level to the first voltage level during the second dimming cycle.

14. The display device according to claim 13, wherein: The second dimming cycle corresponds to half of the second activity cycle; and The voltage level of the bias power supply is reduced based on a preset voltage width and a preset voltage amplitude.

15. The display device according to claim 14, wherein: The voltage width is set by using a horizontal period as the basic unit; and The voltage amplitude is set based on the following equation (3): Vstp'=(Vob2-Vob1_1) / (L_ACTP / (2×W')+1) Equation (3) Wherein, Vstp' represents the voltage amplitude, Vob1_1 represents the first voltage level, Vob2 represents the second voltage level, L_ACTP represents the length of the second active cycle, and W' represents the voltage width.

16. The display device according to claim 11, wherein: The power supply is configured as follows: A second initialization power supply with a fourth voltage level is provided during the first blanking cycle; and During the second activity cycle, a second initialization power supply with a third_1 voltage level different from the fourth voltage level is provided; and The second activity cycle following the first blanking cycle includes a second dimming cycle, in which the second initialization power supply gradually changes from the fourth voltage level to the third voltage level.

17. The display device according to claim 16, wherein: The fourth voltage level is lower than the third_1 voltage level; and The voltage level of the second initialization power supply gradually increases from the fourth voltage level to the third voltage level during the second dimming cycle.

18. The display device according to claim 17, wherein: The second dimming cycle corresponds to half of the second activity cycle; and The voltage level of the second initialization power supply is increased based on a preset voltage width and a preset voltage amplitude.

19. The display device according to claim 18, wherein: The voltage width is set by using a horizontal period as the basic unit; and The voltage amplitude is set based on the following equation (4): Vstp'=(VI1_1-VI2) / (L_ACTP / (2×W')+1) Equation (4) Wherein, Vstp' represents the voltage amplitude, VI1_1 represents the third_1 voltage level, VI2 represents the fourth voltage level, L_ACTP represents the length of the second active cycle, and W' represents the voltage width.

20. The display device according to claim 1, wherein: The pixel is also coupled to the second scan line, the third scan line, the fourth scan line, and the emission control line; The display device further includes a transmitter driver configured to supply a transmitter control signal to the transmitter control line; and The scan driver is configured to supply the first scan signal to the fourth scan signal to the first scan line to the fourth scan line respectively during the period of supplying the transmit control signal.

21. The display device according to claim 20, wherein, Each of the pixels includes: Light-emitting elements; A first transistor is coupled between a first node and a second node, and the first transistor is configured to generate a drive current. A second transistor is coupled between the data line and the first node, and the second transistor is configured to turn on in response to the fourth scan signal; A third transistor is coupled between the second node and a third node corresponding to the gate electrode of the first transistor, the third transistor being configured to turn on in response to the second scan signal; A fourth transistor is configured to be turned on in response to the first scan signal to apply the voltage of the on-bias power supply to the first transistor; A fifth transistor, coupled between the drive power supply and the first node, is configured to turn off in response to the transmit control signal; A sixth transistor, coupled between the second node and the first electrode of the light-emitting element, is configured to turn off in response to the emission control signal; and A seventh transistor, coupled between the third node and the first initialization power supply, is configured to turn on in response to the third scan signal.

22. The display device according to claim 21, wherein: During the first activity cycle, the scan driver is configured as follows: The first scan signal is supplied through the first scan line; and The fourth scan signal is supplied through the fourth scan line; and During the first blanking cycle, the scan driver is configured to supply the first scan signal through the first scan line and not supply the fourth scan signal.

23. The display device according to claim 21, wherein, Each of the pixels also includes: An eighth transistor is coupled between the first electrode of the light-emitting element and the second initialization power supply, and the eighth transistor is configured to turn on in response to the first scan signal.

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