Semiconductor structure and its fabrication methods, semiconductor devices

Abstract

This disclosure relates to a semiconductor structure, a method for fabricating the same, and a semiconductor device. The method for fabricating the semiconductor structure includes: providing a substrate having a plurality of active regions; etching the active regions to form word line channels within the active regions; growing epitaxial silicon on both the sidewalls and bottomwalls of the word line channels; and oxidizing the epitaxial silicon or a portion of the active regions to form a gate oxide layer, the gate oxide layer surrounding word line contact holes; and forming word line structures within the word line contact holes. The semiconductor structure fabricated using this method can reduce the leakage probability between two adjacent word line structures and between the word line structure and the active regions, and can also reduce the linewidth of the word line structure and increase the density of the word line structure.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a semiconductor structure, a method for fabricating the same, and a semiconductor device. Background Technology

[0002] In the field of semiconductor technology, as the size of semiconductor structures continues to shrink, the density of buried word line structures is required to be higher and higher. This means that the distance between two adjacent word line structures needs to be continuously reduced, which greatly increases the probability of leakage between two adjacent word line structures and between word line structures and active regions.

[0003] At the same time, in order to increase the density of the buried character line structure, it is also necessary to reduce the line width of the buried character line structure, which is also a technical problem that urgently needs to be solved in this field.

[0004] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0005] The purpose of this disclosure is to overcome the shortcomings of the prior art and provide a semiconductor structure, a method for fabricating the same, and a semiconductor device. The semiconductor structure fabricated using this method can reduce the leakage probability between two adjacent word line structures and between a word line structure and an active region, and can also reduce the linewidth of the word line structure.

[0006] This disclosure provides a method for fabricating a semiconductor structure, including:

[0007] A substrate is provided, the substrate having a plurality of active regions;

[0008] The active region is etched to form word channel within the active region;

[0009] Epitaxial silicon is grown on both the sidewall and bottom wall of the word line channel, and the epitaxial silicon or the epitaxial silicon and part of the active region are oxidized to form a gate oxide layer, which surrounds the word line contact hole.

[0010] A character line structure is formed within the character line contact hole.

[0011] In one exemplary embodiment of this disclosure, the method for fabricating the semiconductor structure further includes:

[0012] A passivation layer is formed within the active region, such that the passivation layer is located on the side of the gate oxide layer away from the surface of the active region.

[0013] In one exemplary embodiment of this disclosure, the substrate material includes silicon; the step of forming a passivation layer within the active region, such that the passivation layer is located on the side of the gate oxide layer away from the surface of the active region, includes:

[0014] Oxygen ions are implanted in a portion of the active region to form an oxygen ion layer, such that the oxygen ion layer is located on the side of the gate oxide layer away from the surface of the active region.

[0015] The oxygen ion layer reacts with the silicon in the active region to form the passivation layer.

[0016] In an exemplary embodiment of this disclosure, the oxidation of the epitaxial silicon or the epitaxial silicon and a portion of the active region to form a gate oxide layer includes:

[0017] The epitaxial silicon or the epitaxial silicon and a portion of the active region are oxidized using an in-situ water vapor oxidation process to oxidize the silicon in the epitaxial silicon or the epitaxial silicon and a portion of the active region into silicon dioxide to form the gate oxide layer.

[0018] In one exemplary embodiment of this disclosure, reacting the oxygen ion layer with silicon in the active region to form the passivation layer includes:

[0019] While oxidizing the epitaxial silicon using an in-situ water vapor oxidation process, the heat generated by the in-situ water vapor oxidation process causes the oxygen ions in the oxygen ion layer to react with the silicon in the active region to form silicon dioxide, thereby constituting a passivation layer.

[0020] In one exemplary embodiment of this disclosure, the method for fabricating the semiconductor structure before etching the active region further includes:

[0021] A source / drain region and a channel region are formed within the substrate, such that the channel region is located on the surface of the oxygen ion layer, and the source / drain region is located on the surface of the channel region.

[0022] In an exemplary embodiment of this disclosure, implanting oxygen ions within a portion of the active region to form an oxygen ion layer includes:

[0023] Oxygen ions are implanted in a portion of the active region using the first energy to form an oxygen ion layer;

[0024] The first energy is between 100 keV and 1000 keV.

[0025] In one exemplary embodiment of this disclosure, the amount of oxygen ions implanted in a portion of the active region is 1×e. 14 pcs / cm 2 up to 1×e17 pcs / cm 2 .

[0026] In one exemplary embodiment of this disclosure, the thickness of the epitaxial silicon grown on the sidewalls and bottomwalls of the word line channel is 5 nm to 20 nm.

[0027] In an exemplary embodiment of this disclosure, the reaction temperature for oxidizing the epitaxial silicon or the epitaxial silicon and a portion of the active region using the in-situ water vapor oxidation process is 800°C to 1100°C, and the reaction pressure for oxidizing the epitaxial silicon or the epitaxial silicon and a portion of the active region is 1 Torr to 20 Torr.

[0028] In an exemplary embodiment of this disclosure, the reaction gas used to oxidize the epitaxial silicon or the epitaxial silicon and part of the active region using the in-situ water vapor oxidation process includes one or more of the following: a mixed gas composed of oxygen and hydrogen, a mixed gas composed of nitric oxide and hydrogen, and a mixed gas composed of nitrogen dioxide and hydrogen.

[0029] In one exemplary embodiment of this disclosure, the volume concentration of hydrogen in the reaction gas is 0.1% to 33%.

[0030] Another aspect of this disclosure provides a semiconductor structure, including:

[0031] A substrate having multiple active regions;

[0032] The word channel is located within the active region;

[0033] A gate oxide layer is located on the sidewall and bottom wall of the word line channel, and the gate oxide layer forms a word line contact hole;

[0034] The character line structure is located inside the character line contact hole;

[0035] The gate oxide layer is formed by growing epitaxial silicon on both the sidewalls and bottomwalls of the word channel, and oxidizing the epitaxial silicon or the epitaxial silicon and a portion of the active region.

[0036] In one exemplary embodiment of this disclosure, the semiconductor structure further includes:

[0037] A passivation layer is located on the side of the gate oxide layer away from the surface of the active region.

[0038] In another aspect, this disclosure provides a semiconductor device comprising the semiconductor structure described in any one of the preceding claims.

[0039] The technical solution provided in this disclosure can achieve the following beneficial effects:

[0040] The semiconductor structure fabrication method disclosed herein employs the method of growing epitaxial silicon on both the sidewalls and bottomwalls of the word line channel, and oxidizing the epitaxial silicon or a portion of the active region to form a gate oxide layer. Since epitaxial silicon has advantages such as fewer lattice defects and uniform resistivity, the resulting gate oxide layer exhibits excellent electrical performance and stability. Furthermore, by directly oxidizing the epitaxial silicon to form the gate oxide layer, the resulting gate oxide layer has fewer dangling bonds and trapped charges on the contact surface with the active region, thereby significantly reducing the probability of leakage current in the final word line structure during operation.

[0041] Furthermore, since this disclosure grows epitaxial silicon directly on the sidewalls and bottomwalls of the word line channel, and mainly oxidizes the grown epitaxial silicon when forming the gate oxide layer, it can consume little or no silicon in the active region, thereby reducing the silicon consumption between the two word line channels. This can prevent the problem of the final two word line structures being too close, the word line structure and the bit line contact pad, and the word line structure and the external signal line from being too close, and can further reduce the leakage probability of the manufactured semiconductor structure.

[0042] At the same time, since this disclosure can reduce the silicon consumption between the two word line channels, it can make the distance between the two word line channels as close as possible, thereby increasing the density of the word line structure.

[0043] In addition, this disclosure grows epitaxial silicon directly on the sidewalls and bottomwalls of the word line channel and oxidizes the epitaxial silicon into a gate oxide layer, which enables the width of the final word line contact hole to be narrower, thereby enabling the linewidth of the final word line structure to be smaller, which is beneficial to reducing the size of the semiconductor structure.

[0044] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0045] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0046] Figure 1 A schematic flowchart of a method for fabricating an example semiconductor structure according to the present disclosure is shown;

[0047] Figures 2-7A schematic flowchart of a method for fabricating an example semiconductor structure according to the present disclosure is shown.

[0048] Figure 8 A schematic flowchart of a method for fabricating another example semiconductor structure according to this disclosure is shown;

[0049] Figures 9-14 A schematic flow diagram of a method for fabricating another example semiconductor structure according to this disclosure is shown;

[0050] Figure 15 A schematic flowchart of a method for fabricating yet another example semiconductor structure according to this disclosure is shown.

[0051] Explanation of reference numerals in the attached figures:

[0052] 1. Substrate; 2. Word line channel; 3. Epitaxial silicon; 4. Gate oxide layer; 5. Word line contact hole; 6. Word line structure; 7. Oxygen ion layer; 8. Passivation layer; 11. Active region; 12. Source / drain region; 13. Channel region. Detailed Implementation

[0053] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, they are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and therefore their detailed description will be omitted.

[0054] Furthermore, in the following detailed description, numerous specific details are set forth for ease of explanation to provide a thorough understanding of the embodiments disclosed herein. However, it will be apparent that one or more embodiments may be practiced without these specific details.

[0055] It should be noted that the terms "on," "formed on," and "set on" used in this article can indicate that one layer is directly formed or set on another layer, or that one layer is indirectly formed or set on another layer, meaning that there are other layers between the two layers.

[0056] The terms “a,” “one,” “the,” “the,” and “at least one” are used to indicate the presence of one or more elements / components / etc.; the terms “including” and “having” are used to indicate an open-ended inclusion meaning and to mean that there may be other elements / components / etc. in addition to the listed elements / components / etc.

[0057] It should be noted that while terms such as "first," "second," etc., may be used herein to describe various components, parts, elements, regions, layers, and / or portions, these components, parts, elements, regions, layers, and / or portions should not be limited by these terms. Rather, these terms are used to distinguish one component, part, element, region, layer, and / or portion from another.

[0058] In this disclosure, unless otherwise stated, the term "same-layer arrangement" means that two layers, components, elements, or portions can be formed by the same patterning process, and that the two layers, components, elements, or portions are generally formed of the same material.

[0059] Currently, in the field of semiconductor technology, the formation of the gate oxide layer consumes silicon in the active region, which leads to the consumption of silicon between two adjacent word line channels. This reduces the distance between two adjacent word line structures, between word line structures and bit line contact pads, and between word line structures and external signal lines, making it easy for leakage problems to occur between these structures.

[0060] Furthermore, as semiconductor structure dimensions continue to shrink, the density of word lines in the semiconductor structure needs to be increased, which necessitates a continuous reduction in the distance between adjacent word line structures. If silicon between adjacent word line channels continues to be consumed during the formation of the gate oxide layer, the distances between adjacent word line structures, between word line structures and bit line contact pads, and between word line structures and external signal lines will become too small, thus exacerbating leakage problems between these structures.

[0061] In existing technologies, the method used to solve this technical problem is to first deposit a layer of silicon dioxide on the sidewalls and bottomwalls of the word channel using atomic layer deposition, while keeping the total gate oxide layer thickness constant. Then, a portion of the silicon in the active region is oxidized to form another layer of silicon dioxide on the side closest to the active region. These two layers of silicon dioxide together constitute the gate oxide layer. Thus, from the perspective of existing technology, this allows a portion of the gate oxide layer to be achieved without oxidizing the silicon in the active region, thereby reducing silicon consumption.

[0062] However, the applicant of this disclosure has discovered that in the prior art, the side of silicon dioxide manufactured by atomic layer deposition that contacts the active region contains a large number of dangling bonds and trapped charges, which can lead to leakage current and performance instability in the semiconductor structure. Furthermore, since the prior art still consumes a large portion of the silicon between two adjacent word line channels, it is impossible to significantly increase the density of the word line structure, and therefore impossible to significantly reduce the size of the semiconductor structure.

[0063] To address the aforementioned technical problems discovered by the inventors of this disclosure, the inventors, after careful consideration and considerable creative effort, have ultimately provided a new method for fabricating a semiconductor structure. This method can significantly reduce the probability of leakage current occurring in the final word line structure 6 during operation, and can also increase the density of the word line structure and reduce the linewidth of the word line structure, thereby facilitating the reduction of the size of the semiconductor structure.

[0064] In one embodiment of this disclosure, such as Figure 1 and Figures 2 to 7 As shown, the method for fabricating the above-mentioned semiconductor structure may include:

[0065] Step S10: Improve a substrate 1, wherein the substrate 1 has multiple active regions 11;

[0066] Step S20: Etch the active region 11 to form word line channels 2 within the active region 11;

[0067] Step S30: Epitaxial silicon 3 is grown on both the sidewall and bottom wall of the word line channel 2, and the epitaxial silicon 3 or the epitaxial silicon 3 and part of the active region 11 are oxidized to form a gate oxide layer 4, and the gate oxide layer 4 surrounds the word line contact hole 5.

[0068] Step S40: Form the word line structure 6 within the word line contact hole 5.

[0069] Therefore, this disclosure grows epitaxial silicon 3 on both the sidewalls and bottomwalls of the word line channel 2, and oxidizes the epitaxial silicon 3 or a portion of the active region 11 to form a gate oxide layer 4. Since the epitaxial silicon 3 has the advantages of few lattice defects and uniform resistivity, the formed gate oxide layer 4 exhibits excellent electrical performance and stability. Furthermore, by directly oxidizing the epitaxial silicon 3 to the gate oxide layer 4, the resulting gate oxide layer 4 has fewer dangling bonds and trapped charges on its contact surface with the active region 11, thereby greatly reducing the probability of leakage current in the final word line structure 6 during operation.

[0070] Furthermore, since the present disclosure grows epitaxial silicon 3 directly on the sidewalls and bottomwalls of the word line channel 2, and mainly oxidizes the grown epitaxial silicon 3 when forming the gate oxide layer 4, the silicon in the active region 11 can be consumed in small amounts or even not at all, thereby reducing the consumption of silicon between the two word line channels 2. This can prevent the problem of the two word line structures 6 being too close together, the word line structure 6 and the bit line contact pad, and the word line structure 6 and the external signal line, and further reduce the leakage probability of the manufactured semiconductor structure.

[0071] Furthermore, since this disclosure significantly reduces silicon consumption between the two word line channels 2 compared to existing technologies, it allows for making the distance between the two word line channels 2 as close as possible, thereby increasing the density of the word line structure 6. Moreover, this disclosure avoids leakage problems between adjacent word line structures 6, between word line structures 6 and bit line contact pads, and between word line structures 6 and external signal lines after increasing the density of the word line structure 6.

[0072] In addition, this disclosure grows epitaxial silicon 3 directly on the sidewalls and bottomwalls of the word line channel 2 and oxidizes the epitaxial silicon 3 into a gate oxide layer 4. This allows the width of the final word line contact hole 5 to be narrower than that of the prior art, thereby allowing the line width of the final word line structure 6 to be smaller than that of the prior art, which is more conducive to reducing the size of the semiconductor structure.

[0073] The steps of the method for fabricating the semiconductor structure according to the present disclosure will be described in detail below:

[0074] like Figure 2 In step S10, a substrate 1 can be provided. The substrate 1 can be a flat plate structure, which can be rectangular, circular, elliptical, polygonal or irregular shape. Its material can be silicon or other semiconductor materials. No special limitation is made on the shape and material of the substrate 1.

[0075] In one embodiment, the substrate 1 may be a silicon substrate 1 or the material of the substrate 1 may include silicon. Multiple shallow trench isolation structures are formed within the substrate 1. These shallow trench isolation structures are formed by creating trenches within the substrate 1 and then filling the trenches with an isolation material layer. The multiple shallow trench isolation structures may be arranged side-by-side or intersected, thereby isolating multiple active regions 11 on the substrate 1. The material of the shallow trench isolation structure may include silicon nitride or silicon dioxide, etc., and is not specifically limited herein; it can be selected according to actual needs. Furthermore, this disclosure does not limit the cross-sectional shape of the shallow trench isolation structure; it can also be set according to actual needs, all of which are within the protection scope of this disclosure.

[0076] In step S20, as Figure 4 As shown, the active region 11 can be etched to form word line channels 2 within the active region 11. Specifically, two word line channels 2 can be formed within one active region 11, and there is a gap between the two word line channels 2. Since the word line channels 2 can penetrate the substrate 1 in the semiconductor structure, word line channels 2 connected to the word line channels 2 in the active region 11 can also be provided in the shallow trench isolation structure. Furthermore, the width and depth of the word line channels 2 located in the shallow trench isolation structure can be the same as the width and depth of the word line channels 2 located in the active region 11.

[0077] In this embodiment, the active region 11 and the shallow trench isolation structure can be etched to form the aforementioned word line channel 2. Specifically, an anisotropic dry etching process, such as plasma etching, can be used. That is, a mask layer can be formed on the substrate 1 first, which may have two adjacent openings that expose a portion of the surface of the substrate 1. Plasma can be used to bombard the mask layer and the substrate 1 to form the word line channel 2 corresponding to the openings. This disclosure utilizes plasma etching to make the width and depth of the word line channel 2 located in the shallow trench isolation structure the same as the width and depth of the word line channel 2 located in the active region 11. However, it is not limited to this; other etching methods can also be used to form the aforementioned word line channel 2, such as wet etching, etc., which can be selected according to actual needs, all of which are within the protection scope of this disclosure.

[0078] In step S30 above, such as Figure 5 As shown, epitaxial silicon 3 can be grown on both the sidewalls and bottomwalls of the word channel 2 using epitaxial technology. Since growing epitaxial silicon 3 using epitaxial technology is a less complex process, it reduces the overall difficulty of fabricating the semiconductor structure, thereby effectively lowering the manufacturing cost.

[0079] In one embodiment of this disclosure, the thickness of the epitaxial silicon 3 grown on the sidewalls and bottomwalls of the word line channel 2 can be from 5 nm to 20 nm. By setting the thickness of the epitaxial silicon 3 to this range, the epitaxial silicon 3 can meet the subsequent oxidation reaction as much as possible, so that the oxidation of silicon in the active region 11 can be minimized during the oxidation reaction, thereby ensuring that there can be a large distance between two adjacent word line structures 6.

[0080] In one embodiment of this disclosure, such as Figure 6 As shown, an in-situ water vapor oxidation process can be used to oxidize the epitaxial silicon 3 or the epitaxial silicon 3 and part of the active region 11 to oxidize the silicon in the epitaxial silicon 3 or the epitaxial silicon 3 and part of the active region 11 into silicon dioxide, which can form the gate oxide layer 4 mentioned above.

[0081] This disclosure utilizes an in-situ water vapor oxidation process to allow oxygen free radicals to attack silicon, thereby growing relatively dense silicon dioxide. It can also repair dangling bonds and trapped charges between silicon dioxide and silicon substrate 1, thus ensuring that the grown silicon dioxide does not pose a risk of leakage and also gives it high stability.

[0082] In this embodiment, the reaction temperature for oxidizing epitaxial silicon 3 or epitaxial silicon 3 and part of the active region 11 using in-situ water vapor oxidation process can be from 800°C to 1100°C, for example: 800°C, 900°C, 1000°C, etc., but is not limited to this.

[0083] The reaction pressure for oxidizing the epitaxial silicon 3 or the epitaxial silicon 3 and part of the active region 11 using the in-situ water vapor oxidation process can be 1 Torr to 20 Torr, for example: 1 Torr, 4 Torr, 8 Torr, 12 Torr, 16 Torr, 20 Torr, etc., but is not limited to this.

[0084] In this embodiment, the reaction gas used to oxidize the epitaxial silicon 3 or a portion of the active region 11 using the in-situ water vapor oxidation process may include one or more of the following: a mixed gas composed of oxygen and hydrogen, a mixed gas composed of nitric oxide and hydrogen, and a mixed gas composed of nitrogen dioxide and hydrogen. Furthermore, the volume concentration of hydrogen in the reaction gas for the oxidation reaction can be from 0.1% to 33%.

[0085] In this embodiment, the thickness of the in-situ water vapor oxidation process can be For example: And so on, but not limited to these.

[0086] Furthermore, it should be noted that although this disclosure mentions above that epitaxial silicon 3 or epitaxial silicon 3 and part of the active region 11 can be oxidized, the oxidation of epitaxial silicon 3 accounts for the vast majority, or even the entire epitaxial silicon 3, during the oxidation process. That is to say, even if part of the active region 11 is oxidized, it accounts for a very small proportion, which is negligible compared to the prior art.

[0087] In step S40, as Figure 7 As shown, a word line structure 6 can be formed within the word line contact hole 5. Specifically, material for forming the word line structure 6 can be deposited within the word line contact hole 5, such that the top of the word line structure 6 is lower than the surface of the active region 11 or flush with the surface of the active region 11.

[0088] In this embodiment, the material of the word line structure 6 can be conductive materials such as aluminum, tungsten, copper, nickel, silver, or polycrystalline silicon.

[0089] In one embodiment of this disclosure, such as Figure 8 and Figures 9 to 14 As shown, the method for fabricating a semiconductor structure may also include:

[0090] Step S50: A passivation layer 8 is formed in the active region 11, and the passivation layer 8 is located on the side of the gate oxide layer 4 away from the surface of the active region 11.

[0091] This disclosure, by forming a passivation layer 8 in the active region 11 and disposing the passivation layer 8 on the side of the gate oxide layer 4 away from the surface of the active region 11, can completely isolate the word line structure 6 from leakage into the active region 11 through the passivation layer 8, thereby further preventing leakage problems in the manufactured semiconductor structure and further improving the electrical performance of the semiconductor structure.

[0092] Specifically, step S50 may include:

[0093] Step S501: Implant oxygen ions in a portion of the active region 11 to form an oxygen ion layer 7.

[0094] Step S502: React the oxygen ion layer 7 with the silicon in the active region 11 to form the passivation layer 8.

[0095] In step S501, the oxygen ion layer 7 can be located on the side of the gate oxide layer 4 away from the surface of the active region 11.

[0096] In this embodiment, oxygen ions can be implanted in a portion of the active region 11 using a first energy to form an oxygen ion layer 7. Furthermore, the first energy can be from 100 keV to 1000 keV, for example: 100 keV, 200 keV, 400 keV, 600 keV, 800 keV, 1000 keV, etc., but is not limited to these.

[0097] In addition, in this embodiment, the amount of oxygen ions implanted in a portion of the active region 11 can be 1×e 14 pcs / cm 2 up to 1×e 17 pcs / cm 2 However, this is not the only requirement, to ensure that the thickness of the passivation layer 8 is at least 5 nm, thereby effectively isolating leakage current in the active region 11 of the word line structure 6.

[0098] In one embodiment of this disclosure, step S501 can be performed after step S10 and before step S20. That is, before etching the active region 11, oxygen ions can be implanted in a portion of the active region 11 to form an oxygen ion layer 7. Thus, during step S20, the active region 11 can be etched to form a word line channel 2 on the side of the oxygen ion layer 7 near the surface of the active region 11, and a gap can be formed between the word line channel 2 and the oxygen ion layer 7.

[0099] In addition, step S502 can be performed simultaneously with the step of oxidizing the epitaxial silicon 3 or the epitaxial silicon 3 and part of the active region 11 to form the gate oxide layer 4. That is, while oxidizing the epitaxial silicon 3 using the in-situ water vapor oxidation process, the heat from the in-situ water vapor oxidation process can be used to react the oxygen ions in the oxygen ion layer 7 with the silicon in the active region 11 to form silicon dioxide, which can constitute the passivation layer 8.

[0100] Therefore, this disclosure can simultaneously form the gate oxide layer 4 and the passivation layer 8 through an in-situ oxidation process step, thereby simplifying the fabrication steps of the semiconductor structure. Furthermore, this disclosure utilizes the heat applied during the in-situ oxidation process to form the passivation layer 8, thus enabling the same amount of energy to be used for more tasks, reducing energy waste and effectively lowering the fabrication cost of the semiconductor structure.

[0101] In one embodiment of this disclosure, such as Figure 15 As shown, prior to step S20, the method for fabricating this semiconductor structure may further include:

[0102] Step S60: Form source / drain region 12 and channel region 13 in substrate 1, such that channel region 13 is located on the surface of oxygen ion layer 7, and source / drain region 12 is located on the surface of channel region 13.

[0103] Specifically, step S60 is performed after step S501. P-type and N-type ions can be injected into the active region 11, such that the P-type and N-type ions are located on the side of the oxygen ion layer 7 near the surface of the active region 11, thereby forming a channel region 13. P-type or N-type ions can be injected into the active region 11, such that the P-type or N-type ions are located on the side of the channel region 13 near the surface of the active region 11, thereby forming a source / drain region 12. The aforementioned word line channel 2 can pass through the source / drain region 12 and can be located within the channel region 13.

[0104] In this embodiment, P-type ions may include boron ions and indium ions, etc.; N-type ions may include phosphorus ions and antimony ions, etc.

[0105] In addition, it should be noted that any of the steps described above that are performed simultaneously or concurrently can be performed separately or in stages, and can be selected according to actual needs, all of which are within the scope of protection of this disclosure.

[0106] This disclosure also provides a semiconductor structure that can be fabricated using the methods described above, but is not limited thereto. This semiconductor structure can significantly reduce the probability of leakage current occurring in the word line structure 6 during operation, and can increase the density of the word line structure 6 and reduce the linewidth of the word line structure 6, thereby enabling the semiconductor structure to have a smaller size.

[0107] In one embodiment of this disclosure, such as Figure 14 As shown, the semiconductor structure may include: a substrate 1, a word channel 2, a gate oxide layer 4, and a word line structure 6.

[0108] The substrate 1 may have multiple active regions 11. The substrate 1 may be a flat plate structure, which may be rectangular, circular, elliptical, polygonal or irregular in shape, and its material may be silicon or other semiconductor materials. No special restrictions are placed on the shape and material of the substrate 1.

[0109] In one embodiment, the substrate 1 may be a silicon substrate 1 or the material of the substrate 1 may include silicon. Multiple shallow trench isolation structures are formed within the substrate 1. These shallow trench isolation structures are formed by creating trenches within the substrate 1 and then filling the trenches with an isolation material layer. The multiple shallow trench isolation structures may be arranged side-by-side or intersected, thereby isolating multiple active regions 11 on the substrate 1. The material of the shallow trench isolation structure may include silicon nitride or silicon dioxide, etc., and is not specifically limited herein; it can be selected according to actual needs. Furthermore, this disclosure does not limit the cross-sectional shape of the shallow trench isolation structure; it can also be set according to actual needs, all of which are within the protection scope of this disclosure.

[0110] The aforementioned word line channel 2 can be located within the active region 11, and two word line channels 2 can be formed within one active region 11, with a gap between the two word line channels 2.

[0111] The gate oxide layer 4 can be located on the sidewall and bottom wall of the word line channel 2, and the gate oxide layer 4 can form a word line contact hole 5. The gate oxide layer 4 can be formed by growing epitaxial silicon 3 on both the sidewall and bottom wall of the word line channel 2, and oxidizing the epitaxial silicon 3 or the epitaxial silicon 3 and part of the active region 11.

[0112] Therefore, this disclosure grows epitaxial silicon 3 on both the sidewalls and bottomwalls of the word line channel 2, and oxidizes the epitaxial silicon 3 or a portion of the active region 11 to form a gate oxide layer 4. Since the epitaxial silicon 3 has the advantages of few lattice defects and uniform resistivity, the formed gate oxide layer 4 exhibits excellent electrical performance and stability. Furthermore, by directly oxidizing the epitaxial silicon 3 to the gate oxide layer 4, the resulting gate oxide layer 4 has fewer dangling bonds and trapped charges on its contact surface with the active region 11, thereby greatly reducing the probability of leakage current in the final word line structure 6 during operation.

[0113] Furthermore, since the present disclosure grows epitaxial silicon 3 directly on the sidewalls and bottomwalls of the word line channel 2, and mainly oxidizes the grown epitaxial silicon 3 when forming the gate oxide layer 4, the silicon in the active region 11 can be consumed in small amounts or even not at all, thereby reducing the consumption of silicon between the two word line channels 2. This can prevent the problem of the two word line structures 6 being too close together, the word line structure 6 and the bit line contact pad, and the word line structure 6 and the external signal line, and further reduce the leakage probability of the manufactured semiconductor structure.

[0114] Furthermore, since this disclosure significantly reduces silicon consumption between the two word line channels 2 compared to existing technologies, it allows for making the distance between the two word line channels 2 as close as possible, thereby increasing the density of the word line structure 6. Moreover, this disclosure avoids leakage problems between adjacent word line structures 6, between word line structures 6 and bit line contact pads, and between word line structures 6 and external signal lines after increasing the density of the word line structure 6.

[0115] In addition, this disclosure grows epitaxial silicon 3 directly on the sidewalls and bottomwalls of the word line channel 2 and oxidizes the epitaxial silicon 3 into a gate oxide layer 4. This allows the width of the final word line contact hole 5 to be narrower than that of the prior art, thereby allowing the line width of the final word line structure 6 to be smaller than that of the prior art, which is more conducive to reducing the size of the semiconductor structure.

[0116] The aforementioned word line structure 6 can be located inside the word line contact hole 5. The top of the word line structure 6 can be lower than the surface of the active area 11 or the top of the word line structure 6 can be flush with the surface of the active area 11 to prevent the risk of leakage at the top of the word line structure 6.

[0117] In this embodiment, the material of the word line structure 6 can be conductive materials such as aluminum, tungsten, copper, nickel, silver, or polycrystalline silicon.

[0118] In one embodiment of this disclosure, the semiconductor structure may further include a passivation layer 8. The passivation layer 8 may be located on the side of the gate oxide layer 4 away from the surface of the active region 11.

[0119] This disclosure provides a passivation layer 8 within the active region 11, and the passivation layer 8 is disposed on the side of the gate oxide layer 4 away from the active region 11. The passivation layer 8 can completely isolate the word line structure 6 from leakage into the active region 11, thereby further preventing leakage problems in the semiconductor structure during operation and further improving the electrical performance of the semiconductor structure.

[0120] In addition, there may be a gap between the word line structure 6 and the gate oxide layer 4 and the passivation layer 8 in this disclosure to prevent the passivation layer 8 from affecting the word line structure 6 and the gate oxide layer 4.

[0121] In one embodiment of this disclosure, the substrate 1 may include a channel region 13 and a source / drain region 12. The channel region 13 may be located on the side of the passivation layer 8 near the surface of the active region 11, and the source / drain region 12 may be located on the side of the channel region 13 near the surface of the active region 11.

[0122] The channel region 13 can be formed by injecting P-type ions and N-type ions into the active region 11. The source / drain region 12 can be formed by injecting P-type ions or N-type ions into the active region 11, such that the P-type ions or N-type ions are located on the side of the channel region 13 close to the surface of the active region 11.

[0123] In this embodiment, P-type ions may include boron ions and indium ions, etc.; N-type ions may include phosphorus ions and antimony ions, etc.

[0124] In this embodiment, the thickness of the channel region 13 can be greater than the thickness of the source / drain region 12, and the thicknesses of both the channel region 13 and the source / drain region 12 can be greater than the thickness of the passivation layer 8, but are not limited thereto.

[0125] In one embodiment of this disclosure, the word line structure 6 and the gate oxide layer 4 can pass through the source / drain region 12 and be located within the channel region 13.

[0126] In addition, it should be noted that since the semiconductor structure can be fabricated using the aforementioned semiconductor structure fabrication method, the specific fabrication method and beneficial effects of the semiconductor structure will not be elaborated upon in the process of describing the semiconductor structure topic. For the specific fabrication method, please refer to the specific description of the semiconductor structure fabrication method in the previous topic, all of which are within the protection scope of this disclosure.

[0127] This disclosure also provides a semiconductor device that may include the semiconductor structure described above. Therefore, this semiconductor device can significantly reduce the probability of leakage current occurring in the word line structure 6 during operation, and can increase the density of the word line structure 6 and reduce the linewidth of the word line structure 6, thereby enabling the semiconductor device to have a smaller size.

[0128] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This disclosure is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the appended claims.

Claims

1. A method of fabricating a semiconductor structure, the method comprising: include: A substrate is provided, the substrate having a plurality of active regions; The active region is etched to form word channel within the active region; Epitaxial silicon is grown on both the sidewall and bottom wall of the word line channel, and the epitaxial silicon or the epitaxial silicon and part of the active region are oxidized to form a gate oxide layer, which surrounds the word line contact hole. A character line structure is formed within the character line contact hole; The method for fabricating the semiconductor structure further includes: A passivation layer is formed within the active region, such that the passivation layer is located on the side of the gate oxide layer away from the active region; the substrate material includes silicon; the formation of the passivation layer within the active region, such that the passivation layer is located on the side of the gate oxide layer away from the active region, includes: Oxygen ions are implanted in a portion of the active region to form an oxygen ion layer, such that the oxygen ion layer is located on the side of the gate oxide layer away from the surface of the active region. The oxygen ion layer reacts with the silicon in the active region to form the passivation layer; the oxidation of the epitaxial silicon or the epitaxial silicon and a portion of the active region to form a gate oxide layer includes: The epitaxial silicon or the epitaxial silicon and a portion of the active region are oxidized using an in-situ water vapor oxidation process to oxidize the epitaxial silicon or the silicon in the epitaxial silicon and a portion of the active region into silicon dioxide to form the gate oxide layer; the step of reacting the oxygen ion layer with the silicon in the active region to form the passivation layer includes: While oxidizing the epitaxial silicon using an in-situ water vapor oxidation process, the heat generated by the in-situ water vapor oxidation process causes the oxygen ions in the oxygen ion layer to react with the silicon in the active region to form silicon dioxide, thereby constituting a passivation layer.

2. The method of fabricating a semiconductor structure of claim 1, wherein, Before etching the active region, the method for fabricating the semiconductor structure further includes: A source / drain region and a channel region are formed within the substrate, such that the channel region is located on the surface of the oxygen ion layer, and the source / drain region is located on the surface of the channel region.

3. The method of fabricating a semiconductor structure of claim 1, wherein, The implantation of oxygen ions in a portion of the active region to form an oxygen ion layer includes: Oxygen ions are implanted in a portion of the active region using the first energy to form an oxygen ion layer; The first energy is between 100 keV and 1000 keV.

4. The method of fabricating a semiconductor structure of claim 1, wherein, The implantation amount of oxygen ions in part of the active region is 1 x e 14 10 2 / cm 17 2 2 .

5. The method for fabricating a semiconductor structure according to claim 1, characterized in that, The thickness of the epitaxial silicon grown on the sidewalls and bottomwalls of the word line channel is 5 nm to 20 nm.

6. The method for fabricating a semiconductor structure according to claim 1, characterized in that, The reaction temperature for oxidizing the epitaxial silicon or the epitaxial silicon and part of the active region using the in-situ water vapor oxidation process is 800°C to 1100°C, and the reaction pressure for oxidizing the epitaxial silicon or the epitaxial silicon and part of the active region is 1 Torr to 20 Torr.

7. The method for fabricating a semiconductor structure according to claim 1, characterized in that, The reaction gas used to oxidize the epitaxial silicon or the epitaxial silicon and part of the active region using the in-situ water vapor oxidation process includes one or more of the following: a mixed gas composed of oxygen and hydrogen, a mixed gas composed of nitric oxide and hydrogen, and a mixed gas composed of nitrogen dioxide and hydrogen.

8. The method for fabricating a semiconductor structure according to claim 7, characterized in that, The volume concentration of hydrogen in the reactant gas is between 0.1% and 33%.

9. A semiconductor structure, characterized in that, Prepared by the method of fabricating the semiconductor structure according to any one of claims 1 to 8, comprising: A substrate having multiple active regions; The word channel is located within the active region; A gate oxide layer is located on the sidewall and bottom wall of the word line channel, and the gate oxide layer forms a word line contact hole; The character line structure is located inside the character line contact hole; The gate oxide layer is formed by growing epitaxial silicon on both the sidewalls and bottomwalls of the word channel, and oxidizing the epitaxial silicon or the epitaxial silicon and a portion of the active region.

10. The semiconductor structure according to claim 9, characterized in that, The semiconductor structure also includes: A passivation layer is located on the side of the gate oxide layer away from the surface of the active region.

11. A semiconductor device, characterized in that, The semiconductor device includes the semiconductor structure described in any one of claims 9 to 10.

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