Semiconductor structure and method of forming the same
By employing a combination of bottom and top dielectric walls in the semiconductor structure, the electrical isolation problem between NMOS and PMOS devices is solved, the leakage probability is reduced, and the performance of the semiconductor structure is improved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SEMICON MFG INT (SHANGHAI) CORP
- Filing Date
- 2021-05-25
- Publication Date
- 2026-07-21
Smart Images
Figure CN115394719B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to a semiconductor structure and a method for forming the same. Background Technology
[0002] With the rapid development of semiconductor manufacturing technology, semiconductor transistors are evolving towards higher device density and higher integration, and semiconductor process nodes are continuously shrinking in accordance with Moore's Law. Transistors, as the most basic semiconductor material, are currently widely used. Therefore, as the device density and integration of semiconductor transistors increase, the channel length of transistors must be continuously shortened to adapt to the shrinking process nodes.
[0003] To better adapt to the requirement of proportionally shrinking transistor dimensions, semiconductor manufacturing processes have gradually transitioned from planar transistors to more efficient three-dimensional transistors, such as FinFETs and Gate-all-around (GAA) transistors. GAA transistors include vertical and horizontal types. In a GAA transistor, the gate surrounds the channel region from all sides. Compared to planar transistors, GAA transistors offer stronger control over the channel and better suppress short-channel effects.
[0004] As device sizes continue to shrink, achieving better electrical isolation between NMOS devices with fully enclosed gate structures and PMOS devices with fully enclosed gate structures is becoming increasingly difficult and challenging. Summary of the Invention
[0005] The problem solved by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, which is beneficial to further improve the performance of the semiconductor structure.
[0006] To address the aforementioned problems, the present invention provides a semiconductor structure comprising: a substrate, the substrate including discrete device regions and isolation regions located between the device regions, the device regions including a first region and a second region spaced apart, the substrate including a substrate and fins respectively protruding from the substrates of the first region and the second region; a channel structure layer suspended on top of the fins of the device regions, the channel structure layer including one or more spaced-apart channel layers along the normal direction of the substrate surface; an isolation layer located on the substrate of the isolation region and exposing the sidewalls of the channel structure layer; a dielectric wall located on the substrate at the junction of the first region and the second region and covering the sidewalls of the channel structure layer, the dielectric wall including a bottom dielectric wall and a top dielectric wall located above the bottom dielectric wall; a gate dielectric layer covering a portion of the top, a portion of the sidewalls, and a portion of the bottom of the channel structure layer; and a gate electrode layer located on the substrate and spanning the channel structure layer and the dielectric wall, the gate electrode layer surrounding and covering the gate dielectric layer.
[0007] Accordingly, the present invention also provides a method for forming a semiconductor structure, comprising: providing a substrate, the substrate including discrete device regions, the device regions including adjacent first regions and second regions, the substrate including a substrate and fins respectively protruding from the substrates of the first and second regions, a channel stack structure formed on the fins, the channel stack structure including one or more longitudinally stacked channel stacks, each channel stack including a sacrificial layer and a channel layer located on the sacrificial layer, and in the device regions, adjacent channel stacks of the first and second regions, the fins, and the substrate at the boundary between the first and second regions form an isolation trench; A bottom sidewall material layer is formed to cover the trench stack structure and the substrate, and the bottom sidewall material layers on the opposite sidewalls of the isolation trench are in contact with each other; the sidewall material layers located on the top of the substrate and the top of the trench stack structure, as well as a portion of the thickness of the sidewall material layer in the isolation trench, are removed to form a bottom dielectric wall in a portion of the space of the isolation trench, the top surface of the bottom dielectric wall being higher than the top surface of the trench stack; after forming the bottom dielectric wall, a top dielectric wall is formed in the remaining space of the isolation trench to cover the top of the bottom dielectric wall, the top of the top dielectric wall being flush with the top of the trench stack structure, and the top dielectric wall and the bottom dielectric wall constituting a dielectric wall.
[0008] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages:
[0009] This invention provides a semiconductor structure in which a dielectric wall is located on a substrate at the junction of a first region and a second region and covers the sidewalls of a channel structure layer. The dielectric wall includes a bottom dielectric wall and a top dielectric wall located above the bottom dielectric wall. A gate dielectric layer conformally covers a portion of the top, a portion of the sidewalls, and a portion of the bottom of the channel structure layer. A gate electrode layer is located on a substrate and spans the channel structure layer and the dielectric wall, and the gate electrode layer surrounds and covers the gate dielectric layer. Compared to the current approach of forming a monolithic dielectric wall at the boundary between the first and second regions of the device region, the dielectric wall in this embodiment of the invention includes a bottom dielectric wall and a top dielectric wall located on top of the bottom dielectric wall. Therefore, the top dielectric wall can fill the gap formed by the bottom dielectric wall and the channel structure layer, resulting in a higher flatness of the top surface of the dielectric wall. This helps ensure that the dielectric wall can completely cover the sidewall of the channel structure layer, thereby enabling the dielectric wall to better isolate the adjacent channel structure layers in the first and second regions of the device region. This reduces the probability of leakage between devices subsequently formed in the first and second regions, and improves the performance of the semiconductor structure.
[0010] This invention provides a method for forming a semiconductor structure, wherein a bottom dielectric wall is formed in a portion of the space of an isolation trench, the top surface of the bottom dielectric wall being lower than the top surface of the channel stack structure; after forming the bottom dielectric wall, a top dielectric wall is formed in the remaining space of the isolation trench, covering the top of the bottom dielectric wall, the top dielectric wall and the bottom dielectric wall constituting a dielectric wall, and the top of the top dielectric wall being flush with the top of the channel stack structure. Compared to current solutions that form an integral dielectric wall structure within the isolation trench, this embodiment of the invention first removes a portion of the sidewall material layer in the isolation trench, forming a bottom dielectric wall in a portion of the space within the isolation trench to reserve the remaining space. Then, a top dielectric wall is formed in the remaining space of the isolation trench. The bottom and top dielectric walls together constitute a dielectric wall, with the top of the top dielectric wall flush with the top of the channel stack structure. The top dielectric wall fills the gap between the sidewalls of the channel stack structure and the bottom dielectric wall, resulting in a high degree of flatness on the top surface of the dielectric wall and the channel stack structure. This ensures that the dielectric wall can completely cover the sidewalls of the channel stack structure, thereby better isolating the adjacent channel stack structures in the first and second regions of the device region. This reduces the probability of leakage between devices subsequently formed in the first and second regions, improving the performance of the semiconductor structure. Attached Figure Description
[0011] Figures 1 to 3 This is a schematic diagram of the structure corresponding to each step in a method for forming a semiconductor structure.
[0012] Figure 4This is a schematic diagram of a semiconductor structure according to an embodiment of the present invention;
[0013] Figures 5 to 16 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention. Detailed Implementation
[0014] The performance of current semiconductor structures needs improvement. This paper analyzes the reasons why the performance of a semiconductor structure needs further improvement, using a specific semiconductor structure formation method as an example.
[0015] Figures 1 to 3 This is a schematic diagram of the structure corresponding to each step in a method for forming a semiconductor structure.
[0016] refer to Figure 1 The substrate is provided, the substrate including discrete device regions 10A and isolation regions 10B located between device regions 10A. Device regions 10A include adjacent first regions A and second regions B. The substrate includes a substrate 10 and fins 11 protruding from the substrate 10 of the first regions A and the second regions B, respectively. One or more longitudinally stacked channel stacks 14 are formed on the fins 11. Each channel stack 14 includes a sacrificial layer 12 and a channel layer 13 located on the sacrificial layer 12. An isolation layer 17 is formed on the substrate 10 exposed by the channel stack 14. In the device region 10A, the sidewalls of adjacent channel stacks 14 and the top of the isolation layer 17 form an isolation trench 15.
[0017] refer to Figure 2 A dielectric material layer 18 is formed to form a conformal covering trench stack and an isolation layer. The dielectric material layer 18 also fills the isolation trench 15 of the device region 10A.
[0018] refer to Figure 3 The dielectric material layer 18 on top of the isolation layer 17 of the isolation region 10B and the top of the channel stack 14 is removed, and a dielectric wall 18 is formed in the isolation trench 15 at the junction of the first region A and the second region B.
[0019] The first region A of device region 10A is used to form an NMOS transistor, and the second region B of device region 10A is used to form a PMOS transistor.
[0020] Research has revealed that during the formation of the dielectric wall 18, in order to completely remove the dielectric material layer 18 on top of the isolation layer 17 and the top of the channel stack 14 in the isolation region 10B, the dielectric material layer 18 in the isolation trench 15 is prone to over-etching (e.g. Figure 3As shown by the dashed circle in the middle, the top of the dielectric wall 18 and the top of the channel stack 14 are prone to poor flatness, that is, the dielectric wall 18 exposes part of the sidewall of the channel stack 14, thereby reducing the isolation effect of the dielectric wall 18 on the adjacent channel stack 14 in the device region 10A. Correspondingly, it increases the probability of leakage between the devices subsequently formed in the first region A and the second region B, thus affecting the performance of the semiconductor structure.
[0021] To address the technical problem, embodiments of the present invention provide a method for forming a semiconductor structure, comprising: providing a substrate, the substrate including discrete device regions, the device regions including adjacent first regions and second regions, the substrate including a substrate and fins respectively protruding from the substrates of the first and second regions, a channel stack structure formed on the fins, the channel stack structure including one or more longitudinally stacked channel stacks, each channel stack including a sacrificial layer and a channel layer located on the sacrificial layer, and in the device regions, the adjacent channel stacks of the first and second regions, the fins, and the substrate at the boundary between the first and second regions form a... An isolation trench; forming a bottom sidewall material layer that conformally covers the trench stack structure and the substrate, with the bottom sidewall material layers on opposite sidewalls of the isolation trench in contact; removing the sidewall material layers located on the top of the substrate and the top of the trench stack structure, as well as a portion of the sidewall material layer in the isolation trench, to form a bottom dielectric wall in a portion of the space of the isolation trench, with the top surface of the bottom dielectric wall higher than the top surface of the trench stack; after forming the bottom dielectric wall, forming a top dielectric wall covering the top of the bottom dielectric wall in the remaining space of the isolation trench, with the top of the top dielectric wall flush with the top of the trench stack structure, the top dielectric wall and the bottom dielectric wall constituting a dielectric wall.
[0022] The dielectric wall in this embodiment of the invention includes a bottom dielectric wall and a top dielectric wall located on top of the bottom dielectric wall. Therefore, the top dielectric wall can fill the gap formed by the bottom dielectric wall and the channel structure layer, resulting in a high flatness of the top surface of the dielectric wall. This helps to ensure that the dielectric wall can completely cover the sidewall of the channel structure layer, thereby enabling the dielectric wall to better isolate the adjacent channel structure layers in the first and second regions of the device region. This reduces the probability of leakage between devices subsequently formed in the first and second regions, which is beneficial to improving the performance of the semiconductor structure.
[0023] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.
[0024] Figure 4 This is a schematic diagram of a semiconductor structure according to an embodiment of the present invention.
[0025] The semiconductor structure includes: a substrate, the substrate including discrete device regions 200A and isolation regions 200B located between the device regions 200A, the device regions 200A including a first region c and a second region d spaced apart, the substrate including a substrate 200 and fins 201 protruding from the substrate 200 in the first region c and the second region d respectively; a channel structure layer 290, suspended on top of the fins 201 in the device regions 200A, the channel structure layer 290 including one or more spaced channel layers 203 along the normal direction of the surface of the substrate 200; and an isolation layer 217 located in the isolation region 200B. On substrate 200, and exposing the sidewalls of channel structure layer 290; dielectric wall 216, located on substrate 200 at the junction of first region c and second region d, and covering the sidewalls of channel structure layer 290, dielectric wall 216 includes bottom dielectric wall 212 and top dielectric wall 215 located on top of bottom dielectric wall 212; gate dielectric layer 222, covering part of the top, part of the sidewalls and part of the bottom of channel structure layer 290; gate electrode layer 223, located on substrate and spanning channel structure layer 290 and dielectric wall 216, gate electrode layer 223 surrounds and covers gate dielectric layer 222.
[0026] The dielectric wall 216 in this embodiment includes a bottom dielectric wall 212 and a top dielectric wall 215 located on top of the bottom dielectric wall 212. Therefore, the top dielectric wall 215 can fill the gap formed by the bottom dielectric wall 212 and the sidewall of the channel structure layer 290, making the top surface of the dielectric wall 216 have a high flatness. This is beneficial to ensure that the dielectric wall 216 can completely cover the sidewall of the channel structure layer 290, so that the dielectric wall 216 can better isolate the adjacent channel structure layers 290 of the first region c and the second region d in the device region 200A, thereby reducing the probability of leakage between the devices subsequently formed in the first region c and the second region d, which is beneficial to improving the performance of the semiconductor structure.
[0027] In this embodiment, the first region c of device region 200A is used to form a first-type transistor, and the second region d of device region 200A is used to form a second-type transistor. The first-type transistor and the second-type transistor have different channel conductivity types. Specifically, the first-type transistor is an NMOS transistor, and the second-type transistor is a PMOS transistor; in other embodiments, the first-type transistor is a PMOS transistor, and the second-type transistor is an NMOS transistor.
[0028] In this embodiment, the substrate also includes an isolation region 200B located between device regions 200A.
[0029] Isolation region 200B is used to electrically isolate adjacent device region 200A.
[0030] In this embodiment, the substrate has a three-dimensional structure, including a substrate 200 and fins 201 protruding from the substrate 200 in the first region c and the second region d, respectively. In other embodiments, the substrate may also be a planar substrate. In this embodiment, the substrate 200 is a silicon substrate, and the fins 201 are made of the same material as the substrate 200, namely silicon.
[0031] In this embodiment, the top of the substrate 200 at the junction of the first region c and the second region d is lower than the top of the substrate 200 of the isolation region 200B.
[0032] Well regions are typically formed in the substrates of the first region c and the second region d. In order to improve the electrical isolation effect of the dielectric wall 216 between the well regions in the first region c substrate and the well regions in the second region d substrate, and to satisfy the electrical isolation effect between the first region c and the second region d, the top of the substrate 200 at the junction of the first region c and the second region d is lower than the top of the substrate 200 of the isolation region 200B.
[0033] It should be noted that the distance h1 from the top of the substrate 200 at the junction of the first region c and the second region d to the top of the substrate 200 in the isolation region 200B should not be too large or too small. If the distance h1 is too large, even if the isolation layer 217 in the isolation region 200B satisfies the isolation effect, the filling performance of the bottom dielectric wall 212 on the substrate 200 at the junction of the first region c and the second region d will be poor, which will easily lead to a decrease in the isolation effect of the bottom dielectric wall, thereby affecting the performance of the semiconductor structure. If the distance h1 from the top of the substrate 200 at the junction of the first region c and the second region d to the top of the substrate 200 in the isolation region 200B is too large, the isolation effect of the bottom dielectric wall will be reduced, thus affecting the performance of the semiconductor structure. If the distance h1 at the top of the substrate 200 is too small, the dielectric wall on the substrate 200 located at the junction of the first region c and the second region d will have a poorer electrical isolation effect between the well region in the substrate of the first region c and the well region in the substrate of the second region d, thereby affecting the performance of the semiconductor structure. Therefore, in this embodiment, the distance h1 from the top of the substrate 200 at the junction of the first region c and the second region d to the top of the substrate 200 in the isolation region 200B is 50 angstroms to 300 angstroms.
[0034] In this embodiment, the channel structure layer 290 is suspended on top of the fin 201 of the device region 200A. Along the normal direction of the substrate 200 surface, the channel structure layer 290 includes one or more spaced-apart channel layers 203. In this embodiment, the channel layer 203 is used to provide conductive channels for the first type transistor and the second type transistor.
[0035] In this embodiment, the material of the channel layer 203 includes one or more of silicon, silicon germanide, germanium, and group III-V semiconductor materials. The material of the channel layer 203 in the first region c is determined according to the performance of the first type transistor, and the material of the channel layer 203 in the second region is determined according to the performance of the second type transistor.
[0036] In this embodiment, there are three channel layers 203. In other embodiments, the number of channel layers may be other numbers.
[0037] In this embodiment, the semiconductor structure further includes an isolation layer 217 located on the substrate 200 of the isolation region 200B and exposing the sidewalls of the channel structure layer 290. The isolation layer 217 is used to isolate adjacent device regions 200A. Therefore, the material of the isolation layer 217 is a dielectric material, which may include silicon oxide, silicon nitride, or silicon oxynitride. In this embodiment, the material of the isolation layer 217 is silicon oxide.
[0038] The dielectric wall 216 is used to isolate the first region c and the second region d in the same device region 200A. In order to improve the isolation effect of the dielectric wall 216 on the channel structure layer 290 in the first region c and the second region d, the top of the dielectric wall 216 is higher than the top of the channel structure layer 290.
[0039] In this embodiment, the dielectric wall 216 includes a bottom dielectric wall 212 and a top dielectric wall 215 located on top of the bottom dielectric wall 212.
[0040] In this embodiment, the top of the bottom dielectric wall 212 is higher than the top of the channel structure layer 290. This higher top of the bottom dielectric wall 212 ensures uniform insulation between the channel structure layers 290.
[0041] In this embodiment, the bottom dielectric wall 212 is made of a dielectric material, such as one or more of silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon carbonitride, and silicon borosilicate, thereby ensuring that the bottom dielectric wall 212 can function as an isolation barrier. In this embodiment, the bottom dielectric wall 212 is made of silicon nitride.
[0042] It should be noted that the distance from the top of the bottom dielectric wall 212 to the top of the channel structure layer 290 should not be too large or too small. If the distance is too large, the space of the bottom dielectric wall 215 will be too small, affecting the filling effect of the bottom dielectric wall 215 during its formation process, and consequently affecting the isolation effect of the dielectric wall 216, increasing the probability of leakage between the devices in the first region c and the second region d. If the distance is too small, the insulation between the bottom dielectric wall 212 and the channel structure layer 290 will be uneven, affecting the performance of the semiconductor structure. Therefore, in this embodiment, the distance h2 from the top of the bottom dielectric wall 212 to the top of the channel structure layer 290 is 5 nanometers to 20 nanometers.
[0043] It should be noted that, in order to reduce process steps and save costs, during the process of forming the top dielectric wall 215, an isolation layer 217 is formed in the isolation region 200B. Therefore, the material of the top dielectric wall 215 is the same as the material of the isolation layer 217. Therefore, in this embodiment, the material of the top dielectric wall 215 is silicon oxide.
[0044] In this embodiment, the gate dielectric layer 222 conformally covers a portion of the top, a portion of the sidewalls, and a portion of the bottom of the channel layer 203. In this embodiment, the material of the gate dielectric layer 222 includes one or more of HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, SiO2, and La2O3.
[0045] Specifically, the gate dielectric layer 222 includes a gate oxide layer that conformally covers part of the top, part of the sidewalls, and part of the bottom of the conformally covered channel structure layer 290, and a high-k gate dielectric layer that conformally covers the gate oxide layer. The high-k gate dielectric layer is made of a high-k dielectric material, which refers to a dielectric material with a relative permittivity greater than that of silicon oxide.
[0046] It should be noted that the gate dielectric layer 222 also conformally covers part of the top of the isolation layer 217, as well as part of the sidewalls and part of the top of the exposed dielectric wall 216 of the channel layer 203.
[0047] In this embodiment, the gate electrode layer 223 is located on the substrate and spans the channel structure layer 290 and the dielectric wall 216, surrounding the gate dielectric layer 222. The gate electrode layer 223 is used for subsequent electrical connection with external structures. The material of the gate electrode layer 223 includes one or more of TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN, and TiAlC. Specifically, the gate electrode layer 223 may include a work function layer and an electrode layer covering the work function layer, or the gate electrode layer 223 may only include a work function layer.
[0048] In this embodiment, the semiconductor structure further includes a sidewall 220 located on the sidewall of the gate electrode layer 223. The sidewall protects the sidewall of the gate electrode layer 223. The sidewall 220 can be a single-layer structure or a multilayer structure, and the material of the sidewall 220 includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride, silicon oxynitride, silicon oxynitride, boron nitride, and boron carbonitride. In this embodiment, the sidewall 220 is a single-layer structure, and the material of the sidewall 220 is silicon nitride.
[0049] In this embodiment, the semiconductor structure further includes an interlayer dielectric layer 219, located on top of the gate electrode layer 223 and the exposed isolation layer 217 of the sidewall 220, and the interlayer dielectric layer 219 covers the sidewall of the sidewall 220. The interlayer dielectric layer 219 is used to isolate adjacent devices. The material of the interlayer dielectric layer 219 is an insulating material, such as one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon carbonitride. In this embodiment, the material of the interlayer dielectric layer 219 is silicon oxide.
[0050] Figures 5 to 16 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention.
[0051] refer to Figures 5 to 6 A substrate is provided, the substrate including discrete device regions 100A, device regions 100A including adjacent first regions a and second regions b, the substrate including substrate 100 and fins 101 protruding from the substrate 100 of the first regions a and the second regions b respectively, a channel stack structure 301 is formed on the fins 101, the channel stack structure 301 includes one or more longitudinally stacked channel stacks 104, each channel stack 104 including a sacrificial layer 102 and a channel layer 103 located on the sacrificial layer 102, and in the device region 100A, the adjacent channel stacks 104 of the first regions a and the second regions b, the fins 101, and the substrate 100 at the junction of the first regions a and the second regions b form an isolation trench 109.
[0052] The substrate is used to provide a process platform for subsequent process manufacturing.
[0053] In this embodiment, the first region a of device region 100A is used to form a first-type transistor, and the second region b of device region 100A is used to form a second-type transistor. The first-type transistor and the second-type transistor have different channel conductivity types. Specifically, the first-type transistor is an NMOS transistor, and the second-type transistor is a PMOS transistor; in other embodiments, the first-type transistor is a PMOS transistor, and the second-type transistor is an NMOS transistor.
[0054] In this embodiment, the substrate also includes an isolation region 100B located between device regions 100A. The isolation region 100B is used to electrically isolate adjacent device regions 100A.
[0055] In this embodiment, the adjacent channel stack 104 closest to the isolation zone 100B and the fin 101 together with the remaining base of the isolation zone 100B form an isolation opening 110, and the bottom of the isolation groove 109 is lower than the bottom of the isolation opening 110.
[0056] The isolation groove 109 provides space for the subsequent formation of the dielectric wall.
[0057] In order to improve the electrical isolation effect of the dielectric wall between the well region in the first region a substrate and the well region in the second region b substrate, and to satisfy the electrical isolation effect between the first region a and the second region b, the bottom of the isolation groove 109 is lower than the bottom of the isolation opening 110.
[0058] In this embodiment, the steps of forming the substrate and channel stack 104 include: as follows Figure 5 As shown, an initial substrate 190 is provided, the initial substrate 190 including discrete device regions 100A, the device regions 100A including adjacent first regions a and second regions b, and one or more longitudinally stacked channel material stacks 180 are formed on the initial substrate 190, each channel material stack 180 including a sacrificial material layer 179 and a channel material layer 178 located on the sacrificial material layer 179; as Figure 6 As shown, an initial substrate 190 and a channel material stack 180 located on the initial substrate 190 are patterned. The initial substrate 190 is patterned as a substrate, which includes a substrate 100 and fins 101 protruding from the substrate 100 in the first region a and the second region b, respectively. The channel material stack 180 is patterned as a channel stack 104 located on the fins 101.
[0059] In this embodiment, the channel stack 104 and the isolation groove 109 are formed in the same step, which reduces the number of process steps and lowers the process cost.
[0060] In this embodiment, the substrate has a three-dimensional structure, including a substrate 100 and fins 101 protruding from the substrate 100 in the first region a and the second region b, respectively. In other embodiments, the substrate may also be a planar substrate.
[0061] In this embodiment, the substrate 100 is a silicon substrate, and the fin 101 is made of the same material as the substrate 100, which is silicon.
[0062] Accordingly, in this embodiment, a channel stack structure 301 is formed on the fin 101, and the channel stack structure 301 includes one or more longitudinally stacked channel stacks 104.
[0063] In this embodiment, the material of the sacrificial layer 102 includes silicon and germanium; the material of the channel layer 103 includes silicon, silicon germanide, germanium, or group III-V semiconductor materials, and there is an etch selectivity between the sacrificial layer 102 and the channel layer 103.
[0064] The channel stack 104 extends in the same direction as the fin 101. The stacking direction of the plurality of channel stacks 104 is perpendicular to the surface of the substrate 100.
[0065] The channel stack 104 provides a technological basis for the subsequent formation of a channel layer with suspended space partitions.
[0066] As an example, the number of channel stacks 104 is three. In other embodiments, the number of channel stacks may also be other numbers.
[0067] In this embodiment, the channel layer 103 of the first region a is used to provide a conductive channel for the first type of transistor, and the sacrificial layer 102 is used to support the channel layer 103. After the sacrificial layer 102 of the first region a is removed, the channel layer 103 can be suspended at intervals. The sacrificial layer 102 of the first region a also occupies space for the subsequent formation of the gate dielectric layer and the gate electrode layer.
[0068] In this embodiment, the channel layer 103 of the second region b is used to provide a conductive channel for the second type transistor, and the sacrificial layer 102 is used to support the channel layer 103. After the sacrificial layer 102 of the second region b is removed, the channel layer 103 can be suspended in a spaced manner. The sacrificial layer 102 of the second region b also occupies space for the subsequent formation of the gate dielectric layer and the gate electrode layer.
[0069] In this embodiment, the number of sacrificial layers 102 and channel layers 103 are the same in the step of providing the substrate.
[0070] Continue to refer to Figures 5 to 6The steps of patterning the initial substrate 190 and the channel material stack 180 located on the initial substrate 190 include: forming a core layer 106 on top of the channel material stack 180, wherein a mask opening 108 is formed in the core layer 106 at the junction of the first region a and the second region b; forming a discrete second mask layer 107 on top of the core layer 106 in the first region a and the second region b, wherein the second mask layer 107 exposes the top of the core layer 106 in the isolation region 100B; and etching the core layer 106, the channel material stack 180 and a portion of the thickness of the initial substrate 190 using the second mask layer 107 as a mask.
[0071] It should be noted that a mask opening 108 is formed in the core layer 106 at the junction of the first region a and the second region b. Therefore, compared with the other regions, the channel material stack 180 at the junction of the first region a and the second region b is etched earlier. Correspondingly, under the same etching time, the initial substrate 190 at the junction of the first region a and the second region b has a greater etching depth, which is beneficial to make the bottom of the isolation trench 109 lower than the bottom of the isolation opening 110 during the formation of the isolation trench 109 and the isolation opening 110.
[0072] In this embodiment, the sacrificial layer 102 in the channel stack 104 is used as the first sacrificial layer 102, and the channel stack structure 301 also includes a second sacrificial layer 300 located at the top of the topmost channel stack 104.
[0073] The second sacrificial layer 300 occupies space for the height of the subsequently formed gate electrode layer.
[0074] Therefore, as Figure 5 As shown, with the sacrificial material layer 179 in the channel material stack 180 as the first sacrificial material layer 179, before the initial substrate 190 and the channel material stack 180 located on the initial substrate 190 are patterned, the method further includes: forming a second sacrificial material layer 500 on the top of the topmost channel material stack 180.
[0075] Accordingly, during the formation of the substrate and channel stack 104, the second sacrificial material layer 500, the channel material stack 180, and the initial substrate 190 are sequentially patterned, and the second sacrificial material layer 500 is patterned as the second sacrificial layer 300. The second sacrificial layer 300 and the channel stack 104 constitute the channel stack structure 301.
[0076] In this embodiment, the material of the first sacrificial layer 102 is the same as that of the second sacrificial layer 300, which facilitates its removal in the same step.
[0077] In this embodiment, the forming method further includes: forming a hard mask layer 105 on top of the channel material stack 180, and a core layer 107 is correspondingly formed on the hard mask layer 105. Specifically, the hard mask layer 105 is formed on top of the second sacrificial material layer 500.
[0078] The patterned hard mask layer 105 is used as a mask for etching the second sacrificial material layer 500 and the channel material stack 180. By first transferring the pattern to the hard mask layer 105, the accuracy of pattern transfer is improved.
[0079] In this embodiment, the material of the hard mask layer 105 includes one or more of silicon nitride, silicon carbide, and silicon carbide nitride.
[0080] refer to Figure 7 The bottom sidewall material layer 111 of the substrate forms a conformal covering trench layer structure 301 and a base layer, which are in contact with each other on the opposite sidewall of the isolation trench 109.
[0081] The bottom sidewall material layer 111 provides a process basis for the subsequent formation of the bottom dielectric wall.
[0082] In this embodiment, the process for forming the bottom sidewall material layer 111 includes atomic layer deposition.
[0083] The atomic layer deposition process involves multiple atomic layer deposition cycles, which has good step coverage characteristics. This is beneficial for improving the thickness uniformity of the bottom sidewall material layer 111 and enabling the bottom sidewall material layer 111 to cover the channel stack 104 and the substrate in a conformal manner.
[0084] It should be noted that the subsequently formed bottom dielectric wall is obtained from the patterned bottom sidewall material layer 111. To ensure electrical isolation between adjacent first regions a and second regions b, the bottom sidewall material layer 111 is made of a dielectric material, such as one or more of silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon carbonitride, and silicon borosilicate, thereby ensuring that the subsequently formed bottom dielectric wall can play an isolating role. In this embodiment, the bottom sidewall material layer 111 is made of silicon nitride.
[0085] refer to Figure 8 The sidewall material layer 111 located on top of the substrate and top of the channel stack 301, as well as a portion of the sidewall material layer 111 in the isolation trench 109, is removed, and a bottom dielectric wall 112 is formed in a portion of the space of the isolation trench 109, with the top surface of the bottom dielectric wall 112 being higher than the top surface of the channel stack 104.
[0086] In order to form the gate electrode layer that spans the channel structure layer and the dielectric wall, the sidewall material layer 111 on the top of the substrate and the top of the channel stack structure 301 needs to be completely removed, that is, to provide space for the subsequent formation of the gate electrode layer.
[0087] Remove a portion of the sidewall material layer 111 in the isolation groove 109 to provide space for the subsequent formation of a top dielectric wall on top of the bottom dielectric wall 112.
[0088] In this embodiment, the process of removing the sidewall material layer 111 located on the top of the substrate and the top of the trench stack structure 301, as well as a portion of the sidewall material layer 111 in the isolation trench 109, includes a dry etching process.
[0089] Dry etching processes include anisotropic dry etching processes, which possess the characteristics of anisotropic etching. That is, the longitudinal etching rate is greater than the transverse etching rate. This allows for the removal of the sidewall material layer 111 located on top of the substrate and the top of the trench stack 104, as well as a portion of the sidewall material layer 111 in the isolation trench 109, while ensuring the morphological quality of the sidewalls of the trench stack 104, thus providing a good process foundation for subsequent processes.
[0090] In this embodiment, the bottom dielectric wall 112 can isolate the channel stack 104 between the first region a and the second region b. At the same time, the bottom dielectric wall 112 is also located between the fins 101 of the first region a and the second region b, and is also used to isolate the fins 101 of the first region a and the second region b. It can ensure that the channel stack 104 of the first region a and the second region b can be completely isolated, thereby improving the isolation effect of the bottom dielectric wall 112 on the adjacent channel stack 104 of the first region a and the second region b.
[0091] Therefore, the bottom dielectric wall 112 is made of a dielectric material, such as one or more of silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon carbonitride, and silicon borosilicate, to ensure that the bottom dielectric wall 112 can function as an isolation barrier. In this embodiment, the bottom dielectric wall 112 is made of silicon nitride.
[0092] In this embodiment, after the bottom dielectric wall 112 is formed, the top of the bottom dielectric wall 112 is higher than the top of the channel stack 104. That is, the bottom dielectric wall 112 can penetrate the channel stack, thereby making the insulation between the channel structure layers uniform after the channel structure layers are subsequently formed.
[0093] The distance from the top of the bottom dielectric wall 112 to the top of the channel stack 104 should not be too small or too large. If the distance is too large, it will occupy too much space for the subsequently formed top dielectric wall, affecting the filling effect of the top dielectric wall and thus the isolation effect of the subsequently formed dielectric wall, increasing the probability of leakage between the devices in the first and second regions. If the distance is too small, it will lead to uneven insulation between the subsequently formed channel structure layers, thus affecting the performance of the semiconductor structure. Therefore, in this embodiment, the distance from the top of the bottom dielectric wall 112 to the top of the channel stack 104 is 5 nanometers to 20 nanometers.
[0094] refer to Figures 9 to 13 After the bottom dielectric wall 112 is formed, a top dielectric wall 115 is formed in the remaining space of the isolation trench 109, covering the top of the bottom dielectric wall 112. The top of the top dielectric wall 115 is flush with the top of the channel stack structure 301. The top dielectric wall 115 and the bottom dielectric wall 112 constitute a dielectric wall 116.
[0095] In this embodiment, a portion of the sidewall material layer 111 of the isolation trench 109 is first removed, forming a bottom dielectric wall 112 in a portion of the space of the isolation trench 109 to reserve the remaining space of the isolation trench 109. Then, a top dielectric wall 115 is formed in the remaining space of the isolation trench 109. The bottom dielectric wall 112 and the top dielectric wall 115 constitute a dielectric wall 116, and the top of the top dielectric wall 115 is flush with the top of the channel stack structure 301. The top dielectric wall 115 fills the channel stack structure 301. The gap formed by the sidewalls and bottom dielectric walls 112 results in a high degree of flatness on the top surface of the dielectric wall 116 and the channel stack structure 301. This helps ensure that the dielectric wall 116 can completely cover the sidewalls of the channel stack structure 301, thereby enabling the dielectric wall 116 to better isolate the adjacent channel stack structures 301 in the first region a and the second region b in the device region 100A. This reduces the probability of leakage between devices subsequently formed in the first region a and the second region b, which is beneficial to improving the performance of the semiconductor structure.
[0096] In this embodiment, the step of forming the top dielectric wall 115 includes: as follows Figure 9 As shown, a top sidewall material layer 113 forms a composite structure 301 covering the substrate and trench, and the top sidewall material layer 113 also fills the remaining space in the isolation groove 109; as Figures 10 to 13The top sidewall material layer 113 is etched back to remove the top sidewall material layer 113 above the top of the channel stack structure 301 in the device region 100A. In the remaining space of the isolation trench 109, a top dielectric wall 115 is formed that covers the top of the bottom dielectric wall 112. The top of the top dielectric wall 115 is flush with the top of the channel stack structure 301. The top dielectric wall 115 and the bottom dielectric wall 112 constitute a dielectric wall 116.
[0097] In this embodiment, the top dielectric wall 115 can isolate the channel stack structure 301 between the first region a and the second region b, ensuring that the channel stack structure 301 between the first region a and the second region b can be completely isolated, thereby improving the isolation effect of the top dielectric wall 115 on the adjacent channel stack structure 301 between the first region a and the second region b.
[0098] Therefore, the top dielectric wall 115 is made of a dielectric material, such as one or more of silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon carbonitride, and silicon borosilicate, to ensure that the top dielectric wall 115 can function as an isolation barrier. In this embodiment, the top dielectric wall 115 is made of silicon oxide.
[0099] In this embodiment, the process for forming the top sidewall material layer 113 covering the substrate and the trench stack structure 301 includes a chemical vapor deposition process.
[0100] The chemical vapor deposition process is characterized by high controllability, high utilization rate, and good uniformity.
[0101] In this embodiment, the process of etching back the top sidewall material layer 113 in the step of forming the top dielectric wall 115 includes a dry etching process.
[0102] Dry etching processes include anisotropic dry etching processes, which possess the characteristics of anisotropic etching. That is, the longitudinal etching rate is greater than the transverse etching rate, which can ensure the morphological quality of the sidewalls of the trench stack 104 while etching the top sidewall material layer 113, thus providing a good process foundation for subsequent processes.
[0103] refer to Figures 10 to 12 In this embodiment, the step of etching back the top sidewall material layer 113 includes: performing a first etching process on the top sidewall material layer 113 of the isolation region 100B to remove the top sidewall material layer 113 of a preset thickness H in the isolation region 100B.
[0104] In this embodiment, the step of performing the first etching process on the top sidewall material layer 113 of the isolation zone 100B includes: as follows Figure 10As shown, a patterned first mask layer 114 is formed on top of the top sidewall material layer 113, and the first mask layer 114 is located on top of the top sidewall material layer 113 of the device region 100A; as Figure 11 As shown, the top sidewall material layer 113 of a preset thickness H is etched in the isolation region 100B using the first mask layer 114 as a mask.
[0105] The first etching process reduces the effective height of the top sidewall material layer 113 in the isolation zone 100B, which is beneficial for forming the top dielectric wall 115 in the remaining space of the isolation trench 109 and forming an isolation layer in the isolation zone 100B during the subsequent second etching process. Moreover, the second etching process can use the top of the channel stack structure 301 as the etching stop position, reducing the probability that the top sidewall material layer 113 in the isolation trench 109 has been over-etched during the second etching process, thereby improving the flatness of the top surface of the top dielectric wall 115.
[0106] It should be noted that the preset thickness H of the top sidewall material layer 113 removed from isolation region 100B should not be too large or too small. If the preset thickness H of the top sidewall material layer 113 removed from isolation region 100B is too large, it is easy to remove all the remaining top sidewall material layer 113 in isolation region 100B during the subsequent second etching process, or the thickness of the remaining top sidewall material layer 113 in isolation region 100B may be too small, making it difficult to meet the isolation effect between adjacent device regions 100A, thereby affecting the performance of the semiconductor structure. If the preset thickness H of the top sidewall material layer 113 removed from isolation region 100B is too small, during the subsequent second etching process, if the top dielectric wall 115 formed in the remaining space of isolation trench 109 meets the process requirements, it is easy for the isolation layer in isolation region 100B to fail to fully expose the sidewall of the channel stack 104, thereby affecting the performance of the semiconductor structure. Therefore, in this embodiment, the preset thickness H of the top sidewall material layer 113 in the isolation zone 100B is 50 angstroms to 300 angstroms during the first etching process.
[0107] In this embodiment, the process of etching the top sidewall material layer 113 of the isolation region 100B using the first mask layer 114 as a mask includes a dry etching process.
[0108] Dry etching processes include anisotropic dry etching processes, which possess the characteristics of anisotropic etching. That is, the longitudinal etching rate is greater than the transverse etching rate, which can ensure the morphological quality of the sidewalls of the trench stack 104 while etching back the top sidewall material layer 113 of the isolation region 100B, thus providing a good process foundation for subsequent processes.
[0109] It should also be noted that after the first etching process, the process also includes: removing the first mask layer 114.
[0110] refer to Figures 12 to 13 After the first etching process, the top of the channel stack 104 is used as the etching stop position, and the remaining top sidewall material layer 113 in the isolation region 100B and device region 100A is etched a second time to form the top dielectric wall 115 in the isolation trench 109 and the isolation layer 117 on the substrate 100 of the isolation region 100B.
[0111] The top dielectric wall 115 occupies the remaining space of the isolation trench 109. That is, the top of the top dielectric wall 115 is flush with the top of the channel stack 104, which makes the top surface of the dielectric wall 116 and the channel stack 104 have a high degree of flatness. This helps to ensure that the dielectric wall 116 can completely cover the sidewall of the channel stack 104, so that the dielectric wall 116 can better isolate the adjacent channel stacks 104 of the first region a and the second region b in the device region 100A.
[0112] The isolation layer 117 located on the substrate 100 of the isolation region 100B serves to isolate the adjacent device region 100A.
[0113] refer to Figure 14 The method of forming also includes: forming a pseudo gate 118 that spans the channel stack 104 and the dielectric wall 116, the pseudo gate 118 covering part of the top and part of the sidewall of the channel stack 104.
[0114] The pseudo-gate 118 occupies space for the subsequent formation of the gate structure.
[0115] In this embodiment, the dummy gate 118 spans the channel stack 104 and the dielectric wall 116. That is, the dummy gate 118 covers part of the top of the channel stack 104 and the dielectric wall 116, as well as part of the sidewalls of the channel stack 104 and the dielectric wall 116 opposite to each other.
[0116] In this embodiment, the material of the dummy gate 118 includes polycrystalline silicon.
[0117] In this embodiment, after forming the dummy gate 118, the forming method further includes forming a sidewall 120 on the sidewall of the dummy gate 118.
[0118] Sidewall 120 is used to protect the sidewalls of the subsequently formed gate structure. Sidewall 120 can be a single-layer structure or a multilayer structure, and the material of sidewall 120 includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride, silicon oxynitride, silicon oxynitride, boron nitride, and boron carbonitride. In this embodiment, sidewall 120 is a single-layer structure, and the material of sidewall 120 is silicon nitride.
[0119] In this embodiment, after forming the sidewall 120, the formation method further includes: forming a source / drain doped layer (not shown) in the channel stack 104 on both sides of the dummy gate 118. The conductivity type of the doped ions in the source / drain doped layer is the same as the channel conductivity type of the transistor in the same region. The specific description of the source / drain doped layer will not be repeated here in this embodiment.
[0120] In this embodiment, the forming method further includes: forming an interlayer dielectric layer 119 on top of the isolation layer 117 exposed on the dummy gate 118 and the sidewall 120, wherein the interlayer dielectric layer 119 covers the sidewall of the sidewall 120 and exposes the top of the dummy gate 118.
[0121] Interlayer dielectric layer 119 is used to isolate adjacent devices. The material of interlayer dielectric layer 119 is an insulating material, such as one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon carbonitride. In this embodiment, the material of interlayer dielectric layer 119 is silicon oxide.
[0122] refer to Figure 15 Remove the dummy gate 118 to form the gate opening 121.
[0123] The gate opening 121 provides space for the subsequent formation of the gate structure. Moreover, after the dummy gate 118 is removed, the gate opening 121 exposes the channel stack 104, which facilitates the subsequent removal of the sacrificial layer 102 through the gate opening 121.
[0124] Specifically, the process for removing the dummy gate 118 includes one or both of dry etching and wet etching processes.
[0125] refer to Figure 16 The first sacrificial layer 102 and the second sacrificial layer 300 exposed by the gate opening 121 are removed. After removing the sacrificial layer 102 exposed by the gate opening 121, a gate dielectric layer 122 is formed in the gate opening 121 to conformally cover part of the top, part of the sidewalls and part of the bottom of the channel layer 103. The gate dielectric layer 122 also conformally covers the dielectric wall 116 exposed by the gate opening 121. After forming the gate dielectric layer 122, a gate electrode layer 123 is formed in the gate opening 121 that spans the channel layer 103 and the dielectric wall 116. The gate electrode layer 123 surrounds and covers the gate dielectric layer 122. The gate dielectric layer 122 and the gate electrode layer 123 constitute the gate structure 180.
[0126] Specifically, when the device is in operation, the gate structure 180 is used to control the opening or closing of the conductive channels of the first type transistor and the second type transistor in the device region 100A.
[0127] In this embodiment, the material of the gate dielectric layer 122 includes one or more of HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, SiO2 and La2O3.
[0128] Specifically, the gate dielectric layer 122 includes a gate oxide layer that conformally covers a portion of the top, a portion of the sidewalls, and a portion of the bottom of the channel layer 103, and a high-k gate dielectric layer that conformally covers the gate oxide layer. The high-k gate dielectric layer is made of a high-k dielectric material, which refers to a dielectric material with a relative permittivity greater than that of silicon oxide.
[0129] It should be noted that the gate dielectric layer 122 also conformally covers part of the top of the isolation layer 117, as well as part of the top and part of the sidewalls of the exposed dielectric wall 116 of the channel layer 103.
[0130] The gate electrode layer 123 is used for subsequent electrical connection with external structures. The material of the gate electrode layer 123 includes one or more of TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN, and TiAlC. Specifically, the gate electrode layer 123 may include a work function layer and an electrode layer covering the work function layer, or the gate electrode layer 123 may only include a work function layer.
[0131] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.
Claims
1. A semiconductor structure, characterized in that, include: The substrate includes discrete device regions and isolation regions located between the device regions, the device regions including a first region and a second region spaced apart, and the substrate including a substrate and fins protruding from the substrates of the first region and the second region respectively; A channel structure layer is suspended on top of the fin of the device region and, along the normal direction of the substrate surface, the channel structure layer includes one or more spaced-apart channel layers. An isolation layer is located on the substrate of the isolation region and exposes the sidewalls of the channel structure layer; A dielectric wall is located on the substrate at the junction of the first region and the second region and covers the sidewall of the channel structure layer. The dielectric wall includes a bottom dielectric wall and a top dielectric wall located on top of the bottom dielectric wall. The top of the bottom dielectric wall is higher than the top of the channel structure layer, and the top dielectric wall is used to fill the gap formed by the bottom dielectric wall and the channel structure layer. A gate dielectric layer that covers a portion of the top, a portion of the sidewalls, and a portion of the bottom of the channel structure layer; A gate electrode layer is located on the substrate and spans the channel structure layer and the dielectric wall, the gate electrode layer surrounding and covering the gate dielectric layer.
2. The semiconductor structure as described in claim 1, characterized in that, The distance from the top of the bottom dielectric wall to the top of the channel structure layer is 5 nanometers to 20 nanometers.
3. The semiconductor structure as described in claim 1, characterized in that, The material of the top dielectric wall is the same as the material of the insulating layer.
4. The semiconductor structure as described in claim 1, characterized in that, The top of the substrate at the junction of the first region and the second region is lower than the top of the substrate in the isolation region.
5. The semiconductor structure as described in claim 4, characterized in that, The distance from the top of the substrate at the junction of the first and second regions to the top of the substrate in the isolation region is 50 angstroms to 300 angstroms.
6. The semiconductor structure as described in claim 4, characterized in that, The material of the top dielectric wall includes one or more of silicon oxide, silicon nitride, and silicon oxynitride.
7. The semiconductor structure as described in claim 1, characterized in that, The material of the bottom dielectric wall includes one or more of silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon carbonitride, and silicon carbonitride.
8. The semiconductor structure as described in claim 1, characterized in that, The channel layer material includes one or more of silicon, silicon germanide, germanium, and group III-V semiconductor materials.
9. The semiconductor structure as described in claim 1, characterized in that, The material of the gate dielectric layer includes one or more of HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, SiO2, and La2O3; The material of the gate electrode layer includes one or more of TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN, and TiAlC.
10. The semiconductor structure as claimed in claim 1, characterized in that, The first region of the device region is used to form a first type transistor, and the second region of the device region is used to form a second type transistor. The first type transistor and the second type transistor have different channel conductivity types.
11. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided, the substrate including discrete device regions, the device regions including adjacent first regions and second regions, the substrate including a substrate and fins protruding from the substrates of the first regions and the second regions respectively, the fins having a channel stack structure formed thereon, the channel stack structure including one or more longitudinally stacked channel stacks, each channel stack including a sacrificial layer and a channel layer located on the sacrificial layer, and in the device regions, adjacent channel stacks of the first regions and the second regions, the fins, and the substrate at the junction of the first regions and the second regions form an isolation trench; A bottom sidewall material layer is formed to cover the trench stacked structure and the base in a conformal manner, and the bottom sidewall material layers on the opposite sidewalls of the isolation trench are in contact with each other; Remove the sidewall material layer located on top of the substrate and on top of the trench stack, as well as a portion of the sidewall material layer in the isolation trench, to form a bottom dielectric wall in a portion of the space of the isolation trench, the top surface of the bottom dielectric wall being higher than the top surface of the trench stack; After the bottom dielectric wall is formed, a top dielectric wall is formed in the remaining space of the isolation trench, covering the top of the bottom dielectric wall. The top dielectric wall is used to fill the gap formed by the bottom dielectric wall and the channel structure layer. The channel structure layer includes one or more channel layers spaced apart. The top of the top dielectric wall is flush with the top of the channel stack structure. The top dielectric wall and the bottom dielectric wall constitute a dielectric wall.
12. The method for forming a semiconductor structure as described in claim 11, characterized in that, The step of forming the top dielectric wall includes: forming a top sidewall material layer covering the substrate and the trench stack structure, the top sidewall material layer also filling the remaining space of the isolation trench; The top sidewall material layer is etched back to remove the top sidewall material layer in the device area that is higher than the top of the channel stack structure. A top dielectric wall is formed in the remaining space of the isolation trench, covering the top of the bottom dielectric wall. The top of the top dielectric wall is flush with the top of the channel stack structure. The top dielectric wall and the bottom dielectric wall constitute a dielectric wall.
13. The method for forming a semiconductor structure as described in claim 12, characterized in that, In the step of providing the substrate, the substrate further includes an isolation region located between the device regions; The step of etching the top sidewall material layer includes: performing a first etching process on the top sidewall material layer of the isolation area to remove the top sidewall material layer of a predetermined thickness in the isolation area; After the first etching process, the top of the channel stack structure is used as the etching stop position, and the remaining top sidewall material layer in the isolation region and device region is etched a second time to form the top dielectric wall in the isolation trench and the isolation layer on the substrate of the isolation region.
14. The method for forming a semiconductor structure as described in claim 13, characterized in that, The step of performing a first etching process on the top sidewall material layer of the isolation region includes: forming a patterned first mask layer on top of the top sidewall material layer of the device region; and etching away the top sidewall material layer of a predetermined thickness in the isolation region using the first mask layer as a mask.
15. The method for forming a semiconductor structure as described in claim 11, characterized in that, The steps of forming the substrate and channel stack include: An initial substrate is provided, the initial substrate including discrete device regions, the device regions including adjacent first regions and second regions, and one or more longitudinally stacked channel material stacks are formed on the initial substrate, each of the channel material stacks including a sacrificial material layer and a channel material layer located on the sacrificial material layer; The initial substrate and the channel material stack located on the initial substrate are graphically represented as the substrate, which includes a substrate and fins protruding from the substrates of the first region and the second region, respectively. The channel material stack is graphically represented as a channel stack located on the fins.
16. The method for forming a semiconductor structure as described in claim 11 or 15, characterized in that, In the step of forming the substrate, the substrate further includes an isolation region located between the device regions; In the step of forming the substrate, the adjacent channel stacks closest to the isolation zone and the fins together with the remaining substrate of the isolation zone form an isolation opening, the bottom of the isolation groove being lower than the bottom of the isolation opening.
17. The method for forming a semiconductor structure as described in claim 15, characterized in that, The step of graphically representing the initial substrate and the channel material stack on the initial substrate includes: forming a core layer on top of the channel material stack, wherein a mask opening is formed in the core layer at the junction of the first region and the second region; A discrete second mask layer is formed on top of the core layer of the first and second regions. The second mask layer exposes the top of the core layer of the isolation region, which is located between the device regions and is used to electrically isolate adjacent device regions. Using the second mask layer as a mask, the core layer, the channel material stack, and a portion of the initial substrate thickness are etched.
18. The method for forming a semiconductor structure as described in claim 13, characterized in that, In the first etching process, the preset thickness of the top sidewall material layer removed from the isolation zone is 500 to 1500 angstroms.
19. The method for forming a semiconductor structure as described in claim 11, characterized in that, The first region of the device region is used to form a first type transistor, and the second region of the device region is used to form a second type transistor. The first type transistor and the second type transistor have different channel conductivity types.