Integrated circuit devices and methods of manufacturing integrated circuit devices

Abstract

An integrated circuit device and a method of manufacturing an integrated circuit are disclosed. The integrated circuit device includes a first type of active region semiconductor structure, a first gate conductor, a second type of active region semiconductor structure stacked with the first type of active region semiconductor structure, and a second gate conductor. The integrated circuit device also includes a front conductive layer above the two active region semiconductor structures and a back conductive layer below the two active region semiconductor structures. The integrated circuit device also includes a front power rail and a front signal line in the front conductive layer, and a back power rail and a back signal line in the back conductive layer. The integrated circuit device also includes a first source conductive segment connected to the front power rail and a second source conductive segment connected to the back power rail. The integrated circuit device also includes a drain conductive segment connected to the front signal line or the back signal line.

Description

Technical Field

[0001] This disclosure relates to integrated circuit devices and their manufacturing methods, particularly the power rails and signal arrangements in integrated circuit devices having multiple stacked transistors. Background Technology

[0002] An integrated circuit (IC) typically comprises multiple integrated circuit devices fabricated according to one or more integrated circuit layouts. IC devices sometimes include complementary field-effect transistor (CFET) devices. In a stacked configuration, a CFET device typically has a higher CFET that covers a lower CFET. Both the higher and lower CFETs in the CFET device are located above a plurality of conductors in the back conductive layer but below a plurality of conductors in the front conductive layer. Summary of the Invention

[0003] Some embodiments of this invention provide an integrated circuit device comprising: a first type active region semiconductor structure, a first gate conductor, a second type active region semiconductor structure, a second gate conductor, a front conductive layer, a back conductive layer, a front power rail, a back power rail, a front signal line, a back signal line, a first source conductive segment, a second source conductive segment, and a drain conductive segment. The first type active region semiconductor structure extends in a first direction. The first gate conductor extends in a second direction perpendicular to the first direction and intersects the first type active region semiconductor structure at a channel region of a first type transistor. The second type active region semiconductor structure extends in the first direction, stacks with the first type active region semiconductor structure, and is offset from the first type active region semiconductor structure along a third direction perpendicular to both the first and second directions. The second gate conductor extends in the second direction and intersects the second type active region semiconductor structure at a channel region of a second type transistor. The front conductive layer faces the third direction and is located above the first and second type active region semiconductor structures. The back conductive layer faces the third direction and is located below the first and second type active region semiconductor structures. A front-side power rail extends in a first direction within a front-side conductive layer and is configured to maintain a first supply voltage. A back-side power rail extends in a first direction within a back-side conductive layer and is configured to maintain a second supply voltage. A front-side signal line extends in the first direction within the front-side conductive layer. A back-side signal line extends in the first direction within the back-side conductive layer. A first source conductive segment extends in a second direction, intersecting with a first-type active region semiconductor structure at the source region of a first-type transistor, and is conductively connected to the front-side power rail via a first via connector. A second source conductive segment extends in a second direction, intersecting with a second-type active region semiconductor structure at the source region of a second-type transistor, and is conductively connected to the back-side power rail via a second via connector. A drain conductive segment extends in a second direction, intersecting with one or both of the first-type and second-type active region semiconductor structures, and is conductively connected to the front-side or back-side signal line via a third via connector.

[0004] Other embodiments of this disclosure provide an integrated circuit device comprising: a first type of active region semiconductor structure, a second type of active region semiconductor structure, a front conductive layer, a back conductive layer, a plurality of gate conductors, a plurality of conductive segments, a front signal line, a back signal line, a front power rail, and a back power rail. The first type of active region semiconductor structure extends in a first direction. The second type of active region semiconductor structure extends in the first direction and is stacked with the first type of active region semiconductor structure. The front conductive layer is higher than both the first and second type of active region semiconductor structures. The back conductive layer is lower than both the first and second type of active region semiconductor structures. A plurality of gate conductors extend in a second direction perpendicular to the first direction, each of these gate conductors intersecting with one or both of the first and second type of active region semiconductor structures, simultaneously forming a gate terminal of at least one transistor. Multiple conductive segments extend in a second direction, each of which intersects one or both of a first-type active-region semiconductor structure and a second-type active-region semiconductor structure, simultaneously forming a source or drain terminal of at least one transistor. The multiple conductive segments include a first conductive segment, a second conductive segment, a third conductive segment intersecting the first-type active-region semiconductor structure, and a fourth conductive segment intersecting the second-type active-region semiconductor structure. A front-side signal line extends in a first direction within the front-side conductive layer and is configured to transmit a first voltage change at the first conductive segment to one or more of these gate conductors or to one or more of these conductive segments. A back-side signal line extends in a first direction within the back-side conductive layer and is configured to transmit a second voltage change at the second conductive segment to one or more of these gate conductors or to one or more of these conductive segments. A front-side power rail extends in a first direction within the front-side conductive layer, is configured to maintain a first supply voltage, and is conductively connected to a third conductive segment via a first via connector. The back-side power rail extends in a first direction within the back-side conductive layer, is configured to maintain a second supply voltage, and is conductively connected to a fourth conductive segment via a second via connector.

[0005] Further embodiments of this disclosure provide a method for manufacturing an integrated circuit device, comprising: fabricating a first type active region semiconductor structure extending in a first direction on a substrate; fabricating a first gate conductor intersecting the first type active region semiconductor structure at a channel region of a first type transistor; fabricating a first source conductive segment intersecting the first type active region semiconductor structure at a first source region; depositing a dielectric material layer that at least covers the first type active region semiconductor structure; fabricating a second type active region semiconductor structure extending in the first direction on top of the dielectric material layer, wherein the second type active region semiconductor structure is stacked with the first type active region semiconductor structure; fabricating a second gate conductor intersecting the second type active region semiconductor structure at a channel region of a first second type transistor; fabricating a second type active region semiconductor structure extending in the first direction on top of the dielectric material layer; fabricating a second type active region semiconductor structure extending in the first direction on top of the first type active region semiconductor structure; fabricating a second gate conductor intersecting the second type active region semiconductor structure at a channel region of a first second type transistor; and fabricating a third type active region semiconductor structure extending in the first direction on a substrate. A second source conductive segment intersects with a second type of active region semiconductor structure at the second source region; a first insulating material is deposited covering the second gate conductor and the second source conductive segment; a front-side metal layer is deposited over the first insulating material and patterned to form a front-side power rail extending in a first direction and a front-side signal line extending in a first direction, wherein the front-side power rail is conductively connected to the second source conductive segment through a first via connector, and wherein the front-side signal line is conductively connected to the second gate conductor through a front-side gate via connector; and a back-side metal layer is formed on the back side of the substrate and patterned to form a back-side power rail extending in a first direction and a back-side signal line extending in a first direction, wherein the back-side power rail is conductively connected to the first source conductive segment through a second via connector. Attached Figure Description

[0006] The various aspects of this disclosure can be best understood by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with industry standard practice, the features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the features may be arbitrarily increased or decreased.

[0007] Figure 1A This is a diagram of an inverter circuit according to some implementations, which has multiple power rails and multiple signal lines in both the front conductive layer and the back conductive layer.

[0008] Figure 1B Based on some implementation methods Figure 1A The layout diagram of the inverter circuit depicted in the figure;

[0009] Figure 1C It is based on some implementation methods Figure 1A Multiple cross-sectional views of the inverter circuit;

[0010] Figure 1D It is based on some implementation methods Figure 1AA cross-sectional view of the inverter circuit;

[0011] Figure 2A Based on some implementation methods Figure 1A Modification of the inverter circuit in the text;

[0012] Figure 2B Based on some implementation methods Figure 2A Multiple layout diagrams of inverter circuits in the image;

[0013] Figure 2C Based on some implementation methods Figure 2A Multiple cross-sectional views of the inverter circuit in the image;

[0014] Figure 3A Based on some implementation methods Figure 1A Another modification to the inverter circuit in the diagram;

[0015] Figure 3B Based on some implementation methods Figure 3A Multiple layout diagrams of inverter circuits in the image;

[0016] Figure 3C Based on some implementation methods Figure 3A Multiple cross-sectional views of the inverter circuit in the image;

[0017] Figure 4A Based on some implementation methods Figure 3A Modification of the inverter circuit in the text;

[0018] Figure 4B Based on some implementation methods Figure 4A Multiple layout diagrams of inverter circuits in the image;

[0019] Figure 4C Based on some implementation methods Figure 4A Multiple cross-sectional views of the inverter circuit in the image;

[0020] Figure 5A Based on some implementation methods Figure 4A Modification of the inverter circuit in the text;

[0021] Figure 5B Based on some implementation methods Figure 5A Multiple layout diagrams of inverter circuits in the image;

[0022] Figure 5C Based on some implementation methods Figure 5A Multiple cross-sectional views of the inverter circuit in the image;

[0023] Figure 5D Based on some implementation methods Figure 5AA cross-sectional view of the inverter circuit in the image;

[0024] Figure 6A Based on some implementation methods Figure 5A Modification of the inverter circuit in the text;

[0025] Figure 6B Based on some implementation methods Figure 6A Multiple layout diagrams of inverter circuits in the image;

[0026] Figure 6C It is based on some implementation methods Figure 6A A cross-sectional view of the inverter circuit in the image;

[0027] Figures 7A to 7B These are multiple circuit diagrams of inverter circuits and sub-circuits according to some implementation methods;

[0028] Figure 8A It is implemented using complementary field-effect transistors according to some implementation methods. Figure 7B The diagram of the sub-circuit in the diagram;

[0029] Figure 8B Based on some implementation methods Figure 8A Multiple layout diagrams of sub-circuits in the circuit;

[0030] Figure 8C Based on some implementation methods Figure 8A A cross-sectional view of the sub-circuit in the diagram;

[0031] Figure 9A These are multiple layout diagrams of AOI (AND-OR-INVENTER) logic circuits according to some implementations.

[0032] Figure 9B Based on some implementation methods Figure 9A The circuit diagram of the AOI logic circuit in the document;

[0033] Figure 9C Based on some implementation methods Figure 9A A list of transistors showing the positions of multiple transistors in a layout diagram;

[0034] Figure 10A These are multiple layout diagrams of a Scan D Flip-flop (SDF) circuit according to some implementation methods;

[0035] Figure 10B It is based on some implementation methods Figure 10A The circuit diagram of the scan D-type flip-flop circuit specified in the multiple layout diagrams;

[0036] Figure 10C Based on some implementation methods Figure 10A A list of transistors located in multiple layout diagrams within a given configuration.

[0037] Figure 11A It is based on some implementation methods Figure 10B The equivalent circuit diagram of the scanning D-type flip-flop circuit in the image;

[0038] Figure 11B This is a circuit diagram of a scanning D-type flip-flop circuit represented by multiple functional blocks according to some implementation methods.

[0039] Figure 12A and Figure 12B According to some implementation methods, these are the upper and lower portions of a layout diagram corresponding to a multi-unit circuit;

[0040] Figure 13 These are multiple layout diagrams of circuit units according to some implementation methods, wherein the circuit units have multiple marked dimensions;

[0041] Figure 14 It is a flowchart of a method for generating an integrated circuit (IC) layout diagram according to some implementation methods;

[0042] Figure 15 This is a flowchart of a method 1500 for manufacturing an integrated circuit (IC) having a complementary field-effect transistor device according to some embodiments;

[0043] Figure 16 This is a block diagram of an electronic design automation (EDA) system according to some implementation methods;

[0044] Figure 17 It is a block diagram of an integrated circuit (IC) manufacturing system and the associated integrated circuit manufacturing process according to some implementation methods.

[0045] [Symbol Explanation]

[0046] 100: Inverter circuit (inverter)

[0047] 110: Virtual gate strip pattern

[0048] 1110: Two-input multiplier

[0049] 1111: First input

[0050] 1112: Second input

[0051] 1119: Output

[0052] 1120: Master latch

[0053] 1122: Inverter

[0054] 1124: Clock-controlled inverter

[0055] 1130: Transfer Gate

[0056] 1140: From latch

[0057] 1142: Inverter

[0058] 1144: Clock-controlled inverter

[0059] 1150: Inverter

[0060] 1170: Inverter

[0061] 1180: Inverter

[0062] 1190: Inverter

[0063] 1200: Multi-unit circuit

[0064] 120B: Rear side signal line

[0065] 120B(1), 120B(2), 120B(3): Backside signal line

[0066] 120F: Front signal line

[0067] 120F(1), 120F(2), 120F(3): Front signal line

[0068] 1251n: First Edge

[0069] 1251p: First Edge

[0070] 1259n: Second Edge

[0071] 1259p: Second Edge

[0072] 1290AB: Shared element boundary

[0073] 1290BC: Shared element boundary

[0074] 132n, 132p, 134n, 134p: Conductive segments

[0075] 136n: Conductive segment

[0076] 138p: Conductive segment

[0077] 1400: Method

[0078] 1402, 1404, 1406, 1408, 1410, 1412: Operations

[0079] 140B: Rear side signal line

[0080] 140B(1), 140B(2), 140B(3): Backside signal line

[0081] 140F: Front signal line

[0082] 140F(1), 140F(2), 140F(3): Front signal line

[0083] 150: Gate conductor

[0084] 1500: Method

[0085] 1510, 1512, 1514, 1520, 1530, 1532, 1534, 1540, 1550, 1555, 1560, 1570, 1575: Operation

[0086] 150n: Gate conductor

[0087] 150p: Gate conductor

[0088] 1600: System

[0089] 1602: Processor

[0090] 1604: Storage medium

[0091] 1606: Instruction

[0092] 1607: Standard cell library

[0093] 1608: Bus

[0094] 1609: Layout Diagram

[0095] 1610: Input / Output Interface

[0096] 1612: Network Interface

[0097] 1614: Network

[0098] 1642: User Interface

[0099] 160B: Rear side signal line

[0100] 160F: Front signal line

[0101] 1700: System

[0102] 1720: Design Company

[0103] 1722: Design Layout Diagram

[0104] 1730: Mask Company

[0105] 1732: Data Preparation

[0106] 1744: Mask Making

[0107] 1745: Mask

[0108] 1750: Integrated Circuit Manufacturing Plant

[0109] 1752: Manufacturing Tools

[0110] 1753: Semiconductor wafers

[0111] 1760: Integrated Circuit Device

[0112] 200: Inverter Circuit

[0113] 300: Inverter Circuit

[0114] 30B: Rear power rail

[0115] 30B(1), 30B(2), 30B(3): Rear power rail

[0116] 30F: Front power rail

[0117] 30F(1), 30F(2), 30F(3): Front power rail

[0118] 32B: Rear power rail

[0119] 32F: Front power rail

[0120] 34B: Rear power rail

[0121] 34F: Front power rail

[0122] 400: Inverter Circuit

[0123] 500: Inverter Circuit

[0124] 50n: n-type active region semiconductor structure

[0125] 50n(1), 50n(2), 50n(3): n-type active region semiconductor structures

[0126] 50p:p-type active region semiconductor structure

[0127] 50p(1), 50p(2), 50p(3): p-type active region semiconductor structure

[0128] 52n: n-type active region semiconductor structure

[0129] 52p: p-type active region semiconductor structure

[0130] 54n: n-type active region semiconductor structure

[0131] 54p: p-type active region semiconductor structure

[0132] 600: Inverter Circuit

[0133] 800: Sub-circuit

[0134] 815: Gate Stack Insulator

[0135] 885: Special Symbols

[0136] 900: AOI Logic Circuit

[0137] 920F: Front signal line

[0138] 922B: Rear side signal line

[0139] 924B: Rear side signal line

[0140] 932n, 932p, 934n, 934p, 935n, 935p, 936n, 936p, 938n, 938p: Conductive segments

[0141] 942B: Rear side signal line

[0142] 942F: Front signal line

[0143] 944B: Backside signal line

[0144] 944F: Front signal line

[0145] B22, B24, B26, B42, B44, B46, B62, B64, B66, B82, B84, B86: Rear-side signal lines

[0146] C30n, C30p, C31n, C31p, C32n, C32p, C33n, C33p, C34n, C34p, C35n, C35p, C36n, C36p, C37n, C37p, C38n, C38p, C39n, C39p, C70n, C70p, C71n, C71p, C72n, C72p, C73n, C73p, C74n, C74p, C75n, C75p, C76n, C76p, C77n, C77p, C78n, C78p, C79n, C79p: Conductive segment

[0147] Cell A: Unit A

[0148] Cell B: Unit B

[0149] Cell C: Unit C

[0150] ckb: clock signal

[0151] ckbb: clock signal

[0152] CP: Clock signal

[0153] CPODE: Continuous polysilicon at the oxide boundary

[0154] D: Data signal

[0155] F22, F24, F26, F28, F42, F44, F62, F64, F66, F68, F82, F86: Front signal lines

[0156] gA1, gA2, gB1, gB2: Gate conductors

[0157] gCKb_0, gCP, gD, gML_ax, gML_b, gnCKb, gnCKbb, gpCKb, gpCKbb, gQB, gSE, gSEB, gSI, gSL_a, gSL_bx: Gate conductors

[0158] IN: Input logic signal

[0159] IN_A: Input logic signal

[0160] IN_B: Input logic signal

[0161] M1_1, M1_2: Conductive wiring lines

[0162] N1_1, N1_2: Conductive wiring lines

[0163] nA1, nA2, nB1, nB2: n-type transistors

[0164] nCK_ML, nCK_MX, nCK_SL, nCK_TX, nCKb_0,

[0165] nCKb_MX, nCKb_SL, nCP, nD, nML_ax, nML_b: n-type transistors

[0166] NMOS: N-type metal-oxide semiconductor

[0167] nMX_ax, nSE, nSE_0, nSEB, nSI, nSL_a, nSL_bx,

[0168] nQB: n-type transistor

[0169] oCK_ML, oCK_MX, oCK_SL, oCKb_0, oCP, oML_ax, oQB, oSE_0, oSL_a: Signal output nodes

[0170] OUT: Output

[0171] P-P': Cutting plane (line)

[0172] pA1, pA2, pB1, pB2: p-type transistors

[0173] pCK_MX, pCK_SL, pCKb_0, pCKb_ML, pCKb_TX, pCP, pD, pML_ax, pML_b: p-type transistors

[0174] PMOS: P-type metal oxide semiconductor

[0175] pQB, pSE, pSE_0, pSEB, PSI, pSL_a, PSL_bx: p-type transistors

[0176] Q: Output data

[0177] Q-Q': Cutting a plane (line)

[0178] R-R': Cutting plane (line)

[0179] SE: Select Enable Signal

[0180] SEB: Inverted Select Enable Signal

[0181] SI: Scan input signal

[0182] T1n: NMOS transistor

[0183] T1p: PMOS transistor

[0184] VB: Bottom guide hole connector (guide hole connector, guide hole connector pattern)

[0185] VB1: Bottom guide hole connector

[0186] VB2: Bottom guide hole connector

[0187] VB3: Bottom guide hole connector

[0188] VBT: Bottom-to-top via connector (bottom-to-top via connector pattern)

[0189] VBT_e1: Bottom-to-top guide hole connector VBT edge

[0190] VDD: Supply voltage

[0191] VG: Gate via connector (gate via connector pattern)

[0192] VIA0: Hole Connector

[0193] VIIA0: Guide Hole Connector

[0194] VMD: Inter-conductor connector (connector pattern)

[0195] VSS: Supply Voltage

[0196] VT: Top-mounted guide hole connector (guide hole connector, guide hole connector pattern)

[0197] VT1: Top guide hole connector

[0198] VT2: Top-mounted connector

[0199] VT3: Top-mounted connector

[0200] VTB: Top-to-bottom via connector (top-to-bottom via connector pattern)

[0201] VTB_e1: Bottom-to-top guide hole connector VTB edge

[0202] Wa, Wa', Wb, Wb', Wc, Wc', We, We': Width

[0203] X, Y, Z: Direction

[0204] (a), (a'): width

[0205] (b), (b'): Length

[0206] (c), (c'): Width

[0207] (d), (d'): Length

[0208] (e), (e'): width

[0209] (f), (f'): Width

[0210] (g), (g'): Length

[0211] (h), (h'): Length

[0212] (i), (i'): width

[0213] (j), (j'): Length Detailed Implementation

[0214] The following disclosure provides numerous different implementations or embodiments to carry out various features of the provided subject matter. To simplify this disclosure, several specific embodiments of components, materials, values, steps, operations, arrangements, or the like are described below. These are, of course, merely embodiments and are not intended to be limiting. Other components, values, operations, materials, arrangements, or the like are also conceived. For example, in the following description, forming a first feature above or on a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features may be formed between the first and second features, thus the first and second features may not be in direct contact. Additionally, reference numerals and / or letters may be repeated in various embodiments of this disclosure. This repetition is for the purpose of simplicity and clarity, and the repetition itself does not imply a relationship between the various embodiments and / or configurations discussed.

[0215] Furthermore, to facilitate the description of the relationship between one element or feature and another, as illustrated in the accompanying drawings, spatially relative terms such as “below,” “lower,” “lower,” “higher,” “upper,” and similar terms may be used herein. In addition to the directions depicted in the accompanying drawings, the spatially relative terms are intended to cover different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptive terms used herein shall be interpreted in the same manner.

[0216] Complementary field-effect transistors (CFETs) typically have a first type of transistor stacked with a second type of transistor. The first type of transistor has a channel region in a first type of active-area semiconductor structure, and the second type of transistor has a channel region in a second type of active-area semiconductor structure. Integrated circuit devices with CFETs often include a front conductive layer above the plurality of CFETs and a back conductive layer below the plurality of CFETs. In at least some embodiments, the device performance of an integrated circuit device with CFETs depends on the positioning of a plurality of power rails and a plurality of signal lines. In some embodiments, when a cell circuit in an integrated circuit device is powered by a first supply voltage held on a front power rail in the front conductive layer and a second supply voltage held on a back power rail in the back conductive layer, the power connection to the cell circuit is improved by utilizing the reduced resistance between the cell circuit and the power rails. Furthermore, in some embodiments, when both the front signal line in the front conductive layer and the back signal line in the back conductive layer can be used to connect to the plurality of CFETs in the integrated circuit device, some limitations on the width extension of the plurality of active-area semiconductor structures are eliminated. Furthermore, in some embodiments, when multiple front-side power rails in an integrated circuit device intersect with multiple front-side signal lines, and multiple back-side power rails in an integrated circuit device intersect with multiple back-side signal lines, the multiple front-side power rails improve the inter-cell signal shielding for the multiple front-side signal lines, and the multiple back-side power rails improve the inter-cell signal shielding for the multiple back-side signal lines.

[0217] Figure 1A The diagram shows an inverter circuit 100 implemented using complementary field-effect transistors (FETs) according to some embodiments. The inverter circuit 100 has multiple power rails and multiple signal lines in both the front and back conductive layers. The circuit diagram of the inverter circuit is shown in... Figure 7A As shown. In Figure 7A The inverter circuit in the circuit includes a PMOS (P-type metal-oxide-semiconductor) device and an NMOS (N-type metal-oxide-semiconductor) device. The gate terminals of the PMOS and NMOS devices are connected together and function as the input terminals of the inverter. The drain terminals of the PMOS and NMOS devices are connected together and function as the output (OUT) terminals of the inverter. The source terminals of the PMOS and NMOS devices are respectively held at the supply voltage VDD (internal operating voltage of the device) and the supply voltage VSS (circuit common ground voltage).

[0218] exist Figure 1AIn the inverter circuit 100, a p-type active region semiconductor structure 50p extending in the X direction and an n-type active region semiconductor structure 50n extending in the X direction are included. Figure 1A The X, Y, and Z directions are mutually orthogonal, forming an orthogonal coordinate system. A p-type active region semiconductor structure 50p and an n-type active region semiconductor structure 50n are stacked, with the p-type active region semiconductor structure 50p offset from the n-type active region semiconductor structure along the Z direction. A gate conductor 150 extending in the Y direction intersects both the p-type and n-type active region semiconductor structures 50p and 50n. The gate conductor 150 functions as two stacked gate conductors electrically bonded together: one intersects the p-type active region semiconductor structure 50p at the channel region of the PMOS transistor T1p, and the other intersects the n-type active region semiconductor structure 50n at the channel region of the NMOS transistor T1n. The gate conductor 150 is electrically connected to the gate terminals of both the PMOS transistor T1p and the NMOS transistor T1n. In some embodiments, each of the p-type active region semiconductor structure 50p and the n-type active region semiconductor structure 50n includes one or more nanosheets, and therefore, each of the PMOS transistor T1p and the NMOS transistor T1n is a nanosheet transistor. In some embodiments, each of the p-type active region semiconductor structure 50p and the n-type active region semiconductor structure 50n includes one or more nanowires, and therefore, each of the PMOS transistor T1p and the NMOS transistor T1n is a nanowire transistor.

[0219] The inverter circuit 100 also includes multiple conductive segments 132p, 134p, 132n, and 134n. Each of the multiple conductive segments 132p and 134p extending in the Y direction intersects with the p-type active region semiconductor structure 50p at one of the multiple terminal regions of the PMOS transistor T1p. Each of the multiple conductive segments 132n and 134n extending in the Y direction intersects with the n-type active region semiconductor structure 50n at one of the multiple terminal regions of the NMOS transistor T1n. The terminal regions of the transistor are either the source region or the drain region of the transistor. Conductive segment 132p, serving as the source conductive segment, forms the source terminal of the PMOS transistor T1p. Conductive segment 132n, serving as the source conductive segment, forms the source terminal of the NMOS transistor T1n. Conductive segment 134p, serving as the drain conductive segment, forms the drain terminal of the PMOS transistor T1p. Conductive segment 134n, serving as the drain conductive segment, forms the drain terminal of the NMOS transistor T1n. Conductive segments 134p and 134n are conductively connected via an inter-segment connector VMD. When the drain terminals of PMOS transistor T1p and NMOS transistor T1n are conductively connected together via the inter-segment connector VMD, the source terminal of PMOS transistor T1p is conductively connected to the front power rail 30F via the top via connector VT, and the source terminal of NMOS transistor T1n is conductively connected to the back power rail 30B via the bottom via connector VB. The front power rail 30F is configured to maintain a first supply voltage VDD, while the back power rail 30B is configured to maintain a second supply voltage VSS.

[0220] A front power rail 30F extending in the X direction is in the front conductive layer. A back power rail 30B extending in the X direction is in the back conductive layer. Both the front and back conductive layers are in a plane having a normal vector toward the Z direction. The front conductive layer is higher than both the p-type active region semiconductor structure 50p and the n-type active region semiconductor structure 50n. The back conductive layer is lower than both the p-type active region semiconductor structure 50p and the n-type active region semiconductor structure 50n. In some embodiments, the back conductive layer is fabricated as a buried conductive layer on the substrate, and then the n-type active region semiconductor structure 50n is fabricated higher than the buried conductive layer. Subsequently, the p-type active region semiconductor structure 50p is fabricated higher than the n-type active region semiconductor structure 50n, and the front conductive layer is fabricated higher than the p-type active region semiconductor structure 50p. Other arrangements of the back conductive layer are also within the scope of this disclosure. In some embodiments, in the integrated circuit device, the front power rail and the back power rail overlap each other when viewed in a direction perpendicular to the front conductive layer and the back conductive layer. In some embodiments, in the integrated circuit device, the front power rail and the back power rail overlap each other by approximately 80% when viewed in a direction perpendicular to the front conductive layer and the back conductive layer.

[0221] exist Figure 1A In the inverter circuit 100, a plurality of front-side signal lines 120F and 140F are included in the front-side conductive layer, and a plurality of back-side signal lines 120B and 140B are also included in the back-side conductive layer. The front-side signal line 120F is conductively connected to the gate conductor 150 via a top gate via connector VG and is configured as an input signal line for the inverter circuit. The front-side signal line 140F is conductively connected to the conductive segment 134n via a bottom-to-top via connector VBT and is configured as an output signal line for the inverter circuit. In some embodiments, although in Figure 1A The multiple back-side signal lines 120B and 140B are not directly connected to any circuit node in the inverter circuit 100, but are configured to route multiple signals between adjacent cells at opposite sides of the inverter circuit. For example, in some embodiments, a signal from an adjacent cell adjacent to multiple conductive segments 132p and 132n is coupled to another adjacent cell adjacent to multiple conductive segments 134p and 134n via one of the multiple back-side signal lines 120B and 140B.

[0222] Figure 1B Based on some implementation methods Figure 1A The diagram shows multiple layouts of the inverter circuit 100. Figure 1BThe multiple layout diagrams include an upper portion and a lower portion of the layout. The upper portion of the layout includes multiple layout patterns that specify a p-type active region semiconductor structure 50p, a gate conductor 150, multiple conductive segments 132p and 134p, multiple front-side signal lines 120F and 140F, a front-side power rail 30F, an inter-segment connector VMD, and various via connectors. The lower portion of the layout includes multiple layout patterns that specify an n-type active region semiconductor structure 50n, a gate conductor 150, multiple conductive segments 132n and 134n, multiple back-side signal lines 120B and 140B, a back-side power rail 30B, an inter-segment connector VMD, and various via connectors.

[0223] like Figure 1B As specified in the upper part, each of the p-type active region semiconductor structure 50p, the plurality of front-side signal lines 120F and 140F, and the front-side power rail 30F extends in the X direction. The gate conductor 150, extending in the Y direction, intersects the p-type active region semiconductor structure 50p at the channel region of the PMOS transistor. The conductive segment 132p, extending in the Y direction, intersects the p-type active region semiconductor structure 50p at the source region of the PMOS transistor. The conductive segment 134p, extending in the Y direction, intersects the p-type active region semiconductor structure 50p at the drain region of the PMOS transistor.

[0224] The via connector pattern VT at the intersection between conductive segment 132p and front power rail 30F specifies that conductive segment 132p and front power rail 30F are electrically connected via the top via connector VT. The gate via connector pattern VG at the intersection between gate conductor 150 and front signal line 120F specifies that gate conductor 150 and front signal line 120F are electrically connected via the top gate via connector VG.

[0225] As by Figure 1B As specified in the lower portion, each of the n-type active region semiconductor structure 50n, the plurality of back-side signal lines 120B and 140B, and the back-side power rail 30B extends in the X direction. The gate conductor 150, extending in the Y direction, intersects the n-type active region semiconductor structure 50n at the channel region of the NMOS transistor. The conductive segment 132n, extending in the Y direction, intersects the n-type active region semiconductor structure 50n at the source region of the NMOS transistor. The conductive segment 134n, extending in the Y direction, intersects the n-type active region semiconductor structure 50n at the drain region of the NMOS transistor. The via connector pattern VB at the intersection between the conductive segment 132n and the back-side power rail 30B indicates that, in the inverter circuit 100, the conductive segment 132n and the back-side power rail 30B are electrically connected via the bottom via connector VB.

[0226] exist Figure 1B In the diagram, the bottom-to-top via connector pattern VBT covering the front signal line 140F in the upper portion and the bottom-to-top via connector pattern VBT covering the back signal line 140B in the lower portion match each other in the same shape and at the same location in the XY coordinate system. The multiple bottom-to-top via connector patterns VBTs matching in the various layout diagrams indicate that the front signal line 140F and the back signal line 140B are electrically connected together along the Z-direction via the bottom-to-top via connectors VBT in the inverter circuit 100. Figure 1B In the upper and lower portions, the bottom-to-top guide hole connector pattern VBT is shown as a pair of matching patterns. Figure 1B In the diagram, the inter-connector pattern VMD covering conductive segment 134p in the upper portion and the inter-connector pattern VMD covering conductive segment 134n in the lower portion match each other in the XY coordinate system with the same shape and at the same location. The multiple inter-connector patterns VMDs matching in the multiple layout diagrams indicate that conductive segments 134p and 134n in the inverter circuit 100 are electrically connected together via inter-segment connectors VMD. Figure 1B In the upper and lower portions, the VMD pattern between multiple connectors is displayed as a pair of matching patterns.

[0227] exist Figure 1BIn the layout, the upper and lower portions also include dummy gate stripe patterns 110 for specifying multiple dummy gate stripes at multiple edges of the inverter cell. In some embodiments, multiple intersections between the multiple dummy gate stripe patterns 110 and the layout pattern of the p-type active region semiconductor structure 50p specify multiple isolation regions in the p-type active region semiconductor structure 50p for isolating the p-type active regions in the inverter cell from multiple active regions in adjacent cells. In some embodiments, multiple intersections between the multiple dummy gate stripe patterns 110 and the layout pattern of the n-type active region semiconductor structure 50n specify multiple isolation regions in the n-type active region semiconductor structure 50n for isolating the n-type active regions in the inverter cell from multiple active regions in adjacent cells. In some implementations, multiple isolation regions in multiple active-region semiconductor structures (50p or 50n) are created based on poly on oxide definition edge (PODE) technology or continuous poly on oxide definition (CPODE) technology. Other suitable techniques for creating multiple isolation regions in multiple active-region semiconductor structures (50p or 50n) are also within the scope of this disclosure.

[0228] Figure 1C It is based on some implementation methods Figure 1A The inverter circuit 100 is composed of... Figure 1B The cross-sectional view in the cutting plane specified by lines P-P' and Q-Q'. Figure 1D It is based on some implementation methods Figure 1A The inverter circuit 100 is composed of... Figure 1B A cross-sectional view in the cutting plane specified by line R-R'. Figure 1C and Figure 1D In this structure, p-type active region semiconductor structure 50p and n-type active region semiconductor structure 50n are stacked. Multiple front-side signal lines 120F and 140F and a front-side power rail 30F are located in a front-side conductive layer, which is higher than both the p-type and n-type active region semiconductor structures 50p and 50n. Multiple back-side signal lines 120B and 140B and a back-side power rail 30B are located in a back-side conductive layer, which is lower than both the p-type and n-type active region semiconductor structures 50p and 50n.

[0229] exist Figure 1CAs shown in the cross-sectional view of the P-P' cut plane, conductive segment 132p intersects with p-type active region semiconductor structure 50p at the source region of the PMOS transistor, and conductive segment 132n intersects with n-type active region semiconductor structure 50n at the source region of the NMOS transistor. Conductive segment 132p is conductively connected to the front power rail 30F via the top via connector VT, while conductive segment 132n is conductively connected to the rear power rail 30B via the bottom via connector VB.

[0230] exist Figure 1C As shown in the cross-sectional view along the Q-Q' cut plane, conductive segment 134p intersects with p-type active region semiconductor structure 50p at the drain region of the PMOS transistor, and conductive segment 134n intersects with n-type active region semiconductor structure 50n at the drain region of the NMOS transistor. Conductive segment 134n is conductively connected to the front-side signal line 140F via a bottom-to-top via connector VBT. Conductive segment 134p is conductively connected to conductive segment 134n via an inter-segment connector VMD.

[0231] exist Figure 1D As shown in the cross-sectional view along the R-R' cut plane, the gate conductor 150 intersects with the p-type active region semiconductor structure 50p in the channel region of the PMOS transistor and with the n-type active region semiconductor structure 50n in the channel region of the NMOS transistor. The front-side signal line 120F is conductively connected to the gate conductor 150 via the top gate via connector pattern VG.

[0232] Besides, as in Figure 1A Besides the embodiment and implementation of the inverter circuit 100 depicted herein, there are several other designs and implementations of inverter circuits. Figure 2A , Figure 3A , Figure 4A , Figure 5A ,and Figure 6A The various diagrams in the diagrams are diagrams of inverter circuits according to some implementations, implemented with complementary field-effect transistors, wherein the inverter circuit has multiple power rails and multiple signal lines in both the front conductive layer and the back conductive layer.

[0233] exist Figure 2A The inverter circuit 200 in the middle is Figure 1A Modification of inverter circuit 100 in [the circuit]. Figure 1A The bottom-to-top guide hole connector VBT in the middle is replaced with... Figure 2A The bottom-mounted connector VB electrically connects the conductive segment 134n to the back-side signal line 140B. Figure 2AIn the configuration, the back-side signal line 140B is set as the output signal line of the inverter circuit. For comparison, in... Figure 1A In the middle, the front signal line 140F is configured as the output signal line of the inverter circuit.

[0234] Figure 2B Based on some implementation methods Figure 2A Multiple layout diagrams of the inverter circuit 200 in the image. Figure 2B Multiple layout diagrams in and in Figure 1B The multiple layout diagrams in the series are almost identical, except for the ones in the series. Figure 1B The pair of matching bottom-to-top guide hole connector patterns VBT in the upper and lower portions are removed, and... Figure 2B In the lower part, a bottom via connector pattern VB is added at the intersection between the conductive segment 134n and the back signal line 140B, which specifies that the conductive segment 134n is electrically connected to the back signal line 140B through the bottom via connector VB.

[0235] Figure 2C Based on some implementation methods Figure 2A The inverter circuit 200 in the middle is composed of Figure 2B A cross-sectional view in the cutting plane specified by lines P-P' and Q-Q'. Figure 2C The cross section of the cutting plane P-P' in the middle and in Figure 1C The cross-sections of the cutting plane P-P' are the same. Figure 2C The cross section of the cutting plane Q-Q' in the middle and in Figure 1C The cross-sections of the cutting plane Q-Q' are almost identical, except in... Figure 1C The pattern VBT, which connects the front signal line 140F to the bottom-to-top via connector of the conductive segment 134n, is replaced with the pattern VB, which connects the back signal line 140B to the bottom via connector of the conductive segment 134n.

[0236] exist Figure 3A The inverter circuit 300 in the middle is Figure 1A Another modification to the inverter circuit 100 in the circuit. This modification includes removing the inverter circuit 100 in the circuit. Figure 1A The VMD connector between conductive segments was modified, and the terminal functions of multiple conductive segments 132p and 134p were changed. Figure 3A The 134p conduction segment in the PMOS transistor functions as the source terminal, while... Figure 1A The 134p conduction segment functions as the drain terminal of the PMOS transistor. Figure 3A The 132p conductive segment functions as the drain terminal of the PMOS transistor, while... Figure 1A The 132p conduction segment functions as the source terminal of the PMOS transistor. Figure 3AIn this configuration, the source terminal of the PMOS transistor is configured to receive the power supply voltage VDD from the front power rail 30F via a top via connector VT located near the front power rail 30F on the conductive segment 134p. Figure 3A In this configuration, the drain terminals of the PMOS transistor and the NMOS transistor are electrically connected via a conductive connection from conductive segment 132p to conductive segment 134n. Conductive segment 132p is conductively connected to the front signal line 140F via a top via connector VT, and the front signal line 140F is conductively connected to conductive segment 134n via a bottom-to-top via connector VBT.

[0237] Figure 3B Based on some implementation methods Figure 3A The layout diagram of inverter circuit 300 in [the circuit]. Figure 3B The layout diagram in is Figure 1B The layout diagram in [the document] has been modified. This modification includes removing [something] from [the document]. Figure 1B The upper and lower portions of the mating connector pattern VMD will move the top hole connector pattern VT on the front power rail 30F to a new position at the intersection between conductive segment 134p and front power rail 30F, and add a new top hole connector pattern VT at the intersection between conductive segment 132p and front signal line 140F.

[0238] Figure 3C Based on some implementation methods Figure 3A The inverter circuit 300 in the middle is composed of Figure 3B A cross-sectional view in the cutting plane specified by lines P-P' and Q-Q'. Figure 3C The cross section of the cutting plane P-P' in the middle and in Figure 1C The cross-sections of the cutting plane P-P' are almost identical, except in... Figure 1C The top guide hole connector VT connecting the front power rail 30F to the conductive section 132p was replaced with... Figure 3C The front signal line 140F is connected to the top guide hole connector VT of the conductive section 132p. Figure 3C The cross section of the cutting plane Q-Q' in the middle and in Figure 1C The cross-sections of the cutting plane Q-Q' are almost identical, except in... Figure 1C The VMD connector between conductive segments 134p and 134n, which connects multiple conductive segments, was removed, and... Figure 3C The top-mounted connector VT connects the front power rail 30F to the conductive section 134p.

[0239] exist Figure 4A The inverter circuit 400 in the middle is Figure 3AModification of the inverter circuit 300. This modification includes changing the conductive connection from conductive segment 132p to conductive segment 134n. Figure 4A In the circuit, conductive segment 132p is conductively connected to the back-side signal line 140B via a top-to-bottom via-hole connector VTB, and the back-side signal line 140B is conductively connected to conductive segment 134n via a bottom via-hole connector VB. The back-side signal line 140B is configured as the output signal line of the inverter circuit 400.

[0240] Figure 4B Based on some implementation methods Figure 4A Multiple layout diagrams of the inverter circuit 400 in the image. Figure 4B The layout diagram in is Figure 3B Modification of the layout diagram. In Figure 4B In Figure 4B The upper and lower portions of the device are specified by a pair of mating top-to-bottom via connector pattern VTB, which indicates that conductive segment 132p is electrically connected to the back signal line 140B via the top-to-bottom via connector VTB. The bottom via connector pattern VB at the intersection of conductive segment 134n and back signal line 140B indicates that the bottom via connector pattern VB connects conductive segment 134n to back signal line 140B.

[0241] Figure 4C Based on some implementation methods Figure 4A The inverter circuit 400 in Figure 4B A cross-sectional view in the cutting plane specified by lines P-P' and Q-Q'. Figure 4C The cross section of the cutting plane P-P' in the middle and in Figure 3C The cross-sections of the cutting plane P-P' are almost identical, except in... Figure 3C The top-mounted connector VT connecting the front signal line 140F to the conductive segment 132p is replaced with a top-to-bottom-mounted connector VTB connecting the conductive segment 132p to the rear signal line 140B. Figure 4C The cross section of the cutting plane Q-Q' in the middle and in Figure 3C The cross-sections of the cutting plane Q-Q' are almost identical, except in... Figure 4C A bottom-mounted connector VB has been added to connect the conductive segment 134n to the back-side signal line 140B.

[0242] exist Figure 5A The inverter circuit 500 in the middle is Figure 4A Modification of inverter circuit 400 in [the circuit]. Figure 5A In the inverter circuit 500, the front-side signal line 140F is configured as an input signal line, and the front-side signal line 120F is configured as an output signal line. For comparison, in... Figure 4AIn the inverter circuit 400, the front-side signal line 120F is configured as an input signal line, and the back-side signal line 140B is configured as an output signal line. Figure 5A In the middle, the gate conductor 150 is electrically connected to the front signal line 140F through the top gate via connector VG, and the conductive segment 132p is electrically connected to the front signal line 120F through the top via connector VT.

[0243] Figure 5B Based on some implementation methods Figure 5A The layout diagram of inverter circuit 500 in the image. Figure 5B The lower part and Figure 4B The lower part is the same. Figure 5B The upper part is Figure 4B The modifications are to the previous section. The layout pattern covering the gate conductor 150 is... Figure 4B The top gate via connector pattern VG was moved to a new position covering the layout pattern of the front signal line 140F. A top via connector pattern VT was added at the intersection between conductive segment 132p and the front signal line 120F.

[0244] Figure 5C Based on some implementation methods Figure 5A The inverter circuit 500 in the middle is composed of Figure 5B A cross-sectional view in the cutting plane specified by lines P-P' and Q-Q'. Figure 5C The cross section of the cutting plane Q-Q' in the middle and in Figure 4C The cross-sections of the cutting plane Q-Q' are the same. Figure 5C The cross section of the cutting plane P-P' in the middle and in Figure 4C The cross-sections of the cutting plane P-P' are almost identical, except in... Figure 5C A top-mounted connector VT has been added to connect the front signal line 120F to the conductive section 132p.

[0245] Figure 5D Based on some implementation methods Figure 5A The inverter circuit 500 in the middle is composed of Figure 5B A cross-sectional view in the cutting plane specified by line R-R'. Figure 5D The cross-sectional view in the middle is a view of the cross-section in the middle. Figure 1D Modification of the section view in the document. Figure 5D The top gate via connector VG conductively connects the front-side signal line 140F to the gate conductor 150, while... Figure 1D The top gate via connector VG conductively connects the front signal line 120F to the gate conductor 150.

[0246] exist Figure 6AThe inverter circuit 600 in the middle is Figure 5A Modification of inverter circuit 500 in the middle. Figure 6A The inverter circuit 600 uses the back-side signal line 120B as the input signal line, while Figure 5A The inverter circuit 500 uses the front-side signal line 140F as the input signal line. Figure 6A In the middle, the gate conductor 150 is electrically connected to the back-side signal line 120B through the bottom gate via connector VG.

[0247] Figure 6B Based on some implementation methods Figure 6A The layout diagram of inverter circuit 600 in [the circuit]. Figure 6B The layout diagram in is Figure 5B Modification of the layout diagram. In Figure 5B The top gate via connector pattern VG (layout pattern covering the front signal line 140F) in the upper part is replaced with... Figure 6B The bottom gate via connector pattern VG (layout pattern covering the back signal line 120B) in the lower part.

[0248] Figure 6C Based on some implementation methods Figure 6A The inverter circuit 600 in the middle is composed of Figure 6B A cross-sectional view in the cutting plane specified by line R-R'. Figure 6C The cross-sectional view in the middle is a view of the cross-section in the middle. Figure 5D Modification of the section view in the document. Figure 6C In the middle, the gate conductor 150 is electrically connected to the back-side signal line 120B via the bottom gate via connector VG. For comparison, in... Figure 5D In the middle, the gate conductor 150 is electrically connected to the front signal line 140F through the top gate via connector VG.

[0249] exist Figure 1A , Figure 2A , Figure 3A , Figure 4A , Figure 5A ,and Figure 6A The inverter circuits in each inverter circuit include a gate conductor 150, which connects to the gate terminal of the PMOS transistor T1p and the gate terminal of the NMOS transistor T1n. In each inverter circuit, the gate terminals of the PMOS transistor T1p and the NMOS transistor T1n receive the same input logic signal "IN", as shown in... Figure 7A As shown in the diagram. In some configurations of the sub-circuit, the gate terminals of the PMOS transistor T1p and the NMOS transistor T1n receive different input logic signals. For example, in... Figure 7BIn the sub-circuit, when the gate terminals of the PMOS transistor and the NMOS transistor in the complementary field-effect transistor receive different input signals, the gate terminals of the PMOS transistor T1p and the NMOS transistor T1n respectively receive the input logic signal "IN_A" and the input logic signal "IN_B". The gate conductor for the PMOS transistor is separated from the gate conductor for the NMOS transistor via a gate stack insulator.

[0250] Figure 8A It is implemented using complementary field-effect transistors according to some embodiments. Figure 7B The diagram of sub-circuit 800 in [the circuit]. Figure 8A Sub-circuit 800 in the middle is from in Figure 6A The inverter circuit 600 in the middle is modified by replacing the one in the middle with two gate conductors 150p and 150n that are electrically insulated from each other. Figure 6A One of the gate conductors is 150. In... Figure 8A In the PMOS transistor T1p, the gate conductor 150p extending in the Y direction intersects with the p-type active region semiconductor structure 50p in the channel region. The gate conductor 150n extending in the Y direction intersects with the n-type active region semiconductor structure 50n in the channel region of the NMOS transistor T1n. Gate conductors 150p and 150n are separated along the Z direction by a gate stack insulator 815 extending in the Y direction. Gate conductor 150p is conductively connected to the front-side signal line 120F via a top gate via connector VG, and gate conductor 150n is conductively connected to the back-side signal line 120B via a bottom gate via connector VG.

[0251] Figure 8B Based on some implementation methods Figure 8A Multiple layout diagrams of sub-circuit 800 in the circuit. Figure 8B The layout diagram in and in Figure 6B The layout diagrams are almost identical, except for those used in Figure 8B The triangular symbols at each end of the layout pattern of gate conductor 150n indicate that gate conductor pattern 150n is separated from gate conductor 150p via gate stack insulator 815. Various implementations of multiple layout designs are available to indicate the separation of the two stacked gate conductors via gate stack insulator 815. Figure 8BThe layout diagram in the diagram represents one of the specific embodiments, wherein one or more special symbols 885 (e.g., triangle symbols) are placed on at least one of two stacked gate conductor patterns (e.g., a pattern for gate conductor 150p or a pattern for gate conductor 150n). In several alternative embodiments, a comparison between the pattern for gate conductor 150p and the pattern for gate conductor 150n indicates whether gate conductor 150p and gate conductor 150n are separated via gate stack insulator 815. For example, in some embodiments, when the pattern for gate conductor 150p and the pattern for gate conductor 150n are different, the layout diagram indicates that gate conductor 150p and gate conductor 150n are separated via gate stack insulator 815. Conversely, in some embodiments, when the pattern for gate conductor 150p and the pattern for gate conductor 150n are the same, the layout diagram indicates that gate conductor 150p and gate conductor 150n are electrically bonded together.

[0252] Figure 8C Based on some implementation methods Figure 8A Sub-circuit 800 in the middle is composed of Figure 8B A cross-sectional view in the cutting plane specified by line R-R'. Figure 8C In the cross-section of the cut plane R-R', gate conductor 150p and gate conductor 150n are separated by gate stack insulator 815. Gate conductor 150p is conductively connected to the front signal line 120F through the top gate via connector VG, and gate conductor 150n is conductively connected to the back signal line 120B through the bottom gate via connector VG.

[0253] Figure 9A It is a layout diagram of the AOI (AND-OR-INVENTER) logic circuit 900 according to some implementations. Figure 9B Based on some implementation methods Figure 9A The circuit diagram of the AOI logic circuit 900. Figure 9AThe layout diagram includes a top portion and a bottom portion of the layout. The top portion of the layout includes multiple layout patterns for specifying the p-type active region semiconductor structure 50p, multiple gate conductors (gB2, gB1, gA1, and gA2), multiple conductive segments (932p, 934p, 935p, 936p, and 938p), multiple front-side signal lines (920F, 942F, 944F, and 946F), a front-side power rail 30F, and various via connectors. The lower portion of the layout includes multiple layout patterns for specifying an n-type active region semiconductor structure 50n, multiple gate conductors (gB2, gB1, gA1, and gA2), multiple conductive segments (932n, 934n, 935n, 936n, and 938n), multiple back-side signal lines (922B, 924B, 942B, and 944B), a back-side power rail 30B, and various via connectors.

[0254] As by Figure 9A As specified in the upper part, each of the plurality of gate conductors gB2, gB1, gA1, and gA2 intersects with the p-type active region semiconductor structure 50p at the channel region of the PMOS transistor, and correspondingly forms the gate terminals of the plurality of p-type transistors pB2, pB1, pA1, and pA2. As specified by Figure 9A As specified in the lower portion of the diagram, each of the plurality of gate conductors gB2, gB1, gA1, and gA2 intersects with the n-type active region semiconductor structure 50n at the channel region of the NMOS transistor, and correspondingly forms the gate terminals of the plurality of n-type transistors nB2, nB1, nA1, and nA2. Each of the plurality of p-type transistors pB2, pB1, pA1, and pA2 is stacked together with a corresponding one of the plurality of n-type transistors nB2, nB1, nA1, and nA2. Depending on the position of the plurality of transistors in the upper or lower portion of the layout diagram, the plurality of p-type transistors and the plurality of n-type transistors are... Figure 9C The transistors are listed in the diagram. Depending on the position of multiple transistors in the upper or lower part of the layout diagram, in... Figure 9B The circuit diagram also depicts multiple p-type transistors and multiple n-type transistors.

[0255] exist Figure 9A In the layout diagram, according to some embodiments, when the patterns for a pair of stacked gate conductors are identical in the upper and lower portions of the layout diagram, the layout diagram indicates that the plurality of gate conductors in this pair of stacked gate conductors are electrically bonded together. Therefore, as in Figure 9A and Figure 9BAs shown, the gate terminals of transistor pB2 and nB2 are electrically connected together via gate conductor gB2, the gate terminals of transistor pB1 and nB1 are electrically connected together via gate conductor gB1, the gate terminals of transistor pA1 and nA1 are electrically connected together via gate conductor gA1, and the gate terminals of transistor pA2 and nA2 are electrically connected together via gate conductor gA2. Additionally, in Figure 9A and Figure 9B In this configuration, multiple gate conductors gB2 and gB1 are connected to multiple front-side signal lines 942F and 944F via corresponding top gate via connector VG. Multiple gate conductors gA1 and gA2 are connected to multiple back-side signal lines 922B and 924B via corresponding bottom gate via connector VG.

[0256] In addition, such as by Figure 9A The layout diagram specifies and in Figure 9B As shown in the circuit diagram, each of the multiple conductive segments intersects with one of the multiple active region semiconductor structures. Each of the multiple conductive segments 932p, 934p, 935p, 936p, and 938p intersects with the p-type active region semiconductor structure 50p at the terminal region of the p-type transistor. Each of the multiple conductive segments 932n, 934n, 935n, 936n, and 938n intersects with the n-type active region semiconductor structure 50n at the terminal region of the n-type transistor. The terminal region of the transistor (which is either p-type or n-type) is the source region or drain region of the transistor.

[0257] exist Figures 9A to 9B In this configuration, conductive segment 934p is conductively connected to the front power rail 30F via a top via connector VT, and the front power rail 30F is configured to maintain a first supply voltage VDD. Each of the plurality of conductive segments 932n and 938n is conductively connected to the rear power rail 30B via a corresponding bottom via connector VB, and the rear power rail 30B is configured to maintain a second supply voltage VSS. Each of the plurality of conductive segments 932p, 935p, and 938p is conductively connected to the front signal line 920F via a corresponding top via connector VT. Conductive segment 935n is conductively connected to the rear signal line 944B via a corresponding bottom via connector VB. The rear signal line 944B is in turn conductively connected to conductive segment 936p via a corresponding top-to-bottom via connector VTB. Figure 9A In the upper and lower portions, the top to bottom via connectors VTB are specified by a pair of corresponding via connector patterns.

[0258] Figure 10AThis is a layout diagram of a scanning D-type flip-flop (SDF) circuit 1000 according to some embodiments. Figure 10B It is based on some implementation methods Figure 10A The layout diagram in the image specifies the circuit diagram of the scanning D-type flip-flop circuit 1000. Figure 11A Based on some implementation methods Figure 10B The equivalent circuit diagram of the scanning D-type flip-flop circuit. Figure 10B The circuit diagram in the middle is closely tracked in Figure 10A The layout diagram shows the physical locations of various components (e.g., multiple p-type transistors, multiple n-type transistors, multiple front-side signal lines, multiple back-side signal lines, and various via connectors), while... Figure 11A The circuit diagram in will be Figure 10A The multiple transistors in the circuit are grouped into various functional blocks.

[0259] Figure 11B This is a circuit diagram of a scanning D-type flip-flop circuit 1000, represented by multiple functional blocks according to some implementation methods. Figure 11B In the circuit, the scan D-type flip-flop circuit 1000 includes a dual-input multiplier 1110, a master latch 1120, a transfer gate 1130, a slave latch 1140, and an inverter 1150. The dual-input multiplier 1110 receives a data signal D at a first input 1111 and a scan input signal SI at a second input 1112. Each of the dual-input multiplier 1110, the master latch 1120, and the slave latch 1140 is timed by a plurality of clock signals synchronized with a clock signal CP. Depending on the logic level of the selection enable signal SE, either the data signal D or the scan input signal SI is generated at the output 1119 of the dual-input multiplier 1110 as an inverted signal. In some embodiments, when the selection enable signal SE is at a logic high level (HIGH), the inverted data signal is generated at the output 1119, and when the selection enable signal SE is at a logic low level (LOW), the inverted scan input signal SI is generated at the output 1119. The output 1119 of the dual-input multiplier 1110 is connected to the input of the master latch 1120. The transfer gate 1130 is connected between the master latch 1120 and the slave latch 1140. The output of the slave latch 1140 is connected to the input of the inverter 1150. The output of the scan D-type flip-flop circuit 1000 is provided by the output of the inverter 1150.

[0260] exist Figure 10A In this circuit, the various components used to form the scanning D-type flip-flop circuit 1000 are specified by corresponding multiple layout patterns. Figure 10A The layout diagram includes a upper part and a lower part of the layout. (By...) Figure 10AThe plurality of elements specified in the upper portion include a first p-type active region semiconductor structure 52p and a second p-type active region semiconductor structure 54p. Figure 10A The lower portion specifies a plurality of elements including a first n-type active region semiconductor structure 52n and a second n-type active region semiconductor structure 54n. In the context of... Figure 10A In the layout diagram of the scan D-type flip-flop circuit 1000, individual transistors are formed in multiple active region semiconductor structures. According to... Figure 10A The positions of multiple transistors in the layout diagram, in Figure 10C The transistor list includes multiple p-type transistors and multiple n-type transistors in the scanning D-type flip-flop circuit 1000. The multiple transistors in the first p-type active region semiconductor structure 52p include multiple p-type transistors pQB, pSL_a, pSE_0, pSL_bx, pCK_SL, pCKb_TX, pML_ax, and pCP. The multiple transistors in the second p-type active region semiconductor structure 54p include multiple p-type transistors pSI, pSEB, pD, pSE, pCK_MX, pCKb_ML, pML_b, and pCKb_0. The multiple transistors in the first n-type active region semiconductor structure 52n include multiple n-type transistors nQB, nSL_a, nSE_0, nSL_bx, nCKb_SL, nCK_TX, nML_ax, and nCP. The multiple transistors in the second n-type active region semiconductor structure 54n include multiple n-type transistors nSI, nSEB, nD, nSE, nCKb_MX, pCK_ML, nML_b, and nCKb_0.

[0261] exist Figure 10A In the upper portion, each of the plurality of gate conductors gQB, gSL_a, gSE, gSL_bx, gpCKbb, gpCKb, gML_ax, and gCP intersects with the first p-type active region semiconductor structure 52p at the channel region of the PMOS transistor, and correspondingly forms the gate terminal of one of the plurality of p-type transistors pQB, pSL_a, pSE_0, pSL_bx, pCK_SL, pCKb_TX, pML_ax, and pCP. Figure 10AIn the lower portion, each of the plurality of gate conductors gQB, gSL_a, gSE, gSL_bx, gnCKb, gnCKbb, gML_ax, and gCP intersects with the first n-type active region semiconductor structure 52n at the channel region of the NMOS transistor, and correspondingly forms the gate terminal of one of the plurality of n-type transistors nQB, nSL_a, nSE_0, nSL_bx, nCKb_SL, nCK_TX, nML_ax, and nCP. Each of the plurality of p-type transistors pQB, pSL_a, pSE_0, pSL_bx, pCK_SL, pCKb_TX, pML_ax, and pCP is stacked correspondingly with one of the plurality of n-type transistors nQB, nSL_a, nSE_0, nSL_bx, nCKb_SL, nCK_TX, nML_ax, and nCP.

[0262] exist Figure 10A In the upper portion, each of the plurality of gate conductors gSI, gSEB, gD, gSE, gpCKbb, gpCKb, gML_b, and gCKb_0 intersects with the second p-type active region semiconductor structure 54p at the channel region of the PMOS transistor, and correspondingly forms the gate terminal of one of the plurality of p-type transistors pSI, pSEB, pD, pSE, pCK_MX, pCKb_ML, pML_b, and pCKb_0. Figure 10A In the lower portion, each of the plurality of gate conductors gSI, gSEB, gD, gSE, gnCKb, gnCKbb, gML_b, and gCKb_0 intersects with the second n-type active region semiconductor structure 54n at the channel region of the NMOS transistor, and correspondingly forms the gate terminal of one of the plurality of n-type transistors nSI, nSEB, nD, nSE, nCKb_MX, nCK_ML, nML_b, and nCKb_0. Each of the plurality of p-type transistors pSI, pSEB, pD, pSE, pCK_MX, pCKb_ML, pML_b, and pCKb_0 is stacked correspondingly to one of the plurality of n-type transistors nSI, nSEB, nD, nSE, nCKb_MX, nCK_ML, nML_b, and nCKb_0.

[0263] In the Figure 10AIn the layout diagram of the scanned D-type flip-flop circuit 1000, in addition to the PMOS and NMOS in the four pairs of stacked transistors associated with multiple gate conductors gpCKbb, gnCKb, gpCKb, and gnCKbb, the gate terminals of the PMOS and NMOS in each pair of stacked transistors are electrically connected through a common gate conductor shared by the PMOS and NMOS. A special symbol 885 (e.g., a triangle symbol) at the end of the layout pattern for the gate conductor gnCKb indicates that the stacked multiple gate conductors gpCKbb and gnCKb are separated by a gate stack insulator. A special symbol 885 (e.g., a triangle symbol) at the end of the layout pattern for the gate conductor gnCKbb indicates that the stacked multiple gate conductors gpCKb and gnCKbb are separated by a gate stack insulator. The gate terminals of the following four pairs of stacked transistors are not directly connected due to the gate stack insulator: the first pair of stacked transistors pCK_SL and nCKb_SL, the second pair of stacked transistors pCKb_TX and nCK_TX, the third pair of stacked transistors pCK_MX and nCKb_MX, and the fourth pair of stacked transistors pCKb_ML and nCK_ML. In several alternative embodiments, the separation of the stacked gate conductors gpCKbb and gnCKb by the gate stack insulator is specified using multiple distinguishable layout patterns for the stacked gate conductors gpCKbb and gnCKbb.

[0264] In addition, Figure 10AThe layout diagram also includes multiple dummy gate stripe patterns 110 within the cells of the scanned D-type flip-flop cells and at the edges of the scanned D-type flip-flop cells. Multiple isolation regions in the p-type active region semiconductor structure are designated at the intersections between the dummy gate stripe patterns 110 and the layout patterns of the p-type active region semiconductor structures (52p and 54p). Multiple isolation regions in the n-type active region semiconductor structure are designated at the intersections between the dummy gate stripe patterns 110 and the layout patterns of the n-type active region semiconductor structures (52n and 54n). The multiple isolation regions at the multiple edges of the scanned D-type flip-flop cells electrically isolate the multiple active regions in the scanned D-type flip-flop cells from the multiple active regions in adjacent cells. Within the scanned D-type flip-flop unit, a virtual gate stripe pattern 110 intersecting with the p-type active region semiconductor structure 52p defines an isolation region between p-type transistors pSL_a and pSE_0, and a virtual gate stripe pattern 110 intersecting with the p-type active region semiconductor structure 54p defines an isolation region between p-type transistors pSE and pCK_MX. Within the scanned D-type flip-flop unit, a virtual gate stripe pattern 110 intersecting with the n-type active region semiconductor structure 52n defines an isolation region between n-type transistors nSL_a and nSE_0, and a virtual gate stripe pattern 110 intersecting with the n-type active region semiconductor structure 54n defines an isolation region between n-type transistors nSE and nCKb_MX. Each of the multiple isolation regions in the multiple active region semiconductor structures (52p, 54p, 52n, or 54n) is... Figure 10C The transistor is identified as CPODE in the transistor list. Figure 10C The inclusion of CPODE in the transistor list indicates that Continuous Polysilicon on Oxide-Defined Edge (CPODE) technology is a possible technique for constructing multiple isolation regions within multiple active region semiconductor structures (52p, 54p, 52n, or 54n). Other suitable techniques, such as Polysilicon on Oxide-Defined Edge (PODE) technology, are also within the scope of this disclosure.

[0265] exist Figure 10AIn the upper portion, each of the plurality of conductive segments C31p-C39p and C30p intersects with the first p-type active region semiconductor structure 52p at the terminal region of at least one of the plurality of p-type transistors pQB, pSL_a, pSE_0, pSL_bx, pCK_SL, pCKb_TX, pML_ax, and pCP. Each of the plurality of conductive segments C71p-C79p and C70p intersects with the second p-type active region semiconductor structure 54p at the terminal region of at least one of the plurality of p-type transistors pSI, pSEB, pD, pSE, pCK_MX, pCKb_ML, pML_b, and pCKb_0. In addition to the plurality of gate conductors and the plurality of conductive segments intersecting with the plurality of p-type active region semiconductor structures (52p and 54p), as in Figure 10A As specified in the upper part, the scan D-type flip-flop circuit 1000 also includes multiple front-side signal lines (F22, F24, F26, F28, F42, F44, F62, F64, F66, F68, F82, F84, and F86) and multiple front-side power rails (32F and 34F).

[0266] exist Figure 10A In the lower portion, each of the plurality of conductive segments C31n-C39n and C30n intersects with the first n-type active region semiconductor structure 52n at the terminal region of at least one of the plurality of n-type transistors nQB, nSL_a, nSE_0, nSL_bx, nCKb_SL, nCK_TX, nML_ax, and nCP. Each of the plurality of conductive segments C71n-C79n and C70n intersects with the second n-type active region semiconductor structure 54n at the terminal region of at least one of the plurality of n-type transistors nSI, nSEB, nD, nSE, nCKb_MX, nCK_ML, nML_b, and nCKb_0. In addition to the plurality of gate conductors and the plurality of conductive segments intersecting with the plurality of n-type active region semiconductor structures (52n and 54n), as Figure 10A As shown in the lower part, the scanning D-type flip-flop circuit 1000 also includes multiple back-side signal lines (B22, B24, B26, B42, B44, B46, B62, B64, B66, B82, B84, and B86) and multiple back-side power rails (32B and 34B).

[0267] exist Figure 10A Layout diagram and Figures 11A to 11BThe circuit diagrams depict the conductive connections between various components of the scanning D-type flip-flop circuit 1000. Each of the multiple conductive segments C32p, C35p, and C39p is connected to the first front power rail 32F via a corresponding top-mounted connector VT. Each of the multiple conductive segments C71p, C75p, and C79p is connected to the second front power rail 34F via a corresponding top-mounted connector VT. Each of the multiple conductive segments C32n, C35n, and C39n is connected to the first rear power rail 32B via a corresponding bottom-mounted connector VB. Each of the multiple conductive segments C72n and C79n is connected to the second rear power rail 34B via a corresponding bottom-mounted connector VB.

[0268] exist Figure 10A In this configuration, multiple stacked conductive segments C31p and C31n are conductively connected via corresponding inter-segment connectors (VMD), forming signal output node oQB. Multiple stacked conductive segments C33p and C33n are conductively connected via corresponding inter-segment connectors (VMD), forming signal output node oSL_a. Multiple stacked conductive segments C34p and C34n are conductively connected via corresponding inter-segment connectors (VMD), forming signal output node oSE_0. Multiple stacked conductive segments C37p and C37n are conductively connected via corresponding inter-segment connectors (VMD), forming signal output node oCK_SL. Multiple stacked conductive segments C77p and C77n are conductively connected via corresponding inter-segment connectors (VMD), forming signal output nodes oCK_MX and oCK_ML. Multiple stacked conductive segments C38p and C38n are conductively connected via corresponding inter-segment connectors (VMD), forming signal output node oML_ax. Multiple stacked conductive segments C30p and C30n are conductively connected via corresponding inter-segment connectors VMD, forming a signal output node oCP. Multiple stacked conductive segments C70p and C70n are conductively connected via corresponding inter-segment connectors VMD, forming a signal output node oCKb_0. Figure 10A The layout diagram also includes multiple signal output nodes (oQB, oSL_a, oSE_0, oCK_SL, oCK_MX, oCK_ML, oML_ax, oCP, and oCKb_0). Figure 10B and Figure 11A They are identified and marked in the circuit diagram.

[0269] Depend on Figure 10AThe layout diagram specifies multiple elements, including various via connectors. When the top gate via connector VG is placed at the intersection of the front signal line and the gate conductor, it specifies that the front signal line is directly connected to the gate conductor. When the via connector VT is placed at the intersection of the front signal line and the conductive segment, it specifies that the front signal line is directly connected to the conductive segment. When the bottom gate via connector VG is placed at the intersection of the back signal line and the gate conductor, it specifies that the back signal line is directly connected to the gate conductor. When the via connector VB is placed at the intersection of the back signal line and the conductive segment, it specifies that the back signal line is directly connected to the conductive segment.

[0270] exist Figures 10A to 10B In the diagram, front-side signal line F42 is directly connected to multiple gate conductors gQB and gSL_bx, and directly to conductive segment C33p. Front-side signal line F64 is directly connected to each of multiple conductive segments C73p and C76p. To transmit the inverted clock signal ckb from signal output node oCP to gate conductor gpCKb, front-side signal line F44 is directly connected to gate conductor gpCKb and conductive segment C30p. To transmit the clock signal ckbb from signal output node oCKb_0 to gate conductor gpCKbb, front-side signal line F86 is directly connected to gate conductor gpCKbb and conductive segment C70p. To connect signal output node oSE_0 to gate conductor gSEB, front-side signal line F22 is directly connected to conductive segment C34p, and front-side signal line F82 is directly connected to gate conductor gSEB. Multiple front-side signal lines F22 and F82 are conductively connected together via conductive wiring line M1_1 extending in the Y direction. To connect multiple signal output nodes oCK_MX and oCK_ML to the gate conductor gML_ax, front-side signal line F26 is directly connected to the gate conductor gML_ax, and front-side signal line F66 is directly connected to the conductive segment C77p. The multiple front-side signal lines F26 and F66 are conductively connected together through a conductive wiring line M1_2 extending in the Y direction.

[0271] In the Figure 10A In the integrated circuit device specified in the layout diagram, multiple conductive traces M1_1 and M1_2 are multiple traces in a conductive layer (e.g., layer M1), which is separated from the front conductive layer via an insulating layer. Each of multiple front signal lines F22 and F82 is directly connected to conductive trace M1_1 via a corresponding via connector VIIA0 passing through the insulating layer. Each of multiple front signal lines F26 and F66 is directly connected to conductive trace M1_2 via a corresponding via connector VIIA0 passing through the insulating layer. Figure 10A In the layout diagram, although the via connector VIIA0 is represented by the corresponding layout pattern, multiple conductive wiring lines M1_1 and M1_2 are represented only by "bar" lines to improve the readability of the layout diagram. Figure 10A In several alternative implementations of the layout diagram, in addition to the via connector VIIA0, each of the multiple conductive wiring lines M1_1 and M1_2 is also represented by a corresponding layout pattern, which specifies not only the location of the represented conductive wiring line, but also its geometry (e.g., width and length).

[0272] exist Figures 10A to 10B In the diagram, back-side signal line B24 is directly connected to the gate conductor gSL_a and conductive segment C37n. Back-side signal line B64 is directly connected to multiple conductive segments C74n and C76n. Back-side signal line B82 is directly connected to multiple conductive segments C71n and C75n. To transmit the inverted clock signal ckb from the signal output node oCP to the gate conductor gnCKb, back-side signal line B46 is directly connected to the gate conductor gnCKb and conductive segment C30n. To transmit the clock signal ckbb from the signal output node oCKb_0 to the gate conductor gnCKbb, back-side signal line B66 is directly connected to the gate conductor gnCKbb and conductive segment C70n. To connect the signal output node oML_ax to the gate conductor gML_b, back-side signal line B26 is directly connected to conductive segment C38n, and back-side signal line B84 is directly connected to the gate conductor gML_b. Multiple back-side signal lines B26 and B84 are conductively connected together via conductive wiring line N1_1 extending in the Y direction. To connect the signal output node oCP to the gate conductor gCKb_0, back-side signal line B86 is directly connected to the gate conductor gCKb_0, and back-side signal line B86 is conductively connected to back-side signal line B46 via conductive wiring line N1_2 extending in the Y direction.

[0273] In the Figure 10A In the integrated circuit device specified in the layout diagram, multiple conductive traces N1_1 and N1_2 are multiple traces in another back-side conductive layer, which is separated from the original back-side conductive layer by an insulating material. Each of the multiple back-side signal lines B26 and B84 is directly connected to conductive trace N1_1 through a corresponding back-side via connector VIA0 passing through the insulating material. Each of the multiple back-side signal lines B46 and B86 is directly connected to conductive trace N1_2 through a corresponding back-side via connector VIA0 passing through the insulating material. Figure 10AIn the layout diagram, although the back-side via connector VIA0 is represented by the corresponding layout pattern, multiple conductive wiring lines N1_1 and N1_2 are represented only by "bar" lines to improve the readability of the layout diagram. Figure 10A In several alternative implementations of the layout diagram, in addition to the back-side via connector VIA0, each of the multiple conductive wiring lines N1_1 and N1_2 is also represented by a corresponding layout pattern, which specifies not only the location of the represented conductive wiring line, but also its geometry (e.g., width and length).

[0274] In addition, Figures 10A to 10B In this circuit, front-side signal line F62 is directly connected to the gate conductor gSI and functions as an input signal line for scanning the input signal "SI". Front-side signal line F84 is directly connected to the gate conductor gD and functions as an input signal line for scanning the input data "D" of the D-type flip-flop circuit 1000. Front-side signal line F28 is directly connected to the gate conductor gCP and functions as an input signal line for the clock signal "CP". Back-side signal line B44 is directly connected to the gate conductor gSE and functions as an input signal line for scanning the enable signal "SE". Back-side signal line B22 is directly connected to the conductive segment C31n and functions as an output signal line for scanning the output data "Q" of the D-type flip-flop circuit 1000.

[0275] exist Figure 10B Closely track the circuit diagrams in Figure 10A The physical locations of various components (e.g., multiple transistors, multiple wiring traces, and multiple via connectors) in the layout diagram, while Figure 11A The circuit diagram in will be Figure 10B The multiple transistors in the circuit are grouped into various functional blocks.

[0276] exist Figure 11A and Figure 10B In this circuit, five p-type transistors (pSI, pSEB, pSE, pD, and pCK_MX) and five n-type transistors (nSI, nSE, nSEB, nD, and nCK_MX) are used to form a two-input multiplier 1110 (as in...). Figure 11B(As shown in the diagram). P-type transistor pML_ax and n-type transistor nML_ax form an inverter 1122 in the master latch 1120. Two p-type transistors (pML_b and pCKb_ML) and two n-type transistors (nML_b and nCK_ML) form a clocked inverter 1124 in the master latch 1120. P-type transistor pCKb_TX and n-type transistor nCK_TX form a transfer gate 1130. P-type transistor pSL_a and n-type transistor nSL_a form an inverter 1142 in the slave latch 1140. Two p-type transistors (pSL_bx and pCK_SL) and two n-type transistors (nSL_bx and nCKb_SL) form a clocked inverter 1144 in the slave latch 1140. P-type transistor pQB and n-type transistor nQB form an inverter 1150.

[0277] exist Figure 11A and Figure 10B In this circuit, p-type transistor pSE_0 and n-type transistor nSE_0 form inverter 1170 to generate an inverted selection enable signal SEB from the selection enable signal SE. The selection enable signal SE is coupled to the gate terminals of the p-type transistor pSE and the n-type transistor nSE. P-type transistor pCP and n-type transistor nCP form inverter 1180 to generate an inverted clock signal ckb from the clock signal CP. P-type transistor pCKb_0 and n-type transistor nCKb_0 form inverter 1190 to generate a clock signal ckbb from the inverted clock signal CKb. The inverted clock signal ckb is coupled to the gate terminals of multiple p-type transistors pCKb_TX and pCKb_ML, and multiple n-type transistors nCKb_SL and nCKb_MX. The clock signal ckbb is coupled to the gate terminals of multiple p-type transistors pCK_SL and pCK_MX, and multiple n-type transistors nCK_TX and nCK_ML.

[0278] As described in this disclosure, various integrated circuit devices (e.g., 100-600 and 800-1000) have improved power connections from the source terminals of PMOS and NMOS transistors to their corresponding supply voltages compared to some alternative solutions in other implementations of power rails. Typically, it is possible to connect the source terminals of the PMOS and NMOS transistors to their corresponding supply voltages with reduced source resistance when a first supply voltage VDD is provided by a front-side power rail 30F in the front conductive layer and a second supply voltage VSS is provided by a back-side power rail 30B in the back conductive layer. Specifically, when the first supply voltage VDD is provided by the front-side power rail 30F, the source terminals of the PMOS transistors are connected to the first supply voltage VDD via a top via connector VT, connecting the source conductive segment of the PMOS transistor to the front-side power rail 30F. When the second supply voltage VSS is provided by the back-side power rail 30B, the source terminal of the NMOS transistor is connected to the back-side power rail 30B via the bottom via connector VB, and the source terminal of the NMOS transistor is connected to the second supply voltage VSS.

[0279] In contrast, in some alternative embodiments, if both the first supply voltage VDD and the second supply voltage VSS are provided in the back conductive layer, the source conductive segment of the PMOS transistor needs to be connected to the power rail for VDD via a top-to-bottom via connector VTB. Because the resistance of the top-to-bottom via connector VTB is greater than that of the top via connector VT (primarily due to the length difference), the connection from the source terminal of the PMOS transistor to the power rail in the back conductive layer (as in the alternative embodiments) has a greater resistivity than the connection from the source terminal of the PMOS transistor to the front power rail 30F (as described in this disclosure). Similarly, in some alternative embodiments, if both the first supply voltage VDD and the second supply voltage VSS are provided in the front conductive layer, the source conductive segment of the NMOS transistor needs to be connected to the power rail for VSS via a bottom-to-top via connector VBT. Because the resistance of the bottom-to-top via connector VBT is greater than that of the bottom via connector VB (primarily due to the length difference), the connection from the source terminal of the NMOS transistor to the power rail in the front conductive layer (as in several alternative embodiments) has a greater resistivity than the connection from the source terminal of the NMOS transistor to the back power rail 30B (as described in this disclosure).

[0280] In addition to improving the power connection for both PMOS and NMOS transistors, when multiple integrated circuit cells are located in a row (extending in the Y direction), the front power rail also provides inter-cell signal shielding for the front signal lines, and the back power rail also provides inter-cell signal shielding for the back signal lines. Figure 12A and Figure 12B According to some embodiments, this corresponds to the upper and lower portions of the layout diagram of the multi-cell circuit 1200. The multi-cell circuit 1200 includes at least three integrated circuit cells (e.g., Cell A, Cell B, and Cell C)) which are adjacent to each other in a row extending in the Y direction. Cell A and Cell B share a common cell boundary 1290AB, and Cell B and Cell C share a common cell boundary 1290BC. Each of Cell A, Cell B, and Cell C includes a p-type active region semiconductor structure, corresponding to 50p(1), 50p(2), and 50p(3), as shown in Figure 12A As shown in the figure. Each of units A, B, and C includes an n-type active region semiconductor structure, corresponding to 50n(1), 50n(2), and 50n(3), as shown in Figure 12B As shown in the image.

[0281] exist Figures 12A to 12B In the multi-cell circuit 1200, each of the multiple integrated circuit cells is associated with a corresponding front-side power rail to provide a first power supply VDD. For example, each of cells A, B, and C is associated with one of the front-side power rails 30F(1), 30F(2), and 30F(3). Each of the multiple integrated circuit cells in the multi-cell circuit 1200 is associated with a corresponding rear-side power rail to provide a second power supply VSS. For example, each of cells A, B, and C is associated with one of the multiple rear-side power rails 30B(1), 30B(2), and 30B(3).

[0282] When each of the multiple front power rails is maintained at a constant power supply voltage VDD, each of the multiple front power rails 30F(1), 30F(2), and 30F(3) is effectively “signal grounded”. Therefore, each of the multiple front power rails reduces stray capacitive coupling between multiple front signal lines in adjacent integrated circuit cells. For example, stray capacitive coupling between front signal lines 120F(1) / 140F(1) in cell A and front signal lines 120F(2) / 140F(2) in cell B is reduced via front power rail 30F(2). Stray capacitive coupling between front signal lines 120F(2) / 140F(2) in cell B and front signal lines 120F(3) / 140F(3) in cell C is reduced via front power rail 30F(3). Similarly, when each of the multiple back-side power rails is maintained at a constant power supply voltage VSS, each of the multiple back-side power rails 30B(1), 30B(2), and 30B(3) is effectively “signal grounded.” Therefore, each of the multiple back-side power rails reduces stray capacitive coupling between multiple back-side signal lines in adjacent integrated circuit cells. For example, stray capacitive coupling between back-side signal lines 120B(1) / 140B(1) in cell A and back-side signal lines 120B(2) / 140B(2) in cell B is reduced via back-side power rail 30B(2). Stray capacitive coupling between back-side signal lines 120B(2) / 140B(2) in cell B and back-side signal lines 120B(3) / 140B(3) in cell C is reduced via back-side power rail 30B(3).

[0283] In the various integrated circuit devices (e.g., 100-600, 800-1000, and 1200) described in this disclosure, each integrated circuit cell is powered by a front-side power rail and a rear-side power rail, and each integrated circuit cell also provides both front-side signal lines and rear-side signal lines for signal routing. In the various integrated circuit devices (e.g., 100-600, 800-1000, and 1200, as described in this disclosure), the maximum permissible width (along the Y direction) of the multiple active region semiconductor structures is greater than the maximum permissible width in some alternative implementations of the signal lines and power rails.

[0284] For example, in each embodiment of inverters 100-600, it is possible for the width of the p-type active region semiconductor structure 50p to extend beyond the edge of the front-side signal line 120F along the negative Y direction, and for the width of the n-type active region semiconductor structure 50n to extend beyond the edge of the back-side signal line 120B along the negative Y direction, at least because both the front-side signal line 120F and the back-side signal line 120B are feasible in their stacked configurations. Specifically, the width of the p-type active region semiconductor structure 50p is not limited by any bottom-to-top via connectors VBTs used to connect the source / drain terminals of the NMOS to the front-side signal line 120F. The width of the n-type active region semiconductor structure 50n is not limited by any top-to-bottom via connectors VTBs used to connect the source / drain terminals of the PMOS to the back-side signal line 120B.

[0285] In Figure 12A In the embodiment of Unit B, it is possible to extend the width of the p-type active region semiconductor structure 50p(2) to such a degree that the two edges of the front signal line 120F(2) are parallel between the first edge 1251p and the second edge 1259p of the p-type active region semiconductor structure 50p(2). In fact, the width of the p-type active region semiconductor structure 50p(2) is extended until the first edge 1251p of the active region semiconductor structure 50p(2) reaches the edge VBT_e1 of the bottom-to-top via connector VBT. The bottom-to-top via connector VBT in Unit B connects the front signal line 140F(2) and the conductive segment intersecting with the n-type active region semiconductor structure 50n(2) (e.g., in Figure 12B The 136n in the middle is electrically connected.

[0286] In Figure 12B In the embodiment of Unit B, it is possible to extend the width of the n-type active region semiconductor structure 50n(2) to such that the two edges of the front signal line 120B(2) are parallel between the first edge 1251n and the second edge 1259n of the n-type active region semiconductor structure 50n(2). In fact, the width of the n-type active region semiconductor structure 50n(2) is extended until the first edge 1251n of the active region semiconductor structure 50n(2) reaches the edge VBT_e1 of the top-to-bottom via connector VTB. The top-to-bottom via connector VTB in Unit B connects the front signal line 140B(2) and the conductive segment intersecting with the p-type active region semiconductor structure 50p(2) (e.g., in Figure 12A The 138p in the middle is electrically connected.

[0287] Furthermore, in each embodiment of inverters 100-600, there is no via connector VBT for connecting the source terminals of the NMOS to the bottom-to-top power rails in the front conductive layer. Therefore, if the width extension of the active region semiconductor structure 50p along the positive Y direction is not limited by other factors (e.g., design rules related to adjacent cells), it is possible for the width of the active region semiconductor structure 50p to extend beyond the edge of the power rails in the front conductive layer. Similarly, in each embodiment of inverters 100-600, there is no via connector VTB for connecting the source terminals of the PMOS to the top-to-bottom power rails in the back conductive layer. Therefore, if the width extension of the active region semiconductor structure 50p along the positive Y direction is not limited by other factors (e.g., design rules related to adjacent cells), it is possible for the width of the active region semiconductor structure 50n to extend beyond the edge of the power rails in the back conductive layer.

[0288] In Figures 12A to 12B In the example of unit B, since there is no bottom-to-top via connector VBT below the front power rail 30F(2), it is possible to extend the width of the p-type active region semiconductor structure 50p(2) to such that the two edges of the front power rail 30F(2) are parallel between the first edge 1251p and the second edge 1259p of the p-type active region semiconductor structure 50p(2). Similarly, since there is no top-to-bottom via connector VTB located above the back power rail 30B(2), it is possible to extend the width of the n-type active region semiconductor structure 50n(2) to such that the two edges of the back power rail 30B(2) are parallel between the first edge 1251n and the second edge 1259n of the n-type active region semiconductor structure 50n(2).

[0289] In some alternative embodiments, even when two or more front signal lines (not shown in the figure) are implemented between the front power rail 30F(2) and the front signal line 140F(2), the bottom-to-top via connector VBT in cell B is still implemented only for the front signal line 140F(2) to conductively connect the front signal line 140F(2) to the conductive segment intersecting the n-type active region semiconductor structure 50n(2) (e.g., in Figure 12B 136n in the example). In several alternative embodiments, no bottom-to-top via connector VBT is implemented for the other two or more front-side signal lines between the front-side power rail 30F(2) and the front-side signal line 140F(2), nor is a bottom-to-top via connector VBT implemented to conductively connect the other two or more front-side signal lines and the conductive segment intersecting with the n-type active region semiconductor structure 50n(2) (e.g., in the example). Figure 12B In other words, in several alternative implementations, the distance between each bottom-to-top via connector VBT and the cell boundary 1290BC is minimized to maximize the width of the p-type active region semiconductor structure 50p(2), and the bottom-to-top via connector VBT is implemented only for front-side signal lines, such as 140F(2), adjacent to the cell boundary extending in the X direction.

[0290] In some alternative embodiments, even when two or more back-side signal lines (not shown in the figures) are implemented between the back-side power rail 30B(2) and the back-side signal line 140B(2), the top-to-bottom via connector VTB in cell B is still implemented only for the back-side signal line 140B(2) to conductively connect the back-side signal line 140B(2) and the conductive segment intersecting with the p-type active region semiconductor structure 50p(2) (e.g., in Figure 12A 136p in the middle). In several alternative embodiments, no top-to-bottom via connectors VTB are implemented for the other two or more back-side signal lines between the back-side power rail 30B(2) and the back-side signal line 140B(2), and no top-to-bottom via connectors VTB are implemented to conductively connect the other two or more back-side signal lines and the conductive segments intersecting with the n-type active region semiconductor structure 50n(2) (e.g., in Figure 12A (136p in the example). That is, in several alternative implementations, the distance between each top-to-bottom via connector VTB and the cell boundary 1290BC is minimized to maximize the width of the n-type active region semiconductor structure 50n(2), and the top-to-bottom via connector VTB is implemented only for back-side signal lines, such as 140B(2), adjacent to the cell boundary extending in the X direction.

[0291] Figure 13 This is a layout diagram of circuit cells with multiple markings according to some implementation methods. Figure 13 The upper section marks several dimensions for the front power rail, front signal lines, and top guide hole connector. Figure 13 The lower section indicates the dimensions of the rear power rail, rear signal lines, and bottom via connector. Figure 13 The upper and lower sections both indicate multiple sizes of the bottom-to-top and top-to-bottom guide hole connectors.

[0292] exist Figure 13In the upper portion, the width Wa of the front-side signal line 120F is in the range of 1.0 to 1.5 times the minimum metal width in the wafer. The width Wb of the front-side power rail 30F is in the range of 0.8 to 5.0 times the width Wa. The width Wc of the front-side signal line 140F is in the range of 0.8 to 1.5 times the width Wa. The width We of the front-side signal line 160F is in the range of 0.8 to 2.0 times the width Wa. In some embodiments, the lower limit of the width Wa is typically determined by the photolithography capability at the technology node of interest. In some embodiments, the upper limit of the width Wa is typically determined by the number of routing lines required. In some embodiments, increasing the width Wa reduces the number of routing lines available per cell, which increases the cell area.

[0293] exist Figure 13 In the upper part, top via connector VT1 connects the front power rail 30F to the conductive section, top via connector VT2 connects the front signal line 120F to the conductive section, and top via connector VT3 connects the front signal line 160F to the conductive section. The width "(a)" of top via connector VT2 is in the range of 1.0 to 1.5 times the minimum via width in the wafer, and the length "(b)" of top via connector VT2 is in the range of 1.0 to 1.5 times the minimum via length in the wafer. The width "(c)" of top via connector VT1 is in the range of 0.8 to 2.0 times the width "(a)", and the length "(d)" of top via connector VT1 is in the range of 0.8 to 5.0 times the length "(b)". The width “(I)” of the top guide hole connector VT3 is in the range of 0.8 to 2.0 times the width “(a)”, and the length “(j)” of the top guide hole connector VT3 is in the range of 0.8 to 2.0 times the length “(b)”.

[0294] exist Figure 13 In the upper part, the bottom-to-top via connector VBT connects the front-side signal line 140F to the conductive segment for the transistors at the bottom of the complementary field-effect transistor stack, while the top-to-bottom via connector VTB connects the conductive segment for the transistors at the top of the complementary field-effect transistor stack to the back-side signal line 140B (as in...). Figure 13 (As shown in the lower part).

[0295] The upper end of the bottom-to-top via connector VBT contacts the front signal line 140F. The upper end of the top-to-bottom via connector VTB contacts the conductive segment. The width (e) of the bottom-to-top via connector VBT at the upper end is in the range of 0.8 to 1.5 times the width (a), and the length (g) of the bottom-to-top via connector VBT at the upper end is in the range of 0.8 to 1.5 times the length (b). The width (f) of the top-to-bottom via connector VTB at the upper end is in the range of 0.8 to 1.5 times the width (a), and the length (h) of the top-to-bottom via connector VTB at the upper end is in the range of 0.8 to 1.5 times the length (b).

[0296] In some implementations, the lower limits of width "(a)" and length "(b)" are typically determined by reliability requirements and voltage drop (IR drop) requirements at the technology node of interest. If width "(a)" or length "(b)" becomes too small, the via failure rate increases during manufacturing because some vias used to accommodate the top via connector may not be fully open. Furthermore, if width "(a)" or length "(b)" becomes too small, the voltage drop (IR drops) of the top via connector increases, which can affect the reliability and performance of the manufactured integrated circuit. In some implementations, if width "(a)" or length "(b)" becomes too large, the number of available via connectors or available wiring per cell decreases, increasing the cell area.

[0297] exist Figure 13 In the lower portion, the width Wa' of the back-side signal line 120B is in the range of 1.0 to 1.5 times the minimum metal width in the wafer. The width Wb' of the back-side power rail 30B is in the range of 0.8 to 5.0 times the width Wa'. The width Wc' of the back-side signal line 140B is in the range of 0.8 to 1.5 times the width Wa'. The width We' of the back-side signal line 160B is in the range of 0.8 to 2.0 times the width Wa'. In some embodiments, the lower limit of the width Wa' is determined by the photolithography capability at the technology node of interest. In some embodiments, the upper limit of the width Wa' is determined by the number of routing lines required. In some embodiments, increasing the width Wa' reduces the number of available routing lines for each cell, which increases the cell area.

[0298] exist Figure 13In the lower portion, bottom via connector VB1 connects the back-side power rail 30B to the conductive section, bottom via connector VB2 connects the back-side signal line 120B to the conductive section, and bottom via connector VB3 connects the back-side signal line 160B to the conductive section. The width "(a')" of bottom via connector VB2 is in the range of 1.0 to 1.5 times the minimum via width in the wafer, and the length "(b')" of bottom via connector VB2 is in the range of 1.0 to 1.5 times the minimum via length in the wafer. The width "(c')" of bottom via connector VB1 is in the range of 0.8 to 2.0 times the width "(a')", and the length "(d')" of bottom via connector VB1 is in the range of 0.8 to 5.0 times the length "(b')". The width “(I')” of the bottom guide hole connector VB3 is in the range of 0.8 to 2.0 times the width “(a')”, and the length “(j')” of the bottom guide hole connector VB3 is in the range of 0.8 to 2.0 times the length “(b')”.

[0299] exist Figure 13 In the lower portion, the lower end of the bottom-to-top via connector VBT contacts the conductive segment, and the lower end of the top-to-bottom via connector VTB contacts the back signal line 140B. The width "(e')" of the bottom-to-top via connector VBT at the lower end is in the range of 0.8 to 1.5 times the width "(a')", and the length "(g')" of the bottom-to-top via connector VBT at the lower end is in the range of 0.8 to 1.5 times the length "(b')". The width "(f')" of the top-to-bottom via connector VTB at the lower end is in the range of 0.8 to 1.5 times the width "(a')", and the length "(h')" of the top-to-bottom via connector VTB at the lower end is in the range of 0.8 to 1.5 times the length "(b')".

[0300] In some implementations, the lower limits of the width "(a')" and length "(b')" are determined by the reliability requirements and voltage drop (IR drop) requirements at the technology node of interest. If the width "(a')" or length "(b')" becomes too small, the via failure rate increases during manufacturing because some vias used to accommodate the top via connector may not be fully open. Furthermore, in some implementations, if the width "(a')" or length "(b')" becomes too small, the voltage drop of the top via connector increases, which affects the reliability and performance of the manufactured integrated circuit. In some implementations, if the width "(a')" or length "(b')" becomes too large, the number of available via connectors or available wiring per cell decreases, which increases the cell area.

[0301] Figure 14 This is a flowchart of a method 1400 for generating an integrated circuit (IC) layout diagram according to some implementation methods. It should be understood that... Figure 14 Additional operations are performed before, during, and / or after the method 1400 shown, and some other processes may be briefly described herein. In some embodiments, method 1400 may be used to produce one or more layout designs, for example in Figure 10A or Figures 12A to 12B The layout design in the text. In some implementations, method 1400 can be used to form a layout with a design based on... Figure 10A ,or Figures 12A to 12B Integrated circuits with similar structural relationships of one or more semiconductor structures formed by layout design in the process. In some embodiments, method 1400 is performed by a processing device (e.g., in...). Figure 16 The processor 1602 in the process is configured to execute instructions for generating one or more layout designs, such as in Figure 10A ,or Figures 12A to 12B Multiple layout designs within.

[0302] In operation 1402 of method 1400, an array of multiple front-side power rail patterns is generated. Each of the multiple front-side power rail patterns specifies a front-side power rail in the front-side conductive layer. Figures 12A to 12B In the implementation layout design, the front power rail pattern of this array includes multiple layout patterns for multiple front power rails 30F(1), 30F(2), and 34F(3). After operation 1402, the process proceeds to operation 1404.

[0303] In operation 1404 of method 1400, an array of multiple first-type active region patterns is generated. The first-type active region patterns are positioned parallel to the front power rail pattern. Each of the multiple first-type active region patterns specifies a first-type active region semiconductor structure. Figures 12A to 12B In the embodiment layout design, the first type of active region pattern of this array includes multiple layout patterns for multiple p-type active region semiconductor structures 50p(1), 50p(2), and 50p(3). The multiple layout patterns for the multiple p-type active region semiconductor structures 50p(1), 50p(2), and 50p(3) are arranged in parallel between multiple layout patterns for multiple front-side power rails 30F(1), 30F(2), and 34F(3). After operation 1404, the process proceeds to operation 1406.

[0304] In operation 1406 of method 1400, an array of multiple back-side power rail patterns is generated. Each back-side power rail pattern specifies a back-side power rail in the back-side conductive layer. Figures 12A to 12B In the layout design of the various embodiments, the multiple back-side power rail patterns of this array include multiple layout patterns for multiple back-side power rails 30B(1), 30B(2), and 34B(3). After operation 1406, the process proceeds to operation 1408.

[0305] In operation 1408 of method 1400, an array of multiple second-type active region patterns is generated. The second-type active region patterns are positioned parallel to the back-side power rail pattern. Each of the multiple second-type active region patterns specifies a second-type active region semiconductor structure stacked with a corresponding first-type active region semiconductor structure. Figures 12A to 12B In the layout design of multiple embodiments, the multiple second-type active region patterns of this array include multiple layout patterns for multiple n-type active region semiconductor structures 50n(1), 50n(2), and 50n(3). According to... Figures 12A to 12B In the integrated circuits manufactured by multiple layout designs, n-type active region semiconductor structure 50n(1) and p-type active region semiconductor structure 50p(1) are stacked, n-type active region semiconductor structure 50n(2) and p-type active region semiconductor structure 50p(2) are stacked, and n-type active region semiconductor structure 50n(3) and p-type active region semiconductor structure 50p(3) are stacked. After operation 1408, the process proceeds to operation 1410.

[0306] In operation 1410 of method 1400, at least one front-side signal line pattern is generated between a pair of adjacent front-side power rail patterns. The at least one front-side signal line pattern specifies a front-side signal line in a front-side conductive layer, which is higher than both the first type active region semiconductor structure and the second type active region semiconductor structure. Figures 12A to 12B In the various implementation layout designs, multiple layout patterns for multiple front-side signal lines 120F(1) and 140F(1) are positioned between multiple layout patterns for multiple front-side power rails 30F(1) and 30F(2). Multiple layout patterns for multiple front-side signal lines 120F(2) and 140F(2) are positioned between multiple layout patterns for multiple front-side power rails 30F(2) and 30F(3). After operation 1410, the process proceeds to operation 1412.

[0307] In operation 1412 of method 1400, at least one back-side signal line pattern is generated between a pair of adjacent back-side power rail patterns. The at least one back-side signal line pattern specifies a back-side signal line in a back-side conductive layer, which is lower than both the first type active region semiconductor structure and the second type active region semiconductor structure. Figures 12A to 12BIn the layout design of multiple embodiments, multiple layout patterns for multiple back-side signal lines 120B(1) and 140B(1) are positioned between multiple layout patterns for multiple back-side power rails 30B(1) and 30B(2). Multiple layout patterns for multiple back-side signal lines 120B(2) and 140B(2) are positioned between multiple layout patterns for multiple back-side power rails 30B(2) and 30B(3).

[0308] Figure 15 This is a flowchart of a method 1500 for manufacturing an integrated circuit (IC) having a complementary field-effect transistor device according to some embodiments. It should be understood that... Figure 15 Additional operations are performed before, during, and / or after the method 1500 shown, and some other processes can only be briefly described here.

[0309] In operation 1510 of method 1500, a second type of active region semiconductor structure is fabricated on a substrate. Then, in operation 1512 of method 1500, a second gate conductor is fabricated, and the second gate conductor intersects with the second type of active region semiconductor structure. As a non-limiting embodiment, in such... Figure 1A and Figures 1C to 1D In the various embodiments shown, in operation 1510, an n-type active region semiconductor structure 50n is fabricated on a substrate. In operation 1512, a lower portion of a gate conductor 150 is fabricated, and the lower portion of the gate conductor 150 intersects with the n-type active region semiconductor structure 50n. As another non-limiting embodiment, in Figure 8A and Figure 8C In several embodiments shown, a gate conductor 150n is fabricated in operation 1512, and the gate conductor 150n intersects with an n-type active region semiconductor structure 50n.

[0310] In addition to operation 1512, another operation following operation 1510 is operation 1514. In operation 1514, a second source conductive segment is fabricated, and the second source conductive segment intersects with a second type of active region semiconductor structure. As a non-limiting embodiment, in such... Figure 1A and Figures 1C to 1D In several embodiments shown, a conductive segment 132n is fabricated, and the conductive segment 132n (as a source conductive segment) intersects with the n-type active region semiconductor structure 50n to form the source terminal of the NMOS transistor T1n. In the process flow of method 1500, operations 1512 and 1514 are performed after operation 1510. In some embodiments, operation 1512 is performed before operation 1514. In some alternative embodiments, operation 1512 is performed after operation 1514. After multiple operations 1510, 1512, and 1514, the process flow proceeds to 1520.

[0311] In operation 1520 of method 1500, a dielectric material layer is deposited and at least covers the second type of active region semiconductor structure, and in operation 1530 of method 1500, a first type of active region semiconductor structure is fabricated on top of the dielectric material layer. As a non-limiting embodiment, in... Figure 1A and Figures 1C to 1D In several embodiments shown, a p-type active region semiconductor structure 50p is fabricated on top of a dielectric material layer (which is above the n-type active region semiconductor structure 50n). Then, in operation 1532 of method 1500, a first gate conductor is fabricated, and the first gate conductor intersects with the first type of active region semiconductor structure. As a non-limiting embodiment, in... Figure 1A and Figures 1C to 1D In several embodiments shown, an upper portion of the gate conductor 150 is fabricated, and the upper portion of the gate conductor 150 intersects with the p-type active region semiconductor structure 50p.

[0312] In some embodiments, the lower and upper portions of the gate conductor 150 are fabricated separately in corresponding operations 1512 and 1532. In some embodiments, the integrated gate conductor 150 is formed from the lower and upper portions of the gate conductor. Specifically, before fabricating the upper portion of the gate conductor 150, an inter-gate connector is fabricated through a dielectric material layer above the n-type active region semiconductor structure 50n, and the inter-gate connector directly connects the lower portion of the gate conductor 150 to the upper portion of the gate conductor 150 to form the integrated gate conductor 150. In some alternative embodiments, the first gate conductor fabricated in operation 1532 and the second gate conductor fabricated in operation 1512 are not directly connected to the inter-gate connector. For example, in Figure 8A and Figure 8C In the various embodiments shown, gate conductor 150p is fabricated in operation 1532, and gate conductor 150n is fabricated in operation 1512. Gate conductor 150p and gate conductor 150n are not directly connected.

[0313] In operation 1534, a first source conductive segment is fabricated, and the first source conductive segment intersects with a first type of active region semiconductor structure. As a non-limiting embodiment, in such... Figure 1A and Figures 1C to 1DIn several embodiments shown, a conductive segment 132p is fabricated, and the conductive segment 132p (as a source conductive segment) intersects with the p-type active region semiconductor structure 50p to form the source terminal of the PMOS transistor T1p. In the process flow of method 1500, operations 1532 and 1534 are performed after operation 1530. In some embodiments, operation 1532 is performed before operation 1534. In some alternative embodiments, operation 1532 is performed after operation 1534. After multiple operations 1530, 1532, and 1534, the process flow proceeds to 1540.

[0314] In operation 1540 of method 1500, a first insulating material is deposited, and the first insulating material covers the first gate conductor and the first source conductive segment. After operation 1540, in operation 1550 of method 1500, a front-side metal layer is deposited over the first insulating material. Then, in operation 1555 of method 1500, the front-side metal layer is patterned to form a front-side power rail and a front-side signal line. The front-side power rail is conductively connected to the first source conductive segment via a first via connector, and the front-side signal line is conductively connected to the first gate conductor via a front-side gate via connector. As a non-limiting embodiment, in such... Figure 1A ,and Figures 1C to 1D In the various embodiments shown, a front power rail 30F and a plurality of front signal lines (120F and 140F) are fabricated in a front metal layer on an insulating material covering the gate conductor 150 and the conductive segment 132p. The front power rail 30F is conductively connected to the conductive segment 132p via a top via connector VT, and the front signal line 120F is conductively connected to the gate conductor 150 via a top gate via connector VG.

[0315] After operations 1540, 1550, and 1555, the wafer containing the substrate is flipped in operation 1560. The process flow then proceeds to 1570. In operation 1570 of method 1500, a back-side metal layer is formed on the back side of the substrate. After operation 1570, in operation 1575 of method 1500, the back-side metal layer is patterned to form back-side power rails and back-side signal lines. The back-side power rails are conductively connected to a second source conductor via a second via connector, and the back-side signal lines are conductively connected to a second gate conductor via a back-side gate via connector. As a non-limiting embodiment, in... Figure 1A ,and Figures 1C to 1D In several embodiments shown, a back-side power rail 30B and a plurality of back-side signal lines (120B and 140B) are fabricated in a back-side metal layer on the back side of the substrate. The back-side power rail 30B is electrically connected to the conductive segment 132n via a bottom via connector VB.

[0316] Figure 16 This is a block diagram of an electronic design automation (EDA) system 1600 according to some implementations.

[0317] In some embodiments, the electronic design automation system 1600 includes an APR (Automatic Placement & Routing) system. Various methods for representing wiring and routing arrangements according to one or more embodiments described herein are feasible, for example, using the electronic design automation system 1600 according to some embodiments.

[0318] In some embodiments, the electronic design automation system 1600 is a general-purpose computing device, which includes a hardware processor 1602 and a non-transitory computer-readable storage medium 1604. The storage medium 1604 is encoded (i.e., stored) with computer program code 1606 (i.e., a set of executable instructions). Execution of the instructions 1606 by the hardware processor 1602 represents (at least partially) an electronic design automation tool that implements some or all of the methods described herein according to one or more embodiments (hereinafter, the multiple processes and / or multiple methods).

[0319] Processor 1602 is electrically coupled to computer-readable storage medium 1604 via bus 1608. Processor 1602 is also electrically coupled to input / output interface 1610 via bus 1608. Network interface 1612 is also electrically connected to processor 1602 via bus 1608. Network interface 1612 is connected to network 1614, enabling processor 1602 and computer-readable storage medium 1604 to be connected to multiple external components via network 1614. Processor 1602 is configured to execute computer program code 1606 encoded in computer-readable storage medium 1604 to make system 1600 available for performing part or all of the aforementioned processes and / or methods. In one or more embodiments, processor 1602 is a central processing unit (CPU), a multiprocessor, a distributed processing system, an application-specific integrated circuit (ASIC), and / or a suitable processing unit.

[0320] In one or more embodiments, the computer-readable storage medium 1604 is an electronic, magnetic, optical, electromagnetic, infrared, and / or semiconductor system (or device or apparatus). For example, the computer-readable storage medium 1604 includes semiconductor or solid-state memory, magnetic tape, removable computer disk, random access memory (RAM), read-only memory (ROM), hard disk, and / or optical disk. In one or more embodiments using optical disk, the computer-readable storage medium 1604 includes optical disc read-only memory (CD-ROM), compact disk-read / write (CD-R / W), and / or digital video disc (DVD).

[0321] In one or more embodiments, storage medium 1604 stores computer program code 1606 configured to enable system 1600 (where such execution represents (at least partially) electronic design automation tools) to perform part or all of the said processes and / or methods. In one or more embodiments, storage medium 1604 also stores information that facilitates the execution of part or all of the said processes and / or methods. In one or more embodiments, storage medium 1604 stores a library 1607 of standard cells including the various standard cells disclosed herein. In one or more embodiments, storage medium 1604 stores one or more layout figures 1609 corresponding to one or more layouts disclosed herein.

[0322] The electronic design automation system 1600 includes an input / output interface 1610. The input / output interface 1610 is coupled to external circuitry. In one or more embodiments, the input / output interface 1610 includes a keyboard, keypad, mouse, trackball, trackpad, touchscreen, and / or cursor arrow keys for transmitting information and commands to the processor 1602.

[0323] The electronic design automation system 1600 also includes a network interface 1612 coupled to the processor 1602. The network interface 1612 allows the system 1600 to communicate with a network 1614, to which one or more other computer systems are connected. The network interface 1612 may include a wireless network interface, such as Bluetooth, Wi-Fi, WiMAX, GPRS, or WCDMA, or a wired network interface, such as Ethernet, USB, or IEEE-1364. In one or more embodiments, part or all of the described processes and / or methods are implemented in two or more systems 1600.

[0324] System 1600 is configured to receive information via input / output interface 1610. The information received via input / output interface 1610 includes instructions, data, design rules, libraries of multiple standard cells, and / or one or more other parameters processed by processor 1602. This information is transmitted to processor 1602 via bus 1608. Electronic design automation system 1600 is configured to receive information related to the user interface (UI) via input / output interface 1610. This information is stored in computer-readable medium 1604 as user interface (UI) 1642.

[0325] In some embodiments, part or all of the process and / or method is implemented as a standalone software application executed by a processor. In some embodiments, part or all of the process and / or method is implemented as a software application that is part of an additional software application. In some embodiments, part or all of the process and / or method is implemented as a plug-in to a software application. In some embodiments, at least one of the process and / or method is implemented as a software application that is part of an electronic design automation tool. In some embodiments, part or all of the process and / or method is implemented as a software application used by the electronic design automation system 1600. In some embodiments, the layout diagram including multiple standard cells is created using tools such as VIRTUOSO®, available from Cadence Design Systems, Inc., or another suitable layout generation tool.

[0326] In some implementations, these processes are implemented as the functionality of a program stored in a non-transitory computer-readable recording medium. Embodiments of non-transitory computer-readable recording media include, but are not limited to, external / removable and / or internal / built-in storage or memory units, such as optical discs (e.g., DVDs), magnetic disks (e.g., hard disks), semiconductor memory (e.g., read-only memory, random access memory), memory cards, and one or more of the like.

[0327] Figure 17 This is a block diagram of an integrated circuit manufacturing system 1700 and an associated integrated circuit manufacturing process according to some embodiments. In some embodiments, based on a layout diagram, the manufacturing system 1700 is used to manufacture at least one of (A) one or more semiconductor masks or (B) at least one component of a layer of a semiconductor integrated circuit.

[0328] exist Figure 17 In this system, integrated circuit manufacturing system 1700 includes multiple entities, such as design company 1720, masking company 1730, and integrated circuit manufacturer / fab (“fab”) 1750, that interact in the design, development, and manufacturing cycles and / or services associated with manufacturing integrated circuit apparatus 1760. The multiple entities in system 1700 are connected via a communication network. In some embodiments, the communication network is a single network. In some embodiments, the communication network is a variety of different networks, such as an intranet and the Internet. The communication network includes wired and / or wireless communication channels. Each entity interacts with one or more other entities and provides services to and / or receives services from one or more other entities. In some embodiments, two or more of design company 1720, masking company 1730, and integrated circuit fabrication plant 1750 are owned by a single, larger company. In some embodiments, two or more of design company 1720, masking company 1730, and integrated circuit fabrication plant 1750 coexist in shared facilities and use shared resources.

[0329] Design company (or design team) 1720 produces integrated circuit design layout 1722. Integrated circuit design layout 1722 includes various geometric patterns designed for integrated circuit device 1760. These geometric patterns correspond to multiple patterns of metal, oxide, or semiconductor layers constituting various components of the integrated circuit device 1760 to be manufactured. The layers are combined to form various integrated circuit features. For example, a portion of integrated circuit design layout 1722 includes various integrated circuit features such as active regions, gate electrodes, source and drain electrodes, metal lines or vias for interlayer interconnects, and openings for bonding pads, which will be formed in a semiconductor substrate (e.g., a silicon wafer) and in various material layers disposed on the semiconductor substrate. Design company 1720 implements appropriate design procedures to form integrated circuit design layout 1722. Design procedures include one or more of logic design, physical design, or placement and wiring. Integrated circuit design layout 1722 is presented in one or more data files containing information of multiple geometric patterns. For example, integrated circuit design layout 1722 can be expressed in GDSII or DFII file format.

[0330] Masking company 1730 includes data preparation 1732 and mask manufacturing 1744. Masking company 1730 uses an integrated circuit design layout 1722 to manufacture one or more masks 1745, which are used to manufacture various layers of integrated circuit device 1760 according to the integrated circuit design layout 1722. Masking company 1730 performs mask data preparation 1732, in which the integrated circuit design layout 1722 is translated into a representative data file (RDF). Mask data preparation 1732 provides the representative data file (RDF) to mask manufacturing 1744. Mask manufacturing 1744 includes a mask writer. The mask writer converts the representative data file (RDF) into an image on a substrate, such as a mask (reduction mask) 1745 or a semiconductor wafer 1753. Design layout 1722 is manipulated by mask data preparation 1732 to conform to the specific characteristics of the mask writer and / or the requirements of the integrated circuit manufacturing plant 1750. Figure 17 In this diagram, mask data preparation 1732 and mask manufacturing 1744 are illustrated as separate elements. In some embodiments, mask data preparation 1732 and mask manufacturing 1744 may be collectively referred to as mask data preparation.

[0331] In some embodiments, mask data preparation 1732 includes optical proximity correction (OPC), which uses lithography enhancement techniques to compensate for image errors, such as those that may be caused by diffraction, interference, other process effects, and the like. Optical proximity correction adjustment integrated circuit design layout diagram 1722. In some embodiments, mask data preparation 1732 includes further resolution enhancement techniques (RET), such as off-axis illumination, sub-resolution auxiliary features, phase-shift masking, other suitable techniques, and the like, or combinations thereof. In some embodiments, inverse lithography technology (ILT) is also used, which treats optical proximity correction as an inverse imaging problem.

[0332] In some embodiments, mask data preparation 1732 includes a mask rule checker (MRC) that uses a set of mask creation rules to check the integrated circuit design layout 1722, which has already undergone processing in optical proximity correction. This set of mask creation rules includes certain geometric and / or connectivity constraints to ensure sufficient margin to accommodate variability in semiconductor manufacturing processes, and the like. In some embodiments, the mask rule checker modifies the integrated circuit design layout 1722 to compensate for constraints during mask fabrication 1744, which can cancel some modifications performed by optical proximity correction to satisfy the mask creation rules.

[0333] In some implementations, mask data preparation 1732 includes lithography process checking (LPC), which simulates the processes performed by integrated circuit manufacturing plant 1750 to manufacture integrated circuit device 1760. Lithography process checking simulates this process based on integrated circuit design layout 1722 to create a simulated manufactured device, such as integrated circuit device 1760. Multiple processing parameters in the lithography process checking simulation may include multiple parameters associated with various processes in the integrated circuit manufacturing cycle, multiple parameters associated with the tools used to manufacture the integrated circuit, and / or other aspects of the manufacturing process. Lithography process checking considers various factors, such as spatial image contrast, depth of focus (DOF), mask error enhancement factor (MEEF), other suitable factors, and similar factors, or combinations thereof. In some implementations, after the simulated fabricated device has been created by lithography inspection, if the simulated device is not close enough in shape to meet the design rules, the optical proximity correction and / or masking rule checker is repeated to further refine the integrated circuit design layout diagram 1722.

[0334] It should be understood that the above description of masking data preparation 1732 has been simplified for clarity. In some embodiments, data preparation 1732 includes additional features, such as logic operations (LOPs), to modify the integrated circuit design layout 1722 according to manufacturing rules. Furthermore, multiple processes applied to the integrated circuit design layout 1722 during data preparation 1732 can be performed in various different sequences.

[0335] Following mask data preparation 1732 and during mask fabrication 1744, a mask 1745 or a group of multiple masks 1745 is fabricated based on a modified integrated circuit design layout 1722. In some embodiments, mask fabrication 1744 includes performing one or more lithography exposures based on the integrated circuit design layout 1722. In some embodiments, a pattern is formed on the mask (photomask or magnifying mask) 1745 using a single electron beam or multiple electron beam mechanism based on the modified integrated circuit design layout 1722. Various techniques can be used to form the mask 1745. In some embodiments, a binary technique is used to form the mask 1745. In some embodiments, the mask pattern includes opaque areas and transparent areas. A radiation beam (e.g., ultraviolet (UV)) is used to expose an image-sensitive material layer (e.g., photoresist) already coated on the wafer; the radiation beam is blocked by the opaque areas and transmitted through the transparent areas. In one embodiment, the binary mask version of mask 1745 includes a transparent substrate (e.g., fused quartz) and an opaque material (e.g., chromium) coated on the opaque regions of the binary mask. In another embodiment, mask 1745 is formed using a phase shift technique. In the phase shift mask (PSM) version of mask 1745, various features in the pattern formed on the phase shift mask are configured to have appropriate phase differences to improve resolution and imaging quality. In various embodiments, the phase shift mask may be an attenuated PSM or an alternating PSM. In various processes, the mask produced by mask fabrication 1744 is used. For example, such a mask is used in ion implantation processes to form various doped regions in semiconductor wafer 1753, in etching processes to form various etched regions in semiconductor wafer 1753, and / or in other suitable processes.

[0336] Integrated circuit manufacturing plant 1750 is an integrated circuit manufacturing enterprise that includes one or more manufacturing facilities for manufacturing various different integrated circuit products. In some embodiments, integrated circuit manufacturing plant 1750 is a semiconductor foundry. For example, there may be manufacturing facilities for front-end manufacturing (front-end-of-line (FEOL) manufacturing) of multiple integrated circuit products, while a second manufacturing facility may provide back-end manufacturing (back-end-of-line (BEOL) manufacturing) for interconnects and packaging of integrated circuit products, and a third manufacturing facility may provide other services for foundry operations.

[0337] Integrated circuit manufacturing plant 1750 includes manufacturing tools 1752 configured to perform various manufacturing operations on semiconductor wafers 1753, thereby manufacturing integrated circuit devices 1760 according to a mask (e.g., mask 1745). In various embodiments, manufacturing tools 1752 include one or more of the following: wafer stepper, ion implanter, photoresist coater, processing chamber (e.g., chemical vapor deposition chamber or low-pressure chemical vapor deposition furnace), chemical mechanical polishing system, plasma etching system, wafer cleaning system, or other manufacturing equipment capable of performing one or more suitable manufacturing processes discussed herein.

[0338] Integrated circuit manufacturing plant 1750 uses a mask 1745 manufactured by mask company 1730 to manufacture integrated circuit device 1760. Therefore, integrated circuit manufacturing plant 1750 uses integrated circuit design layout 1722 at least indirectly to manufacture integrated circuit device 1760. In some embodiments, integrated circuit manufacturing plant 1750 uses mask 1745 to manufacture semiconductor wafer 1753 to form integrated circuit device 1760. In some embodiments, integrated circuit manufacturing includes performing one or more lithography exposures at least indirectly based on integrated circuit design layout 1722. Semiconductor wafer 1753 includes a silicon substrate or other suitable substrate on which multiple material layers are formed. Semiconductor wafer 1753 also includes one or more various doped regions, dielectric features, multilayer interconnects, and the like (formed in subsequent manufacturing steps).

[0339] Regarding integrated circuit (IC) manufacturing systems (e.g., Figure 17 Details of the system (1700), and the associated integrated circuit manufacturing process, can be found, for example, in U.S. Patent No. 9,256,709, granted February 9, 2016; U.S. Patent Publication No. 20150278429, published October 1, 2015; U.S. Patent Publication No. 20140040838, published February 6, 2014; and U.S. Patent No. 7,260,442, granted August 21, 2007, the entire contents of which are incorporated herein by reference.

[0340] This disclosure relates to several forms of integrated circuit devices. The integrated circuit device includes a first type of active region semiconductor structure extending in a first direction and a first gate conductor extending in a second direction perpendicular to the first direction. The first gate conductor intersects the first type of active region semiconductor structure at a channel region of a first type of transistor. The integrated circuit device also includes a second type of active region semiconductor structure extending in the first direction and a second gate conductor extending in the second direction, the second gate conductor intersecting the second type of active region semiconductor structure at a channel region of a second type of transistor. The second type of active region semiconductor structure is stacked with the first type of active region semiconductor structure and offset from the first type of active region semiconductor structure along a third direction perpendicular to both the first and second directions. The integrated circuit device also includes a front conductive layer and a back conductive layer. The front conductive layer faces the third direction and is located above the first and second type of active region semiconductor structures. The back conductive layer faces the third direction and is located below the first and second type of active region semiconductor structures. The integrated circuit device also includes a front power rail, a back power rail, a front signal line, and a back signal line. A front-side power rail extends in a first direction within a front-side conductive layer and is configured to maintain a first supply voltage. A back-side power rail extends in a first direction within a back-side conductive layer and is configured to maintain a second supply voltage. A front-side signal line extends in a first direction within the front-side conductive layer. A back-side signal line extends in a first direction within the back-side conductive layer. The integrated circuit device also includes a first source conductive segment, a second source conductive segment, and a drain conductive segment. The first source conductive segment extends in a second direction and intersects with a first-type active region semiconductor structure at the source region of a first-type transistor, and is conductively connected to the front-side power rail via a first via connector. The second source conductive segment extends in a second direction and intersects with a second-type active region semiconductor structure at the source region of a second-type transistor, and is conductively connected to the back-side power rail via a second via connector. The drain conductive segment extends in a second direction and intersects with one or both of the first-type and second-type active region semiconductor structures, and is conductively connected to the front-side signal line or the back-side signal line via a third via connector.

[0341] In some implementations, in an integrated circuit device, a first gate conductor is combined with a second gate conductor to form a third gate conductor.

[0342] In some implementations, in an integrated circuit device, a first gate conductor is separated from a second gate conductor along a third direction via a gate stack insulator.

[0343] In some implementations, in an integrated circuit device, the front power rail and the rear power rail overlap each other when viewed along a third direction.

[0344] In some implementations, in an integrated circuit device, when viewed along a third direction, the front power rail and the rear power rail are aligned with each other along multiple boundaries.

[0345] Another aspect of this disclosure relates to an integrated circuit device. The integrated circuit device includes a first type of active-area semiconductor structure, a second type of active-area semiconductor structure, a front conductive layer, a back conductive layer, a plurality of gate conductors, a plurality of conductive segments, a front signal line, a back signal line, a front power rail, and a back power rail. The first type of active-area semiconductor structure extends in a first direction. The second type of active-area semiconductor structure extending in the first direction is stacked with the first type of active-area semiconductor structure. The front conductive layer is higher than both the first and second type of active-area semiconductor structures. The back conductive layer is lower than both the first and second type of active-area semiconductor structures. The plurality of gate conductors extend in a second direction perpendicular to the first direction. Each of the plurality of gate conductors intersects with one or both of the first and second type of active-area semiconductor structures, simultaneously forming a gate terminal of at least one transistor. The plurality of conductive segments extend in the second direction. Each of the plurality of conductive segments intersects with one or both of the first and second type of active-area semiconductor structures, simultaneously forming a source terminal or a drain terminal of at least one transistor. The plurality of conductive segments include a first conductive segment, a second conductive segment, a third conductive segment intersecting a first type of active region semiconductor structure, and a fourth conductive segment intersecting a second type of active region semiconductor structure. A front-side signal line extends in a first direction within the front-side conductive layer and is configured to transmit a first voltage change at the first conductive segment to one or more gate conductors or to one or more conductive segments. A back-side signal line extends in a first direction within the back-side conductive layer and is configured to transmit a second voltage change at the second conductive segment to one or more gate conductors or to one or more conductive segments. A front-side power rail extends in the front-side conductive layer in the first direction and is configured to maintain a first supply voltage and is conductively connected to the third conductive segment via a first via connector. A back-side power rail extends in the back-side conductive layer in the first direction and is configured to maintain a second supply voltage and is conductively connected to the fourth conductive segment via a second via connector.

[0346] In some embodiments, in the integrated circuit device, the front power rail and the back power rail overlap each other when viewed in a direction perpendicular to the front conductive layer and the back conductive layer. In some embodiments, in the integrated circuit device, the front power rail and the back power rail overlap each other by approximately 80% when viewed in a direction perpendicular to the front conductive layer and the back conductive layer.

[0347] In some implementations, in an integrated circuit device, when viewed in a direction perpendicular to the front conductive layer and the back conductive layer, the front power rail and the back power rail are aligned with each other along multiple boundaries.

[0348] In some implementations, in an integrated circuit device, a first type of active region semiconductor structure is located below a second type of active region semiconductor structure.

[0349] In some embodiments, in an integrated circuit device, each of the first type of active region semiconductor structure and the second type of active region semiconductor structure includes at least one nanosheet.

[0350] In some embodiments, in an integrated circuit device, each of the first type of active region semiconductor structure and the second type of active region semiconductor structure includes at least one nanowire.

[0351] Another embodiment of this disclosure relates to a method. This method includes fabricating a first type of active region semiconductor structure extending in a first direction on a substrate, fabricating a first gate conductor intersecting the first type of active region semiconductor structure at a channel region of a first type of transistor, and fabricating a first source conductive segment intersecting the first type of active region semiconductor structure at a first source region. This method includes depositing a dielectric material layer that at least covers the first type of active region semiconductor structure, and fabricating a second type of active region semiconductor structure extending in the first direction on top of the dielectric material layer. The second type of active region semiconductor structure is stacked with the first type of active region semiconductor structure. This method includes fabricating a second gate conductor intersecting the second type of active region semiconductor structure at a channel region of a first type of second type transistor, and fabricating a second type of source conductive segment intersecting the second type of active region semiconductor structure at a second source region. This method includes depositing a first insulating material that covers the second gate conductor and the second source conductive segment, depositing a front-side metal layer over the first insulating material, and patterning the front-side metal layer to form a front-side power rail extending in the first direction and a front-side signal line extending in the first direction. A front-side power rail is conductively connected to a second source conductor via a first via connector, and a front-side signal line is conductively connected to a second gate conductor via a front-side gate via connector. This method includes forming a back-side metal layer on the back side of a substrate and patterning the back-side metal layer to form a back-side power rail extending in a first direction and a back-side signal line extending in the first direction. The back-side power rail is conductively connected to the first source conductor via a second via connector.

[0352] In some embodiments, in a method of manufacturing an integrated circuit device, a patterned front metal layer includes a patterned front metal layer to form a second front signal line extending in a first direction, the second front signal line being electrically connected to a second gate conductor via a front gate via connector.

[0353] In some embodiments, in a method of manufacturing an integrated circuit device, a patterned back-side metal layer includes a patterned back-side metal layer to form a second back-side signal line extending in a first direction, the second back-side signal line being electrically connected to a first gate conductor via a back-side gate via connector.

[0354] In some embodiments, the method of manufacturing an integrated circuit device further includes: manufacturing an inter-gate connector that passes through a dielectric material layer to directly connect a second gate conductor and a first gate conductor.

[0355] In some embodiments, the method of manufacturing an integrated circuit device further includes: manufacturing a first drain conductive segment that intersects with a first type of active region semiconductor structure at a first drain region; and manufacturing a second drain conductive segment that intersects with a second type of active region semiconductor structure at a second drain region.

[0356] In some embodiments, the method of manufacturing an integrated circuit device further includes: manufacturing a connector between conductive segments passing through a dielectric material layer to directly connect a first drain conductive segment and a second drain conductive segment.

[0357] In some embodiments, in the method of manufacturing an integrated circuit device, manufacturing a first drain conductive segment includes manufacturing a first drain conductive segment that intersects with a first type active region semiconductor structure at a first drain region of a first type transistor.

[0358] In some embodiments, in the method of manufacturing an integrated circuit device, manufacturing a first drain conductive segment includes manufacturing a first drain conductive segment that intersects with a first type active region semiconductor structure at a first drain region of a second first type transistor.

[0359] In some embodiments, in the method of manufacturing an integrated circuit device, manufacturing a first source conductive segment includes: manufacturing a first source conductive segment that intersects with a first type active region semiconductor structure at a first source region of a second first type transistor.

[0360] Those skilled in the art will readily recognize that one or more of the disclosed embodiments achieve one or more of the aforementioned advantages. After reading the foregoing specification, those skilled in the art will be able to implement various variations, equivalents, and various other embodiments broadly disclosed herein. Therefore, the protection granted herein is limited only by the definitions contained in the appended claims and their equivalents.

Claims

1. An integrated circuit device, characterized in that, Include: A first type of active-region semiconductor structure extending in a first direction; A first gate conductor extends in a second direction perpendicular to the first direction and intersects with the first type active region semiconductor structure at a channel region of a first type transistor; A second type of active region semiconductor structure extends in the first direction, is stacked with the first type of active region semiconductor structure, and is offset from the first type of active region semiconductor structure along a third direction perpendicular to both the first direction and the second direction; A second gate conductor extends in the second direction and intersects with the second type of active region semiconductor structure at a channel region of a second type of transistor; A front conductive layer, facing the third direction, is located above the first type of active region semiconductor structure and the second type of active region semiconductor structure; A back-side conductive layer, facing the third direction, is located below the first type of active region semiconductor structure and the second type of active region semiconductor structure; A front power rail extends in the first direction, and in the front conductive layer, the front power rail is configured to maintain a first supply voltage. A back-side power rail extends in the first direction and is configured to maintain a second supply voltage in the back-side conductive layer. A front-side signal line extends in the first direction within the front-side conductive layer; A back-side signal line extends in the first direction within the back-side conductive layer; A first source conductive segment extends in the second direction, intersects with the first type active region semiconductor structure at a source region of the first type transistor, and is conductively connected to the front power rail through a first via connector. A second source conductive segment extends in the second direction, intersects with the second type of active region semiconductor structure at a source region of the second type of transistor, and is conductively connected to the back power rail through a second via connector. as well as A drain conductive segment extends in the second direction, intersects with one or both of the first type active region semiconductor structure and the second type active region semiconductor structure, and is conductively connected to the front signal line or the back signal line through a third via connector. In the second direction, the width of the first type of active region semiconductor structure is greater than the width of the front power rail and the width of the front signal line, and the width of the second type of active region semiconductor structure is greater than the width of the back power rail and the width of the back signal line.

2. The integrated circuit device according to claim 1, characterized in that, The first gate conductor is combined with the second gate conductor to form a third gate conductor.

3. The integrated circuit device according to claim 1, characterized in that, The first gate conductor is separated from the second gate conductor along the third direction via a gate stack insulator.

4. The integrated circuit device according to claim 1, characterized in that, When viewed along this third direction, the front power rail and the rear power rail overlap each other.

5. The integrated circuit device according to claim 1, characterized in that, When viewed along this third direction, the front power rail and the rear power rail are aligned with each other along multiple boundaries.

6. An integrated circuit device, characterized in that, Include: A first type of active-region semiconductor structure extending in a first direction; A second type of active region semiconductor structure extends in the first direction and is stacked with the first type of active region semiconductor structure; A front conductive layer is provided above the first type of active region semiconductor structure and the second type of active region semiconductor structure. A back-side conductive layer is provided below the first type of active region semiconductor structure and the second type of active region semiconductor structure. Multiple gate conductors extend in a second direction perpendicular to the first direction, and each of the gate conductors intersects with one or both of the first type of active region semiconductor structure and the second type of active region semiconductor structure, thereby forming a gate terminal of at least one transistor. Multiple conductive segments extend in the second direction, each of which intersects with one or both of the first type active region semiconductor structure and the second type active region semiconductor structure, thereby forming a source terminal or a drain terminal of at least one transistor, and wherein the multiple conductive segments include a first conductive segment, a second conductive segment, a third conductive segment intersecting with the first type active region semiconductor structure, and a fourth conductive segment intersecting with the second type active region semiconductor structure; A front-side signal line extends in the first direction within the front-side conductive layer, and the front-side signal line is configured to transmit a first voltage change at the first conductive segment to one or more of the gate conductors or to one or more of the conductive segments. A back-side signal line extends in the first direction within the back-side conductive layer, and the back-side signal line is configured to transmit a second voltage change at the second conductive segment to one or more of the gate conductors or to one or more of the conductive segments. A front power rail extends in the first direction, and in the front conductive layer, the front power rail is configured to maintain a first supply voltage and is conductively connected to the third conductive segment via a first via connector. as well as A back-side power rail extends in the first direction, and in the back-side conductive layer, the back-side power rail is configured to maintain a second supply voltage and is conductively connected to the fourth conductive segment via a second via connector. In the second direction, the width of the first type of active region semiconductor structure is greater than the width of the front power rail and the width of the front signal line, and the width of the second type of active region semiconductor structure is greater than the width of the back power rail and the width of the back signal line.

7. The integrated circuit device according to claim 6, characterized in that, When viewed in a direction perpendicular to the front conductive layer and the back conductive layer, the front power rail and the back power rail overlap by 80%.

8. The integrated circuit device according to claim 6, characterized in that, When viewed in a direction perpendicular to the front conductive layer and the back conductive layer, the front power rail and the back power rail are aligned with each other along multiple boundaries.

9. The integrated circuit device according to claim 6, characterized in that, The first type of active region semiconductor structure is located below the second type of active region semiconductor structure.

10. The integrated circuit device according to claim 6, characterized in that, Each of the first type of active region semiconductor structure and the second type of active region semiconductor structure includes at least one nanosheet.

11. The integrated circuit device according to claim 6, characterized in that, Each of the first type of active region semiconductor structure and the second type of active region semiconductor structure includes at least one nanowire.

12. A method for manufacturing an integrated circuit device, characterized in that, Include: A first type of active region semiconductor structure extending in a first direction is fabricated on a substrate; A first gate conductor is fabricated that intersects with the first type active region semiconductor structure in a channel region of a first type transistor; A first source conductive segment is fabricated that intersects with the first type of active region semiconductor structure in a first source region; Deposit a dielectric material layer that at least covers the first type of active region semiconductor structure; A second type of active region semiconductor structure extending in the first direction is fabricated on top of the dielectric material layer, wherein the second type of active region semiconductor structure is stacked with the first type of active region semiconductor structure. A second gate conductor is fabricated that intersects with the second type active region semiconductor structure at a channel region of a first second type transistor; A second source conductive segment is fabricated that intersects with the second type of active region semiconductor structure at a second source region; A first insulating material is deposited to cover the second gate conductor and the second source conductive segment; A front-side metal layer is deposited over the first insulating material and patterned to form a front-side power rail extending in the first direction and a front-side signal line extending in the first direction, wherein the front-side power rail is conductively connected to the second source conductive segment through a first via connector, and wherein the front-side signal line is conductively connected to the second gate conductor through a front-side gate via connector, wherein in a second direction perpendicular to the first direction, the width of the first type active region semiconductor structure is greater than the width of the front-side power rail and the width of the front-side signal line; as well as A back-side metal layer is formed on one back side of a substrate, and the back-side metal layer is patterned to form a back-side power rail extending in the first direction and a back-side signal line extending in the first direction, wherein the back-side power rail is conductively connected to the first source conductive segment through a second via connector, wherein in the second direction, the width of the second type active region semiconductor structure is greater than the width of the back-side power rail and the width of the back-side signal line.

13. The method for manufacturing an integrated circuit device according to claim 12, characterized in that, Patterning the front metal layer includes patterning the front metal layer to form a second front signal line extending in the first direction, the second front signal line being conductively connected to the second gate conductor via a front gate via connector.

14. The method for manufacturing an integrated circuit device according to claim 12, characterized in that, Patterning the back metal layer includes patterning the back metal layer to form a second back signal line extending in the first direction, the second back signal line being conductively connected to the first gate conductor via a back gate via connector.

15. The method of manufacturing an integrated circuit device according to claim 12, characterized in that, Also includes: A gate connector is manufactured through the dielectric material layer to directly connect the second gate conductor and the first gate conductor.

16. The method of manufacturing an integrated circuit device according to claim 12, characterized in that, Also includes: Fabricate a first drain conductive segment that intersects with the first type of active region semiconductor structure at a first drain region; and A second drain conductive segment is fabricated that intersects with the second type of active region semiconductor structure at a second drain region.

17. The method of manufacturing an integrated circuit device according to claim 16, characterized in that, Also includes: A connector is manufactured that passes through the dielectric material layer to directly connect the first drain conductive segment and the second drain conductive segment.

18. The method of manufacturing an integrated circuit device according to claim 16, characterized in that, Manufacturing the first drain conductive segment includes manufacturing the first drain conductive segment that intersects with the first type active region semiconductor structure at the first drain region of the first type transistor.

19. The method of manufacturing an integrated circuit device according to claim 16, characterized in that, Manufacturing the first drain conductive segment includes manufacturing the first drain conductive segment intersecting with the first type active region semiconductor structure at the first drain region of a second first type transistor.

20. The method for manufacturing an integrated circuit device according to claim 12, characterized in that, Manufacturing the first source conductive segment includes: The first source conductive segment is manufactured to intersect with the first type active region semiconductor structure at the first source region of a second first type transistor.

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