Passive electrostatic discharge sensor and method for detecting electrostatic discharge

Abstract

Embodiments of the present disclosure relate to a passive electrostatic discharge sensor and a method for detecting electrostatic discharge. An integrated circuit is formed from a semiconductor component having a semiconductor substrate and an interconnect component including a metal layer. The electrostatic discharge sensor includes a semiconductor structure in the semiconductor component and a metal antenna network in the interconnect component. The electrostatic discharge sensor has at least one pair of two nodes having one of a resistive link or a capacitive link or a PN junction link in the semiconductor structure. An antenna of the antenna network coupled to a node of the at least one pair of two nodes exhibits one of a shape asymmetry and a size asymmetry.

Description

[0001] Priority requirements

[0002] This application claims priority to French patent application No. 2105435, filed on May 25, 2021, the entire contents of which are incorporated herein by reference to the fullest extent permitted by law. Technical Field

[0003] The specific implementation methods and embodiments relate to integrated circuits, and more particularly to integrated circuits including electrostatic discharge sensors. Background Technology

[0004] Electrostatic discharge (ESD) can occur during steps in the fabrication of integrated circuits and degrade components of the integrated circuit. For example, methods used for plasma etching can generate charges on the physical nodes of devices in an integrated circuit, such as metal-oxide-semiconductor (MOS) transistors. The accumulation of ESD on the physical nodes of the device can create a potential difference between these nodes, which can cause degradation (breakdown) of the material present between the nodes during ESD.

[0005] This type of degradation is largely random, and it is desirable to be able to detect, identify, and quantify electrostatic discharge phenomena, for example, during the testing and characterization of products.

[0006] Therefore, methods for quantifying the risk of electrostatic discharge (ESD) damage to integrated circuits, such as those based on a charged device model (CDM), may include stages in which the nodes of the device are charged to a given voltage and then discharged. Depending on the discharge dynamics of each node, the potential difference between two nodes may degrade due to ESD.

[0007] The goal here is also to be able to detect, identify, and quantify electrostatic discharge phenomena.

[0008] Conventional preventative solutions exist for electrostatic discharge (ESD) problems, such as allowing ESD to be locally discharged via a dedicated diode. However, this type of preventative and localized solution does not allow for the identification and quantification of ESD.

[0009] Conventional detection solutions can identify degradation occurring in test equipment, but are generally not very sensitive and have limited measurement possibilities. For example, when testing a MOS transistor, gate oxide breakdown can be detected, but degradation of the conductive or gate regions cannot be measured individually. Therefore, the characteristics of components in an integrated circuit can deviate slightly and undetectably individually, but significantly across the entire product (this deviation is often referred to as "corner effect"), without the need for conventional solutions to detect such deviations.

[0010] Therefore, there is a need in the art for integrated circuits equipped with electrostatic discharge sensors that can detect various types of characteristic degradation and deviations with increased sensitivity. Summary of the Invention

[0011] According to one aspect, an integrated circuit is proposed that includes: a semiconductor component including a semiconductor substrate; an interconnect component including a metal layer; and an electrostatic discharge sensor including a semiconductor structure in the semiconductor component and a metal antenna network in the interconnect component, the sensor including at least one pair of nodes having a resistive link, a capacitive link, or a PN junction link in the semiconductor structure; and antennas of the antenna network having shape asymmetry and / or size asymmetry, the antennas of the antenna network being respectively connected to the nodes of each pair.

[0012] The asymmetry in shape and size of the antennas connected to the two nodes of each pair of sensors allows for the amplification of differences in the accumulation of electrostatic charge on the physical nodes of the sensors, and thus amplifies the potential differences between these nodes, which can cause material degradation between the nodes during electrostatic discharge.

[0013] Similarly, the shape and size asymmetry of the antenna can amplify the differences in the discharge dynamics of the corresponding nodes, thereby amplifying the potential differences that occur during the discharge of the nodes, which can lead to material degradation between the nodes through electrostatic discharge.

[0014] Therefore, phenomena leading to relatively weak electrostatic discharge (charge accumulation or differences in discharge kinetics) are amplified and can be detected by the degradation of materials between the nodes of the sensor pair. Relatively weak electrostatic discharge is one that can cause deviations in link characteristics without observable deterioration. Therefore, the sensor proposed according to this aspect has increased sensitivity.

[0015] Furthermore, the various types of links between possible pairs of nodes of the sensor allow for a large number of measurements that can represent a variety of phenomena that generate electrostatic discharge. For example, a node can be dedicated to a single pair of two nodes with a given link (resistive, capacitive, PN junction) between them, or conversely, the node can belong to several pairs of two nodes with different or different links (resistive, capacitive, PN junction) between them.

[0016] In one implementation, the antennas connected to each pair of nodes are asymmetrical in size, with the ratio of their surface areas being greater than or equal to 10. In effect, the size difference (asymmetry) between the two antennas connected to the two nodes of the sensor pair introduces a substantially proportional difference in charge accumulation between the two nodes of that pair. The antenna size also affects the discharge dynamics of the pair of nodes.

[0017] According to one implementation, the antennas connected to each pair of nodes are asymmetrical in shape, with one antenna having the shape of a rake including branches adapted to pass through several surface units in the corresponding metal layer, while the other antenna has the shape of a plate covering only one surface unit in the corresponding metal layer.

[0018] In fact, the rake shape extends further than the plate shape, allowing for more comprehensive charge accumulation in various regions than in localized areas of a plate. Therefore, the shape difference (asymmetry) between the two antennas connected to the two nodes of the sensor pair also introduces a difference in charge accumulation between the two nodes of the pair.

[0019] According to one embodiment, the integrated circuit includes multiple electrostatic discharge (ESD) sensors, each with an antenna network located on a corresponding metal layer. This allows, for example, identification of whether one metal layer is more likely to cause ESD than another.

[0020] According to one embodiment, the semiconductor structure includes a polycrystalline silicon strip located on the front surface of a semiconductor substrate.

[0021] According to one embodiment, the at least one pair of sensors includes a pair of two nodes with a resistive link, wherein a polysilicon strip forms a resistive link between the nodes of the pair.

[0022] According to one embodiment, a dielectric layer is located between a polysilicon strip and a semiconductor substrate, and the at least one pair of sensors includes a pair of two nodes with a capacitive link, wherein the overlap of the polysilicon strip, the dielectric layer and the semiconductor substrate forms a capacitive link between the nodes of the pair.

[0023] According to one embodiment, the semiconductor structure includes at least one doped region in a semiconductor substrate.

[0024] According to one embodiment, the at least one doped region includes a surface layer of a half-metal compound, and the at least one pair of sensors includes a pair of two nodes with a resistive link, the surface layer of the metal compound forming the resistive link between the nodes of the pair.

[0025] Half-metal compounds, also known as intermetallic compounds, are the association of metallic and semiconductor materials through chemical bonds, such as metal silicides, typically copper or tungsten silicides.

[0026] According to one embodiment, the semiconductor structure includes a first doped region of a first type in a semiconductor substrate and a second doped region of a second type in a semiconductor substrate opposite to the first doped region, the at least one pair of sensors including a pair of two nodes having a PN junction link, the interface between the first doped region and the second doped region forming the PN junction link between the nodes of the pair.

[0027] According to one implementation, the semiconductor structure includes a buried oxide region between a semiconductor substrate and a carrier substrate, and the at least one pair of sensors includes a pair of nodes with a capacitive link, wherein the overlap of the semiconductor substrate, the buried oxide region and the carrier substrate forms a capacitive link between the nodes of the pair.

[0028] This corresponds to silicon-on-insulator (SOI) type substrates, where the capacitive interface between the carrier substrate (called the "back gate") and the semiconductor substrate serves as a capacitive link between nodes of a pair of sensors.

[0029] According to another aspect, a method for detecting electrostatic discharge is proposed, the method comprising the fabrication of an integrated circuit as defined above, a measurement step including characterization of the link between the at least one pair of nodes, and a determination step including a comparison between the measured characterization and the nominal characteristics of the corresponding resistance, capacitance or PN junction link.

[0030] According to one embodiment, the fabrication of the metal layer includes exposing the antenna network to a charged plasma environment.

[0031] According to one embodiment, the manufacture of the electrostatic discharge sensor is carried out simultaneously with the manufacture of other components of the integrated circuit, and the determination step includes assessing the damage caused in other components of the integrated circuit based on the deviation between the measured characterization and the nominal characteristics of the corresponding link, as well as the size asymmetry and / or shape asymmetry of the antenna coupled to the corresponding node, in the event of a deviation between the measured characterization and the nominal characteristics of the corresponding link. Attached Figure Description

[0032] Other advantages and features of the invention will become apparent upon examination of the detailed description (in no way limiting) of the specific embodiments and examples, as well as the accompanying drawings, in which:

[0033] Figure 1 and Figure 2 An example of an electrostatic discharge sensor is shown;

[0034] Figure 3 It can be shown schematically, such as Figure 1 and 2 Representation of the sensor circuitry in the diagram;

[0035] Figures 4 to 7 An example of a link between two nodes in a "separate" pair of electrostatic discharge detectors is shown, along with the electrical characteristics of each link; and

[0036] Figure 8 A method for detecting electrostatic discharge is shown. Detailed Implementation

[0037] Figure 1 and Figure 2 An example of an electrostatic discharge sensor SNS belonging to integrated circuit C1 is shown.

[0038] Figure 1 The top view corresponds to the sensor SNS located on the front surface FA of the semiconductor substrate. The sensor SNS is a semiconductor component of the integrated circuit CI, which is referred to as and labeled as the front-end process FEOL. Furthermore, the antenna network RANT of the sensor SNS is located in a plane parallel to the plane of the front surface FA, and is also schematically shown in the top view.

[0039] Figure 2 The cross-sectional view corresponding to the sensor SNS shows the interconnection between the semiconductor component FEOL and the integrated circuit CI, which is referred to as and labeled as the back-end process BEOL.

[0040] The sensor SNS is a passive type of sensor, meaning that it is not intended to function when the integrated circuit is powered and operated, but rather to withstand possible electrostatic discharges that could modify the structure of the sensor SNS. The structural modifications are then observed to deduce and characterize the electrostatic discharges occurring in the integrated circuit C1.

[0041] An electrostatic discharge sensor SNS includes a semiconductor structure SSM fabricated in a semiconductor component FEOL of an integrated circuit, and a network of metal antennas RANT fabricated in one or more layers of metal M1 of an interconnect component BEOL.

[0042] Semiconductor structures (SSMs) are designed to modify the structure to detect electrostatic discharge (ESD), while antenna networks (RANTs) are designed to collect charge or influence the discharge dynamics of nodes to generate ESD in semiconductor structures (SSMs).

[0043] In this respect, the sensor includes at least one pair of two nodes ND1, NS1, NG1, NB1, ND2, NS2, NG2, NB2, which have resistive links, capacitive links, or PN junction links in the semiconductor structure SSM, and antennas AD1, AS1, AG1, AB1, AD2, AS2, AG2, AB2 of the antenna network RANT are connected to each node of the semiconductor structure SSM.

[0044] The antennas of the antenna network RANT are connected to the nodes via conventional contact posts (CNTs) and pass through a pre-metal dielectric layer (PMD) located between the semiconductor component FEOL and the interconnect component BEOL. The front surface FA of the semiconductor substrate is defined as the surface where the pre-metal dielectric layer PMD is located, that is, the surface where the components of the semiconductor component FEOL are located.

[0045] The antenna network (RANT) of the sensor SNS can be formed in a single metal layer, such as the first metal layer M1, or it can be formed in several metal layers.

[0046] Metal layers M1, M2, and M3 are vertically separated by intermetallic dielectric layers IMD1, IMD2, and IMD3. The metal rails of each metal layer M2 and M3 can be electrically connected through vias V23 and V34 that pass vertically through the intermetallic dielectric layers IMD2 and IMD3.

[0047] Furthermore, the integrated circuit CI can advantageously include multiple electrostatic discharge sensors SNS as described herein, with the antenna network RANT of each sensor located in the corresponding metal level. This allows for the use of information about the electrostatic discharge relative to each metal level, and thus enables the identification of the location where the electrostatic discharge occurs.

[0048] Furthermore, the antenna pairs AD1, AS1, AG1, AB1, AD2, AS2, AG2, AB2 connected to the nodes ND1, NS1, NG1, NB1, ND2, NS2, NG2, NB2 of each pair have shape asymmetry and / or size asymmetry among them.

[0049] Shape asymmetry and size asymmetry allow for imbalances in phenomena that generate electrostatic discharge, and thus amplify their effects in the sensor SNS, enabling their detection with greater sensitivity.

[0050] For example, for a given pair of nodes, such as nodes NG1 and NG2, the antennas AG1 and AG2 connected to these nodes are asymmetrical in size because the ratio of their surface areas is greater than or equal to 10.

[0051] According to another example, for a given pair of nodes such as nodes ND1 and ND2, the antennas AD1 and AD2 connected to these nodes are asymmetrical in shape, with one antenna AD1 having a rake shape including branches adapted to pass through several surface units in the corresponding layer of metal M1, while the other antenna AD2 has a plate shape covering only one surface unit in the corresponding layer of metal M1.

[0052] Therefore, the term "surface unit" defined by the surface occupied by plate AD2 has a relative meaning and does not correspond to a given or defined absolute size.

[0053] On the one hand, the asymmetry in the shape and size of the antenna allows for an imbalance in the amount of charge accumulated at each of the two corresponding nodes, and thus amplifies the potential difference between these nodes caused by the accumulation.

[0054] In retrospect, charge accumulation can be caused, in particular, by etching steps in a plasma environment used during the fabrication of the metal rails at the M1-M3 levels of the interconnect component BEOL.

[0055] On the other hand, the shape and size asymmetry of the antenna allows the discharge dynamics of the corresponding node to become unbalanced after polarization at a given voltage, and thus amplifies the potential difference generated during the discharge of the node.

[0056] Recall that the polarization of circuit nodes at a given voltage can be provided during the testing and characterization phase of integrated circuits, particularly based on the CDM charging device model.

[0057] These amplified potential differences between the nodes generate electrostatic discharges, and the damage is also amplified in the material forming the corresponding links between the nodes.

[0058] Therefore, the sensor SNS has increased sensitivity and is particularly capable of detecting electrostatic discharges, which typically (i.e., without amplification) cause deviations in link characteristics without observable degradation.

[0059] Furthermore, in the semiconductor region FEOL, different types of links between nodes of different pairs of sensor SNS allow for the use of multiple measurements, which can represent different phenomena that generate electrostatic discharge.

[0060] Figure 1 and Figure 2 The semiconductor structure SSM shown is a favorable example of a MOS (metal-oxide-semiconductor) type structure, which allows for a variety of combinations of nodes connected to the various antennas, with resistive links, capacitive links, or PN junction links between them, and its characteristics can vary depending on the selected pair.

[0061] In fact, in this example, the semiconductor structure SSM is equivalent to a MOS transistor and includes a conductive strip of polysilicon G on the front surface FA of the semiconductor substrate B, and two implantation regions S and D in the semiconductor substrate B.

[0062] The dielectric layer OX is also located between the polysilicon strip G and the semiconductor substrate B, such as the gate region and gate oxide of a MOS transistor.

[0063] Semiconductor substrate B forms a first doped region of a first type (e.g., P-type), which is typically referred to as the host or ground in similar MOS transistors, and implantation regions S and D form a second doped region of a second type (e.g., N-type) opposite to the first type, which is similar to the source S and drain D regions of a MOS transistor.

[0064] Furthermore, in the example shown, the substrate is of the silicon-on-insulator (SOI) type, meaning that the substrate B on which the semiconductor components (such as the semiconductor structure SSM of a MOS transistor or sensor SNS) are fabricated are relatively fine (thin) semiconductor layers (silicon), separated from the carrier substrate SP by the buried oxide region BOX.

[0065] This example of an SOI substrate specifically allows for the use of capacitive links formed by overlapping a semiconductor substrate B, a buried oxide region BOX, and a carrier substrate SP between two nodes of a pair.

[0066] In other words, traditional substrates, namely the volume or bulk of crystalline silicon that typically does not include the buried oxide region (BOX), are perfectly suitable for sensor SNS.

[0067] A semiconductor structure SSM may, for example, include two nodes formed in each of the aforementioned regions. Each node is implemented, for example, by a contact post CNT that electrically connects the region of the semiconductor component FEOL to the first metal layer M1 of the interconnect component BEOL.

[0068] Therefore, the semiconductor structure SSM of the sensor SNS includes two nodes NG1 and NG2, which will be referred to as "gate nodes," contacting the strip of polysilicon G. The gate nodes NG1 and NG2 can be advantageously arranged at the antipodal position of the strip G, that is, at the position that maximizes the distance between nodes NG1 and NG2.

[0069] Because it is conductive, the polysilicon strip G establishes a resistive link between the two gate nodes NG1 and NG2.

[0070] For example, the "strip" of polysilicon G can have a shape that is not strictly a strip when viewed from top (i.e., a rectangular outline in the literal sense), but rather a combination of H-shapes, for example, with two parallel branches and a vertical branch, with one of the gate nodes NG1, NG2 connected to each branch. Any other shape is also possible.

[0071] In addition, the second doped regions S and D, referred to as the source region S and drain region D, include a surface layer of a half-metal compound SMS, SMD, which is often referred to as "silicide," meaning "self-aligned silicide," typically a silicide of a metal such as copper or tungsten.

[0072] The semiconductor structure SSM of the sensor SNS includes two nodes ND1 and ND2 that are in contact with the drain region D. These two nodes will be referred to as "drain nodes" and can be set at the furthest possible distance from each other according to the design rules in the drain region D.

[0073] The surface layer of the metal compound SMD in the drain region D establishes a resistive link between the two drain nodes ND1 and ND2.

[0074] The semiconductor structure SSM of the sensor SNS includes two nodes NS1 and NS2 that are in contact with the source region S, which will be referred to as the "source node".

[0075] In this particular example, source nodes NS1 and NS2 are not connected to the asymmetric antenna, but rather to the same antenna AS, referred to as the source antenna. Therefore, in the sense of the architecture of the sensor SNS described herein, source nodes NS1 and NS2 in this particular example do not form a pair of nodes. That is, in the sense of the structure of the sensor SNS described herein, source nodes NS1 and NS2 considered together can form one of two nodes in a pair, connected to another node of the antenna that has shape and / or size asymmetry with the source antenna AS.

[0076] For example, the set of source nodes NS1 and NS2 can form the first node of a node pair with one of the drain nodes ND1 and ND2, which has a PN junction link. The source antenna AS has shape asymmetry and / or size asymmetry, and the antenna is connected to the drain nodes ND1 and ND2 of the pair.

[0077] Alternatively, source nodes NS1 and NS2 can be connected to an asymmetric antenna, thus forming a pair of nodes with a resistive link. The surface layer of the semi-metallic compound SMS in the source region S establishes a resistive link between the two source nodes NS1 and NS2.

[0078] Furthermore, the overlap of the polysilicon strip G, the dielectric layer OX, and the semiconductor substrate B establishes a capacitive link between one of the gate nodes NG1 and NG2 and one of the source nodes NS1 and NS2 or one of the drain nodes ND1 and ND2.

[0079] However, the spatially closest gate-source or drain node pair may be preferred to avoid introducing resistive components into the link.

[0080] For example, NG1-NS1 and NG2-ND2 may be preferred for their capacitive links.

[0081] The semiconductor structure SSM of the sensor SNS includes two nodes NB1 and NB2 that are in contact with the semiconductor substrate B, which will be referred to as the "substrate nodes".

[0082] A capacitive link is established between the polysilicon strip G, the dielectric layer OX, and the semiconductor substrate B, which overlap at one of the gate nodes NG1 and NG2 and the substrate nodes NB1 and NB2.

[0083] Similarly, the spatially closest gate node-substrate node pairs, namely NG1-NB1 and NG2-NB2, can be preferred.

[0084] Although this possibility is not shown, the metal compound surface layer of substrate B can establish a resistive link between the two substrate nodes NB1 and NB2.

[0085] Finally, the interface between the first doped region B (substrate) and the second doped regions S and D (source and drain regions) establishes a PN junction link between one of the substrate nodes NB1 and NB2 and one of the source nodes NS1 and NS2 or the drain nodes ND1 and ND2.

[0086] Here, the spatially closest node pairs are selected again, especially NB1-NS1, NB1-ND1, NB2-NS2, and NB2-ND2 pairs.

[0087] Therefore, there is a PN junction link between the source nodes NS1, NS2 and the drain nodes ND1, ND2, or more precisely, an NPN double junction.

[0088] Therefore, this example of a MOS-type semiconductor structure SSM has the advantage of allowing for many possible combinations of two node pairs with resistive, capacitive, or PN junction links between them.

[0089] The combination of node pairs can be defined in various ways, especially to parameterize the resistance, capacitance and PN junction link characteristics between them.

[0090] For example, a given node may belong to a single pair of two nodes with a specific link between them; or, a given node may belong to a first pair of two nodes with a first link (e.g., resistivity) between them, and to a second pair of two nodes with a second link (e.g., capacitance) between them, and even further to a third pair of two nodes with a third link (e.g., a PN junction) between them.

[0091] Furthermore, the dimensions of the semiconductor structure SSM of the sensor SNS can be selected in a parameterized manner for the link. For example, the length lg and width wg of the polysilicon strip G can be adjusted in this respect, just like the distance ds between the two source nodes NS1, NS2 and between the two drain nodes ND1, ND2.

[0092] For example, in the 28nm fully depleted silicon-on-insulator (FD-SOI) technology known to those skilled in the art, there can be a width wg between 28nm and 200nm, a length lg between 100nm and 5μm, and a distance ds between 100nm and 2μm.

[0093] Figure 3 This is a circuit representation, schematically illustrating the above regarding... Figure 1 and Figure 2 The aforementioned sensor SNS.

[0094] In practice, the electrostatic discharge sensor SNS comprises a semiconductor structure SSM and a metal antenna network RANT. The semiconductor structure SSM includes a conductive gate region G insulated from a semiconductor substrate B by a dielectric layer, and two doped regions S and D of the opposite doping type to those of the substrate B, implanted in the substrate B on either side of the portion covered by the conductive gate region G. Each of the gate region G and the doped regions S and D of the substrate B includes at least two nodes NS1, NS2, ND1, ND2, NG1, NG2, NB1, NB2, with resistive links RS, RD, RG, RB between them in the corresponding regions S, D, G, B. Antennas AS1, AS2, AD1, AD2, AG1, AG2, AB1, and AB2 of the antenna network RANT are coupled to the nodes. Antennas AG1 and AG2 are coupled to at least one pair of nodes NG1-NG2 with a resistive link RG having asymmetric shape and / or asymmetric size. Antennas AG1 and AB1 are coupled to at least one pair of nodes NG1-NB1 with asymmetric shape and / or asymmetric size. Antennas AD2 and AS2 are coupled to at least one pair of nodes ND2-NS2 with a PN junction link having asymmetric shape and / or asymmetric size.

[0095] On substrate B-BOX-SP ( Figure 2 In the case of SOI (Silicon-on-Insulator) type, the sensor may also include a connection to the carrier substrate SP (Silicon-on-Insulator) in the node. Figure 2 At least one back gate node NBG.

[0096] Figures 4 to 7An example of a link between two nodes in a “separate” pair of electrostatic discharge detectors is shown, along with the electrical characteristics of each link.

[0097] Figures 4 to 6 The curves 400, 500, and 600 show the response of the corresponding links to the electrical stress applied to them. In particular, curves 400, 500, and 600 show the current intensity flowing through the links as a response to an increased voltage ramp.

[0098] Figure 4 The resistive link LRsa1 is shown between two nodes NS / D1 and NS / D2, formed by a surface layer of a semi-metallic compound on the surface of the doped region S / D formed in the semiconductor substrate B.

[0099] Graph 400 shows the characteristics of current (A) relative to voltage (V) of link LRsa1. For small voltage (V) values, the current / voltage ratio is essentially linear until the breakdown voltage, for example, slightly below 2V.

[0100] Beyond the breakdown voltage, the behavior of link LRsa1 is no longer linear and does not follow simple electrical laws, but rather corresponds to degradation of the link material. In particular, silicide migration leads to an increase in resistance up to approximately 6V, where degradation causes the connection to break.

[0101] Figure 5 A resistive link LRpoly is shown between two nodes NG1 and NG2, made of a polycrystalline silicon conductive strip G formed on a semiconductor substrate B.

[0102] The curve 500 shows the characteristics of the current (A) relative to the voltage (V) of the link LRpoly.

[0103] Here, the current / voltage ratio is essentially linear for small voltage (V) values ​​until the breakdown voltage, for example, approximately 3V. Above the breakdown voltage, the behavior of the link LRpoly is no longer linear and does not follow simple electrical laws, but can correspond to degradation phenomena of the link material.

[0104] Figure 6 A capacitive link LC is shown formed between two nodes NG and NB by superimposing a conductive strip and a dielectric layer of polysilicon G on a substrate B.

[0105] Graph 600 shows the characteristics of current (A) relative to voltage (V) of the LC link. The current intensity (A) is zero until a voltage known as the threshold voltage, which is approximately 6V, at which point current leakage occurs at a substantially exponential rate through the dielectric layer until the breakdown voltage is slightly greater than 8V. Beyond the breakdown voltage, the oxide is destroyed, and due to material degradation, the current becomes zero again.

[0106] Figure 7 The diagram illustrates a PN junction link LPN formed between two nodes NS / D and NB, which are respectively connected to regions with relative doping formed in a semiconductor substrate B. One of the regions is, for example, a P-type doped substrate B, while the N-type doped region is an implanted region S / D in substrate B.

[0107] The response of a PN junction link LPN to electrical stress of a voltage ramp type (not shown) will correspond to diode characteristics, that is, in the case of direct polarization, it changes exponentially from the threshold voltage, for example, the threshold voltage is essentially at 0.6V. Apart from the breakdown voltage, for example, between 1V and 1.8V, the behavior of the link LPN does not follow simple electrical laws, but can correspond to degradation phenomena of the link material.

[0108] Furthermore, in the case of reverse polarization, this characteristic will correspond to a zero current response, or negligible leakage current, until a breakdown voltage known as avalanche generates current through the avalanche effect, which can also cause degradation in the material of the link LPN.

[0109] Degradation of the link LPN can result in a short-circuit effect, where the leakage current is several orders of magnitude larger (e.g., approximately 1 μA of leakage current relative to the expected leakage current of approximately 1 nA during non-degrading operation), or optionally, an open-circuit effect, i.e., zero current, depending on the measured optional current limit.

[0110] Figure 8 A method for detecting electrostatic discharge 800 using the aforementioned sensor SNS is shown.

[0111] Testing is performed after the manufacturing of integrated circuit C1 (801), including the manufacturing of other components for the operation of the integrated circuit and the manufacturing of electrostatic discharge sensor SNS.

[0112] Advantageously, the manufacture 801 of the electrostatic discharge sensor SNS can be carried out simultaneously with the manufacture 801 of other components of the integrated circuit C1.

[0113] Specifically, fabricating the 801 metal layer BEOL may include exposing the antenna network RANT to a charged plasma environment. Exposure to a plasma environment can indeed cause damage to integrated circuits caused by electrostatic discharge between circuit nodes.

[0114] In method 800, measurement step 802 includes characterizing the link between nodes of the at least one pair of sensors SNS, and determination step 803 includes comparing the measured characterization with the nominal characteristics of the corresponding resistance, capacitance or PN junction link.

[0115] For example, a link can correspond to the application of voltage values ​​between the pair of nodes and the measurement of current flowing between the pair of nodes.

[0116] For example, characterization can be performed using a measurement device such as an ohmmeter external to the integrated circuit (CI).

[0117] For example, in voltage intervals below the breakdown voltage, the nominal characteristics of the corresponding link can be defined by the behavior represented by curves 400, 500, and 600 corresponding to that link.

[0118] For example, if the current-voltage measurement point of the resistive link LRsal is not on the linear portion of curve 400 between 0V and 2V, it is detected that the link LRsal experienced a potential difference greater than its breakdown voltage during the manufacturing process.

[0119] For example, if the current-voltage measurement point of the resistive link LRpoly is not on the linear portion of curve 500 between 0V and V, it is detected that the link LRpoly has experienced electrostatic discharge greater than its breakdown voltage during the manufacturing process.

[0120] For example, if the current-voltage measurement point of a capacitive link LC is not on the exponential portion of curve 600 between the threshold voltage of 6V and the breakdown voltage of 8V, then the link LC has been detected to have experienced electrostatic discharge greater than its breakdown voltage during the manufacturing process.

[0121] For example, if the current-voltage measurement point of a PN junction link LPN has a leakage current several orders of magnitude lower than the threshold voltage in the forward direction (e.g., a leakage current of about 1 μA relative to the expected leakage current of about 1 nA during non-degrading operation), and a leakage current lower than the avalanche voltage in the reverse direction, then the link LPN has been detected to have undergone electrostatic discharge greater than its breakdown voltage during the manufacturing process.

[0122] Finally, in the event of a discrepancy between the measured feature (802) and the nominal characteristics of the corresponding link, the determination step 803 of the method may advantageously include an assessment of damage caused in other components of the integrated circuit CI.

[0123] In fact, models can be built based on the size of the antenna coupled to the corresponding node and the implementation of other structures of the integrated circuit, which can evaluate the damage caused by other structures of the integrated circuit.

[0124] In fact, the electrostatic discharge phenomenon occurring in the sensor can be quantified, and from this quantification, the amplification obtained by the size and / or shape asymmetry of the individual antenna pairs can be derived, as well as the electrostatic discharge phenomenon occurring in other structures of the integrated circuit.

[0125] In addition, the above regarding Figures 4 to 7 Each of the described links LRsal, LRpoly, LPN, and LC can each form the semiconductor structure SSM of the electrostatic discharge sensor SNS.

[0126] In fact, despite the above regarding Figures 1 to 3 The described example has the advantage of benefiting from a variety of combinations of two node pairs and corresponding link pairs, but it is entirely possible to include only a pair of two nodes with a single specific link between them in a semiconductor structure SSM.

[0127] The semiconductor structure SSM of the sensor SNS can also be made from about Figures 4 to 7 The described links are generated by any combination of LRsal, LRpoly, LPN, LC types, or even by other links such as back-gate capacitive links in a substrate like SOI (Silicon on Insulator) without necessarily leading to... Figures 1 to 3 A "complete" example of the description.

Claims

1. An integrated circuit, comprising: Semiconductor components, including semiconductor substrates; Interconnect components, including metal layers; as well as An electrostatic discharge sensor, comprising a semiconductor structure in the semiconductor component and a metal antenna network in the interconnect component; The electrostatic discharge sensor includes: At least one pair of two nodes, having one of a resistive link, a capacitive link, or a PN junction link in the semiconductor structure; and The first antenna and the second antenna of the antenna network are respectively connected to the at least one pair of nodes, wherein the first antenna and the second antenna have one or more of the following: shape asymmetry and size asymmetry; The electrostatic discharge sensor, in response to sensing an electrostatic discharge, exhibits a structural modification to one of the resistive links, capacitive links, or PN junction links in the semiconductor structure.

2. The integrated circuit of claim 1, wherein the dimensional asymmetry of the first antenna and the second antenna corresponds to a ratio of the surface areas of the first antenna and the second antenna being greater than or equal to 10.

3. The integrated circuit of claim 1, wherein the shape asymmetry of the first antenna and the second antenna corresponds to one of the first antenna and the second antenna having a rake shape including branches that penetrate a plurality of surface units in the corresponding metal layer, and the other of the first antenna and the second antenna having a plate shape that covers only one surface unit in the corresponding metal layer.

4. The integrated circuit of claim 1, wherein the integrated circuit comprises a plurality of electrostatic discharge sensors, and wherein the antenna network for each sensor is located in a corresponding metal layer.

5. The integrated circuit of claim 1, wherein the semiconductor structure comprises a polycrystalline silicon strip located on the front surface of the semiconductor substrate.

6. The integrated circuit of claim 5, wherein the at least one pair of nodes comprises a pair of nodes having the resistive link, wherein the polysilicon strip forms the resistive link between the nodes of the pair.

7. The integrated circuit of claim 5, further comprising a dielectric layer located between the polysilicon strip and the semiconductor substrate, wherein the at least one pair of nodes includes a pair of nodes having the capacitive link, wherein the overlap of the polysilicon strip, the dielectric layer and the semiconductor substrate forms the capacitive link between the pair of nodes.

8. The integrated circuit of claim 1, wherein the semiconductor structure includes at least one doped region in the semiconductor substrate.

9. The integrated circuit of claim 8, wherein the at least one doped region comprises a surface layer made of a half-metal compound, wherein the at least one pair of nodes comprises a pair of nodes having the resistive link, wherein the surface layer of the half-metal compound forms the resistive link between the nodes of the pair.

10. The integrated circuit of claim 1, wherein the semiconductor structure includes a first doped region of a first type in the semiconductor substrate and a second doped region of a second type in the semiconductor substrate opposite to the first type, wherein the at least one pair of nodes includes a pair of nodes having a PN junction link, wherein the interface between the first doped region and the second doped region forms the PN junction link between the nodes of the pair.

11. The integrated circuit of claim 1, wherein the semiconductor structure includes a buried oxide region between the semiconductor substrate and the carrier substrate, wherein the at least one pair of nodes includes a pair of nodes having the capacitive link, wherein the overlap of the semiconductor substrate, the buried oxide region and the carrier substrate forms the capacitive link between the nodes of the pair.

12. A method for sensing electrostatic discharge, comprising: Manufacture the integrated circuit according to claim 1; Measure the characteristics of the link between the at least one pair of nodes; The measured characteristics are compared with the nominal characteristics of the corresponding resistive link, capacitive link, or PN junction link of the electrostatic discharge to detect the structural modification. as well as The electrostatic discharge is sensed in response to the detection of the structural modification.

13. The method of claim 12, wherein manufacturing the integrated circuit includes manufacturing the interconnect components comprising a metal layer, wherein the antenna network is exposed to a charged plasma environment.

14. The method of claim 12, wherein manufacturing is performed concurrently with the manufacturing of other components of the integrated circuit, and wherein the determination of the divergence between the measured characteristic and the nominal characteristic includes assessing damage in the other components of the integrated circuit based on the divergence and the asymmetry of the size and / or shape of the antenna coupled to the corresponding node.

15. An integrated circuit, comprising: A semiconductor substrate comprising at least one pair of two nodes, wherein the at least one pair of two nodes has one of a resistive link, a capacitive link, or a PN junction link; A first antenna and a second antenna are formed in a plurality of metal layers on the semiconductor substrate, and the first antenna and the second antenna are respectively connected to the at least one pair of nodes; The first antenna and the second antenna have one or more of shape asymmetry and size asymmetry, and the first antenna and the second antenna are configured to generate electrostatic discharge on one of the resistive link, the capacitive link or the PN junction link in response to antenna charge collection; The resistive link, the capacitive link, or the PN junction link is configured to be structurally modified in response to the electrostatic discharge.

16. The integrated circuit of claim 15, further comprising a polysilicon strip located on the front surface of the semiconductor substrate and formed as a resistive link between the at least one pair of nodes.

17. The integrated circuit of claim 15, further comprising a polysilicon strip located on the front surface of the semiconductor substrate, and a dielectric layer located between the polysilicon strip and the semiconductor substrate, wherein the overlap of the polysilicon strip, the dielectric layer and the semiconductor substrate forms the capacitive link between the at least one pair of nodes.

18. The integrated circuit of claim 15, further comprising at least one doped region in the semiconductor substrate, and the surface layer of the at least one doped region being made of a half-metal compound, wherein the surface layer of the half-metal compound forms the resistive link between the at least one pair of nodes.

19. The integrated circuit of claim 15, further comprising a first doped region of a first type in the semiconductor substrate and a second doped region of a second type in the semiconductor substrate opposite to the first type, wherein the PN junction link between the at least one pair of nodes is formed at the interface between the first doped region and the second doped region.

20. The integrated circuit of claim 15, further comprising a buried oxide region between the semiconductor substrate and the carrier substrate, wherein the overlap of the semiconductor substrate, the buried oxide region and the carrier substrate forms the capacitive link between the at least one pair of nodes.

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