Electrostatic protection structure

Abstract

The application provides a static protection structure, which comprises a semiconductor substrate, a first well region and a second well region arranged adjacent to the first well region, a first doped region formed in a surface layer at a junction of the first well region and the second well region, a second doped region formed in a surface layer of the first well region, a third doped region formed in a surface layer of the second well region, and a MOS tube comprising a gate, a drain region and a source region, formed between the first doped region and the second doped region or between the first doped region and the third doped region, and the gate and the drain region are short-circuited with the first doped region. The application solves the problem of low voltage maintenance and easy occurrence of latch effect of the existing SCR static protection structure.

Description

Technical Field

[0001] This invention relates to the field of electrostatic discharge (ESD) protection devices, and in particular to an ESD protection structure. Background Technology

[0002] Semiconductor chips are susceptible to damage from electrostatic discharge (ESD) during manufacturing, testing, packaging, transportation, and use, resulting in losses. Currently, silicon controlled rectifier (SCR) devices, formed by PNP and NPN coupling, are used for ESD protection due to their advantages of low holding voltage and low on-resistance.

[0003] SCR (Self-Device Response) devices can conduct large amounts of current, allowing excess charge to be discharged quickly and preventing damage to internal circuitry. Furthermore, they achieve a high level of ESD protection with only a small portion of the chip area. However, existing conventional SCR devices have a low sustaining voltage, lower than the operating voltage (VDD), making them prone to latch-up and potentially causing chip burnout. Summary of the Invention

[0004] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide an electrostatic protection structure to solve the problem that the existing SCR electrostatic protection structure has a low maintenance voltage and is prone to latch-up effect.

[0005] To achieve the above and other related objectives, the present invention provides an electrostatic protection structure, the structure comprising:

[0006] A semiconductor substrate having a first well region and a second well region disposed adjacent to the first well region;

[0007] The first doped region is formed in the surface layer at the junction of the first well region and the second well region;

[0008] The second doped region is formed on the surface of the first well region;

[0009] The third doped region is formed on the surface of the second well region;

[0010] A MOS transistor includes a gate, a drain region, and a source region, formed between the first doped region and the second doped region or between the first doped region and the third doped region, wherein the gate and the drain region are shorted to the first doped region;

[0011] Specifically, when the MOS transistor is formed between the first doped region and the second doped region, the source region and the second doped region are connected to a first voltage; when the MOS transistor is formed between the first doped region and the third doped region, the source region and the third doped region are connected to a second voltage.

[0012] Optionally, the MOS transistor formed between the first doped region and the second doped region is a PMOS transistor.

[0013] Optionally, the first well region is an N-well, and the second well region is a P-well; the first doped region and the second doped region have the same ion doping type, both being N-type; and the third doped region has the same ion doping type, P-type.

[0014] Optionally, the structure further includes a fourth doped region formed in the surface layer of the second well region, located between the first doped region and the third doped region, and connected to the second voltage.

[0015] Optionally, the ion doping type of the fourth doped region is N-type.

[0016] Optionally, the MOS transistor formed between the first doped region and the third doped region is an NMOS transistor.

[0017] Optionally, the first well region is an N-well, and the second well region is a P-well; the first doped region and the third doped region have the same ion doping type, which is P-type; the second doped region has an N-type ion doping type.

[0018] Optionally, the structure further includes a fifth doped region formed in the surface layer of the first well region, located between the first doped region and the second doped region, and connected to the first voltage.

[0019] Optionally, the ion doping type of the fifth doped region is P-type.

[0020] Optionally, the MOS transistor further includes an LDD region formed on both sides of the gate of the MOS transistor and extending partially below the gate.

[0021] Optionally, the ion doping type of the LDD region is the same as the ion doping type of the source region and the drain region of the MOS transistor.

[0022] As described above, the electrostatic protection structure of the present invention effectively reduces the on-resistance of the device structure and increases the holding voltage by embedding a PMOS transistor in the N-type well region or an NMOS transistor in the P-type well region, thereby avoiding latch-up effects. Attached Figure Description

[0023] Figure 1The diagram shown is a cross-sectional view of the electrostatic protection structure provided in Embodiment 1 of the present invention.

[0024] Figures 2-6 The diagram shown is a cross-sectional view of the preparation process of the electrostatic protection structure provided in Embodiment 1 of the present invention.

[0025] Figure 7 This shows a cross-sectional structure and an equivalent circuit diagram of the electrostatic protection structure provided in Embodiment 1 of the present invention.

[0026] Figure 8 The diagram shown is a cross-sectional view of the electrostatic protection structure provided in Embodiment 2 of the present invention.

[0027] Figure 9 The diagram shown is a cross-sectional view of the electrostatic protection structure provided in Embodiment 2 of the present invention and a schematic diagram of its equivalent circuit.

[0028] Explanation of icon numbers

[0029] 10: Semiconductor substrate; 11: First well region; 12: Second well region; 21: First doped region; 22: Second doped region; 23: Third doped region; 24: Fourth doped region; 25: Fifth doped region; 30: PMOS transistor; 31: First gate; 32: First drain region; 33: First source region; 34: First LDD region; 40: Shallow trench isolation structure; 50: NMOS transistor; 51: Second gate; 52: Second drain region; 53: Third source region; 54: Second LDD region Detailed Implementation

[0030] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0031] Please see Figures 1 to 9 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Although the illustrations only show components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation, the shape, quantity and proportion of each component in the actual implementation can be arbitrarily changed, and the layout of the components may also be more complex.

[0032] like Figure 6 and Figure 8 As shown, this embodiment provides an electrostatic protection structure, the structure comprising:

[0033] The semiconductor substrate 10 has a first well region 11 and a second well region 12 disposed adjacent to the first well region 11;

[0034] The first doped region 21 is formed in the surface layer at the junction of the first well region 11 and the second well region 12;

[0035] The second doped region 22 is formed in the surface layer of the first well region 11;

[0036] The third doped region 23 is formed in the surface layer of the second well region 12;

[0037] A MOS transistor, including a gate, a drain region and a source region, is formed between the first doped region 21 and the second doped region 22 or between the first doped region 21 and the third doped region 23, and the gate and the drain region are shorted to the first doped region 21.

[0038] When the MOS transistor is formed between the first doped region 21 and the second doped region 22, the source region and the second doped region 22 are connected to the first voltage VDD. When the MOS transistor is formed between the first doped region 21 and the third doped region 23, the source region and the third doped region 23 are connected to the second voltage.

[0039] In this embodiment, the semiconductor substrate 10 is a P-type substrate. The first voltage VDD is the operating voltage, and the second voltage VSS is the ground voltage.

[0040] Specifically, the MOS transistor also includes an LDD region, which is formed on both sides of the gate of the MOS transistor and extends partially below the gate.

[0041] As an example, the ion doping type of the LDD region is the same as that of the source and drain regions of the MOS transistor. In this embodiment, the LDD region is a lightly doped drain region to improve the reliability of the device.

[0042] Example 1

[0043] Specifically, the MOS transistor formed between the first doped region 21 and the second doped region 22 is a PMOS transistor 30.

[0044] like Figure 7As shown, in this embodiment, the gate of the PMOS transistor 30 is a first gate 31, its drain region is a first drain region 32, and its source region is a first source region 33. The first gate 31 and the first drain region 32 are shorted to the first doped region 21 through a metal interconnect layer formed on the surface of the semiconductor substrate 10. The first source region 33 is connected to the first voltage VDD through the metal interconnect layer. At this time, the LDD region is a first LDD region 34, and its ion doping type is P-type, which is used to improve the reliability of the PMOS transistor 30.

[0045] Specifically, the first well region 11 is an N-well, and the second well region 12 is a P-well; the first doped region 21 and the second doped region 22 have the same ion doping type, both being N-type; and the third doped region 23 has the same ion doping type, being P-type.

[0046] Specifically, the structure further includes a fourth doped region 24, which is formed in the surface layer of the second well region 12 and located between the first doped region 21 and the third doped region 23, and is connected to the second voltage VSS.

[0047] Specifically, the ion doping type of the fourth doped region 24 is N-type.

[0048] As an example, the structure further includes a shallow trench isolation structure 40, which is formed in the first well region 11 and located between the PMOS transistor 30 and the first doped region 21 and the second doped region 22, and is formed in the second well region 12 and located between the fourth doped region 24 and the first doped region 21 and the third doped region 23.

[0049] Furthermore, in this embodiment, the shallow trench isolation structure 40 is also formed in the first well region 11 and located on the side of the second doped region 22 away from the PMOS transistor 30, and formed in the second well region 12 and located on the side of the third doped region 23 away from the fourth doped region 24.

[0050] The specific fabrication method of the electrostatic protection structure in this embodiment includes: providing a semiconductor substrate 10, and forming the shallow trench isolation structure 40 (e.g., ...) within the semiconductor substrate 10. Figure 1 (as shown); the first well region 11 and the second well region 12 are formed by ion implantation (as shown). Figure 2 (as shown); the first gate 31 of the PMOS transistor 30 is formed on the surface of the first well region 11 (as shown). Figure 3 (as shown); the first LDD region 34 is formed by ion implantation (as shown). Figure 4(As shown); the first source region 33 and the first drain region 32 of the PMOS transistor 30 are formed by ion implantation, and the third doped region 23 is formed in the surface layer of the second well region 12 (as shown). Figure 5 (As shown); the first doped region 21 is formed at the junction of the first well region 11 and the second well region 12 by ion implantation, the second doped region 22 is formed in the surface layer of the first well region 11, and the fourth doped region 24 is formed in the surface layer of the second well region 12 (as shown). Figure 6 As shown); the metal connection layer is formed on the surface of the device structure formed in the above steps. The metal connection layer is used to realize the connection between the first source region 33 and the second doped region 22 of the PMOS transistor 30 and the first voltage VDD, the short circuit between the first gate 31, the first drain region 32 and the first doped region 21 of the PMOS transistor 30, and the connection between the fourth doped region 24 and the third doped region 23 and the second voltage VSS.

[0051] In this embodiment, a PMOS transistor 30 is embedded in the first well region 11 (N-well), and the first source region 33 of the PMOS transistor 30 is shorted to the first voltage (VDD), and its first gate 31 and first drain region 32 are shorted to the first doped region 21. When the ESD voltage is applied to the VDD terminal, the following states will occur:

[0052] 1) When the ESD voltage is low, the first source region 33, the first well region 11 (NW), the first doped region 21, the second well region 12 (PW), and the fourth doped region 24 are reverse biased, and there is only a small reverse bias leakage current in the device.

[0053] 2) When ESD increases to the breakdown voltage of the first doped region 21 and the second well region 12 (PW), avalanche breakdown occurs, and the internal current of the device increases instantaneously. When the on-state voltage drop Vgs in the first well region 11 (NW) is greater than the turn-on voltage (Vth) of the internal PMOS transistor 30, the PMOS transistor 30 turns on, and the current flows from the channel, the first drain region 32 of the PMOS transistor 30, the metal interconnect, and the first doped region 21 into the second well region 12 (PW) (e.g. Figure 7 The dashed line indicates the direction of the current, where the on-state voltage drop is equivalent to Vgs = I*(R). NW1 +R NW2 ), where I represents the internal current of the device.

[0054] 3) As the ESD voltage continues to increase, due to the parasitic resistance R of the second well region 12 (PW) PW1 R PW2The presence of this makes it easy for the on-state voltage difference to exceed the 0.7V voltage difference between the base and emitter of the parasitic NPN transistors Q2 and Q3. Therefore, Q2 and Q3 turn on. Similarly, the parasitic PNP transistor Q1 in the first well region 11 (NW) will also turn on, thus forming a complete PNPN SCR bleed channel (such as...). Figure 7 The solid line indicates the direction of the current.

[0055] The PMOS transistor has two functions: it can reduce the on-resistance. After the PMOS transistor is turned on, part of the current will flow from the first drain region, the metal interconnect, and the first doped region of the PMOS transistor into the second well region (PW) and enter the second voltage (VSS). Compared with the first well region (NW), the first doped region, the second well region (PW) to the second voltage (VSS), the on-resistance is much smaller. It can also improve the sustaining voltage. After the PMOS transistor is turned on, it bypasses the base current of the PNP transistor Q1 (the first source region, the first well region, and the second well region of the PMOS transistor), which is equivalent to reducing the base transport efficiency, thereby reducing the current gain of the PNP transistor Q1 and improving the sustaining voltage of the SCR.

[0056] Example 2

[0057] Specifically, the MOS transistor formed between the first doped region 21 and the third doped region 23 is an NMOS transistor 50.

[0058] In this embodiment, the gate of the NMOS transistor 50 is a second gate 51, the drain region of the NMOS transistor 50 is a second drain region 52, and the source region of the NMOS transistor 50 is a second source region 53. The second gate 51 and the second drain region 52 are shorted by a metal interconnect layer formed on the surface of the semiconductor substrate 10, and the second source region 53 is connected to the second voltage VSS through the metal interconnect layer. At this time, the LDD region is a second LDD region 54, and its ion doping type is N-type, which is used to improve the reliability of the NMOS transistor 50.

[0059] Specifically, the first well region 11 is an N-well, and the second well region 12 is a P-well; the first doped region 21 and the third doped region 23 have the same ion doping type, which is P-type; the second doped region 22 has an N-type ion doping type.

[0060] Specifically, the structure further includes a fifth doped region 25, which is formed in the surface layer of the first well region 11 and located between the first doped region 21 and the second doped region 22, and is connected to the first voltage VDD.

[0061] Specifically, the ion doping type of the fifth doped region 25 is P-type.

[0062] The specific fabrication method of the electrostatic protection structure in this embodiment includes: providing a semiconductor substrate 10 and forming the shallow trench isolation structure 40 within the semiconductor substrate 10; forming the first well region 11 and the second well region 12 by ion implantation; forming the second gate 51 of the NMOS transistor 50 on the surface of the first well region 11; forming the second LDD region 54 by ion implantation; forming the second source region 53 and the second drain region 52 of the NMOS transistor 50 by ion implantation, and forming the second doped region 22 in the surface layer of the first well region 11; and forming the second doped region 22 in the first well region 11 and the second well region 54 by ion implantation. The first doped region 21 is formed at the junction of 12, and the fifth doped region 25 is formed in the surface layer of the first well region 11, and the third doped region 23 is formed in the surface layer of the second well region 12; the metal connection layer is formed on the surface of the device structure formed in the above steps, and the metal connection layer is used to realize the connection between the first source region 33 and the third doped region 23 of the NMOS transistor 50 and the first voltage VSS, the short circuit between the second gate 51, the second drain region 52 and the first doped region 21 of the NMOS transistor 50, and the connection between the fifth doped region 25 and the second doped region 22 and the first voltage VDD.

[0063] In this embodiment, an NMOS transistor 50 is embedded in the second well region 12 (P-well), and the second source region 53 of the NMOS transistor 50 is shorted to the second voltage (VSS), and its second gate 51, second drain region 52, and first doped region 21 are shorted. When the ESD voltage is applied to the VDD terminal, the following states will occur:

[0064] 1) When the ESD voltage is small, the fifth doped region 25, the first well region 11 (NW), the first doped region 21, the second well region 12 (PW), and the second source region 53 are reverse biased, and there is only a small reverse bias leakage current in the device.

[0065] 2) When ESD increases the breakdown voltage of the first doped region 21 and the second well region 12 (PW), avalanche breakdown occurs, and the internal current of the device increases instantaneously. When the on-state voltage drop Vgs in the second well region 12 (PW) is greater than the turn-on voltage (Vth) of the internal NMOS transistor 50, the NMOS transistor 50 turns on, and the current flows from the first doped region 21, the metal interconnect, the second drain region 52 of the NMOS transistor 50, and the channel into the second source region 53 of the NMOS transistor 50 (e.g., ...). Figure 9 (The dashed line indicates the direction of the current).

[0066] 3) As the ESD voltage continues to increase, due to the parasitic resistance R of the second well region 12 (PW) PW1 R PW2The presence of this makes it easy for the on-state voltage difference to exceed the 0.7V voltage difference between the base and emitter of the parasitic NPN transistors Q2 and Q3. Therefore, Q2 and Q3 turn on. Similarly, the parasitic PNP transistor Q1 in the first well region 11 (NW) will also turn on, thus forming a complete PNPN SCR bleed channel (such as...). Figure 9 (The solid line indicates the direction of the current).

[0067] The NMOS transistor has two functions: it can reduce the on-resistance. After the NMOS transistor is turned on, part of the current will flow from the first doped region, metal interconnect, second drain region, and channel of the NMOS transistor into the second source region of the NMOS transistor. Compared with the first well region (NW), first doped region, second well region (PW) to the second voltage (VSS), the on-resistance is much smaller. It can also improve the sustaining voltage. After the NMOS transistor is turned on, the base current of the NPN transistor Q2 (the second source region, first well region, and second well region of the NMOS transistor) is bypassed, which is equivalent to reducing the base transport efficiency, thereby reducing the current gain of the NPN transistor Q2 and improving the sustaining voltage of the SCR.

[0068] In summary, the electrostatic discharge (ESD) protection structure of the present invention, by embedding a PMOS transistor in the N-type well region or an NMOS transistor in the P-type well region, can effectively reduce the on-resistance of the device structure and increase the holding voltage, thereby avoiding latch-up effects. Therefore, the present invention effectively overcomes the various shortcomings of the prior art and has high industrial applicability.

[0069] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. An electrostatic protection structure, characterized in that, The structure includes: A semiconductor substrate having an N-well and a P-well disposed adjacent to the N-well; The first doped region is formed in the surface layer at the junction of the N-well and the P-well, and the ion doping type is N-type. The second doped region is formed in the surface layer of the N-well, and the ion doping type is N-type. The third doped region is formed in the surface layer of the P-well, and the ion doping type is P-type. The fourth doped region is formed in the surface layer of the P-well and is located between the first doped region and the third doped region. The ion doping type is N-type. The third and fourth doped regions are connected to the ground voltage. A PMOS transistor is formed between the first doped region and the second doped region; The source region of the PMOS transistor and the second doped region are connected to the operating voltage; The gate and drain regions of the PMOS transistor are shorted to the first doped region.

2. The electrostatic protection structure according to claim 1, characterized in that, The PMOS transistor also includes an LDD region, which is formed on both sides of the gate of the PMOS transistor and extends partially below the gate.

3. The electrostatic protection structure according to claim 2, characterized in that, The ion doping type of the LDD region is the same as that of the source and drain regions of the PMOS transistor.

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