Method for manufacturing a cmos image sensor

Abstract

The application provides a preparation method of a CMOS image sensor, comprising the following steps: providing a substrate; etching a third medium layer, a second medium layer and a first medium layer with a partial thickness of a pixel region and a logic region; taking the first medium layer with the remaining thickness as a mask, performing an ion implantation process on the substrate of the pixel region to form a second clamping region on the surface of a first clamping region; and etching the first medium layer with the remaining thickness of the pixel region and the logic region to the surface of the substrate. In the process of etching to form a side wall structure, the first medium layer with the remaining thickness is reserved, and the ion implantation process is performed on the substrate of the pixel region to form the second clamping region on the surface of the first clamping region by taking the first medium layer with the remaining thickness as the mask, so that the damage of the ion implantation process to the surface of the substrate can be effectively reduced, the white pixels can be reduced, and the performance of the image sensor can be improved.

Description

Technical Field

[0001] This application relates to the field of semiconductor manufacturing technology, specifically to a method for fabricating a CMOS image sensor. Background Technology

[0002] In recent years, with the advancement of integrated circuit manufacturing technology and the development of 5G and artificial intelligence, CMOS image sensors have played an increasingly important role.

[0003] White noise in image sensors has always been a crucial research area for performance improvement, as its performance directly determines the performance of high-end image sensors. However, in current image sensor manufacturing processes, during PIN IMP (second clamping region ion implantation), the substrate surface is only covered with an intrinsic oxide layer, which cannot effectively prevent ion implantation plasma from damaging the substrate surface, leading to dark current, which in turn affects device performance and may even cause device failure. Summary of the Invention

[0004] This application provides a method for fabricating a CMOS image sensor, which can solve the problem of damage to the substrate surface caused by ion implantation during the formation of the second clamping region.

[0005] On one hand, embodiments of this application provide a method for fabricating a CMOS image sensor, including:

[0006] A substrate is provided, the substrate comprising a pixel region and a logic region, wherein a photodiode region and a floating diffusion region are formed in the substrate of the pixel region, and a first clamping region is formed on the surface of the photodiode region; a plurality of lightly doped drain regions are formed in the substrate of the logic region; a gate structure, a first dielectric layer covering the gate structure, a second dielectric layer covering the first dielectric layer, and a third dielectric layer covering the second dielectric layer are formed on both the substrate of the pixel region and the substrate of the logic region.

[0007] The third dielectric layer, the second dielectric layer, and a portion of the thickness of the first dielectric layer on the top and both sides of the gate structure of the pixel region are etched, and the third dielectric layer, the second dielectric layer, and a portion of the thickness of the first dielectric layer on the top and both sides of the gate structure of the logic region are etched simultaneously.

[0008] Using the remaining thickness of the first dielectric layer as a mask, an ion implantation process is performed on the substrate of the pixel region to form a second clamping region on the surface of the first clamping region;

[0009] The remaining thickness of the first dielectric layer in the pixel region and the logic region is etched onto the surface of the substrate, wherein in the pixel region, the third dielectric layer, the second dielectric layer, and the first dielectric layer retained near the gate structure constitute the sidewall structure of the pixel region; in the logic region, the third dielectric layer, the second dielectric layer, and the first dielectric layer retained near the gate structure constitute the sidewall structure of the logic region.

[0010] Optionally, in the fabrication method of the CMOS image sensor, the thickness of the first dielectric layer is...

[0011] Optionally, in the fabrication method of the CMOS image sensor, after etching the top and sides of the gate structure of the pixel region, the third dielectric layer, the second dielectric layer, and a portion of the thickness of the first dielectric layer, and simultaneously etching the top and sides of the gate structure of the logic region, the remaining thickness of the first dielectric layer is...

[0012] Optionally, in the fabrication method of the CMOS image sensor, using the remaining thickness of the first dielectric layer as a mask, during the ion implantation process performed on the substrate of the pixel region to form a second clamping region on the surface of the first clamping region, the ion implantation energy is 5–20 keV; the ion implantation dose is 1.0E12 atoms / cm². 2 ~2.0E13 atoms / cm 2 .

[0013] Optionally, in the fabrication method of the CMOS image sensor, using the remaining thickness of the first dielectric layer as a mask, a P-type doped ion implantation process is performed on the substrate of the pixel region to form a P-second clamping region on the surface of the first clamping region.

[0014] Optionally, in the fabrication method of the CMOS image sensor, a dry etching process is used to etch the remaining thickness of the first dielectric layer of the pixel region and the logic region to the surface of the substrate.

[0015] Optionally, in the fabrication method of the CMOS image sensor, the gate structure of the pixel region includes: a gate oxide layer and a polysilicon gate located on the gate oxide layer.

[0016] Optionally, in the method for fabricating the CMOS image sensor, after forming the sidewall structures of the pixel region and the logic region, the method further includes:

[0017] An ion implantation process is performed on the substrate of the logic region to form source and drain electrodes on the surface of the lightly doped drain region, respectively.

[0018] Optionally, in the method for fabricating the CMOS image sensor, after forming the source and drain of the logic region, the method further includes:

[0019] A metal silicide barrier layer is formed, which covers the gate structure and sidewall structure of the pixel region, the gate structure and sidewall structure of the logic region, and all exposed substrate surfaces.

[0020] The technical solution of this application has at least the following advantages:

[0021] In the process of etching to form the sidewall structure, this application retains the remaining thickness of the first dielectric layer and uses the remaining thickness of the first dielectric layer as a mask to perform an ion implantation process on the substrate of the pixel region to form a second clamping region on the surface of the first clamping region. This can effectively reduce the damage to the substrate surface caused by the ion implantation process, reduce white pixels, avoid the generation of dark current, improve image quality, and improve the performance of the CMOS image sensor.

[0022] Furthermore, for the first clamping region, forming the second clamping region on its surface can provide good isolation. Attached Figure Description

[0023] To more clearly illustrate the technical solutions in the specific embodiments of this application or the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0024] Figure 1 This is a flowchart of a method for fabricating a CMOS image sensor according to an embodiment of the present invention;

[0025] Figures 2-5 This is a schematic diagram of the semiconductor structure in each process step of fabricating a CMOS image sensor according to an embodiment of the present invention;

[0026] The accompanying drawings are labeled as follows:

[0027] 10 - Substrate, A - Pixel region, B - Logic region, 111 - First well region, 112 - Second well region, 113 - Third well region, 114 - Fourth well region, 115 - First clamping region, 116 - Lightly doped drain region, 117 - Second clamping region;

[0028] 121 - Deep well region, 122 - Lightly doped drain region, 123 - Lightly doped drain region;

[0029] 21-Gate structure, 211-Gate oxide layer, 212-Polysilicon gate; 22-Gate structure, 221-Gate oxide layer, 222-Polysilicon gate;

[0030] 30-Side wall structure, 31-First dielectric layer, 32-Second dielectric layer, 33-Third dielectric layer. Detailed Implementation

[0031] The technical solutions of this application will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0032] In the description of this application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0033] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal connection of two components; and they can refer to a wireless connection or a wired connection. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0034] Furthermore, the technical features involved in the different embodiments of this application described below can be combined with each other as long as they do not conflict with each other.

[0035] This application provides a method for fabricating a CMOS image sensor, referring to... Figure 1 , Figure 1 This is a flowchart of a method for fabricating a CMOS image sensor according to an embodiment of the present invention.

[0036] For details, please refer to Figures 2-5 , Figures 2-5 This is a schematic diagram of the semiconductor structure in each process step of fabricating a CMOS image sensor according to an embodiment of the present invention. The method for fabricating the CMOS image sensor includes:

[0037] Step S10: As Figure 2 As shown, a substrate 10 is provided, which includes a pixel region A and a logic region B. A photodiode region PD and a floating diffusion region FD are formed in the substrate 10 of the pixel region A. Specifically, the photodiode region PD includes a first well region 111 and a second well region 112 spaced apart. A third well region 113 is also formed on the first well region 111, and a fourth well region 114 is also formed on the second well region 112. A first clamping region 115 is formed on the surface of the third well region 113, and a lightly doped drain region 116 is formed on the surface of the fourth well region 114. In this embodiment, the first well region 111 can be an N-type well region, the third well region 113 can be a P-type well region, and the first clamping region 115 can be a P-type clamping region; the second well region 112 can be an N-type well region, the fourth well region 114 can be a P-type well region, and the lightly doped drain region 116 can be an N-type lightly doped drain region.

[0038] Furthermore, a deep well region 121 and multiple lightly doped drain regions 122 / 123 are formed in the substrate 10 of the logic region B. Specifically, in a PMOS device structure within the logic region B, the deep well region 121 is an N-well, and the lightly doped drain regions 122 / 123 are P-type lightly doped drain regions (PLDD); if it is an NMOS device structure, then the deep well region is a P-well, and the lightly doped drain regions 122 / 123 are N-type lightly doped drain regions (NLDD).

[0039] In this embodiment, a gate structure 21 is formed on the substrate 10 of the pixel region A, and a gate structure 22 is formed on the substrate 10 of the logic region B. The pixel region A and the logic region B include a first dielectric layer 31 covering the gate structure, a second dielectric layer 32 covering the first dielectric layer 31, and a third dielectric layer 33 covering the second dielectric layer 32. Further, the first dielectric layer 31 may be silicon oxide, the second dielectric layer 32 may be silicon nitride, and the third dielectric layer 33 may be silicon oxide.

[0040] Preferably, the thickness of the first dielectric layer 31 can be

[0041] Furthermore, the gate structure 21 of the pixel region A includes a gate oxide layer 211 and a polysilicon gate 212 located on the gate oxide layer 211. Similarly, the gate structure 22 of the logic region B includes a gate oxide layer 221 and a polysilicon gate 222 located on the gate oxide layer 221.

[0042] Step S20: As Figure 3 As shown, the third dielectric layer 33, the second dielectric layer 32, and a portion of the first dielectric layer 31 on the top and both sides of the gate structure 21 in the pixel region A are etched, while the third dielectric layer 33, the second dielectric layer 32, and a portion of the first dielectric layer 31 on the top and both sides of the gate structure 22 in the logic region B are etched.

[0043] In this embodiment, a dry etching process can be used to etch half the thickness of the original first dielectric layer 31 to obtain the remaining thickness of the first dielectric layer 31.

[0044] In this embodiment, after etching the third dielectric layer 33, the second dielectric layer 32, and a portion of the thickness of the first dielectric layer 31, the remaining thickness of the remaining thickness of the first dielectric layer 31 can be...

[0045] Step S30: As Figure 4 As shown, using the remaining thickness of the first dielectric layer 31 as a mask, an ion implantation process is performed on the substrate 10 of the pixel region A to form a second clamping region 117 on the surface of the first clamping region 115.

[0046] Specifically, using the remaining thickness of the first dielectric layer 31 as a mask, during the ion implantation process performed on the substrate 10 of the pixel region A to form a second clamping region 117 on the surface of the first clamping region 115, the ion implantation energy can be 5–20 keV; the ion implantation dose can be 1.0E12 atoms / cm. 2 ~2.0E13 atoms / cm 2 .

[0047] In this embodiment, the remaining thickness of the first dielectric layer 31 can be used as a mask to perform a P-type doped ion implantation process on the substrate 10 of the pixel region A to form a P-second clamping region on the surface of the first clamping region 115.

[0048] Step S40: Etch the remaining thickness of the first dielectric layer 31 of the pixel region A and the logic region B to the surface of the substrate 10, wherein, in the pixel region A, the retained third dielectric layer 33 near the gate structure 21, the L-shaped second dielectric layer 32, and the L-shaped first dielectric layer 31 constitute the sidewall structure 30 of the pixel region A; in the logic region B, the retained third dielectric layer 33 near the gate structure 22, the second dielectric layer 32, and the first dielectric layer 31 constitute the sidewall structure 30 of the logic region B.

[0049] In this embodiment, the remaining thickness of the first dielectric layer 31 of the pixel region A and the logic region B can be etched to the surface of the substrate 10 using a dry etching process.

[0050] In this application, during the etching process to form the sidewall structure 30, the remaining thickness of the first dielectric layer 31 is retained. Using the remaining thickness of the first dielectric layer 31 as a mask, an ion implantation process is performed on the substrate 10 of the pixel region A to form a second clamping region 117 on the surface of the first clamping region 115. This effectively reduces damage to the surface of the substrate 10 caused by the ion implantation process, reduces white pixels in the pixel region, avoids the generation of dark current, improves image quality, and enhances the performance of the CMOS image sensor. Furthermore, forming the second clamping region 117 on the surface of the first clamping region 115 provides good isolation.

[0051] Furthermore, after forming the sidewall structure 30 of the pixel region A and the sidewall structure 30 of the logic region B, or after forming the second clamping region 117 and before etching the remaining thickness of the first dielectric layer 31 of the pixel region A and the logic region B in the etching process, the fabrication method of the CMOS image sensor may further include:

[0052] Step S50: Perform an ion implantation process on the substrate 10 of the logic region B to form source and drain electrodes (not shown) on the surface of the lightly doped drain regions 122 / 123, respectively.

[0053] Furthermore, after forming the source and drain of the logic region B, or after etching away the remaining thickness of the first dielectric layer 31, the fabrication method of the CMOS image sensor may further include:

[0054] Step S60: Form a metal silicide barrier layer (not shown), wherein the metal silicide barrier layer may cover the gate structure 21 and sidewall structure 30 of the pixel region A, the gate structure 22 and sidewall structure 30 of the logic region B, and cover all exposed substrate 10 surfaces.

[0055] Obviously, the above embodiments are merely illustrative examples for clear explanation and are not intended to limit the implementation. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of protection of this application.

Claims

1. A method for fabricating a CMOS image sensor, characterized in that, include: A substrate is provided, the substrate comprising a pixel region and a logic region, wherein a photodiode region and a floating diffusion region are formed in the substrate of the pixel region, and a P-type first clamping region is formed on the surface of the photodiode region; a plurality of lightly doped drain regions are formed in the substrate of the logic region; a gate structure, a first dielectric layer covering the gate structure, a second dielectric layer covering the first dielectric layer, and a third dielectric layer covering the second dielectric layer are formed on both the substrate of the pixel region and the substrate of the logic region. The third dielectric layer, the second dielectric layer, and a portion of the thickness of the first dielectric layer on the top and both sides of the gate structure of the pixel region are etched, and the third dielectric layer, the second dielectric layer, and a portion of the thickness of the first dielectric layer on the top and both sides of the gate structure of the logic region are etched simultaneously. Using the remaining thickness of the first dielectric layer as a mask, a P-type ion implantation process is performed on the substrate of the pixel region to form a P-second clamping region on the surface of the first clamping region; The remaining thickness of the first dielectric layer in the pixel region and the logic region is etched to the surface of the substrate, wherein, in the pixel region, the third dielectric layer, the second dielectric layer, and the first dielectric layer retained near the gate structure constitute the sidewall structure of the pixel region; in the logic region, the third dielectric layer, the second dielectric layer, and the first dielectric layer retained near the gate structure constitute the sidewall structure of the logic region. Wherein, after etching the top and sides of the gate structure of the pixel region, the third dielectric layer, the second dielectric layer and a portion of the thickness of the first dielectric layer, and simultaneously etching the top and sides of the gate structure of the logic region, the thickness of the remaining thickness of the first dielectric layer is 50Å~100Å. Using the remaining thickness of the first dielectric layer as a mask, an ion implantation process is performed on the substrate of the pixel region to form a second clamping region on the surface of the first clamping region. During this process, the ion implantation energy is 5-20 keV, and the ion implantation dose is 1.0E12 atoms / cm². 2 ~2.0E13 atoms / cm 2 .

2. The method for fabricating a CMOS image sensor according to claim 1, characterized in that, The thickness of the first dielectric layer is 100 Å to 200 Å.

3. The method for fabricating a CMOS image sensor according to claim 1, characterized in that, The remaining thickness of the first dielectric layer in the pixel region and the logic region is etched to the surface of the substrate using a dry etching process.

4. The method for fabricating a CMOS image sensor according to claim 1, characterized in that, The gate structure of the pixel region includes a gate oxide layer and a polysilicon gate located on the gate oxide layer.

5. The method for fabricating a CMOS image sensor according to claim 1, characterized in that, After forming the sidewall structures of the pixel region and the logic region, the fabrication method of the CMOS image sensor further includes: An ion implantation process is performed on the substrate of the logic region to form source and drain electrodes on the surface of the lightly doped drain region, respectively.

6. The method for fabricating a CMOS image sensor according to claim 5, characterized in that, After forming the source and drain of the logic region, the fabrication method of the CMOS image sensor further includes: A metal silicide barrier layer is formed, which covers the gate structure and sidewall structure of the pixel region, the gate structure and sidewall structure of the logic region, and all exposed substrate surfaces.

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