Silicon carbide semiconductor device

Abstract

A silicon carbide semiconductor device capable of maintaining ESD tolerance even when field oxide films are removed is provided. The silicon carbide semiconductor device includes a silicon carbide semiconductor substrate of a first conductivity type, a first semiconductor layer (2) of the first conductivity type, a second semiconductor layer (6) of a second conductivity type, a first semiconductor region of the first conductivity type, a second semiconductor region (8) of the second conductivity type, a gate insulating film, a gate electrode, a first electrode, a second electrode, and a gate pad portion (23). The gate pad portion (23) includes a gate electrode pad and a connection portion. A first region (6a) in which the second semiconductor region (8) is not provided is present in a region opposite the connection portion in a depth direction. A second region in which the second semiconductor region (8) is not provided is present in a region opposite a corner portion of the gate electrode pad in the depth direction. An oxide film (16) identical to the gate insulating film is provided on surfaces of the second semiconductor region (8), the first region (6a), and the second region.

Description

Technical Field

[0001] This invention relates to silicon carbide semiconductor devices. Background Technology

[0002] Traditionally, silicon (Si) has been used as the constituent material for power semiconductor devices that control high voltage and / or high current. Power semiconductor devices include various types such as bipolar transistors and / or IGBTs (Insulated Gate Bipolar Transistors) and MOSFETs (Metal-Oxide Semiconductor Field Effect Transistors), which are used differently depending on the application.

[0003] For example, bipolar transistors and / or IGBTs have higher current densities than MOSFETs, enabling high-current operation, but they cannot switch at high speeds. Specifically, the switching frequency of bipolar transistors is limited to a few kHz, while the switching frequency of IGBTs is limited to tens of kHz. On the other hand, power MOSFETs have lower current densities than bipolar transistors and / or IGBTs, making high-current operation difficult, but they can perform high-speed switching operations up to several MHz.

[0004] However, the market demand for power semiconductor devices that combine high current and high speed is strong, leading to a surge in efforts to improve IGBTs and / or power MOSFETs, with development now approaching material limits. From the perspective of power semiconductor devices, research is underway to find alternatives to silicon, with silicon carbide (SiC) attracting significant attention as a semiconductor material capable of producing next-generation power semiconductor devices with low on-state voltage, high-speed characteristics, and excellent high-temperature performance.

[0005] Regarding its background, SiC is a chemically very stable material with a wide bandgap of up to 3 eV, and it can be used as a semiconductor with extreme stability even at high temperatures. Furthermore, its maximum electric field strength is more than an order of magnitude greater than that of silicon. SiC has the potential to surpass the material limits of silicon, therefore its future development in power semiconductor applications, especially in MOSFETs, is highly anticipated. Its low on-resistance is particularly noteworthy. Vertical SiC-MOSFETs with even lower on-resistance while maintaining high voltage withstand characteristics can be expected.

[0006] here, Figure 9This is a top view showing the gate pad portion of a conventional silicon carbide semiconductor device. As a conventional silicon carbide semiconductor device, a vertical SiC-MOSFET will be used as an example for explanation. In a vertical SiC-MOSFET, a gate pad portion 123 and a source pad portion are provided on the front side. The source pad portion is provided around the gate pad portion 123. The gate pad portion 123 includes a gate electrode pad 119 connected to the gate electrode and a connection portion 119a connecting the gate electrode pad 119 to the gate channel. Figure 10 It is a traditional silicon carbide semiconductor device Figure 9 A cross-sectional view of the E-E' section. Figure 11 It is a traditional silicon carbide semiconductor device Figure 9 A cross-sectional view of the F-F' section.

[0007] In the conventional vertical SiC-MOSFET gate pad portion 123, in n + The front side of the silicon carbide substrate is laminated with n - The silicon carbide layer 102 and the n-type region (not shown) are selectively provided with a lower p-type region inside the n-type region. + Base region 103a, upper p + The n-type base region 103b has a p-type base layer 106 disposed thereon. Furthermore, p-type base layers 106 are selectively disposed on the surface of the p-type base layer 106. ++ Type contact area 108.

[0008] Furthermore, in the gate pad portion 123 of the vertical SiC-MOSFET, a field oxide film 121 with a thickness of approximately 500 nm is provided in the edge termination region for mitigating the electric field and maintaining the withstand voltage in order to improve ESD (Electro Static Discharge) withstand capability. An HTO (High Temperature Oxide) film 116 with a thickness of approximately 100 nm is provided on the field oxide film 121.

[0009] Polysilicon 117 is disposed on HTO film 116, and an interlayer insulating film 118 composed of BPSG and NSG is disposed on polysilicon 117. A metal film 124 is disposed on interlayer insulating film 118. Contact holes 122a reaching HTO film 116 are formed in polysilicon 117, and interlayer insulating film 118 fills contact holes 122a. Through interlayer insulating film 118, polysilicon 117 is electrically insulated into a portion of gate pad portion 123 and a portion of source pad portion.

[0010] Additionally, a contact hole 122b is formed within the interlayer insulating film 118 to reach the polysilicon 117, electrically connecting the metal film 124 to the polysilicon 117. A contact hole 122c is formed within the metal film 124 to reach the interlayer insulating film 118. The metal film 124 is electrically insulated, forming a portion of the gate pad portion 123 and a portion of the source pad portion. The portion of the metal film 124 in the gate pad portion 123 becomes the gate electrode pad 119.

[0011] In addition, there is a known technology that, by increasing the overall surface area of ​​the gate polysilicon layer disposed on the first main surface of the semiconductor substrate with an oxide film in between, even if a large amount of charge is injected into the gate pad due to ESD or the like, the voltage of the oxide film applied to the lower layer of the gate polysilicon layer can be dispersed, thereby suppressing the insulation breakdown of the oxide film (for example, see Patent Document 1 below).

[0012] Existing technical documents

[0013] Patent documents

[0014] Patent Document 1: Japanese Patent Application Publication No. 2020-150179 Summary of the Invention

[0015] Technical issues

[0016] In this trench MOSFET, the field oxide 121 is selectively deposited after the trench is formed. Forming the field oxide 121 requires the formation of a mask, which increases manufacturing costs. Therefore, a vertical SiC-MOSFET with the field oxide 121 removed has been proposed.

[0017] Figure 12 It is a silicon carbide semiconductor device with the field oxide film removed. Figure 9 A cross-sectional view of the E-E' section. Figure 13 It is a silicon carbide semiconductor device with the field oxide film removed. Figure 9 A cross-sectional view of the F-F' section. In this case, as... Figure 12 and Figure 13 As shown, in p ++ An HTO membrane 116 is provided on the contact area 108.

[0018] However, if the field oxide film 121 is not formed, electric field concentration occurs, leading to a decrease in ESD tolerance. Therefore, if an ESD test is performed on a silicon carbide semiconductor device without the field oxide film, breakdown sometimes occurs at the gate electrode pad 119. In particular, sometimes breakdown occurs at the corners of the gate electrode pad 119 where the electric field is concentrated. Figure 9 Part B) and part of the contact hole 122b of the connection portion 119a, and the area from the contact hole 122b to the gate electrode pad 119 ( Figure 9Part A) breaks down.

[0019] In order to eliminate the problems of the prior art, the present invention aims to provide a silicon carbide semiconductor device that can maintain ESD resistance even when the field oxide film is removed.

[0020] Technical solution

[0021] To address the aforementioned issues and achieve the objectives of this invention, the silicon carbide semiconductor device of this invention has the following features: A first semiconductor layer of a first conductivity type, with an impurity concentration lower than that of the silicon carbide semiconductor substrate, is disposed on the front side of the first conductivity type silicon carbide semiconductor substrate. A second semiconductor layer of a second conductivity type is selectively disposed on the surface layer of the first semiconductor layer opposite to the silicon carbide semiconductor substrate. A first semiconductor region of the first conductivity type is selectively disposed on the surface layer of the second semiconductor layer opposite to the silicon carbide semiconductor substrate. A second semiconductor region of the second conductivity type, with an impurity concentration higher than that of the second semiconductor layer, is selectively disposed on the surface layer of the second semiconductor layer opposite to the silicon carbide semiconductor substrate. A gate electrode is disposed on at least a portion of the surface of the second semiconductor layer sandwiched between the first semiconductor region and the first semiconductor layer, separated by a gate insulating film. A first electrode is disposed on the surfaces of the first semiconductor region and the second semiconductor region. A second electrode is disposed on the back side of the silicon carbide semiconductor substrate. A gate pad portion electrically connected to the gate electrode via gate electrode wiring is provided. The gate pad portion includes a gate electrode pad and a connection portion electrically connecting the gate electrode pad to the gate electrode wiring. It has a first region where the second semiconductor region is not disposed in a region opposite the connection portion in the depth direction, and a second region where the second semiconductor region is not disposed in a region opposite the corner of the gate electrode pad in the depth direction. An oxide film identical to the gate insulating film is disposed on the surfaces of the second semiconductor region, the first region, and the second region. "Identical oxide film" means oxide films formed simultaneously, including oxide films formed simultaneously on surfaces with different planar orientations, and oxide films formed simultaneously with thicknesses corresponding to the planar orientations.

[0022] Furthermore, the silicon carbide semiconductor device of the present invention is characterized in that, in the above invention, the width of the first region is greater than or equal to the width of the first polysilicon layer, and the first polysilicon layer is disposed in a region opposite to the above-mentioned connection portion in the depth direction.

[0023] Furthermore, the silicon carbide semiconductor device of the present invention is characterized in that, in the above invention, the width of the first region extends from the end of the first polysilicon layer by less than 20 μm.

[0024] Furthermore, the silicon carbide semiconductor device of the present invention is characterized in that, in the above invention, the width of the second region is centered on the end of the second polysilicon layer and is 10 μm or more and 40 μm or less, and the second polysilicon layer is disposed in a region opposite to the gate electrode pad in the depth direction.

[0025] Furthermore, the silicon carbide semiconductor device of the present invention is characterized in that, in the above invention, the first region and the second region have the same conductivity type and the same impurity concentration as the second semiconductor layer.

[0026] Furthermore, the silicon carbide semiconductor device of the present invention is characterized in that, in the above invention, a third region is provided in the region opposite to the periphery of the gate electrode pad in the depth direction, wherein the second semiconductor region is not provided, and the oxide film is also provided on the surface of the third region.

[0027] Furthermore, the silicon carbide semiconductor device of the present invention is characterized in that, in the above invention, the thickness of the high-temperature oxide film is 50 nm or more and 150 nm or less.

[0028] According to the above invention, no field oxide film is provided, but a p-type oxide film is provided at the connection portion of the gate pad portion and the corner of the gate electrode pad. ++ The region is formed by extracting the p-type contact region (the second semiconductor region of the second conductivity type). Therefore, at the connection and corners, the HTO film contacts the p-type base layer (the second semiconductor layer of the second conductivity type) in the depth direction. The impurity concentration of the p-type base layer is lower than that of the p-type base layer. ++ The lower the impurity concentration in the p-type contact region, the wider the depletion layer width. Therefore, by increasing the ESD tolerance through the p-type base layer, the same level of ESD tolerance as that achieved with a field oxide film can be obtained. Thus, in this invention, ESD tolerance can be maintained, and manufacturing costs are reduced without the need for a field oxide film.

[0029] Invention Effects

[0030] The silicon carbide semiconductor device according to the present invention produces an effect that maintains ESD tolerance even when the field oxide film is removed. Attached Figure Description

[0031] Figure 1 This is a cross-sectional view showing the structure of a silicon carbide semiconductor device according to an embodiment.

[0032] Figure 2 This is a cross-sectional view showing another structure of the silicon carbide semiconductor device according to an embodiment.

[0033] Figure 3 This is a top view showing the structure of a silicon carbide semiconductor device according to an embodiment.

[0034] Figure 4 This is an enlarged view of the gate pad portion of the silicon carbide semiconductor device according to the embodiment.

[0035] Figure 5 This is an enlarged view of the connection portion of the gate electrode pad of the silicon carbide semiconductor device according to the embodiment.

[0036] Figure 6 The silicon carbide semiconductor device is an embodiment of the invention. Figure 5 A cross-sectional view of the C-C' section.

[0037] Figure 7 This is an enlarged view of the corner of the gate electrode pad of the silicon carbide semiconductor device according to the embodiment.

[0038] Figure 8 The silicon carbide semiconductor device is an embodiment of the invention. Figure 7 A cross-sectional view of the D-D' section.

[0039] Figure 9 This is a top view showing the gate pad portion of a conventional silicon carbide semiconductor device.

[0040] Figure 10 It is a traditional silicon carbide semiconductor device Figure 9 A cross-sectional view of the E-E' section.

[0041] Figure 11 It is a traditional silicon carbide semiconductor device Figure 9 A cross-sectional view of the F-F' section.

[0042] Figure 12 It is a silicon carbide semiconductor device with the field oxide film removed. Figure 9 A cross-sectional view of the E-E' section.

[0043] Figure 13 It is a silicon carbide semiconductor device with the field oxide film removed. Figure 9 A cross-sectional view of the F-F' section.

[0044] Symbol Explanation

[0045] 1 n + Silicon carbide substrate

[0046] 2. 102 n - Type silicon carbide layer

[0047] 3 p + Base region

[0048] 3a, 103a, lower part p + Base region

[0049] 3b, 103b, upper part p + Base region

[0050] 4 n-type well regions

[0051] 5 n-type region

[0052] 6. 106 p-type base layer

[0053] 6a p not set ++ The first zone of the type contact area

[0054] 6b p not set ++ The second zone of the type contact area

[0055] 6c p not set ++ The third zone of the contact area

[0056] 7 n + Type source polar region

[0057] 8, 108 p ++ Type contact area

[0058] 9. Gate insulating film

[0059] 10 Gate electrode

[0060] 11-layer interlayer insulation film

[0061] 12 Source Electrode

[0062] 13 Source electrode pads

[0063] 14 Drain electrode

[0064] 15. Trench

[0065] 16, 116 HTO membrane

[0066] 17, 117 polycrystalline silicon

[0067] 17a Polysilicon facing the gate pad in the depth direction

[0068] 17b Polysilicon facing the gate electrode pad in the depth direction

[0069] 17c The end of the polysilicon facing the gate pad in the depth direction.

[0070] 17d is the end of the polysilicon facing the gate electrode pad in the depth direction.

[0071] 18 and 118 interlayer insulating film

[0072] 19, 119 Gate electrode pads

[0073] 19a, 119a connecting parts

[0074] 20 Active Area

[0075] Contact holes 22a, 22b, 22c, 122a, 122b, 122c

[0076] 23, 123 Gate pad section

[0077] 24, 124 metal film

[0078] 25 Gate Flow Channel

[0079] 26 Source Pad Section

[0080] 30 Edge Terminal Area

[0081] 31 steps

[0082] 32 JTE Structure

[0083] 33 n + Type semiconductor region

[0084] 40 Silicon carbide matrix

[0085] 50 trench MOSFET

[0086] 51 Planar MOSFET

[0087] 121 Field Oxide Film Detailed Implementation

[0088] Hereinafter, preferred embodiments of the silicon carbide semiconductor device of the present invention will be described in detail with reference to the accompanying drawings. In this specification and the drawings, in layers and / or regions marked with 'n', electrons are the majority carriers; in layers and / or regions marked with 'p', holes are the majority carriers. Furthermore, a '+' marked with 'n' or 'p' indicates a higher impurity concentration than layers and / or regions without a '+', and a '-' marked with 'n' or 'p' indicates a lower impurity concentration than layers and / or regions without a '-'. The same '+' or '-' markings for 'n' or 'p' indicate similar, but not limited to, equal, concentrations. It should be noted that in the following description of embodiments and the accompanying drawings, the same symbols are used for the same components, and repeated descriptions are omitted. Additionally, in this specification, in the representation of Miller indices, '-' refers to a horizontal line placed immediately following the index, and a negative index is indicated by placing '-' before the index. Furthermore, considering manufacturing variations, descriptions of identical or equivalent values ​​may be included up to 5%. In addition, the same oxide film refers to oxide films formed simultaneously, including oxide films formed simultaneously on surfaces with different orientations. Oxide films formed simultaneously and with thicknesses corresponding to the orientations of the surfaces are also acceptable.

[0089] (Implementation Method)

[0090] The semiconductor device of the present invention is constructed using a wide-bandgap semiconductor. In the embodiments, a trench MOSFET 50 will be described as an example of a silicon carbide semiconductor device that is fabricated using, for example, silicon carbide (SiC) as the wide-bandgap semiconductor. Figure 1 This is a cross-sectional view showing the structure of a silicon carbide semiconductor device according to an embodiment.

[0091] like Figure 1 As shown, the semiconductor device of the embodiment has an active region 20 and an edge termination region 30 surrounding the active region 20 in a semiconductor substrate (hereinafter referred to as silicon carbide substrate (semiconductor substrate (semiconductor chip))) 40 made of silicon carbide. The active region 20 is the region in which current flows when the device is in the on state. The edge termination region 30 is the region that mitigates the electric field on the front side of the substrate in the drift region and maintains a withstand voltage.

[0092] The silicon carbide substrate 40 is an n-type matrix composed of silicon carbide. + Type support base plate (n + On the front side of a silicon carbide substrate (a first conductivity type silicon carbide semiconductor substrate) 1, n-type silicon carbide semiconductor substrates are sequentially stacked. - Type semiconductor layer (n) - It consists of a first semiconductor layer of a first conductivity type (a first semiconductor layer of a first conductivity type) 2 and a p-type semiconductor layer (a p-type base layer and a second semiconductor layer of a second conductivity type) 6 made of silicon carbide. + The silicon carbide substrate 1 functions as the drain region. In the active region 20, at n... - Type 2 silicon carbide layer with n + The surface layer on the opposite side (front side of the substrate) of the silicon carbide substrate 1 is selectively provided with p + Type 3 and n-type region 5. p + Type base region 3 includes the lower p + Type base region 3a, upper p + The two layers of the base region 3b.

[0093] Additionally, a JTE structure 32 is provided in the edge terminal region 30. This JTE structure 32 uses multiple p-type transistors, where the impurity concentration is lower the further out (to the chip end) they are positioned. - Type low concentration zones (there are 2 in this case, denoted as p from the inside) - Type, p -- The two structures (32a and 32b) are arranged adjacent to each other. Additionally, an n-type channel cutoff element is provided on the outer side (chip end side) of the JTE structure 32. + Type semiconductor region 33. JTE structure 32 and n + Type semiconductor region 33 is disposed on n through step 31. -The bottom 31a of the thinner step 31 of the silicon carbide layer 2. The outermost (chip end side) p + The base region 3 extends from the active region 20 to the edge terminal region 30. It should be noted that n - p-type silicon carbide layer 2 + The region outside the base region 3 is the drift region. Region 5 of the n-type is where the impurity concentration is lower than n. + Type 1 silicon carbide substrate and higher than n - The high-concentration n-type drift layer with high impurity concentration of silicon carbide layer 2.

[0094] In n - Type 2 silicon carbide layer with n + A p-type base layer 6 is disposed on the surface opposite to one side of the silicon carbide substrate 1. The impurity concentration of the p-type base layer 6 is lower than that of the p-type substrate 1. + The impurity concentration in the p-type base region 3. N-type impurities are selectively disposed within the p-type base layer 6. + Type source region (first semiconductor region of first conductivity type) 7 and p ++ Type contact area (second semiconductor region of second conductivity type) 8.

[0095] The p-type base layer 6 is configured to partially cover the p+ type base region 3 and the n-type region 5 in the active region 20. Furthermore, the p-type base layer 6 extends to the edge termination region 30, and within the edge termination region 30, it covers the p+ type base region 30. + Type base region 3 and n - The silicon carbide layer 2 is arranged in such a manner that it extends up to step 31.

[0096] A trench structure is formed in a portion of the active region 20 on the front side of the silicon carbide substrate 40. Specifically, the trench 15 extends from the p-type base layer 6 to the n-type base layer 6. + The surface of the silicon carbide substrate 1 on the opposite side (the front side of the silicon carbide substrate 40) has a through-hole. + The source region 7 and the p-type base layer 6 reach the n-type region 5 and the lower p-type region. + Type base region 3a. A gate insulating film 9 is formed along the inner wall of trench 15, at the bottom and sidewalls of trench 15. A gate electrode 10 is formed inside the gate insulating film 9 within trench 15. The gate electrode 10 is connected to the n-type region 5 and p-type region 6 through the gate insulating film 9. + The p-type base region 3 and the p-type base layer 6 are insulated. A portion of the gate electrode 10 may also protrude from above the trench 15 (towards the source electrode pad 13 side) toward the source electrode pad 13 side.

[0097] The interlayer insulating film 11 is configured to cover the entire front side of the silicon carbide substrate 40, including the gate electrode 10 buried in the trench 15. The source electrode 12 is connected to the n via contact holes formed in the interlayer insulating film 11. + Type source polar regions 7 and p++ Type contact area 8 is contacted. The source electrode 12 is electrically insulated from the gate electrode 10 through the interlayer insulating film 11. Source electrode pads 13 are provided on the source electrode 12. On the back side (n) of the silicon carbide substrate 40... + A drain electrode 14 is provided on the back side of the silicon carbide substrate 1.

[0098] exist Figure 1 The diagram shows only one trench MOS structure, but more trench gate structures of MOS gate (insulating gate composed of metal-oxide-semiconductor) can also be arranged side by side.

[0099] Figure 2 This is a cross-sectional view showing another structure of the silicon carbide semiconductor device according to an embodiment. Figure 2 This is an example of a planar MOSFET 51. For example... Figure 2 As shown, the semiconductor device of the embodiment has an active region 20 and an edge terminal region 30 surrounding the active region 20 on a silicon carbide substrate 40 made of silicon carbide.

[0100] The silicon carbide substrate 40 is an n-type matrix composed of silicon carbide. + Type support base plate (n + On the front side of the silicon carbide substrate 1, n layers composed of silicon carbide are stacked sequentially. - Type semiconductor layer (n) - It consists of a p-type silicon carbide layer 2 and a p-type semiconductor layer (p-type base layer) 6 made of silicon carbide. + The silicon carbide substrate 1 functions as the drain region. In the active region 20, at n... - Type 2 silicon carbide layer with n + The surface layer on the opposite side (front side of the substrate) of the silicon carbide substrate 1 is selectively provided with p + Type 3 and n-type region 5.

[0101] Additionally, in the p-type base layer 6, p + The base region 3 is partially provided with n + Type source polar regions 7 and p ++ Type contact area 8. Additionally, n + Type source polar regions 7 and p ++ Type 8 contact areas are in contact with each other. ++ Type contact area 8 is configured in a ratio of n + The source polar region 7 is located on the side of the edge terminal region 30.

[0102] Additionally, in the portion of the p-type base layer 6 above the n-type region 5, an n-type well region 4 is provided that penetrates the p-type base layer 6 in the depth direction to reach the n-type region 5. The n-type well region 4, n-type region 5, and n-type well region 4 are connected together. -The p-type base layer 6 forms a drift region together with the n+ type source region 7 and the n-type well region 4. A gate electrode 10 is disposed on the surface of the portion of the p-type base layer 6 sandwiched between the n+ type source region 7 and the n-type well region 4, separated by a gate insulating film 9. The gate electrode 10 may also be disposed on the surface of the n-type well region 4, separated by a gate insulating film 9.

[0103] The interlayer insulating film 11 is configured to cover the entire front side of the silicon carbide substrate, including the gate electrode 10. The source electrode 12 connects to the n electrode via contact holes formed in the interlayer insulating film 11. + Type source polar regions 7 and p ++ Type contact area 8 is contacted. The source electrode 12 is electrically insulated from the gate electrode 10 through the interlayer insulating film 11. Source electrode pads 13 are provided on the source electrode 12. On the back side (n) of the silicon carbide substrate 40... + A drain electrode 14 is provided on the back side of the silicon carbide substrate 1.

[0104] exist Figure 2 Only one MOS structure is shown in the diagram, but MOS gate (insulated gate composed of metal-oxide-semiconductor) structures with more gate structures can also be arranged side by side. Furthermore, the structure of the edge termination region 30 is the same as that of a trench MOSFET, so its description is omitted.

[0105] Here, Figure 3 This is a top view illustrating the structure of a silicon carbide semiconductor device according to an embodiment. Figure 3 As shown, the silicon carbide semiconductor device has a source pad portion 26 and a gate pad portion 23 on its upper surface. A source electrode pad 13 is provided in the source pad portion 26. The source electrode pad 13 is electrically connected to the source electrode 12, and the gate pad portion 23 is electrically connected to the gate electrode 10 via the gate channel 25.

[0106] Figure 4 This is an enlarged view of the gate pad portion of the silicon carbide semiconductor device according to an embodiment. (As shown) Figure 4 As shown, the gate pad portion 23 includes a gate electrode pad 19 and a connection portion 19a of the gate electrode pad electrically connecting the gate electrode pad 19 to the gate channel 25. Figure 3 Part A). Here, the connection portion 19a is the area between the gate channel 25 and the gate electrode pad 19.

[0107] Figure 5 This is an enlarged view of the connection portion of the gate electrode pads in the embodiment of the silicon carbide semiconductor device. Figure 5 The contact holes 22a, 22b, and 22c are described below. However, since the width of contact hole 22a is narrow, it is described with a single line.

[0108] Figure 6 The silicon carbide semiconductor device is an embodiment of the invention. Figure 5A cross-sectional view of the C-C' portion. In the connection portion 19a of the gate electrode pad of the silicon carbide semiconductor device in the embodiment, at n + The front side of the silicon carbide substrate is laminated with n - Type 2 silicon carbide layer, n-type region (not shown), with a lower p-type region selectively disposed inside the n-type region. + Type base region 3a, upper p + The base region 3b has a p-type base layer 6 disposed on the n-type region. This is achieved by setting a lower p-type base layer 6. + Type base region 3a and upper p + In the p-type base region 3b, the displacement current easily flows to this region due to its low resistance during turn-off, thereby suppressing electric field concentration on the HTO film 16 described later. Furthermore, p-type base layers 6 are selectively provided on their surface. ++ Type 8 contact area. Figure 6 This refers to the trench MOSFET 50. In the planar MOSFET 51, p + Type base region 3 becomes 1 layer (refer to) Figure 2 In this case, it also has the same characteristics as the lower p. + Type base region 3a, upper p + The same effect is achieved in the base region 3b.

[0109] In p ++ An HTO film 16 is disposed on the contact region 8 and the first region 6a (described later). This HTO film 16 is formed simultaneously with the gate insulating film 9, and has the same thickness as the gate insulating film 9 (50 nm or more and 150 nm or less). Even if the thickness of the gate insulating film 9 and the HTO film 16 differs due to different surface orientations, they can still be set within the range of 50 nm or more and 150 nm or less. A polycrystalline silicon 17 is disposed on the HTO film 16, an interlayer insulating film 18 composed of BPSG and NSG is disposed on the polycrystalline silicon 17, and a metal film 24 is disposed on the interlayer insulating film 18. Contact holes 22a extending to the HTO film 16 are formed within the polycrystalline silicon 17, and the interlayer insulating film 18 fills the contact holes 22a. Through the interlayer insulating film 18, the polysilicon 17 is electrically insulated as polysilicon 17a opposite to the gate pad portion 23 in the depth direction (from the source electrode 12 to the drain electrode 14) and a portion opposite to the source pad portion 26 in the depth direction.

[0110] Additionally, a contact hole 22b is formed within the interlayer insulating film 18 to reach the polysilicon 17, electrically connecting the metal film 24 to the polysilicon 17. A contact hole 22c is formed within the metal film 24 to reach the interlayer insulating film 18, and the metal film 24 is electrically insulated to form a portion of the gate pad portion 23 and a portion of the source pad portion 26.

[0111] Here, in the implementation method, such as Figure 6As shown, no field oxide film is provided, but in the p-type base layer 6 and p ++ A thin HTO film 16 is provided on the surface of the contact area 8. If the field oxide film is not provided, electric field concentration will occur, and the ESD resistance will decrease. Therefore, a structure to mitigate the electric field is provided in the part where electric field concentration occurs.

[0112] As a part where electric field concentration occurs, there is a connection portion 19a for the gate electrode pad portion. Therefore, the regions of the connection portion 19a for the gate electrode pad portion opposite each other in the depth direction have a region that can hold p ++ Type 8 contact area is pulled out without p. ++ The first region 6a of the contact region 8. Therefore, in the connection portion 19a, the HTO film 16 is in contact with the p-type base layer 6 in the depth direction. As a structure, for example, p-type base layers can be avoided in the width L2 or more of the polysilicon 17a of the connection portion 19a. ++ The first region 6a is a p-type contact region 8, and the second region 6a is a p-type base layer 6. Preferably, the width L1 of the first region 6a is the same as the width L2 of the polysilicon 17a (e.g., 80 μm), or the width L1 of the first region 6a extends less than 20 μm from the end 17c of the polysilicon 17a. Therefore, the width L1 of the first region 6a is preferably more than 80 μm and less than 120 μm. If the width L1 of the first region 6a is wider than 120 μm, there are more areas with low resistance, and the HTO film 16 may be broken down when displacement current flows during turn-off. In addition, if the width L1 of the first region 6a is narrower than the width L2 of the polysilicon 17a, the depletion layer width is narrow, and the ESD resistance cannot be sufficiently increased.

[0113] The impurity concentration in zone 6a is lower than p. ++ The impurity concentration in the contact region 8 is considered. A lower impurity concentration results in a wider depletion layer width, thus increasing ESD resistance using the first region 6a, achieving the same level of ESD resistance as in the case where a field oxide film is provided. In this embodiment, ESD resistance can be maintained, and manufacturing costs are reduced without providing a field oxide film.

[0114] Figure 7 This is an enlarged view of the corner of the gate electrode pad in the embodiment of the silicon carbide semiconductor device. The corner of the gate electrode pad refers to the four corner portions of the gate electrode pad. Figure 3 Part B). Figure 7 The diagram shows contact holes 22a and 22c. However, because contact hole 22a is narrow, it is shown as a single line.

[0115] Figure 8 The silicon carbide semiconductor device is an embodiment of the invention. Figure 7 Cross-sectional view of portion D-D'. Similarly, in the embodiment of the silicon carbide semiconductor device, the corner of the gate electrode pad and the connection portion 19a are located at n...+ The front side of the silicon carbide substrate is laminated with n - Type 2 silicon carbide layer, n-type region (not shown), with a lower p-type region selectively disposed inside the n-type region. + Type base region 3a, upper p + In the n-type base region 3b, a p-type base layer 6 is disposed on the n-type region. Furthermore, p-type base layers 6 are selectively disposed on the surface of the p-type base layer 6. ++ Type 8 contact area. Figure 8 This refers to the trench MOSFET 50. In the planar MOSFET 51, p + Type base region 3 becomes a layer (refer to) Figure 2 ).

[0116] In p ++ An HTO film 16 is provided on the contact area 8 and the second area 6b (described later). Polysilicon 17 is disposed on the HTO film 16, an interlayer insulating film 18 composed of BPSG and NSG is disposed on the polysilicon 17, and a metal film 24 is disposed on the interlayer insulating film 18. Contact holes 22a extending to the HTO film 16 are formed within the polysilicon 17, and the interlayer insulating film 18 fills the contact holes 22a. Through the interlayer insulating film 18, the polysilicon 17 is electrically insulated into a polysilicon 17b opposite the gate pad portion 23 in the depth direction and a portion opposite the source pad portion 26 in the depth direction.

[0117] Additionally, contact holes 22c are formed within the metal film 24 to reach the interlayer insulating film 18. The metal film 24 is electrically insulated to form a portion of the gate pad portion 23 and a portion of the source pad portion 26. The portion of the metal film 24 in the gate pad portion 23 becomes the gate electrode pad 19.

[0118] The corners of the gate electrode pads are areas where electric field concentration occurs. Therefore, the regions opposite each other in the depth direction at the corners of the gate electrode pads have a potential to increase the p... ++ Type 8 contact area is pulled out without p. ++ The second region 6b of the p-type contact region 8. Therefore, at the corner of the gate electrode pad, the HTO film 16 contacts the p-type base layer 6 in the depth direction. As a structure, for example, no p-type base layer is formed centered on the end 17d of the polysilicon 17b of the gate electrode pad 19. ++ The gate electrode pad has a p-type contact region 8, and the second region 6b serves as the p-type base layer 6. The width L3 of the second region 6b at the corner of this gate electrode pad is preferably 10 μm or more and 40 μm or less, centered on the end 17d of the polysilicon 17b. In this case, if it is wider than 40 μm, there will be more areas with low resistance, and the HTO film 16 may be broken down when displacement current flows during turn-off. Conversely, if it is narrower than 10 μm, the depletion layer width will be narrow, failing to sufficiently increase the ESD tolerance.

[0119] In the gate electrode pad 19, p can also be provided outside the corner. ++ Type 8 contact area is pulled out without p. ++ The area of ​​contact zone 8. For example, as... Figure 4 As shown, the entire outer periphery of the gate electrode pad 19 can have p ++ Type 8 contact area is pulled out without p. ++ The third region 6c of the contact region 8. In this case, for example, no p-type contact is formed centered on the end 17d of the polysilicon 17b of the gate electrode pad 19. ++ The gate electrode pad has a p-type contact region 8, and the third region 6c serves as the p-type base layer 6. The width L3 of the third region 6c on the outer periphery of the gate electrode pad is preferably 10 μm or more and 40 μm or less, centered on the end 17d of the polysilicon 17b.

[0120] The impurity concentrations in Zone 6b and Zone 6c are lower than p. ++ The impurity concentration in contact region 8 is considered. A lower impurity concentration results in a wider depletion layer width. Therefore, by utilizing the second region 6b and the third region 6c, ESD resistance is increased, thereby achieving the same level of ESD resistance as in the case where a field oxide film is provided. Thus, in this embodiment, ESD resistance can be maintained, and manufacturing costs are reduced without providing a field oxide film.

[0121] (Method for manufacturing a silicon carbide semiconductor device according to the embodiments)

[0122] The silicon carbide semiconductor device of the embodiment can be fabricated by the following method. Here, the fabrication of a trench MOSFET with a voltage rating of 1200V will be used as an example. First, prepare, for example, a 2.0 × 10⁻⁶ MOSFET. 19 / cm 3 The method of doping silicon carbide single crystals with n-type impurities such as nitrogen (N) (dopersive agents) in a manner that determines the impurity concentration. + Type 1. Silicon carbide substrate (semiconductor wafer) n + The front side of the silicon carbide substrate 1 can be, for example, a (0001) surface with an offset angle (off angle) of about 4 degrees in the <11-20> direction. Next, in n + The front side of the silicon carbide substrate 1 allows n - The type silicon carbide layer 2 is epitaxially grown with a thickness of, for example, 10 μm, and the n - The silicon carbide layer 2 is, for example, 1.0 × 10⁻⁶. 16 / cm 3 The impurity concentration is determined by the doping of n-type impurities such as nitrogen.

[0123] Next, through photolithography and ion implantation, in n -The surface layer of the silicon carbide layer 2 selectively forms n-type regions 5. In this ion implantation, for example, it can be 1 × 10⁻⁶. 17 / cm 3 Nitrogen and other n-type impurities (dopersants) are injected in a manner that determines the concentration of the dopant.

[0124] Next, p-type regions 5 are selectively formed on the surface layer using photolithography and ion implantation. + Base region 3. The outermost p + The base region 3 is formed to extend to the edge terminal region 30. In this ion implantation, for example, p... + The impurity concentration in base region 3 is 5.0 × 10⁻⁶. 18 / cm 3 p-type impurities (dopers) such as aluminum (Al) are injected in this way.

[0125] Next, in n - The surface of the silicon carbide layer 2 is made to be, for example, 2.0 × 10⁻⁶. 17 / cm 3 The p-type base layer 6, doped with p-type impurities such as aluminum, is epitaxially grown with a thickness of, for example, 1.3 μm, in a manner that determines the impurity concentration.

[0126] Through the processes up to this point, the product is manufactured in n + n layers are stacked sequentially on the front side of the silicon carbide substrate 1. - A silicon carbide substrate 40 is formed by a p-type silicon carbide layer 2 and a p-type base layer 6. Next, by repeatedly performing a series of processes under different ion implantation conditions—forming an ion implantation mask using photolithography and etching, ion implantation using the ion implantation mask, and removing the ion implantation mask—an n-type base layer is formed on the surface of the p-type base layer 6. + Type source polar region 7 and p ++ Type contact area 8. At this time, p does not form in the first area 6a, the second area 6b, and the third area 6c mentioned above. ++ Type 8 contact area.

[0127] Next, using photolithography and etching, a step 31 is formed on the surface of the p-type base layer 6 in the edge terminal region 30 at a depth of, for example, 1.5 μm from the surface of the p-type base layer 6, thus connecting the p-type base layer 6 and the n-type base layer 6. - A portion of the type 2 silicon carbide layer is removed, thus making n - The silicon carbide layer 2 is exposed. Next, the JTE structure 32 is selectively formed using photolithography and ion implantation. Next, n-type silicon carbide layer 2 is selectively formed using photolithography and ion implantation. + Type semiconductor region 33.

[0128] Next, heat treatment (annealing) is performed to, for example, p + Type base region 3, n+ Type source polar region 7, p ++ Type contact area 8, JTE structure 32, n + The semiconductor region 33 is activated. The heat treatment temperature can be, for example, around 1700°C. The heat treatment time can be, for example, around 2 minutes. It should be noted that, either all ion-implanted regions can be activated simultaneously through a single heat treatment as described above, or they can be activated by heat treatment during each ion implantation.

[0129] Next, on the surface of the p-type base layer 6 (i.e., the n+ type source region 7 and p...) ++ On the surface of the n+ type contact region 8, a trench 15 is formed by photolithography and etching, penetrating the n+ type source region 7 and the p-type base layer 6 to reach the n-type region 5. The bottom of the trench 15 reaches the p+ type base region 3.

[0130] Next, along n + Type source polar regions 7 and p ++ A gate insulating film 9 is formed on the surface of the contact region 8 and on the bottom and sidewalls of the trench 15. This gate insulating film 9 is formed by deposition using a chemical reaction such as high-temperature oxidation (HTO). ++ The gate insulating film 9 on the surface of the contact region 8 becomes Figure 6 and Figure 8 The HTO membrane 16 described.

[0131] Next, a polysilicon layer doped with, for example, phosphorus atoms (P) is formed on the gate insulating film 9. This polysilicon layer is formed in a manner that fills the trench 15. The gate electrode 10 is formed by patterning the polysilicon layer and leaving it inside the trench 15. A portion of the gate electrode 10 may also protrude from above the trench 15 (towards the source electrode pad 13 side) toward the source electrode pad 13 side.

[0132] Next, an interlayer insulating film 11 is formed by depositing, for example, phosphor glass (PSG) to a thickness of approximately 1 μm, in a manner that covers the gate insulating film 9 and the gate electrode 10. Contact holes are formed by selectively removing the interlayer insulating film 11 and the gate insulating film 9 through patterning, and n... + Type source polar regions 7 and p ++ The contact area 8 is exposed. Then, heat treatment (reflow) is performed to planarize the interlayer insulating film 11.

[0133] Next, a conductive film, which becomes the source electrode 12, is formed inside the contact hole and on the interlayer insulating film 11. This conductive film is selectively removed, for example, leaving the source electrode 12 only inside the contact hole.

[0134] Next, on the back side (n) of the silicon carbide substrate 40+ A drain electrode 14, for example, formed of a nickel (Ni) film, is formed on the back side of a silicon carbide substrate 1. Then, a heat treatment is performed at a temperature of, for example, around 970°C, to remove the nickel film. + The silicon carbide substrate 1 is ohmically bonded to the drain electrode 14.

[0135] Next, for example, an aluminum film is formed by sputtering to cover the source electrode 12 and the interlayer insulating film 11, with a thickness of approximately 5 μm. Then, the aluminum film is selectively removed, leaving a residue to cover the active region 20, thereby forming the source electrode pad 13.

[0136] Next, drain electrode pads are formed by sequentially stacking, for example, titanium (Ti), nickel (Ni), and gold (Au) on the surface of drain electrode 14. This completes the process described above. Figure 1 The trench MOSFET50 shown. Figure 2 The planar MOSFET 51 shown can also be formed using the same method.

[0137] As described above, according to the embodiment, a field oxide film is not provided, but instead provided at the connection portion of the gate pad and the corner of the gate electrode pad, a p-type oxide film is formed. ++ The area extracted from the contact region. Therefore, at the junctions and corners, the HTO film is in contact with the p-type base layer in the depth direction. The impurity concentration of the p-type base layer is higher than that of the p-type base layer. ++ The p-type contact region has a low impurity concentration, and the lower the impurity concentration, the wider the depletion layer width. Therefore, by increasing the ESD tolerance through the p-type base layer, it is possible to achieve the same level of ESD tolerance as when a field oxide film is provided. Thus, in this embodiment, ESD tolerance can be maintained, and manufacturing costs can be reduced without providing a field oxide film.

[0138] As described above, the present invention can be modified in various ways without departing from its spirit. In the various embodiments described above, for example, the dimensions and / or impurity concentrations of each part are set according to required specifications. Furthermore, in the present invention, the first conductivity type is set to p-type and the second conductivity type is set to n-type in each embodiment, but the present invention can also be made to set the first conductivity type to n-type and the second conductivity type to p-type.

[0139] Industrial availability

[0140] As described above, the silicon carbide semiconductor device of the present invention is useful for power semiconductor devices used in power conversion devices such as inverters, power supply devices for various industrial machinery, inverters for electric vehicles, etc.

Claims

1. A silicon carbide semiconductor device, characterized in that, have: Silicon carbide semiconductor substrate of the first conductivity type; A first semiconductor layer of a first conductivity type is disposed on the front side of the silicon carbide semiconductor substrate, and the impurity concentration is lower than that of the silicon carbide semiconductor substrate. A second semiconductor layer of a second conductivity type is selectively disposed on the surface layer of the first semiconductor layer on the side opposite to the silicon carbide semiconductor substrate. A first semiconductor region of a first conductivity type is selectively disposed on the surface layer of the second semiconductor layer on the side opposite to the silicon carbide semiconductor substrate. The second semiconductor region of the second conductivity type is selectively disposed on the surface layer of the second semiconductor layer opposite to the silicon carbide semiconductor substrate, and the impurity concentration is higher than that of the second semiconductor layer. A gate electrode, which is disposed on at least a portion of the surface of the second semiconductor layer sandwiched between the first semiconductor region and the first semiconductor layer, separated by a gate insulating film; A first electrode is disposed on the surfaces of the first semiconductor region and the second semiconductor region; The second electrode is disposed on the back side of the silicon carbide semiconductor substrate; as well as The gate pad portion is electrically connected to the gate electrode via gate electrode wiring. The gate pad portion includes a gate electrode pad and a connection portion that electrically connects the gate electrode pad to the gate electrode wiring. The silicon carbide semiconductor device has: The first region, in which the second semiconductor region is not provided in the region opposite the connection portion in the depth direction; as well as The second region, in the area opposite the corner of the gate electrode pad in the depth direction, does not have the second semiconductor region. An oxide film identical to the gate insulating film is disposed on the surface of the second semiconductor region, the first region, and the second region.

2. The silicon carbide semiconductor device according to claim 1, characterized in that, The width of the first region is greater than or equal to the width of the first polysilicon layer, and the first polysilicon layer is disposed in a region opposite to the connection portion in the depth direction.

3. The silicon carbide semiconductor device according to claim 2, characterized in that, The width of the first region extends less than 20 μm from the end of the first polysilicon layer.

4. The silicon carbide semiconductor device according to any one of claims 1 to 3, characterized in that, The width of the second region is centered at the end of the second polysilicon layer and is more than 10 μm and less than 40 μm. The second polysilicon layer is disposed in the region opposite to the gate electrode pad in the depth direction.

5. The silicon carbide semiconductor device according to any one of claims 1 to 4, characterized in that, The first region and the second region have the same conductivity type and the same impurity concentration as the second semiconductor layer.

6. The silicon carbide semiconductor device according to any one of claims 1 to 5, characterized in that, In the region opposite the periphery of the gate electrode pad in the depth direction, there is also a third region where the second semiconductor region is not disposed, and the oxide film is also disposed on the surface of the third region.

7. The silicon carbide semiconductor device according to any one of claims 1 to 6, characterized in that, The thickness of the oxide film is greater than 50 nm and less than 150 nm.

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