Semiconductor device and method of manufacturing the same

Abstract

A semiconductor device and a method of manufacturing the same are provided, including forming a fin structure including a stack of a plurality of first semiconductor layers and a plurality of second semiconductor layers disposed above a bottom fin structure and a hardmask layer above the stack, forming an isolation insulating layer such that the hardmask layer and the stack are exposed from the isolation insulating layer, forming a sacrificial cap layer above at least sidewalls of the exposed hardmask layer and the stack, forming one or more layers of a first dielectric layer and an insertion layer above the sacrificial cap layer and the fin structure, performing an anneal operation to convert a portion of the one or more layers of the first dielectric layer and the insertion layer from an amorphous form to a crystalline form, and removing the remaining amorphous portion of the one or more layers of the first dielectric layer and the insertion layer to form a recess.

Description

Technical Field

[0001] This disclosure relates to semiconductor devices, and more particularly to dielectric layers having concave profiles. Background Technology

[0002] As the semiconductor industry progresses to nanoscale process nodes in pursuit of higher device density, higher performance, and lower costs, challenges from manufacturing and design issues have led to the development of three-dimensional designs, such as multi-gate field-effect transistors (FETs), including fin field-effect transistors (FinFETs) and gate-all-around (GAA) field-effect transistors. Summary of the Invention

[0003] This disclosure provides a method for manufacturing a semiconductor device, comprising forming a fin structure including a stacked layer of a plurality of first semiconductor layers and a plurality of second semiconductor layers disposed above a bottom fin structure, and a hard mask layer disposed above the stacked layer; forming an insulating layer such that the hard mask layer and the stacked layer are exposed from the insulating layer; forming a sacrificial cladding layer over at least a plurality of sidewalls of the exposed hard mask layer and the stacked layer; forming one or more layers of a first dielectric layer and an insertion layer over the sacrificial cladding layer and the fin structure; performing an annealing operation to convert the one or more layers of the first dielectric layer and a portion of the insertion layer from an amorphous form to a crystalline form; and removing the remaining amorphous portions of the one or more layers of the first dielectric layer and the insertion layer to form a groove.

[0004] This disclosure provides a method for manufacturing a semiconductor device, comprising: forming a fin structure; forming an insulating layer such that an upper portion of the fin structure is exposed from the insulating layer; forming a sacrificial layer over at least a plurality of sidewalls of the exposed upper portion of the fin structure; forming a first dielectric layer over the sacrificial layer; forming a second dielectric layer over the first dielectric layer, the second dielectric layer being formed of a material different from the first dielectric layer; etching the second dielectric layer; forming two hafnium oxide and oxide intercalation layers over the recessed second dielectric layer; implanting a plurality of ions into a portion of the two hafnium oxide and oxide intercalation layers; annealing the two hafnium oxide and oxide intercalation layers to transform amorphous portions of the two hafnium oxide and oxide intercalation layers without implanted ions into crystalline portions, wherein the portions of the two hafnium oxide and oxide intercalation layers with implanted ions remain amorphous; and removing the amorphous plurality of film layers to form a groove.

[0005] This disclosure provides a semiconductor device comprising a first source / drain epitaxial layer and a second source / drain epitaxial layer; and a fin structure disposed between the first source / drain epitaxial layer and the second source / drain epitaxial layer and disposed on an insulating layer, wherein the fin structure comprises a first dielectric layer, a second dielectric layer disposed above the first dielectric layer, a plurality of film layers of a third dielectric layer, and an insertion layer disposed above the second dielectric layer; and the film layers of the third dielectric layer comprise a crystalline third dielectric layer. Attached Figure Description

[0006] The embodiments of this disclosure can be best understood from the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with industry standard practice, the various features are not drawn to scale and are for illustrative purposes only. In fact, the dimensions of various components can be arbitrarily enlarged or reduced to clearly demonstrate the features of the embodiments of this disclosure. Figure 1A , Figure 1B , Figure 2A , Figure 2B , Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 as well as Figure 8 This is a cross-sectional schematic diagram illustrating various stages of manufacturing a semiconductor device according to embodiments of the present disclosure. Figure 9A , Figure 9B , Figure 9C as well as Figure 9D These are schematic diagrams illustrating various stages of manufacturing a fin field-effect transistor, according to embodiments of the present disclosure. Figure 10A , Figure 10B as well as Figure 10C These are schematic diagrams illustrating various stages of manufacturing a fin field-effect transistor, according to embodiments of the present disclosure. Figure 11A , Figure 11B as well as Figure 11C These are schematic diagrams illustrating various stages of manufacturing a fin field-effect transistor, according to embodiments of the present disclosure. Figure 12A , Figure 12B as well as Figure 12C These are schematic diagrams illustrating various stages of manufacturing a fin field-effect transistor, according to embodiments of the present disclosure. Figure 13A , Figure 13B , Figure 13C as well as Figure 13D These are schematic diagrams illustrating various stages of manufacturing a fin field-effect transistor, according to embodiments of the present disclosure. Figure 14 A relatively detailed drawing Figure 13A The third dielectric layer and oxide insertion layer. Figure 15A The diagram illustrates the third dielectric layer and oxide insertion layer after the annealing process. Figure 15B The diagram illustrates the recesses in the third dielectric layer after the etching operation. Figure 16 The image shows the result after the etching operation. Figure 15B Semiconductor devices. Figure 17A , Figure 17B , Figure 17C as well as Figure 17D These are schematic diagrams illustrating various stages of manufacturing a fin field-effect transistor, according to embodiments of the present disclosure. Figure 18A , Figure 18B as well as Figure 18C These are schematic diagrams illustrating various stages of manufacturing a fin field-effect transistor, according to embodiments of the present disclosure. Figure 19A , Figure 19B as well as Figure 19C These are schematic diagrams illustrating various stages of manufacturing a fin field-effect transistor, according to embodiments of the present disclosure. Figure 20A , Figure 20B as well as Figure 20C These are schematic diagrams illustrating various stages of manufacturing a fin field-effect transistor, according to embodiments of the present disclosure. Figure 21A , Figure 21B as well as Figure 21C These are schematic diagrams illustrating various stages of manufacturing a fin field-effect transistor, according to embodiments of the present disclosure. Figure 22A , Figure 22B as well as Figure 22C These are schematic diagrams illustrating various stages of manufacturing a fin field-effect transistor, according to embodiments of the present disclosure. Figure 23A , Figure 23B as well as Figure 23C These are schematic diagrams illustrating various stages of manufacturing a fin field-effect transistor, according to embodiments of the present disclosure. Figure 24A , Figure 24B as well as Figure 24C These are schematic diagrams illustrating various stages of manufacturing a fin field-effect transistor, according to embodiments of the present disclosure. Figure 25A , Figure 25B as well as Figure 25C These are schematic diagrams illustrating various stages of manufacturing a fin field-effect transistor, according to embodiments of the present disclosure. Figure 26A , Figure 26B as well as Figure 26C These are schematic diagrams illustrating various stages of manufacturing a fin field-effect transistor, according to embodiments of the present disclosure. Figure 27A , Figure 27B , Figure 27C , Figure 27D , Figure 27E as well as Figure 27F These are schematic diagrams illustrating various stages of manufacturing a fin field-effect transistor, according to embodiments of the present disclosure. The reference numerals in the attached figures are explained as follows: 10: Semiconductor substrate 15: Hard mask layer 15A: First hard mask layer 15B: Second hard mask layer 18: Insulation layer 20: First semiconductor layer 22: Bottom semiconductor layer 22A: First bottom semiconductor layer 22B: Second bottom semiconductor layer 23: Bottom fin structure 24: Top semiconductor layer 25: Second semiconductor layer 26: Covering the semiconductor layer 29: Fin Structure 30: Insulating material layer 35: Sacrifice drapery 40: First dielectric layer 45: Second dielectric layer 50: Third dielectric layer 51: Oxide Insertion Layer 53: Dielectric layer 57: Space 62: Sacrificial gate dielectric layer 64: Sacrificial gate electrode layer 65: Sidewall spacers 66: Hard mask layer 70: Internal spacer 71: Concave hole 82: First epitaxial layer 84: Second epitaxial layer 86: Third epitaxial layer 90: Sixth dielectric layer 92: Contact opening 95: Source / Drain Contacts 102: Gate dielectric layer 104: Gate electrode layer 162: Amorphous core 164: Crystalline shell 165: Dashed line X: Direction Y: direction Z: Direction X1-X1: Section line X2-X2: Section line Y1: Section line Y2: Section line Detailed Implementation

[0007] The following disclosure provides numerous embodiments or examples for implementing different elements of the provided subject matter. Specific examples of each element and its configuration are described below to simplify the description of embodiments of this disclosure. Of course, these are merely examples and are not intended to limit the embodiments of this disclosure. For example, if the description refers to a first element formed on a second element, it may include embodiments where the first and second elements are in direct contact, or embodiments where an additional element is formed between the first and second elements such that they are not in direct contact. Furthermore, reference values ​​and / or letters may be repeated in various examples of embodiments of this disclosure. Such repetition is for the purpose of brevity and clarity and is not intended to indicate a relationship between the different embodiments and / or configurations discussed.

[0008] Furthermore, spatially relative terms, such as "below," "below," "lower," "above," and "higher," may be used to facilitate the description of the relationship between one or more components or features in the diagram and another component or feature(s). Spatially relative terms are used to include different orientations of the device in use or operation, as well as the orientations described in the diagram. When the device is rotated to different orientations (rotated 90 degrees or other orientations), the spatially relative adjectives used will also be interpreted according to the orientation after the rotation. Additionally, the term "made of" can mean "including" or "composed of." In this disclosure, the term "one of A, B, and C" means "A, B, and / or C" (A, B, C, A and B, A and C, B and C, or A and B and C), and unless otherwise stated, does not mean an element from A, an element from B, and an element from C.

[0009] FinFETs are non-planar multi-gate transistors with fins extending perpendicularly from the transistor's gate and source and drain. Multiple finFETs can be coupled together to provide an integrated circuit device. One factor determining the device performance of a finFET or a similar device is the capacitance between adjacent fins. Increased parasitic capacitance reduces circuit speed, thereby degrading device performance.

[0010] In this disclosure, source / drain represents the source and / or drain. It is worth noting that in this disclosure, the source and drain can be used interchangeably, and the structures described above are substantially the same.

[0011] Figure 1A , Figure 1B , Figure 2A , Figure 2B , Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 , Figure 9A , Figure 9B , Figure 9C as well as Figure 9D This disclosure illustrates various stages in the fabrication of a semiconductor FinFET device according to embodiments of the present disclosure. It should be understood that additional operational features may be provided. Figures 1A to 9D The illustrated steps before, during, or after the process, and some of the operational steps described below, can be replaced or omitted for additional embodiments of the method. The order of operations / processes in this disclosure is also interchangeable.

[0012] like Figure 1A As illustrated, a plurality of first semiconductors 20 and a plurality of second semiconductor layers 25 are alternately formed over a semiconductor substrate 10. In some embodiments, the semiconductor substrate 10 is a crystalline Si substrate. In other embodiments, the semiconductor substrate 10 comprises semiconductors of other elements, such as germanium; compound semiconductors comprise group IV-IV compound semiconductors such as SiC and SiGe, group III-V compound semiconductors such as GaAs, GaP, GaN, InP, InAs, InSb, GaAsP, AlGaN, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof. In one embodiment, the semiconductor substrate 10 is a silicon layer of a silicon-on-insulator (SOI) substrate.

[0013] The first semiconductor layer 20 and the second semiconductor layer 25 are formed of materials with different lattice constants, and may comprise one or more layers of Si, Ge, SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, or InP. In some embodiments, the first semiconductor layer 20 and the second semiconductor layer 25 are formed of Si, a Si compound, SiGe, Ge, or a Ge compound. In one embodiment, the first semiconductor layer 20 is Si. 1-x Ge x Where x is equal to or greater than about 0.2 and equal to or less than about 0.6, and the second semiconductor layer 25 is Si 1-y Ge y , where y is less than x and equal to or less than about 0.1. In this disclosure, "M compound" or "M-major compound" means that the main component of the compound is M.

[0014] The thickness of the first semiconductor layer 20 may be equal to or less than the thickness of the second semiconductor layer 25. In some embodiments, the thickness of the first semiconductor layer 20 ranges from about 4 nanometers to about 30 nanometers, while in other embodiments, the thickness of the first semiconductor layer 20 ranges from about 5 nanometers to about 20 nanometers. In some embodiments, the thickness of the second semiconductor layer 25 ranges from about 4 nanometers to about 30 nanometers, while in other embodiments, the thickness of the second semiconductor layer 25 ranges from about 5 nanometers to about 20 nanometers. The thicknesses of the plurality of first semiconductor layers 20 may be the same or different from each other, and the thicknesses of the plurality of second semiconductor layers 25 may be the same or different from each other. Although Figure 1A The illustration shows three first semiconductor layers 20 and three second semiconductor layers 25. The number of semiconductor layers is not limited to three. In some embodiments, the number of semiconductor layers may be 1, 2, or more than 3, or less than 10.

[0015] Furthermore, in some embodiments, the top semiconductor layer 24 is epitaxially grown over the stacked structure of the first semiconductor layer 20 and the second semiconductor layer 25. In some embodiments, the top semiconductor layer 24 is Si. 1-z Ge zWhere z is equal to or greater than about 0.2 and equal to or less than about 0.7. In some embodiments, z is equal to x. The thickness of the top semiconductor layer 24 is greater than the thickness of each first semiconductor layer 20 and each second semiconductor layer 25. In some embodiments, the thickness of the top semiconductor layer 24 ranges from about 10 nanometers to about 100 nanometers, while in other embodiments, the thickness of the top semiconductor layer 24 ranges from about 20 nanometers to about 50 nanometers. Furthermore, in some embodiments, a cap semiconductor layer 26 is epitaxially formed on the top semiconductor layer 24, and the cap semiconductor layer 26 is formed of a material different from that of the top semiconductor layer 24. In some embodiments, the cap semiconductor layer 26 is formed of Si, and its thickness ranges from about 0.5 nanometers to about 10 nanometers. The cap semiconductor layer 26 is used to control the out-diffusion of Ge from the top semiconductor layer 24 and to maintain the surface quality of the top semiconductor layer 24 during subsequent chemical mechanical polishing (CMP) processing.

[0016] Furthermore, a hard mask layer 15 is formed over the cover semiconductor layer 26. The hard mask layer 15 comprises one or more layers of insulating material or amorphous semiconductor material (e.g., amorphous silicon (a-Si)). In some embodiments, the hard mask layer 15 comprises a first hard mask layer 15A and a second hard mask layer 15B. In some embodiments, the first hard mask layer 15A is silicon oxide having a thickness ranging from about 1 nanometer to about 20 nanometers, while the second hard mask layer 15B is silicon nitride having a thickness ranging from about 10 nanometers to about 100 nanometers.

[0017] In formation Figure 1A Following the multiple stacked layers illustrated, multiple fin structures are formed using one or more photolithography and etching operations, such as... Figure 2A As illustrated. The fin structure can be patterned using any suitable method. For example, the fin structure can be patterned using one or more optical lithography processes, including dual patterning or multi-patterning processes. Generally, dual patterning or multi-patterning processes combine lithography with self-alignment processes to create, for example, patterns with smaller pitch than those obtained using a single, direct lithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a lithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the hard mask layer 15. By using the patterned hard mask layer as an etch mask, the stacked semiconductor layers are patterned into a fin structure 29, as shown. Figure 2AAs illustrated. In some embodiments, the top semiconductor layer 24 and the cover semiconductor layer 26 are part of a hard mask layer and an etch stop layer (ESL) for subsequent chemical mechanical polishing.

[0018] exist Figure 2A In this configuration, fin structure 29 extends in the Y direction and is arranged in the X direction. The number of fin structures is not proportional to... Figure 2A The two shown are limited to one, and may be as small as one or as large as three. In some embodiments, one or more dummy fin structures are formed on both sides of the fin structure 29 to improve pattern fidelity during patterning operations. Figure 2A As shown, the alternating stacking of the first semiconductor layer and the second semiconductor layer is disposed on the bottom fin structure 23.

[0019] In some embodiments, the upper portion of the fin structure 29 has a width ranging from about 5 nanometers to about 40 nanometers along the Y direction, while in other embodiments, the upper portion of the fin structure 29 has a width ranging from about 10 nanometers to about 30 nanometers along the Y direction.

[0020] In some embodiments, a first bottom semiconductor layer 22A is epitaxially formed on the semiconductor substrate 10 before the alternating stacking of the first and second semiconductor layers. The first bottom semiconductor layer 22A is formed of a material different from that of the semiconductor substrate 10. In some embodiments, when the semiconductor substrate 10 is a Si substrate, the first bottom semiconductor layer 22A comprises SiGe, wherein the Ge content is from about 10 atomic percent (atomic %) to about 60 atomic percent (SiGe). 0.9 Ge 0.1 To Si 0.4 Ge 0.6 In some embodiments, the thickness of the first bottom semiconductor layer 22A ranges from about 4 nanometers to about 30 nanometers, while in other embodiments, the thickness of the first bottom semiconductor layer 22A ranges from about 5 nanometers to about 25 nanometers.

[0021] Furthermore, a second bottom semiconductor layer 22B is epitaxially formed over the first bottom semiconductor layer 22A. The second bottom semiconductor layer 22B is formed of a material different from that of the first bottom semiconductor layer 22A. In some embodiments, when the first bottom semiconductor layer is SiGe, the second bottom semiconductor layer 22B comprises Si or SiGe, wherein the Ge content is less than the content of the first bottom semiconductor layer 22A and ranges from about 0 atomic percent to about 10 atomic percent. In some embodiments, the thickness of the second bottom semiconductor layer 22B ranges from about 40 nanometers to about 200 nanometers, while in other embodiments, the thickness of the second bottom semiconductor layer 22B ranges from about 50 nanometers to about 150 nanometers.

[0022] Next, as Figure 1B As illustrated, a first semiconductor layer 20 and a second semiconductor layer 25 are alternately formed above the second bottom semiconductor layer 22B. Furthermore, approximately... Figure 2A , forming fin structures 29, such as Figure 2B drawn.

[0023] In the formation of such Figure 2A After the illustrated fin structure 29, one or more insulating layers 18 are formed above the fin structure 29, and an insulating material layer 30 containing one or more layers of insulating material is formed above the substrate, such that the fin structure 29 with the insulating layer 18 is completely embedded in the insulating material layer 30.

[0024] The insulating materials of the insulating substrate 18 and the insulating material layer 30 may be the same or different from each other, and may include one or more silicon oxide, silicon nitride, silicon oxynitride (SiON), SiOCN, SiOC, SiCN, fluoride-doped silicate glass (FSG), or low dielectric constant dielectric materials. In some embodiments, the insulating substrate 18 is formed of silicon oxide or silicon nitride, and the insulating material layer 30 is formed of silicon oxide. The insulating material is formed by low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), flowable chemical vapor deposition (FCVD), and / or atomic layer deposition (ALD). After the insulating material layer 30 is formed, an annealing operation may be performed. Next, planarization operations such as chemical mechanical polishing (CMP) and / or etch-back are performed to expose the upper surface of the hard mask layer 15 (the second hard mask layer 15B) from the insulating material layer 30, such as... Figure 3 drawn.

[0025] Next, as Figure 4 As illustrated, the insulating material layer is etched to form an insulating isolation layer 30, exposing multiple upper portions of the fin structures 29. This operation separates the fin structures 29 from each other by the insulating isolation layer 30, which is also known as shallow trench isolation (STI).

[0026] In some embodiments, the insulating material layer 30 is etched back until the upper portion of the bottom fin structure 23 is exposed. The first semiconductor layer 20 is a sacrificial layer that will subsequently be removed, while the second semiconductor layer 25 is subsequently formed in semiconductor wires or sheets (nano-body or nano-structure) and serves as a channel layer for a fully wound gate (GAA) field-effect transistor (FET). In some embodiments, during or after the recess etching of the insulating material layer 30, the liner insulating layer 18, the hard mask layer 15, and the cap semiconductor layer 26 are removed, thereby exposing the top semiconductor layer 24, such as... Figure 4 drawn.

[0027] After the insulating layer 30 is formed, a sacrificial cladding layer 35 is formed above the exposed portion of the fin structure 29, such as... Figure 5 As illustrated. The sacrificial cladding layer 35 comprises one or more layers of insulating or semiconductor material. In some embodiments, the sacrificial cladding layer 35 comprises an amorphous or polycrystalline semiconductor material (e.g., Si, SiC, SiGe, or Ge). In some embodiments, the sacrificial cladding layer 35 is amorphous SiGe with a Ge concentration ranging from about 20 atomic percent to about 40 atomic percent. In some embodiments, the Ge concentration of the sacrificial cladding layer 35 is the same as or approximately (within ±5%) the Ge concentration of the first semiconductor layer 20. In some embodiments, the thickness of the sacrificial cladding layer 35 ranges from about 5 nanometers to about 50 nanometers. If the thickness of the sacrificial cladding layer 35 is less than this range, the space for forming the metal gate will be too small and some layers of the metal gate structure will not be properly formed. If the thickness of the sacrificial cladding layer 35 is greater than this range, the electrical separation between adjacent fin structures will be insufficient. In some embodiments, a thin semiconductor layer is formed over the exposed portion of the fin structure 29 before forming the sacrificial cladding layer 35. In some embodiments, the thin semiconductor layer is undoped Si. In some embodiments, the undoped Si is crystalline Si. In some embodiments, the thickness of the thin semiconductor layer ranges from about 2 nanometers to about 3 nanometers. In some embodiments, the sacrificial cladding layer 35 is conventionally formed by chemical vapor deposition (CVD) or atomic layer deposition (ALD). In some embodiments, the deposition temperature of the sacrificial cladding layer 35 is less than or approximately the deposition temperature of the first semiconductor layer 20. In some embodiments, the deposition temperature of the sacrificial cladding layer 35 ranges from about 500°C to about 600°C. The source gas comprises a mixture of SiH4, GeH4, and HCl, with H2 or N2 as the carrier gas. The sacrificial cladding layer 35 controls the stress in the isolation region.

[0028] Next, as Figure 6 As illustrated, one or more etch-back operations are performed to remove multiple horizontal portions of the sacrificial cladding layer 35, thereby exposing the upper surface of the top semiconductor layer 24 and the upper surface of the insulating layer 30. In some embodiments, a wet cleaning process to remove residues is performed after the deposition-etch operation.

[0029] Subsequently, a first dielectric layer 40 is formed above the fin structure, and a second dielectric layer 45 is formed above the first dielectric layer 40, such that the fin structure is completely embedded in the second dielectric layer 45, as follows. Figure 7 As illustrated. The first dielectric layer 40 comprises one or more layers of insulating material, such as silicon oxide, silicon oxynitride, silicon nitride, SiOC, SiCN, or SiOCN, and is formed by low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), or any other suitable thin film formation method. In some embodiments, SiCN or SiOCN is used as the first dielectric layer 40. In some embodiments, such as Figure 7 As illustrated, a first dielectric layer 40 is compliantly formed over the fin structures, allowing spaces to be formed between adjacent fin structures. In some embodiments, the thickness of the first dielectric layer 40 ranges from about 2.5 nanometers to about 20 nanometers, while in other embodiments, the thickness of the first dielectric layer 40 ranges from about 5 nanometers to about 10 nanometers.

[0030] The material of the second dielectric layer 45 is different from the material of the first dielectric layer 40. In some embodiments, the second dielectric layer 45 comprises one or more layers of insulating material, such as silicon oxide, silicon oxynitride, silicon nitride, SiOC, SiCN, or SiOCN, and is formed by low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), or any other suitable thin film formation method. In some embodiments, the second dielectric layer 45 is formed of silicon nitride or silicon oxide. In some embodiments, the second dielectric layer 45 comprises a first layer and a second layer. The first layer is silicon oxide and is formed by a thermal annealing process at 400°C to 800°C in an inert gas environment, such as flowable chemical vapor deposition (FCVD). The second layer is also silicon oxide and is formed by a plasma-enhanced chemical vapor deposition (PECVD) process. In some embodiments, the thickness of the second dielectric layer 45 ranges from about 60 nanometers to about 500 nanometers. In some embodiments, such as Figure 7 As illustrated, the second dielectric layer 45 completely fills the space between adjacent fin structures. In other embodiments, voids are formed in the bottom portion of the space. In some embodiments, one or more additional dielectric layers are formed between the first dielectric layer 40 and the second dielectric layer 45.

[0031] After the second dielectric layer 45 is formed, a planarization operation, such as an etch-back process or chemical mechanical polishing (CMP), is performed to planarize the second dielectric layer 45 and expose the upper surface of the top semiconductor layer 24. In some embodiments, the top semiconductor layer 24 is lightly etched from about 5 nanometers to about 10 nanometers. Furthermore, one or more additional etch-back operations are performed to etch the second dielectric layer 45, such as... Figure 8 As illustrated, the second dielectric layer 45 is etched to a level substantially equal to (within ±5 nanometers) the level of the interface between the top semiconductor layer 24 and the uppermost semiconductor layer of the second semiconductor layer 25. In some embodiments, the first dielectric layer 40 is subsequently further trimmed (etched) to expose a portion of the sacrificial cladding layer 35.

[0032] Next, a multilayer film containing a third dielectric layer 50 and an oxide insertion layer 51 is formed (stacked) on the recessed second dielectric layer 45 in an alternating sequence. Figure 9A This is a schematic cross-sectional view along the X direction. Figure 9B To correspond to along the Y direction Figure 9A A schematic diagram of the cross-section along line Y1-Y1, and Figure 9C To correspond to along the Y direction Figure 9A A schematic diagram of the cross section Y2-Y2.

[0033] The material of the third dielectric layer 50 is different from the materials of the first dielectric layer 40 and the second dielectric layer 45. In some embodiments, the third dielectric layer 50 comprises a material having a lower etch rate for etching polycrystalline silicon or amorphous SiGe than the second dielectric layer. In some embodiments, the third dielectric layer 50 comprises a high dielectric constant dielectric layer. In some embodiments, the third dielectric layer 50 comprises a dielectric material having a higher dielectric constant (k) than the second dielectric layer 45 and / or the first dielectric layer 40.

[0034] In some embodiments, the third dielectric layer 50 comprises one or more layers of hafnium oxide (e.g., HfO). x The oxide intercalation layer 51 comprises silicon dioxide (SiO2). In other embodiments, the oxide intercalation layer 51 comprises a silicon-based oxide, a silicon-based nitride, a silicon-based carbide, or a metal-based oxide, a metal-based nitride, or a metal-based carbide. (0 < x ≦ 2)

[0035] In some embodiments, the third dielectric layer 50 comprises a lower film layer on the second dielectric layer 45 and a higher film layer, with an oxide intercalation layer 51 interspersed therebetween. The third dielectric layer 50 may be formed by low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), or any other suitable thin film formation method. Figure 9A As illustrated, the third dielectric layer 50 completely fills the space between adjacent fin structures. After forming the third dielectric layer 50 that completely covers the fin structures, a planarization operation, such as an etch-back process or chemical mechanical polishing (CMP), is performed to planarize the upper surface of the third dielectric layer 40 and expose the upper surface of the top semiconductor layer 24, as shown. Figure 9D As illustrated. In some embodiments, the thickness of the third dielectric layer 50 remaining on the top semiconductor layer 24 ranges from about 5 nanometers to about 100 nanometers, and the width of the third dielectric layer 50 on top of the top semiconductor layer 24 ranges from about 10 nanometers to about 80 nanometers, depending on device and / or process requirements. Therefore, a wall-like fin structure (dummy fin structure) is formed between adjacent fin structures by the first dielectric layer 40, the second dielectric layer 45, and the third dielectric layer 50.

[0036] In some embodiments, the second dielectric layer 45 is omitted, and a third dielectric layer 50 and an oxide insertion layer 51 are formed on the first dielectric layer 40. In other embodiments, both the first dielectric layer 40 and the second dielectric layer 45 are omitted, and a third dielectric layer 50 and an oxide insertion layer 51 are formed on the insulating layer 30.

[0037] In some embodiments, the distance between adjacent fin structures is from about 20 nanometers to about 300 nanometers. In some embodiments, the thickness of the third dielectric layer 50 ranges from about 4 nanometers to about 10 nanometers. In some embodiments, the thickness of the oxide intercalation layer 51 ranges from about 0.5 nanometers to about 1 nanometer.

[0038] Therefore, as Figure 10A , Figure 10B as well as Figure 10C The illustration shows the removal of the top semiconductor layer 24 by one or more dry or wet etching operations. Figure 10A , Figure 10B , Figure 10C , Figure 11A , Figure 11B , Figure 11C , Figure 12A , Figure 12B , Figure 12C , Figure 13A , Figure 13B , Figure 13C , Figure 17A , Figure 17B , Figure 17C, Figure 18A , Figure 18B , Figure 18C , Figure 19A , Figure 19B , Figure 19C , Figure 20A , Figure 20B , Figure 20C , Figure 21A , Figure 21B as well as Figure 21C In the diagram, "Figure B" is a cross-sectional view along the Y-direction corresponding to section line Y1-Y1 in "Figure A," while "Figure C" is a cross-sectional view along the Y-direction corresponding to section line Y2-Y2 in "Figure A." Figure 10A As illustrated, a trench with sidewalls formed by the sacrificial cladding layer 35 is formed. After removing the top semiconductor layer 24, a sacrificial gate dielectric layer 62 is formed on the topmost semiconductor layer of the second semiconductor layer 25, on the sidewalls of the first dielectric layer 45, and on the third dielectric layer 50, as shown. Figures 10A to 10C As illustrated. The sacrificial gate dielectric layer 62 comprises one or more layers of insulating material, such as a silicon oxide-based material. In one embodiment, silicon oxide formed by chemical vapor deposition (CVD) is used. In some embodiments, the thickness of the sacrificial gate dielectric layer 62 ranges from about 1 nanometer to about 5 nanometers.

[0039] In addition, such as Figure 11A , Figure 11B as well as Figure 11C As illustrated, a sacrificial (dummy) gate electrode layer 64 is formed, and a hard mask layer 66 is formed on the sacrificial gate electrode layer 64. The sacrificial gate electrode layer 64 is blanket-deposited on the sacrificial gate dielectric layer 62 and over the third dielectric layer 50, such that the third dielectric layer 50 is completely embedded in the sacrificial gate electrode layer 64. The sacrificial gate electrode layer 64 comprises silicon, such as polycrystalline silicon or amorphous silicon. In some embodiments, the thickness of the sacrificial gate electrode layer 64 ranges from about 100 nanometers to about 200 nanometers. In some embodiments, the sacrificial gate electrode layer 64 is planarized. The sacrificial gate dielectric layer 62 and the sacrificial gate electrode layer 64 are deposited using chemical vapor deposition (CVD), including low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or other suitable processes. Subsequently, a hard mask layer 66 is formed over the sacrificial gate electrode layer. The hard mask layer 66 comprises one or more layers of silicon nitride or silicon oxide.

[0040] Next, a patterning operation is performed on the hard mask layer 66, and the sacrificial gate electrode layer 64 is patterned into a sacrificial gate electrode, as follows: Figure 12A , Figure 12B as well as Figure 12C As illustrated. In some embodiments, the width of the sacrificial gate electrode layer 64 ranges from about 5 nanometers to about 30 nanometers, while in other embodiments, the width of the sacrificial gate electrode layer 64 ranges from about 10 nanometers to about 20 nanometers. In some embodiments, two or more sacrificial gate electrodes are arranged in the Y direction. In some embodiments, one or more dummy sacrificial gate electrodes are formed on both sides of the sacrificial gate electrode to improve pattern fidelity.

[0041] Furthermore, sidewall spacers 65 are formed above the sacrificial gate electrode layer 64, such as Figure 13A , Figure 13B Figure and Figure 13C As illustrated. One or more insulating layers are deposited in a compliant manner to have a thickness substantially equal to that of the sidewalls formed by the first dielectric layer 40 on surfaces such as sidewalls, horizontal surfaces, and vertical surfaces on top of the sacrificial gate electrode. Sidewall spacers 65 are then formed by anisotropic etching. In some embodiments, the sidewall spacers 65 have a thickness ranging from about 3 nanometers to about 20 nanometers. The spacer sidewalls 65 comprise one or more silicon nitride, SiON, SiCN, SiCO, SiOCN, or any other suitable dielectric material. In some embodiments, because the height of the third dielectric layer 50 is much smaller than the height of the sacrificial gate electrode layer 64 with a hard mask layer, the thickness of the sidewall spacers on the sidewalls of the first dielectric layer on the third dielectric layer 50 is less than the thickness of the sidewall spacers on the sacrificial gate electrode layer 64, or no sidewall spacers are formed on the sidewalls of the first dielectric layer on the third dielectric layer 50, such as... Figure 13D drawn.

[0042] To reduce capacitance, an annealing operation is performed to transform the third dielectric layer 50 and the oxide insertion layer 51 from an amorphous form to a crystalline form. In some embodiments, annealing is performed for about 1 second to about 60 seconds at a temperature of about 800°C to about 1000°C in an inert gas environment (such as in an O2N2, Ar, or He environment). In some embodiments, the crystallinity of the third dielectric layer 50 is determined based on the annealing temperature and the concentration of the inert ambient gas.

[0043] In some other embodiments, the crystallinity of the third dielectric layer 50 is determined based on the thickness of the third dielectric layer 50. In some embodiments, the third dielectric layer 50 becomes crystalline when it is about 3 nanometers thick or greater. The third dielectric layer 50 remains amorphous when it is less than about 3 nanometers thick. In some embodiments, nanobeam diffraction (NBD) is used to determine the crystalline and amorphous portions of the third dielectric layer 50.

[0044] Following the annealing operation, an etching operation is performed to remove the amorphous third dielectric layer 50. The crystalline third dielectric layer 50 has a different etching rate than the amorphous third dielectric layer 50, and therefore, during the etching operation, the amorphous third dielectric layer 50 is removed while the crystalline portion is retained. The third dielectric layer 50 can be selectively etched using an isotropic etching process, such as wet etching. In some embodiments, the wet etchant comprises a mixed solution of H2O2, CH3COOH, and HF, followed by rinsing with H2O. In some embodiments, etching with the mixed solution and rinsing with water are repeated 10 to 20 times. In some embodiments, the etching time using the mixed solution ranges from about 1 minute to about 2 minutes. In some embodiments, the mixed solution is used at a temperature ranging from about 60°C to about 90°C.

[0045] In some embodiments, the etching operation includes a plasma etching operation using a source gas containing carbon and fluorine atoms. In some embodiments, the source gas is a mixture of C4F6 and CHF3. Etching the amorphous third dielectric layer 50 creates concavities (grooves).

[0046] Figure 14 A relatively detailed drawing Figure 13A The third dielectric layer 50 and the oxide insertion layer 51 are present. The third dielectric layer 50 has a crystalline structure while the dielectric layer 53 has an amorphous structure. As shown in the figure, the third dielectric layer 50 forms a "shell" surrounding the dielectric layer 53. For ease of explanation and illustration, the first dielectric layer 40 and the second dielectric layer 45 are shown in the figure. Figure 14 The middle part is omitted.

[0047] Figure 15A The diagram illustrates the third dielectric layer 50 and the oxide insertion layer 51 after the annealing operation. Figure 15B The diagram illustrates the recesses in the third dielectric layer after the etching operation. (Example) Figure 15A As illustrated, the annealing process forms a crystalline shell 164 and an amorphous core 162, each containing a third dielectric layer 50 and an oxide insertion layer 51. The dashed line 165 represents the general boundary between the crystalline shell 164 and the amorphous core 162. Figure 15B As illustrated, after the etching operation, the amorphous core 162 is removed, resulting in a recess 71. The recess 71 is surrounded by (or defined by) a crystal shell 164. Figure 16 The image shows the result after the etching operation. Figure 13D The semiconductor device. Due to the presence of the third dielectric layer 50 (e.g., containing hafnium oxide), the shape of the recess 71 reduces the metal gate capacitance.

[0048] In some embodiments, prior to the annealing operation, ions (dopants) are implanted into the third dielectric layer 50 to restrict crystallization of the third dielectric layer 50. The ions are implanted into the relatively central portions of the third dielectric layer 50 between adjacent fins. After the annealing operation, the ion-containing portions of the third dielectric layer 50 remain relatively amorphous, while the portions of the third dielectric layer 50 closer to the fins are crystallized. The amorphous portions have a relatively higher etch rate than the crystalline portions, and the amorphous portions are removed (etched) during the etching operation to form recesses 71. In some embodiments, the dopants comprise silicon (Si) ions, argon (Ar) ions, carbon (C) ions, and / or phosphorus (P) ions. In some embodiments, the dopant concentration is from about 0.1% to about 50%.

[0049] In some embodiments, when an ion implantation operation is used, no oxide insertion layer is formed. Ion implantation is performed to transform the structure of the upper layer of the third dielectric layer 50, which is more easily transformed into an amorphous state by annealing than the remaining lower layer.

[0050] Next, at the source / drain region, the stacked structure of the first dielectric layer 20 and the second dielectric layer 25 is etched downwards using one or more etching operations to form the source / drain space 69, as shown below. Figure 17A , Figure 17B , Figure 17C as well as Figure 17D drawn. Figure 17D Draw the corresponding to Figure 17A A cross-sectional schematic diagram along line Y2-Y2. In some embodiments, the bottom fin structure 23 is also partially etched. In some embodiments, the sacrificial cladding layer 35 is partially or completely removed during etching. In some embodiments, the sacrificial cladding layer 35 is also removed during etching to form the source / drain space 69 when no or only thin sidewall spacers are formed on the sidewalls of the first dielectric layer on the third dielectric layer 50. In some embodiments, prior to forming the sacrificial gate structure, an operation is performed regarding... Figure 14 , Figure 15A as well as Figure 15B The operation explained (annealing and removal of the amorphous layer) in this case is to form a groove by removing the amorphous layer present beneath the sacrificial gate structure (the groove is filled by the sacrificial gate electrode layer 64).

[0051] Furthermore, forming Figure 18A , Figure 18B as well as Figure 18CThe internal spacers are illustrated. The first semiconductor layer 20 is laterally etched in the Y direction within the source / drain space 69 to form a plurality of recesses. In some embodiments, the lateral etching depth of the first semiconductor layer 20 ranges from about 0.5 nanometers to about 10 nanometers, while in other embodiments, the lateral etching depth of the first semiconductor layer 20 ranges from about 1 nanometer to about 5 nanometers.

[0052] When the first semiconductor layer 20 is SiGe and the second semiconductor layer 25 is Si, the first semiconductor layer 20 can be selectively etched by an isotropic etching process, such as wet etching. In some embodiments, the wet etchant comprises a mixed solution of H2O2, CH3COOH, and HF, followed by rinsing with H2O. In some embodiments, etching with the mixed solution and rinsing with water are repeated 10 to 20 times. In some embodiments, the etching time using the mixed solution ranges from about 1 minute to about 2 minutes. In some embodiments, the mixed solution is used at a temperature ranging from about 60°C to about 90°C.

[0053] Next, a fifth dielectric layer is compliantly formed on the lateral etched ends of the first semiconductor layer 20 in the source / drain space 69 and on the end face of the second semiconductor layer 25. The fifth dielectric layer comprises one of silicon nitride and silicon oxide, SiON, SiOC, SiCN, and SiOCN, or any other suitable dielectric material. In some embodiments, the fifth dielectric layer is formed of a material different from that of the sidewall spacers 65. The fifth dielectric layer may be formed by atomic layer deposition (ALD) or any other suitable method.

[0054] After the fifth dielectric layer is formed, an etching operation is performed to partially remove the fifth dielectric layer, thereby forming the inner spacer 70, as shown. Figure 18B As illustrated. In some embodiments, the end face of the inner spacer 70 is recessed more than the end face of the second semiconductor layer 25. In some embodiments, the recess ranges from about 0.2 nanometers to about 3 nanometers, while in other embodiments, the recess ranges from about 0.5 nanometers to about 2 nanometers. In other embodiments, the recess is less than 0.5 nanometers and may be zero (the end face of the inner spacer 70 is flush with the end face of the second semiconductor layer 25). In some embodiments, an additional dielectric layer having a thickness smaller than that of the fifth dielectric layer is formed before the fifth dielectric layer is formed, and thus the inner spacer 70 has a two-layer structure.

[0055] Subsequently, as Figure 19A , Figure 19B as well as Figure 19CAs illustrated, a source / drain epitaxial layer is formed in the source / drain space 69. For an n-type field-effect transistor (FET), the source / drain epitaxial layer comprises one or more layers of SiP, SiAs, SiCP, SiPAs, and / or SiC, while for a p-type field-effect transistor, the source / drain epitaxial layer comprises one or more layers of SiGe, GeSn, and / or SiGeSn. In some embodiments, for a p-type field-effect transistor, the source / drain epitaxial layer is doped with boron (B). In some embodiments, the source / drain epitaxial layer comprises multiple film layers.

[0056] In some embodiments, the source / drain epitaxial layer of an n-type field-effect transistor (FET) includes a first epitaxial layer 82, a second epitaxial layer 84, and a third epitaxial layer 86. In some embodiments, the first epitaxial layer 82 is formed of SiP, SiAs, or SiAs:P, or a combination thereof. In some embodiments, the phosphorus (P) concentration of the first epitaxial layer 82 is in the range of about 0.5 × 10⁻⁶. 19 atoms / cm 3 Approximately 5×10 20 atoms / cm 3 In other embodiments, the phosphorus (P) concentration of the first epitaxial layer 82 ranges from approximately 0.8 × 10⁻⁶. 19 atoms / cm 3 Approximately 2×10 20 atoms / cm 3 In some embodiments, the second epitaxial layer 84 is formed of SiP. In some embodiments, the phosphorus (P) concentration of the second epitaxial layer 84 is greater than the phosphorus (P) concentration of the first epitaxial layer 82, and the phosphorus (P) concentration of the second epitaxial layer 84 ranges from about 1 × 10⁻⁶. 21 atoms / cm 3 Approximately 5×10 21 atoms / cm 3 In other embodiments, the phosphorus (P) concentration of the second epitaxial layer 84 ranges from approximately 2 × 10⁻⁶. 21 atoms / cm 3 To approximately 4×10 21 atoms / cm 3 In some embodiments, the third epitaxial layer 86 is formed of SiGeP. In some embodiments, the phosphorus (P) concentration of the third epitaxial layer 86 is equal to or less than the phosphorus (P) concentration of the second epitaxial layer 84, and higher than the phosphorus (P) concentration of the first epitaxial layer 82, and the phosphorus (P) concentration of the third epitaxial layer 86 is in the range of about 0.5 × 10⁻⁶. 21 atoms / cm 3 To approximately 4×10 21 atoms / cm 3In other embodiments, the phosphorus (P) concentration of the third epitaxial layer 86 ranges from approximately 1 × 10⁻⁶. 21 atoms / cm 3 Approximately 3×10 21 atoms / cm 3 In some embodiments, the germanium (Ge) concentration of the third epitaxial layer 86 ranges from about 0.5 atomic percent to about 10 atomic percent, while in other embodiments, the germanium (Ge) concentration of the third epitaxial layer 86 ranges from about 1 atomic percent to about 5 atomic percent.

[0057] In some embodiments, the source / drain epitaxial layer of a p-type field-effect transistor (FET) includes a first epitaxial layer 82, a second epitaxial layer 84, and a third epitaxial layer 86. In some embodiments, the first epitaxial layer 82 is formed of boron-doped SiGe. In some embodiments, the germanium (Ge) content of the first epitaxial layer 82 ranges from about 15 atomic percent to about 30 atomic percent. In some embodiments, the boron (B) concentration of the first epitaxial layer 82 ranges from about 1 × 10⁻⁶. 19 atoms / cm 3 To approximately 1×10 21 atoms / cm 3 In other embodiments, the boron (B) concentration of the first epitaxial layer 82 ranges from approximately 5 × 10⁻⁶. 19 atoms / cm 3 Approximately 5×10 20 atoms / cm 3 In some embodiments, the second epitaxial layer 84 is formed of boron-doped SiGe. In some embodiments, the germanium (Ge) content of the second epitaxial layer 84 ranges from about 20 atomic percent to about 35 atomic percent. In some embodiments, the boron (B) concentration of the second epitaxial layer 84 is equal to or greater than the boron (B) concentration of the first epitaxial layer 82, and the boron (B) concentration of the second epitaxial layer 84 ranges from about 0.5 × 10⁻⁶. 20 atoms / cm 3 To approximately 1×10 21 atoms / cm 3 In other embodiments, the boron (B) concentration of the second epitaxial layer 84 ranges from approximately 1 × 10⁻⁶. 20 atoms / cm 3 Approximately 5×10 20 atoms / cm 3In some embodiments, the third epitaxial layer 86 is formed of boron-doped SiGe. In some embodiments, the germanium (Ge) concentration of the third epitaxial layer 86 ranges from about 25 atomic percent to about 60 atomic percent. In some embodiments, the average germanium (Ge) content of the third epitaxial layer 86 is greater than the germanium (Ge) content of the second epitaxial layer 84. In some embodiments, the boron (B) concentration of the third epitaxial layer 86 ranges from about 5 × 10⁻⁶. 19 atoms / cm 3 Approximately 5×10 21 atoms / cm 3 In other embodiments, the boron (B) concentration of the third epitaxial layer 86 ranges from approximately 1 × 10⁻⁶. 20 atoms / cm 3 Approximately 3×10 21 atoms / cm 3 .

[0058] Source / drain epitaxial layers are formed using epitaxial growth methods such as chemical vapor deposition (CVD), atomic layer deposition (ALD), or molecular beam epitaxy (MBE).

[0059] After forming the source / drain epitaxial layers, a sixth dielectric layer 90 is formed above the source / drain epitaxial layers, such as... Figure 20A , Figure 20B as well as Figure 20C As illustrated. The sixth dielectric layer 90 comprises one of silicon nitride and silicon oxide, SiON, SiOC, SiCN, and SiOCN, or any other suitable dielectric material. Next, one or more planarization operations, such as chemical mechanical polishing (CMP), are performed to expose the upper surface of the sacrificial gate electrode 64, as shown. Figure 20B as well as Figure 20C drawn.

[0060] Next, the sacrificial gate electrode 64 and the sacrificial gate dielectric layer 62 are removed, as follows: Figure 21A , Figure 21B as well as Figure 21C As illustrated. The sixth dielectric layer 90 protects the source / drain epitaxial layers during the removal of the sacrificial gate structure. The sacrificial gate structure can be removed using plasma dry etching and / or wet etching. When the sacrificial gate electrode 64 is polysilicon, a wet etchant such as tetramethylammonium hydroxide (TMAH) solution can be used to selectively remove the sacrificial gate electrode 64. The sacrificial gate dielectric layer 62 is then removed using plasma dry etching and / or wet etching.

[0061] After removing the sacrificial gate structure, the sacrificial cladding layer 35 is removed by one or more dry etching operations and / or wet etching operations, such as... Figure 22A , Figure 22B as well as Figure 22C drawn.

[0062] Next, the first semiconductor layer 20 is removed to form semiconductor lines or semiconductor wafers (channel regions) of the second semiconductor layer 25, such as... Figure 23A , Figure 23B as well as Figure 23C As illustrated, the first semiconductor layer 20 can be removed or etched using an etchant capable of selectively etching the first semiconductor layer 20 instead of the second semiconductor layer 25. As illustrated in Figure 23B, due to the formation of the inner spacer 70, the etching of the first semiconductor layer 20 stops at the inner spacer 70.

[0063] After releasing the semiconductor lines or semiconductor wafers (channel regions) of the second semiconductor layer 25, a gate dielectric layer 102 is formed around each channel region, and a gate electrode layer 104 is further formed on the gate dielectric layer 102, such as... Figure 24A , Figure 24B as well as Figure 24C As illustrated. In some embodiments, the structure and / or material of the gate electrode of an n-type fully wound gate (GAA) field-effect transistor (FET) differs from the structure and / or material of the gate electrode of a p-type fully wound gate field-effect transistor.

[0064] In some embodiments, the gate dielectric layer 102 comprises one or more layers of dielectric material, such as silicon oxide, silicon nitride, or a high-dielectric-constant dielectric material, other suitable dielectric materials, and / or combinations thereof. Examples of high-dielectric-constant dielectric materials include HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, aluminum oxide, titanium oxide, hafnium dioxide-aluminum (HfO2-Al2O3) alloys, other suitable high-dielectric-constant dielectric materials, and / or combinations thereof. In some embodiments, the gate dielectric layer 102 includes an interface layer (not shown) formed between the channel layers and the dielectric material. The gate dielectric layer 102 may be formed by chemical vapor deposition (CVD), atomic layer deposition (ALD), or any suitable method. In one embodiment, the gate dielectric layer 102 is formed using a highly compliant deposition process such as atomic layer deposition to ensure that the gate dielectric layer has a uniform thickness around each channel layer. In one embodiment, the thickness of the gate dielectric layer 102 ranges from about 1 nanometer to about 6 nanometers.

[0065] Gate electrode layer 104 is formed on gate dielectric layer 102 to surround each channel layer. Gate electrode 104 comprises one or more layers of conductive material, such as polysilicon, aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, metal alloys, other suitable materials, and / or combinations thereof.

[0066] The gate electrode layer 104 can be formed by chemical vapor deposition (CVD), atomic layer deposition (ALD), electroplating, or other suitable methods. The gate dielectric layer and gate electrode layer are then planarized using, for example, chemical mechanical polishing (CMP) until the top surfaces of the sixth dielectric layer 90 and the third dielectric layer 50 are exposed. In some embodiments, after the planarization operation, the gate electrode layer 104 is etched back to form a cap insulating layer (not shown) over the recessed gate electrode layer 104. The cap insulating layer comprises one or more layers of a silicon nitride-based material, such as silicon nitride. The cap insulating layer can be formed by depositing an insulating material followed by a planarization operation.

[0067] In some embodiments of this disclosure, one or more work function adjustment layers (not shown) are interposed between the gate dielectric layer 102 and the gate electrode layer 104. The work function adjustment layer is formed of a conductive material, such as a single layer of TiN, TaN, TaAlC, TiC, TaC, Co, Al, TiAl, HfTi, TiSi, TaSi, or TiAlC, or two or more layers of the aforementioned materials. For n-type field-effect transistors (FETs), one or more TaN, TaAlC, TiN, TiC, Co, TiAl, HfTi, TiSi, and TaSi are used as the work function adjustment layer, while for p-type field-effect transistors, one or more TiAlC, Al, TiAl, TaN, TaAlC, TiN, TiC, and Co are used as the work function adjustment layer. The work function adjustment layer can be formed by atomic layer deposition (ALD), physical vapor deposition (PVD), chemical vapor deposition (CVD), electron beam evaporation, or other suitable processes. Furthermore, for n-channel and p-channel field-effect transistors, different metal layers may be used for the work function adjustment layer, thus allowing the work function adjustment layer to be formed separately.

[0068] Next, as Figure 24A , Figure 24B as well as Figure 24CThe illustration shows the removal of the fourth dielectric layer 55 using a plasma etching operation. In some embodiments, the source gas of the plasma comprises C4F4. In some embodiments, the fourth dielectric layer 55 is selectively removed from the third dielectric layer 50 to form a space 57.

[0069] Furthermore, such as Figure 25A , Figure 25B as well as Figure 25C As illustrated, the remaining third dielectric layer 50 is processed by plasma to form a V-shaped space 57. In some embodiments, the height of the third dielectric layer 50 is reduced by about 30% to about 70% of its original height. In some embodiments, the remaining height of the third dielectric layer 50 ranges from about 2 nanometers to about 6 nanometers. In some embodiments, the source gas of the plasma comprises HBr.

[0070] Next, as Figure 26A , Figure 26B as well as Figure 26C As shown, the sixth dielectric layer 90 above the source / drain epitaxial layer 84 is etched to form a contact opening 92.

[0071] Subsequently, the contact opening 92 is filled with one or more conductive materials to form the source / drain contact 95, such as... Figure 27A , Figure 27B as well as Figure 27C As illustrated. In some embodiments, the source / drain contact 95 includes a liner and a body metal layer. The liner includes one or more Ti, TiN, WN, Ta, or TaN, while the body metal layer includes one or more Cu, Al, Ni, Co, Ru, W, or alloys thereof.

[0072] In some embodiments, such as Figure 27D As illustrated, source / drain contacts 95 connect adjacent source / drain regions. In this case, a portion of the source / drain contacts 95 is disposed within the V-shaped space 57 of the third dielectric layer. In some embodiments, such as Figure 27E As illustrated, when the contact opening 92 is formed, the sidewall spacers 65 and / or a portion of the sidewall spacers 40 are also etched to form a wider opening, and then contact metal is formed in the wider opening to form the source / drain contact 95. In this case, because the third dielectric layer 50 is etched to form a V-shaped space 57, the V-shaped portion has a small aspect ratio, which improves the landing of the contact above the third dielectric layer. Figure 27F To correspond to Figure 27D as well as Figure 27E A plan view (top view).

[0073] The embodiments of this disclosure advantageously reduce capacitive effects (e.g., parasitic capacitance) in FinFET devices by creating a concave profile in the dielectric layer formed between adjacent fins. It should be understood that not all advantages are necessarily discussed herein, nor are all embodiments required to possess specific advantages, and other embodiments may offer different advantages.

[0074] According to one aspect of this disclosure, a method of manufacturing a semiconductor device is provided, comprising forming a fin structure including a stack of a plurality of first semiconductor layers and a plurality of second semiconductor layers disposed above a bottom fin structure and a hard mask layer disposed above the stacked layers, forming an insulating layer such that the hard mask layer and the stacked layers are exposed from the insulating layer, forming a sacrificial cladding layer over at least a plurality of sidewalls of the exposed hard mask layer and the stacked layers, forming one or more layers of a first dielectric layer and an insertion layer over the sacrificial cladding layer and the fin structure, performing an annealing operation to convert a portion of the one or more layers of the first dielectric layer and the insertion layer from an amorphous form to a crystalline form, and removing the remaining amorphous portions of the one or more layers of the first dielectric layer and the insertion layer to form a groove. In some embodiments, prior to the annealing operation, the method of manufacturing the semiconductor device includes implanting a plurality of dopants into the one or more layers of the first dielectric layer and the insertion layer. In some embodiments, the dopants include at least one of silicon (Si) ions, argon (Ar) ions, and phosphorus (P) ions. In some embodiments, the method further includes forming a second dielectric layer over a sacrificial cladding layer, forming a third dielectric layer over the second dielectric layer, the third dielectric layer being formed of a material different from the second dielectric material layer, etching the third dielectric layer, and forming one or more layers of the first dielectric layer and an insertion layer over the recessed third dielectric layer. In some embodiments, the first dielectric layer is formed of a material different from the third dielectric layer. In some embodiments, the second dielectric layer comprises at least one of SiOC, SiOCN, or SiCN. In some embodiments, the third dielectric layer comprises at least one of silicon nitride, silicon oxide, or silicon oxynitride. In some embodiments, the first dielectric layer comprises at least one of hafnium oxide, zirconium oxide, aluminum oxide, or titanium oxide. In some embodiments, the insertion layer comprises silicon oxide. In some embodiments, the sacrificial cladding layer is amorphous or polycrystalline Si or SiGe. In some embodiments, the thickness of the crystalline first dielectric layer is 4 nm to 10 nm. In some embodiments, the thickness of the insertion layer is 0.5 nm to 1 nm. In some embodiments, the crystalline portion of the first dielectric layer contacts and surrounds the amorphous portion of the first dielectric layer with a plurality of sidewalls of the fin structure.

[0075] According to another aspect of this disclosure, a method for manufacturing a semiconductor device is provided, comprising forming a fin structure, forming an insulating layer such that an upper portion of the fin structure is exposed from the insulating layer, forming a sacrificial layer over at least a plurality of sidewalls of the exposed upper portion of the fin structure, forming a first dielectric layer over the sacrificial layer, forming a second dielectric layer over the first dielectric layer, the second dielectric layer being formed of a material different from the first dielectric layer, etching the second dielectric layer, forming two hafnium oxide and oxide intercalation layers over the recessed second dielectric layer, implanting a plurality of ions into a portion of the two hafnium oxide and oxide intercalation layers, annealing the two hafnium oxide and oxide intercalation layers to transform amorphous portions of the two hafnium oxide and oxide intercalation layers without implanted ions into crystalline portions, wherein the portions of the two hafnium oxide and oxide intercalation layers with implanted ions remain amorphous, and removing the amorphous plurality of film layers to form a groove. In some embodiments, the oxide intercalation layer comprises silicon oxide. In some embodiments, the ions include at least one of silicon (Si) ions, argon (Ar) ions, and phosphorus (P) ions. In some embodiments, the crystalline portion surrounds the amorphous portion of the first dielectric layer.

[0076] According to another aspect of this disclosure, a semiconductor device is provided, comprising a first source / drain epitaxial layer and a second source / drain epitaxial layer, and a fin structure disposed between the first and second source / drain epitaxial layers and on an insulating layer. The fin structure includes a first dielectric layer, a second dielectric layer, a plurality of film layers disposed above the first dielectric layer and a third dielectric layer, and an insertion layer disposed above the second dielectric layer. The film layers of the third dielectric layer comprise a crystalline third dielectric layer. In some embodiments, the thickness of the crystalline third dielectric layer is 4 nanometers to 10 nanometers. In some embodiments, the thickness of the insertion layer is 0.5 nanometers to 1 nanometer.

[0077] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand the viewpoints of the embodiments described herein. Those skilled in the art will understand that other processes and structures can be easily designed or modified based on the embodiments described herein to achieve the same purpose and / or advantages as the embodiments described herein. Those skilled in the art will also understand that such equivalent structures do not depart from the spirit and scope of this disclosure, and various changes, substitutions, and replacements can be made without departing from the spirit and scope of this disclosure. Therefore, the scope of protection of this disclosure shall be determined by the appended claims.

Claims

1. A method for manufacturing a semiconductor device, comprising: A fin structure is formed, comprising a stacked layer of a plurality of first semiconductor layers and a plurality of second semiconductor layers disposed above a bottom fin structure, and a hard masking layer located above the stacked layer; An insulating layer is formed so that the hard masking layer and the stacked layer are exposed from the insulating layer; A sacrificial cladding layer is formed over at least a plurality of sidewalls of the exposed hard masking layer and the stacked layer; One or more layers of a first dielectric layer and an insertion layer are formed above the sacrificial cladding layer and the fin structure; An annealing operation is performed to convert the one or more layers of the first dielectric layer and a portion of the insertion layer from an amorphous form to a crystalline form; as well as Remove one or more layers of the first dielectric layer and the remaining amorphous portion of the insertion layer to form a groove.

2. The method of manufacturing a semiconductor device as claimed in claim 1, wherein prior to the annealing operation, the method of manufacturing the semiconductor device further comprises: Multiple dopants are implanted into the first dielectric layer and the insertion layer.

3. The method for manufacturing a semiconductor device as claimed in claim 2, wherein the dopant includes at least one of silicon (Si) ions, argon (Ar) ions, and phosphorus (P) ions.

4. The method for manufacturing a semiconductor device as claimed in claim 1, further comprising: A second dielectric layer is formed above the sacrificial cladding layer; A third dielectric layer is formed above the second dielectric layer, and the third dielectric layer is formed of a material different from the second dielectric layer; The third dielectric layer was etched; and The one or more layers forming the first dielectric layer and the insertion layer are above the recessed third dielectric layer.

5. The method of manufacturing a semiconductor device as claimed in claim 4, wherein the first dielectric layer is formed of a material different from the third dielectric layer.

6. The method of manufacturing a semiconductor device as claimed in claim 4, wherein the second dielectric layer comprises at least one of SiOC, SiOCN, or SiCN.

7. The method of manufacturing a semiconductor device as claimed in claim 4, wherein the third dielectric layer comprises at least one of silicon nitride, silicon oxide, or silicon oxynitride.

8. The method of manufacturing a semiconductor device as claimed in claim 1, wherein the first dielectric layer comprises at least one of hafnium oxide, zirconium oxide, aluminum oxide, or titanium oxide.

9. The method of manufacturing a semiconductor device as claimed in claim 1, wherein the insertion layer comprises silicon oxide.

10. The method of manufacturing a semiconductor device as claimed in claim 1, wherein the sacrificial cladding layer is amorphous or polycrystalline Si or SiGe.

11. The method of manufacturing a semiconductor device as claimed in claim 1, wherein the thickness of the crystalline first dielectric layer is 4 nanometers to 10 nanometers.

12. The method of manufacturing a semiconductor device as claimed in claim 1, wherein the thickness of the insertion layer is 0.5 nanometers to 1 nanometer.

13. The method of manufacturing a semiconductor device as claimed in claim 1, wherein the crystalline portion of the first dielectric layer contacts and surrounds the amorphous portion of the fin structure with respect to a plurality of sidewalls of the first dielectric layer.

14. A method for manufacturing a semiconductor device, comprising: Forming a fin structure; An insulating layer is formed, causing an upper portion of the fin structure to be exposed from the insulating layer; A sacrificial layer is formed above at least a plurality of sidewalls of the exposed upper portion of the fin structure; A first dielectric layer is formed above the sacrificial layer; A second dielectric layer is formed on top of the first dielectric layer, and the second dielectric layer is formed of a material different from the first dielectric layer; The second dielectric layer was etched. Two layers of hafnium oxide and an oxide insertion layer are formed above the recessed second dielectric layer; Multiple ions are implanted into the two hafnium oxide layers and a portion of the oxide insertion layer; Annealing the two hafnium oxide layers and the oxide insertion layer to transform the multiple portions of the two hafnium oxide layers and the oxide insertion layer without implanted ions from amorphous to crystalline, wherein the portions of the two hafnium oxide layers and the oxide insertion layer with implanted ions remain amorphous; as well as Multiple layers of the amorphous film are removed to form a groove.

15. The method of manufacturing a semiconductor device as claimed in claim 14, wherein the oxide intercalation layer comprises silicon oxide.

16. The method of manufacturing a semiconductor device as claimed in claim 14, wherein the ions include at least one of silicon (Si) ions, argon (Ar) ions, and phosphorus (P) ions.

17. The method of manufacturing a semiconductor device as claimed in claim 14, wherein the crystalline portion surrounds the amorphous portion of the first dielectric layer.

18. A semiconductor device, comprising: A first source / drain epitaxial layer and a second source / drain epitaxial layer; as well as A fin structure is disposed between the first source / drain epitaxial layer and the second source / drain epitaxial layer, and on an insulating layer, wherein: The fin structure includes a first dielectric layer, a second dielectric layer disposed above the first dielectric layer, multiple film layers of a third dielectric layer, and an insertion layer disposed above the second dielectric layer. as well as The third dielectric layer comprises a crystalline third dielectric layer, wherein the third dielectric layer has a concave top surface.

19. The semiconductor device of claim 18, wherein the thickness of the crystallized third dielectric layer is 4 nanometers to 10 nanometers.

20. The semiconductor device of claim 18, wherein the thickness of the insertion layer is 0.5 nanometers to 1 nanometer.

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