一种适用于宽频率范围的高精度自适应时钟电路
By combining a time-to-digital converter and a code-to-code converter with a configurable delay chain, and utilizing an ultra-fine-tuned inverter and one-hot code transmission gate logic, the problem of large clock errors in traditional adaptive clock circuits over a wide voltage range is solved. This achieves high-precision clock signal delay and frequency matching, improving the robustness and accuracy of the circuit.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SOUTHEAST UNIV
- Filing Date
- 2022-08-31
- Publication Date
- 2026-07-17
AI Technical Summary
Traditional adaptive clock circuits have large clock errors over a wide voltage range, affecting the performance of the matching clock frequency and adaptive clock stretching system. Furthermore, the buffer delay deviation increases as the voltage decreases, resulting in insufficient circuit accuracy.
A configurable delay chain is combined with a time-to-digital converter and a code-to-code converter. High-precision clock signal delay is achieved through an ultra-fine-tuning inverter and one-hot code transmission gate logic. A closed-loop negative feedback adjustment method is used to adjust the configuration code of the delay chain to match the clock frequency and phase.
It achieves high-precision matching of clock signals over a wide frequency range, reduces circuit complexity and power consumption, improves circuit robustness and accuracy, and reduces signal scheduling pressure.
Smart Images
Figure CN115395929B_ABST