Circuit system and gate circuit thereof

Abstract

The application discloses a circuit system and a gate circuit thereof, which are applied to the technical field of circuits and include a first optocoupler, a second optocoupler and a target resistor. The input sides of the first optocoupler and the second optocoupler are used for receiving first signals and second signals respectively, and the output sides of the first optocoupler and the second optocoupler are connected in series. When the gate circuit is used as an AND gate circuit, the first end of the output side of the first optocoupler is connected with a positive electrode of a first power supply, the second end of the output side of the second optocoupler is used as an output end of the AND gate circuit and is connected with a first end of the target resistor, and a second end of the target resistor is grounded. When the gate circuit is used as a NAND gate circuit, the first end of the output side of the first optocoupler is used as an output end of the NAND gate circuit and is connected with the second end of the target resistor, the first end of the target resistor is connected with the positive electrode of the first power supply, and the second end of the output side of the second optocoupler is grounded. The application can effectively realize the AND gate circuit and the NAND gate circuit, and the circuit structure is simple and has high reliability.

Description

Technical Field

[0001] This invention relates to the field of circuit technology, and in particular to a circuit system and its gate circuit. Background Technology

[0002] In many circuit systems, it is necessary to use AND circuits to perform AND operations on external signals, or to use NAND circuits to perform NAND operations on external signals. External signals are generally voltage signals.

[0003] Figure 1 This is a schematic diagram of the logic structure of the circuit. Figure 1 An AND circuit has two inputs and one output. When all inputs are high (logic 1), the output is high; when any one input is low (logic 0), the output is low. A NAND circuit can be viewed as a superposition of AND and NOT gates. When all inputs are high, the output is low; when at least one input is low, the output is high.

[0004] Current circuit designs typically employ optocouplers for signal isolation, followed by AND or NAND operations using logic chips. The complex structure of logic chips results in high costs and low reliability when implementing AND or NAND circuits in current solutions. Furthermore, since logic chips generally operate at 5V, a 5V power supply is required, further complicating the design. Moreover, current AND or NAND circuits require a greater number of logic chips if there are two or more input signals to process, making the design even more complex.

[0005] In summary, how to effectively implement AND and NAND circuits and improve circuit reliability is a technical problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0006] The purpose of this invention is to provide a circuit system and its gate circuits to effectively implement AND and NAND circuits and improve circuit reliability.

[0007] To solve the above-mentioned technical problems, the present invention provides the following technical solution:

[0008] A gate circuit includes: a first optocoupler, a second optocoupler, and a target resistor;

[0009] The input side of the first optocoupler is used to receive a first signal. When the first signal is high, the output side of the first optocoupler is in an on state, and when the first signal is low, the output side of the first optocoupler is in an off state. The input side of the second optocoupler is used to receive a second signal. When the second signal is high, the output side of the second optocoupler is in an on state, and when the second signal is low, the output side of the second optocoupler is in an off state. The second terminal of the output side of the first optocoupler is connected to the first terminal of the output side of the second optocoupler.

[0010] When the gate circuit is used as an AND gate circuit, the first terminal of the output side of the first optocoupler is connected to the positive terminal of the first power supply, the second terminal of the output side of the second optocoupler serves as the output terminal of the AND gate circuit and is connected to the first terminal of the target resistor, and the second terminal of the target resistor is grounded.

[0011] When the gate circuit is used as a NAND gate circuit, the first terminal of the output side of the first optocoupler serves as the output terminal of the NAND gate circuit and is connected to the second terminal of the target resistor. The first terminal of the target resistor is connected to the positive terminal of the first power supply, and the second terminal of the output side of the second optocoupler is grounded.

[0012] Preferably, it also includes: a first resistor and a second resistor;

[0013] The first end of the first resistor is used to receive the first signal, the second end of the first resistor is connected to the first end of the input side of the first optocoupler, and the second end of the input side of the first optocoupler is grounded.

[0014] The first end of the second resistor is used to receive the second signal, the second end of the second resistor is connected to the first end of the input side of the second optocoupler, and the second end of the input side of the second optocoupler is grounded.

[0015] Preferably, it further includes: a first diode and a second diode;

[0016] The anode of the first diode is connected to the second terminal of the first resistor, and the cathode of the first diode is connected to the first terminal of the input side of the first optocoupler.

[0017] The anode of the second diode is connected to the second end of the second resistor, and the cathode of the second diode is connected to the first end of the input side of the first optocoupler.

[0018] Preferably, both the first resistor and the second resistor are adjustable resistors.

[0019] Preferably, it also includes a resistance value indication circuit for:

[0020] Based on the input voltage drop of the first optocoupler, the current reference value of the input side of the first optocoupler, and the voltage value when the first signal is high, the resistance reference value of the first resistor is determined and output.

[0021] Based on the input voltage drop of the second optocoupler, the current reference value of the input side of the second optocoupler, and the voltage value when the second signal is at a high level, the resistance reference value of the second resistor is determined and output.

[0022] Preferably, it also includes a voltage controller for:

[0023] Receive a voltage adjustment signal carrying a target voltage value, and adjust the voltage value of the positive terminal of the first power supply to the target voltage value.

[0024] Preferably, it further includes: a third to an Nth optocoupler connected in series on the output side, and the first end of the output side of the third optocoupler is connected to the second end of the output side of the second optocoupler;

[0025] The input sides of the third to the Nth optocouplers are used to receive the third to the Nth signals in sequence. When the i-th signal is high, the output side of the i-th optocoupler is in the on state, and when the i-th signal is low, the output side of the i-th optocoupler is in the off state. N is a positive integer not less than 3, and i is a positive integer and 3≤i≤N.

[0026] When the gate circuit is used as an AND gate circuit, the first terminal of the output side of the first optocoupler is connected to the positive terminal of the first power supply, the second terminal of the output side of the Nth optocoupler is used as the output terminal of the AND gate circuit and is connected to the first terminal of the target resistor, and the second terminal of the target resistor is grounded.

[0027] When the gate circuit is used as a NAND gate circuit, the first terminal of the output side of the first optocoupler is used as the output terminal of the NAND gate circuit and is connected to the second terminal of the target resistor. The first terminal of the target resistor is connected to the positive terminal of the first power supply, and the second terminal of the output side of the Nth optocoupler is grounded.

[0028] Preferably, it further includes: a third resistor to an Nth resistor; and the first end of the i-th resistor is used to receive the i-th signal, the second end of the i-th resistor is connected to the first end of the input side of the i-th optocoupler, and the second end of the input side of the i-th optocoupler is grounded.

[0029] Preferably, it further includes: a third diode to an Nth diode; and the anode of the i-th diode is connected to the second terminal of the i-th resistor, and the cathode of the i-th diode is connected to the first terminal of the input side of the i-th optocoupler.

[0030] A circuit system comprising the gate circuits described above.

[0031] By applying the technical solution provided in the embodiments of the present invention, only a first optocoupler, a second optocoupler, and a target resistor are needed to realize the functions of AND circuit and NAND circuit, without the need to set up a logic chip as in traditional solutions. The circuit structure is simple and the reliability is very high.

[0032] Specifically, the input side of the first optocoupler is used to receive a first signal. When the first signal is high, the output side of the first optocoupler is in an on state, and when the first signal is low, the output side of the first optocoupler is in an off state. The input side of the second optocoupler is used to receive a second signal. When the second signal is high, the output side of the second optocoupler is in an on state, and when the second signal is low, the output side of the second optocoupler is in an off state. The second terminal of the output side of the first optocoupler is connected to the first terminal of the output side of the second optocoupler.

[0033] When the first output terminal of the first optocoupler is connected to the positive terminal of the first power supply, and the second output terminal of the second optocoupler is used as the output terminal of the AND gate and connected to the first terminal of the target resistor, and the second terminal of the target resistor is grounded, it can be seen that if both the first signal and the second signal are high level, the output terminal of the gate is high level; if either the first signal or the second signal is low level, the output terminal of the gate is low level. That is, the gate can effectively realize the function of the AND gate at this time.

[0034] When the first output terminal of the first optocoupler is used as the output terminal of a NAND gate and connected to the second terminal of the target resistor, and the first terminal of the target resistor is connected to the positive terminal of the first power supply, and the second output terminal of the second optocoupler is grounded, it can be seen that if both the first and second signals are high, the output terminal of the gate is low; if either the first or second signal is low, the output terminal of the gate is high. In this case, the gate effectively implements the function of a NAND gate. Furthermore, using optocouplers to implement AND and NAND circuits provides signal isolation and high reliability.

[0035] In summary, the solution of this application only requires a first optocoupler, a second optocoupler, and a target resistor to effectively realize AND and NAND circuits. The circuit structure is simple and highly reliable. Attached Figure Description

[0036] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0037] Figure 1 This is a schematic diagram of the logic structure of the circuit;

[0038] Figure 2 This is a schematic diagram of a gate circuit in this invention when it is used as an AND gate circuit;

[0039] Figure 3 This is a schematic diagram of a gate circuit in this invention when it is used as a NAND gate circuit;

[0040] Figure 4 This is a schematic diagram of another structure of the gate circuit in this invention when it is used as an AND gate circuit;

[0041] Figure 5 This is a schematic diagram of another structure of the gate circuit in this invention when it is used as a NAND gate circuit;

[0042] Figure 6 This is another structural diagram of the gate circuit in this invention when it is used as an AND gate circuit;

[0043] Figure 7 This is another structural diagram of the gate circuit in this invention when it is used as a NAND gate circuit. Detailed Implementation

[0044] The core of this invention is to provide a gate circuit that can effectively implement AND and NAND circuits, with a simple circuit structure and high reliability.

[0045] To enable those skilled in the art to better understand the present invention, the invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. Obviously, the described embodiments are merely some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0046] Please refer to Figure 2 and Figure 3 , Figure 2 This is a schematic diagram of a gate circuit in this invention when it is used as an AND gate circuit. Figure 3 This is a schematic diagram of a gate circuit in the present invention when it is used as a NAND gate circuit. The gate circuit may include: a first optocoupler Q1, a second optocoupler Q2, and a target resistor R0.

[0047] The input side of the first optocoupler Q1 is used to receive a first signal. When the first signal is high, the output side of the first optocoupler Q1 is in the on state, and when the first signal is low, the output side of the first optocoupler Q1 is in the off state. The input side of the second optocoupler Q2 is used to receive a second signal. When the second signal is high, the output side of the second optocoupler Q2 is in the on state, and when the second signal is low, the output side of the second optocoupler Q2 is in the off state. The second terminal of the output side of the first optocoupler Q1 is connected to the first terminal of the output side of the second optocoupler Q2.

[0048] When the gate circuit is used as an AND gate circuit, the first terminal of the output side of the first optocoupler Q1 is connected to the positive terminal of the first power supply, the second terminal of the output side of the second optocoupler Q2 is used as the output terminal of the AND gate circuit and is connected to the first terminal of the target resistor R0, and the second terminal of the target resistor R0 is grounded.

[0049] When the gate circuit is used as a NAND gate circuit, the first terminal of the output side of the first optocoupler Q1 is used as the output terminal of the NAND gate circuit and is connected to the second terminal of the target resistor R0. The first terminal of the target resistor R0 is connected to the positive terminal of the first power supply, and the second terminal of the output side of the second optocoupler Q2 is grounded.

[0050] Specifically, in the scheme of this application, the input side of the first optocoupler Q1 is used to receive the first signal, and the input side of the second optocoupler Q2 is used to receive the second signal. Figure 2 and Figure 3 In the diagram, A and B are used to represent the first signal and the second signal, respectively. A+ represents the positive signal line of the first signal and A- represents the negative signal line of the first signal. Correspondingly, B+ represents the positive signal line of the second signal and B- represents the negative signal line of the second signal.

[0051] When the first signal is high, the output of the first optocoupler Q1 is in the ON state; conversely, it is in the OFF state when the first signal is low. Similarly, when the second signal is high, the output of the second optocoupler Q2 is in the ON state; conversely, it is in the OFF state when the second signal is low.

[0052] It should be noted that whether the first signal is high or low depends on whether there is sufficient current on the input side of the first optocoupler Q1 at that level. Only when there is sufficient current on the input side of the first optocoupler Q1 will its output side be effectively turned on. Similarly, whether the second signal is high or low depends on whether there is sufficient current on the input side of the second optocoupler Q2 at that level. Only when there is sufficient current on the input side of the second optocoupler Q2 will its output side be effectively turned on.

[0053] Regardless of whether the gate circuit is used as an AND gate or a NAND gate, in this application, the second terminal of the output side of the first optocoupler Q1 is connected to the first terminal of the output side of the second optocoupler Q2, that is, in this application, the output side of the first optocoupler Q1 and the output side of the second optocoupler Q2 are connected in series.

[0054] Taking a high-level signal and A+ as an example (specifically 24V), current flows through the input side of the first optocoupler Q1 and then returns to A-, forming a loop. Similarly, when the second signal is high and B+ is 24V, current flows through the input side of the second optocoupler Q2 and then returns to B-, forming a loop. If the gate circuit is an AND gate, the first output terminal of the first optocoupler Q1 is connected to the positive terminal of the first power supply, and the second output terminal of the second optocoupler Q2 serves as the output terminal of the AND gate and is connected to the first terminal of the target resistor R0, which is grounded. From the circuit structure, it can be seen that when both the output terminals of the first optocoupler Q1 and the second optocoupler Q2 are conducting, a loop can be formed at the output terminals. That is, the current output from the first power supply can flow through the output terminals of the first optocoupler Q1 and the second optocoupler Q2 to ground. At this time, the output terminal of the AND gate... Figure 2 The OUTPUT signal is high. When either the first or second signal is low, meaning that neither the output of the first optocoupler Q1 nor the output of the second optocoupler Q2 is turned off, a loop will not be formed at the output. In this case, the output of the AND gate circuit... Figure 2 The OUTPUT is low.

[0055] If the gate circuit is used as a NAND gate circuit, please refer to [reference needed]. Figure 3 The first output terminal of the first optocoupler Q1 serves as the output terminal of a NAND gate and is connected to the second terminal of the target resistor R0. The first terminal of the target resistor R0 is connected to the positive terminal of the first power supply, and the second output terminal of the second optocoupler Q2 is grounded. From the circuit structure, it can be seen that when both the output terminals of the first optocoupler Q1 and the second optocoupler Q2 are conducting, a loop can be formed at the output terminals. That is, the current output from the first power supply can reach ground through the output terminals of the first optocoupler Q1 and the second optocoupler Q2. At this time, the output terminal of the AND gate... Figure 3 The OUTPUT signal is low. When either the first or second signal is low, meaning neither the output of the first optocoupler Q1 nor the output of the second optocoupler Q2 is turned off, a loop will not be formed at the output. In this case, the output of the AND gate circuit... Figure 3 The OUTPUT is high.

[0056] This application Figure 2 and Figure 3 In the diagram, the positive terminal of the first power supply is marked as VCC.

[0057] In one specific embodiment of the present invention, it may further include: a first resistor R1 and a second resistor R2;

[0058] The first end of the first resistor R1 is used to receive the first signal, the second end of the first resistor R1 is connected to the first end of the input side of the first optocoupler Q1, and the second end of the input side of the first optocoupler Q1 is grounded.

[0059] The first end of the second resistor R2 is used to receive the second signal, the second end of the second resistor R2 is connected to the first end of the input side of the second optocoupler Q2, and the second end of the input side of the second optocoupler Q2 is grounded.

[0060] This implementation takes into account that when the voltage value of the first signal or the second signal is high, the optocoupler may be damaged. Therefore, two current-limiting resistors are set, namely the first resistor R1 set on the input side of the first optocoupler Q1 and the second resistor R2 set on the input side of the second optocoupler Q2, so as to effectively protect the first optocoupler Q1 and the second optocoupler Q2.

[0061] Furthermore, in one specific embodiment of the present invention, both the first resistor R1 and the second resistor R2 are adjustable resistors.

[0062] As described above, whether the first signal is high or low depends on whether there is enough current on the input side of the first optocoupler Q1 at the corresponding level. Only when there is enough current on the input side of the first optocoupler Q1 will the output side of the first optocoupler Q1 be effectively turned on.

[0063] This embodiment further considers that by setting the first resistor R1 to an adjustable value, when the voltage of the first signal changes significantly in different applications, it is not necessary to replace the first resistor R1. Instead, the resistance value of the first resistor R1 can be adjusted so that when the first signal is high, the input side of the first optocoupler Q1 has a suitable conduction current. In other words, this embodiment of the present application can support a wider range of signal input voltages.

[0064] Similarly, the second resistor R2 can also be selected as an adjustable resistor so that the input side of the second optocoupler Q2 can have a suitable conduction current for the second signal at a high level in different situations.

[0065] There are several ways to implement an adjustable resistor. For example, a sliding rheostat can be used, allowing operators to adjust the resistance values ​​of the first resistor R1 and the second resistor R2 according to the needs of the actual situation. Alternatively, it can be configured as an adjustable resistance circuit, where the topology of the relevant resistors in the adjustable resistance circuit is adjusted by controlling the on / off state of the corresponding switching transistors, thereby achieving the adjustment of the equivalent resistance value of the adjustable resistance circuit.

[0066] Furthermore, in one specific embodiment of the present invention, it may further include: a resistance value indication circuit, used for:

[0067] Based on the input voltage drop of the first optocoupler Q1, the current reference value of the input side of the first optocoupler Q1, and the voltage value when the first signal is high, the resistance reference value of the first resistor R1 is determined and output.

[0068] Based on the input voltage drop of the second optocoupler Q2, the current reference value of the input side of the second optocoupler Q2, and the voltage value when the second signal is high, the resistance reference value of the second resistor R2 is determined and output.

[0069] In this implementation, in order to enable the staff to intuitively and conveniently know the appropriate resistance values ​​of the first resistor R1 and the second resistor R2, the resistance value prompting circuit is used to calculate and output the resistance reference values ​​of the first resistor R1 and the second resistor R2. That is, the staff does not need to calculate it themselves, but can directly determine the resistance reference values ​​of the first resistor R1 and the second resistor R2 through the resistance value prompting circuit.

[0070] There are many different forms of resistance indication circuits. For example, there is an indicator light circuit, which outputs information through a corresponding indicator light. Another example is a resistance indication circuit that outputs information through sound.

[0071] Specifically, for example, when the first signal is at a high level, the voltage value is 24V. Subtracting the input voltage drop of the first optocoupler Q1, we can obtain the reference value of the terminal voltage of the first resistor R1. Then, dividing the reference value of the terminal voltage of the first resistor R1 by the reference value of the current on the input side of the first optocoupler Q1, we get the reference value of the resistance of the first resistor R1.

[0072] Furthermore, it is understandable that when there are other structures on the input side of the first optocoupler Q1, the method for calculating the reference value of the terminal voltage of the first resistor R1 can be adaptively adjusted, for example... Figure 4 In addition to the first resistor R1, a first diode D1 is also provided. Therefore, the voltage value of 24V when the first signal is high needs to be subtracted from the input voltage drop of the first optocoupler Q1 and the diode voltage drop of the first diode D1. The result is used as the terminal voltage reference value of the first resistor R1. Then, the terminal voltage reference value of the first resistor R1 is divided by the input current reference value of the first optocoupler Q1 to obtain the resistance reference value of the first resistor R1, which is also the ideal resistance value of the first resistor R1.

[0073] The input current reference value of the first optocoupler Q1 represents the ideal input current value of the first optocoupler Q1 when it is turned on. This value can be predetermined based on factors such as the model of the first optocoupler Q1 and the current requirements of its output side. The input voltage drop of the first optocoupler Q1 can also be determined based on its model. Multiplying the input current value of the first optocoupler Q1 by its current amplification factor yields the output current of the first optocoupler Q1.

[0074] The calculation principle for the reference value of the second resistor R2 is the same as that for the reference value of the first resistor R1, and will not be repeated here. Furthermore, in specific cases, the models of the first optocoupler Q1, the second optocoupler Q2, and the various optocouplers described in the later embodiments are usually the same, and the voltage levels of the first signal, the second signal, and the various input-side signals described in the later embodiments are usually also the same. Therefore, the first resistor R1 to the Nth resistor are usually designed with the same parameters.

[0075] In one specific embodiment of the present invention, it further includes: a first diode D1 and a second diode D2;

[0076] The anode of the first diode D1 is connected to the second terminal of the first resistor R1, and the cathode of the first diode D1 is connected to the first terminal of the input side of the first optocoupler Q1.

[0077] The anode of the second diode D2 is connected to the second terminal of the second resistor R2, and the cathode of the second diode D2 is connected to the first terminal of the input side of the first optocoupler Q1.

[0078] See also Figure 4 and Figure 5 A first diode D1 and a second diode D2 are respectively set on the input side of the first optocoupler Q1 and the input side of the second optocoupler Q2. This can effectively prevent reverse current and avoid damage to the first optocoupler Q1 or the second optocoupler Q2 due to reverse current, thereby further improving the reliability of the solution.

[0079] In one specific embodiment of the present invention, a voltage controller may be further included, for:

[0080] Receive the voltage regulation signal carrying the target voltage value and set it to the target voltage value.

[0081] In the scheme of this application, the output terminal of the gate circuit usually needs to be connected to the relevant detection circuit in the subsequent stage. The detection circuit usually has a limited input voltage range. That is, the voltage requirement of the positive terminal of the first power supply will be different depending on the specific detection circuit selected.

[0082] Therefore, in order to make the gate circuit of this application readily applicable to different situations, in this specific embodiment of the invention, the voltage value of the positive terminal of the first power supply can be flexibly adjusted by a voltage controller, thereby improving the flexibility of the solution. In other words, this embodiment of the invention can easily support a wider range of signal output voltages.

[0083] Furthermore, it is understood that there can be various specific methods for adjusting the voltage value of the positive terminal of the first power supply, which can usually be designed based on the generation circuit of the first power supply. For example, in one scenario, a DC-DC step-down circuit is provided, and the output terminal of the DC-DC step-down circuit serves as the positive terminal of the first power supply in this application. In this case, the voltage controller can adjust the voltage value of the positive terminal of the first power supply by controlling the duty cycle of the corresponding switching transistor in the DC-DC step-down circuit.

[0084] In one specific embodiment of the present invention, see [reference needed]. Figure 6 and Figure 7 It may also include: a third optocoupler Q3 to an Nth optocoupler connected in series on the output side, and the first end of the output side of the third optocoupler Q3 is connected to the second end of the output side of the second optocoupler Q2;

[0085] The input sides of the third optocoupler Q3 to the Nth optocoupler are used to receive the third signal to the Nth signal in sequence. When the i-th signal is high, the output side of the i-th optocoupler is in the on state, and when the i-th signal is low, the output side of the i-th optocoupler is in the off state. N is a positive integer not less than 3, and i is a positive integer and 3≤i≤N.

[0086] When the gate circuit is used as an AND gate circuit, the first terminal of the output side of the first optocoupler Q1 is connected to the positive terminal of the first power supply, the second terminal of the output side of the Nth optocoupler is used as the output terminal of the AND gate circuit and is connected to the first terminal of the target resistor R0, and the second terminal of the target resistor R0 is grounded.

[0087] When the gate circuit is used as a NAND gate circuit, the first terminal of the output side of the first optocoupler Q1 is used as the output terminal of the NAND gate circuit and is connected to the second terminal of the target resistor R0. The first terminal of the target resistor R0 is connected to the positive terminal of the first power supply, and the second terminal of the output side of the Nth optocoupler is grounded.

[0088] In the aforementioned embodiments, when the gate circuit is used as an AND gate circuit, it can receive two input signals, namely a first signal and a second signal. When the gate circuit is used as a NAND gate circuit, it can also receive two input signals, namely a first signal and a second signal.

[0089] In this embodiment, a third optocoupler Q3 to an Nth optocoupler are further provided in series on the output side. The input sides of the third optocoupler Q3 to an Nth optocoupler are used to receive the third signal to the Nth signal in sequence. This allows the gate circuit of this application to receive multiple input signals when it is used as an AND gate circuit or a NAND gate circuit, and the circuit structure is simple.

[0090] In this embodiment, regardless of whether the gate circuit is used as an AND gate or a NAND gate, the output sides of the first optocoupler Q1, the second optocoupler Q2, and the third optocoupler Q3 to the Nth optocoupler are connected in series. This application's... Figure 6 and Figure 7 In the image, N is set to 3 for easier viewing.

[0091] When the gate circuit is used as an AND gate circuit, the first terminal of the output side of the first optocoupler Q1, i.e., the collector of the first optocoupler Q1, is connected to the positive terminal of the first power supply, and the second terminal of the output side of the Nth optocoupler serves as the output terminal of the AND gate circuit and is connected to the first terminal of the target resistor R0. Figure 6 In this circuit, the emitter on the output side of the third optocoupler Q3 serves as the output terminal of the AND gate and is connected to the first terminal of the target resistor R0. As can be seen from the circuit structure, when the input signals of each optocoupler are high, the output terminal OUTPUT of the gate is high; conversely, if the input signal of any one optocoupler is low, the output terminal OUTPUT of the gate is low.

[0092] Correspondingly, when the gate circuit is used as a NAND gate circuit, it can be seen from the circuit structure that when the signal on the input side of each optocoupler is at a high level, the output terminal OUTPUT of the gate circuit is at a low level, and as long as the signal on the input side of any one optocoupler is at a low level, the output terminal OUTPUT of the gate circuit is at a high level.

[0093] In one specific embodiment of the present invention, it may further include: a third resistor R3 to an Nth resistor; and the first end of the i-th resistor is used to receive the i-th signal, the second end of the i-th resistor is connected to the first end of the input side of the i-th optocoupler, and the second end of the input side of the i-th optocoupler is grounded.

[0094] Similarly to the aforementioned implementation, considering the provision of the third optocoupler Q3 to the Nth optocoupler, this implementation further provides the third resistor R3 to the Nth resistor to achieve the current limiting effect of the corresponding circuit and ensure the reliability of the circuit.

[0095] In one specific embodiment of the present invention, it may further include: a third diode D3 to an Nth diode; and the anode of the i-th diode is connected to the second end of the i-th resistor, and the cathode of the i-th diode is connected to the first end of the input side of the i-th optocoupler.

[0096] Similarly to the aforementioned implementation, considering the inclusion of the third optocoupler Q3 to the Nth optocoupler, this implementation further includes the third diode D3 to the Nth diode, providing anti-reverse current protection for the corresponding circuits and further ensuring circuit reliability. Furthermore, the use of optocouplers to implement both AND and NAND circuits achieves signal isolation, resulting in high reliability.

[0097] By applying the technical solution provided in the embodiments of the present invention, only the first optocoupler Q1, the second optocoupler Q2 and the target resistor R0 are needed to realize the functions of AND circuit and NAND circuit, without the need to set up a logic chip as in the traditional solution. The circuit structure is simple and the reliability is very high.

[0098] Specifically, the input side of the first optocoupler Q1 is used to receive a first signal. When the first signal is high, the output side of the first optocoupler Q1 is in an on state, and when the first signal is low, the output side of the first optocoupler Q1 is in an off state. The input side of the second optocoupler Q2 is used to receive a second signal. When the second signal is high, the output side of the second optocoupler Q2 is in an on state, and when the second signal is low, the output side of the second optocoupler Q2 is in an off state. The second terminal of the output side of the first optocoupler Q1 is connected to the first terminal of the output side of the second optocoupler Q2.

[0099] When the first output terminal of the first optocoupler Q1 is connected to the positive terminal of the first power supply, and the second output terminal of the second optocoupler Q2 is used as the output terminal of the AND gate and connected to the first terminal of the target resistor R0, and the second terminal of the target resistor R0 is grounded, it can be seen that if both the first signal and the second signal are high level, the output terminal of the gate is high level; if either the first signal or the second signal is low level, the output terminal of the gate is low level. That is, the gate can effectively realize the function of the AND gate at this time.

[0100] When the first output terminal of the first optocoupler Q1 is used as the output terminal of the NAND gate and connected to the second terminal of the target resistor R0, the first terminal of the target resistor R0 is connected to the positive terminal of the first power supply, and the second output terminal of the second optocoupler Q2 is grounded, it can be seen that if both the first signal and the second signal are high, the output terminal of the gate is low; if either the first signal or the second signal is low, the output terminal of the gate is high. That is, the gate can effectively realize the function of the NAND gate at this time.

[0101] In summary, the solution of this application only requires the first optocoupler Q1, the second optocoupler Q2, and the target resistor R0 to effectively realize AND and NAND circuits. The circuit structure is simple and highly reliable.

[0102] Corresponding to the above-described gate circuit embodiments, this invention also provides a circuit system that may include gate circuits as described in any of the above embodiments, which can be referred to in correspondence with the above description and will not be repeated here.

[0103] It should also be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0104] This article uses specific examples to illustrate the principles and implementation methods of the present invention. The descriptions of the above embodiments are only for the purpose of helping to understand the technical solutions and core ideas of the present invention. It should be noted that for those skilled in the art, several improvements and modifications can be made to the present invention without departing from the principles of the present invention, and these improvements and modifications also fall within the protection scope of the present invention.

Claims

1. A gate circuit, characterized in that, include: First optocoupler, second optocoupler, and target resistor; The input side of the first optocoupler is used to receive a first signal. When the first signal is high, the output side of the first optocoupler is in an on state, and when the first signal is low, the output side of the first optocoupler is in an off state. The input side of the second optocoupler is used to receive a second signal. When the second signal is high, the output side of the second optocoupler is in an on state, and when the second signal is low, the output side of the second optocoupler is in an off state. The second terminal of the output side of the first optocoupler is connected to the first terminal of the output side of the second optocoupler. When the gate circuit is used as an AND gate circuit, the first terminal of the output side of the first optocoupler is connected to the positive terminal of the first power supply, the second terminal of the output side of the second optocoupler serves as the output terminal of the AND gate circuit and is connected to the first terminal of the target resistor, and the second terminal of the target resistor is grounded. When the gate circuit is used as a NAND gate circuit, the first terminal of the output side of the first optocoupler serves as the output terminal of the NAND gate circuit and is connected to the second terminal of the target resistor. The first terminal of the target resistor is connected to the positive terminal of the first power supply, and the second terminal of the output side of the second optocoupler is grounded.

2. The gate circuit according to claim 1, characterized in that, Also includes: First resistor and second resistor; The first end of the first resistor is used to receive the first signal, the second end of the first resistor is connected to the first end of the input side of the first optocoupler, and the second end of the input side of the first optocoupler is grounded. The first end of the second resistor is used to receive the second signal, the second end of the second resistor is connected to the first end of the input side of the second optocoupler, and the second end of the input side of the second optocoupler is grounded.

3. The gate circuit according to claim 2, characterized in that, Also includes: First diode and second diode; The anode of the first diode is connected to the second terminal of the first resistor, and the cathode of the first diode is connected to the first terminal of the input side of the first optocoupler. The anode of the second diode is connected to the second end of the second resistor, and the cathode of the second diode is connected to the first end of the input side of the first optocoupler.

4. The gate circuit according to claim 2, characterized in that, Both the first resistor and the second resistor are adjustable resistors.

5. The gate circuit according to claim 4, characterized in that, Also includes: Resistance value indication circuit, used for: Based on the input voltage drop of the first optocoupler, the current reference value of the input side of the first optocoupler, and the voltage value when the first signal is high, the resistance reference value of the first resistor is determined and output. Based on the input voltage drop of the second optocoupler, the current reference value of the input side of the second optocoupler, and the voltage value when the second signal is at a high level, the resistance reference value of the second resistor is determined and output.

6. The gate circuit according to claim 1, characterized in that, Also includes: Voltage controller, used for: Receive a voltage adjustment signal carrying a target voltage value, and adjust the voltage value of the positive terminal of the first power supply to the target voltage value.

7. The gate circuit according to any one of claims 1 to 6, characterized in that, Also includes: The third to Nth optocouplers are connected in series on the output side, and the first end of the output side of the third optocoupler is connected to the second end of the output side of the second optocoupler. The input sides of the third to the Nth optocouplers are used to receive the third to the Nth signals in sequence. When the i-th signal is high, the output side of the i-th optocoupler is in the on state, and when the i-th signal is low, the output side of the i-th optocoupler is in the off state. N is a positive integer not less than 3, and i is a positive integer and 3≤i≤N. When the gate circuit is used as an AND gate circuit, the first terminal of the output side of the first optocoupler is connected to the positive terminal of the first power supply, the second terminal of the output side of the Nth optocoupler is used as the output terminal of the AND gate circuit and is connected to the first terminal of the target resistor, and the second terminal of the target resistor is grounded. When the gate circuit is used as a NAND gate circuit, the first terminal of the output side of the first optocoupler is used as the output terminal of the NAND gate circuit and is connected to the second terminal of the target resistor. The first terminal of the target resistor is connected to the positive terminal of the first power supply, and the second terminal of the output side of the Nth optocoupler is grounded.

8. The gate circuit according to claim 7, characterized in that, Also includes: The 3rd to Nth resistors; and the first end of the i-th resistor is used to receive the i-th signal, the second end of the i-th resistor is connected to the first end of the input side of the i-th optocoupler, and the second end of the input side of the i-th optocoupler is grounded.

9. The gate circuit according to claim 8, characterized in that, Also includes: The third to the Nth diodes; and the anode of the i-th diode is connected to the second terminal of the i-th resistor, and the cathode of the i-th diode is connected to the first terminal of the input side of the i-th optocoupler.

10. A circuit system, characterized in that, Includes the gate circuits as described in any one of claims 1 to 9.

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