An enhanced partially parallel architecture high-speed LDPC decoder and decoding method

Abstract

The application provides a high-speed LDPC decoder with enhanced partial parallel architecture and a decoding method, the decoder comprising an operation unit, a channel receiving information storage module, a confidence information storage module, a hard decision storage module, a data alignment module and a controller; the application splits multiple diagonal line matrices and respectively stores the confidence information by using a distributed storage strategy; then, the multiple rows (columns) of confidence information of the split sub-matrices are stored in the same memory address, which doubles the data amount of each memory read and write and the node operation amount, and improves the decoding data throughput rate; and the application designs a low-complexity data aligner between the memory and the operation unit, which effectively avoids the memory access conflict.

Description

Technical Field

[0001] This invention belongs to the field of communication technology, specifically relating to an enhanced partially parallel architecture high-speed LDPC decoder and decoding method. Background Technology

[0002] With the increasing demands of space exploration missions, the payloads carried by spacecraft are becoming more sophisticated and diverse, leading to a significant increase in the amount of data transmitted via space-to-ground links. Low Earth Orbit (LEO) satellites are widely used due to their advantages such as low launch cost, low communication latency, and wide coverage. However, they also have the following characteristics: short transit times and limited data transmission time; they are generally small satellites with limited onboard hardware resources; and the communication channels exhibit time-varying characteristics. Achieving high-speed data transmission under the constraints of limited onboard hardware resources and data transmission time on LEO satellites has become a core challenge that my country's spacecraft development needs to address. Channel coding, as a crucial component of high-speed data transmission, can improve the anti-interference and reliability of the data transmission system. Low-density parity-check (LDPC) codes, whose error correction performance approaches the Shannon limit, have been widely applied in fiber optic communication, space communication, and storage.

[0003] Currently, the most commonly used algorithm for hardware implementation of binary LDPC decoding is the Normalized Min-Sum Algorithm (NMSA) decoding algorithm. This algorithm requires extensive computation and storage of the calculated confidence information, resulting in high hardware resource consumption. Furthermore, memory access conflicts may occur during confidence information storage, further increasing the implementation complexity of the decoder. Designing a high-speed, efficient LDPC decoder that balances hardware complexity and decoding performance presents a significant challenge.

[0004] In LDPC code decoding, the check node and variable node updates can be performed simultaneously, thus enabling the implementation of high-speed decoders using a parallel architecture. The choice of parallelism significantly impacts the decoder's hardware resource consumption and decoding throughput. Common architectures include fully parallel, serial, and partially parallel architectures. Fully parallel LDPC decoders typically offer the highest decoding throughput, but they consume more resources, have complex layout and routing, and experience routing congestion between processing nodes, resulting in high implementation complexity. Serial decoders require the fewest hardware resources, but their low decoding throughput makes them unsuitable for high-speed data transmission. Partially parallel architectures offer a good trade-off between resources and throughput. FPGA-based partially parallel decoders typically utilize Block Random Access Memory (BRAM) to store the confidence information exchanged between processing nodes. However, when calculating adjacent rows simultaneously, multiple BRAM addresses need to be accessed at the same time. Therefore, the storage structure and location of the confidence message in the BRAM need to be carefully designed, and the interface between the BRAM and the processing unit needs to be specially designed. Otherwise, memory access conflicts will cause the decoder to reach a performance bottleneck. Summary of the Invention

[0005] The purpose of this invention is to overcome the memory access conflict problem and the low decoding throughput in the decoding process.

[0006] This invention proposes an enhanced partially parallel architecture high-speed LDPC decoder, which includes an arithmetic unit, a channel received information storage module, a confidence information storage module, a hard decision storage module, a data alignment module, and a controller.

[0007] The computation unit is used to read the information from the channel received information storage module and the confidence information storage module to complete the verification node update and variable node update operations during the decoding process, and output the decoding result.

[0008] The channel receiving information storage module is used to receive and buffer externally input LDPC decoding soft information;

[0009] The confidence information storage module is used to store the node update confidence information calculated by the computing unit during the decoding process.

[0010] The hard decision storage module is used to store the hard decision results calculated by the arithmetic unit during the decoding process.

[0011] The data alignment module: During the decoding process, the data alignment module is used to avoid memory access conflicts;

[0012] The controller is used to coordinate the work of each module and complete the decoding process.

[0013] As an improvement to the above-mentioned device, the channel receiving information storage module consists of n RAMs, each RAM having a bit width of P×Q bits and a depth of L / P;

[0014] Where n is the number of columns in the submatrix of the LDPC code parity-check matrix; P is the enhanced parallelism; Q is the number of quantization bits; and L is the order of the submatrix of the LDPC code parity-check matrix.

[0015] As an improvement to the above device, the confidence information storage module consists of m×n×cir weight It consists of 1 RAM, each RAM has a bit width of P×Q bits and a depth of L / P;

[0016] Where m is the number of rows in the submatrix contained in the LDPC code parity check matrix; cir weight The row and column weights of the submatrix of the LDPC code check matrix.

[0017] As an improvement to the above-mentioned device, the hard decision storage module consists of n RAMs, each RAM having a bit width of P and a depth of L / P.

[0018] As an improvement to the above-mentioned device, the computing unit includes a verification node update module and a variable node update module.

[0019] As an improvement to the above-mentioned device, the verification node update module consists of m×P verification node processing units; the verification node processing unit includes a symbol solution subunit, a minimum and second minimum value solution subunit, and a correction factor unit.

[0020] As an improvement to the above-mentioned device, the variable node update module consists of n×P variable node processing units and is implemented using a tree-structured cascaded accumulator.

[0021] This invention also provides a decoding method for an enhanced partially parallel architecture high-speed LDPC decoder, based on the above-mentioned decoder, the method comprising:

[0022] Step 1: Initialization: First, the received LDPC code information is stored in each RAM block of the channel reception information storage module. Then, the received channel information is divided into n segments in sequence and stored in each RAM block of the confidence information storage module in sequence. The data in the channel reception information storage module and the confidence information storage module are stored in column order. The initial iteration count is 0, and the maximum iteration count is ITER_NUM. ITER_NUM>1, and the specific iteration count is determined based on the decoding performance.

[0023] The LDPC code parity check matrix consists of m×n rows and columns with the same number of rows and columns, denoted by cir. weight L×L submatrix Ai,j constitute;

[0024] Step 2: Verification Node Update: m×P verification node processing units operate in parallel; each clock cycle first reads the confidence information from the confidence information storage block. The read / write address order for each RAM block is as follows:

[0025] floor(b i,j / P),floor(b i,j / P)+1,…0,1,…floor(b i,j / P)-1

[0026] Among them, b i,j Submatrix A i,j The cyclic shift value; P is for enhancing parallelism; floor is the floor function;

[0027] Then, the read confidence information is sent to the verification node processing unit after passing through the data alignment module to calculate and update the confidence information passed to the variable node; finally, after passing through the data alignment module, the result is written back to the confidence information storage module.

[0028] Step 3: Variable Node Update: n×P variable node processing units operate in parallel. Each clock cycle, confidence information and channel reception information are first read from the confidence information storage module and the channel reception information storage module, with the read / write address order for each RAM block being 0, 1, 2, ..., L / P. Then, the read confidence information is sent to the variable node processing unit after passing through the data alignment module, and the channel reception information is also sent to the variable node processing unit. The variable node processing unit calculates and updates the confidence information and hard decision information passed to the verification node. Finally, the results are written back to the confidence information storage module via the data alignment module, and the hard decision information is stored in the hard decision information storage module. The iteration count is incremented by 1.

[0029] Step 4: Termination decision: If the number of iterations reaches the maximum number of iterations ITER_NUM, then terminate the iteration and execute step 5; otherwise, jump to step 2 to continue iterative decoding.

[0030] Step 5: Decoding Output: Read the hard decision results from the hard decision information storage module. The read address order for each RAM block is 0, 1, 2, ... L / P. Output P hard decision results as decoding results every clock cycle.

[0031] As an improvement to the above method, the maximum number of iterations is 10.

[0032] Compared with the prior art, the advantages of the present invention are:

[0033] 1. This invention splits a multi-diagonal matrix and uses a distributed storage strategy to store confidence information separately; then, it stores the confidence information of multiple rows (columns) of the split sub-matrices in the same memory address, which multiplies the amount of data read and written in memory and the amount of node computation, thereby improving the decoding data throughput.

[0034] 2. This invention designs a low-complexity data aligner between the memory and the arithmetic unit, effectively avoiding memory access conflicts.

[0035] 3. The proposed LDPC decoder was implemented on a Xilinx FPGA. The results show that the decoding throughput is 1.02Gbps at a working clock speed of 250MHz. Attached Figure Description

[0036] Figure 1 The diagram shows a high-speed LDPC decoder with an enhanced partial parallel architecture.

[0037] Figure 2 The diagram shown is a schematic of the data alignment module structure.

[0038] Figure 3 The diagram shown is a schematic of the verification node update module structure.

[0039] Figure 4 The diagram shows the structure of the variable node update module. Detailed Implementation

[0040] The technical solution of the present invention will now be described in detail with reference to the accompanying drawings.

[0041] This invention proposes an enhanced partially parallel architecture high-speed LDPC decoder, such as... Figure 1 As shown, the main components include an arithmetic unit (for check node updates and variable node updates), a channel memory bank (CMB), an intermediate memory bank (IMB), a hard decision memory bank (HDMB), a data alignment module, and a controller. The arithmetic unit performs check node updates and variable node updates during decoding; the channel memory bank caches decoding soft information from the channel; the confidence information bank stores the node update confidence information calculated by the arithmetic unit during decoding; the hard decision memory bank stores the decoding hard decision results; the data alignment module avoids memory access conflicts during decoding; and the controller uses a state machine and control signals to coordinate the work of each functional block to complete the decoding process.

[0042] For regular QC-LDPC codes, the parity-check matrix consists of m×n rows and columns, with each row and column having a corresponding cir. weight L×L submatrix A i,j Composition, i.e., A i,j By cir weight The submatrices A are composed of different shifts of an identity matrix. To achieve efficient decoding and avoid memory access conflicts, this invention uses these submatrices A... i,j Split into CIR weight Each unit matrix corresponds to different variable node groups and the same check node group, and a distributed storage strategy is used to store the confidence information transmitted between the variable node group and the check node group corresponding to each unit matrix. To further increase the parallelism of the partially parallel decoder, the confidence information of P rows (columns) of the split unit matrix is ​​stored in the same memory address, which multiplies the amount of data read and written to memory and the amount of node operation. The parallelism of the decoder is enhanced to m×P or n×P, which can simultaneously process the updates of n×P variable nodes or m×P check nodes, improving the decoding data throughput, where P is the enhanced parallelism. Therefore, the channel reception information storage block (CMB) of this invention consists of n RAMs, each RAM with a bit width of P×Q bits and a depth of L / P, where Q is the number of quantization bits. The confidence information storage block consists of m×n×cir weight The hard decision information storage block (HDMB) consists of n RAMs, each with a bit width of P × Q bits and a depth of L / P.

[0043] Because the enhanced parallel architecture LDPC decoder stores P data points in each RAM address, memory access conflicts can occur. Some researchers have used a selection network and two data buffers to resolve these conflicts; however, the selection network consists of multiple multiplexers, and its output logic is complex, resulting in high implementation complexity. This invention designs a simple and effective memory access conflict avoidance strategy, utilizing... Figure 2 The data alignment module shown is implemented.

[0044] like Figure 2 As shown, each time data is read from RAM (messages updated by the arithmetic unit), it is concatenated with the data read from the previous moment (messages updated by the arithmetic unit). The position of the output window is determined based on the offset value, and P consecutive data points are selected and sent to the arithmetic unit (stored in memory). The offset value is determined by mod(b) i,j P) is determined and stored in the lookup table, where b i,j Submatrix A i,j The cyclic shift value.

[0045] The Processing Unit (PU) consists of a verification node update module and a variable node update module, with the following structure: Figure 3 , 4 As shown. The check node update module consists of m×P check node processing units, including the Sign Unit (SU), the First Two Minima Find Module (FTMFM), and the Normalized Modification Module (NMM), which correspond to the sign solution, minimum solution, and normalization factor multiplication in equation (1), respectively.

[0046]

[0047] In equation (1), α is the normalization factor of the NMSA algorithm, and L(r ji R(j) represents the log-likelihood ratio message passed from the check node to the variable node, R(j) represents the set of variable nodes connected to the check node j (excluding variable node i), and L(q) represents the log-likelihood ratio message passed from the check node to the variable node. i'j ) is the log-likelihood ratio message passed from the variable node to the verification node.

[0048] The variable node update module consists of n×P variable node processing units, which are implemented using a tree-structured cascaded accumulator.

[0049] The decoding process is as follows:

[0050] (1) Initialization: First, the received channel information frame is stored in each RAM block of the channel reception information storage block (CMB). Then, the received channel information is divided into n segments in sequence and stored in each RAM block of the confidence information storage block (IMB) in sequence. The data in CMB and IMB are stored in column order. The initialization iteration count is 0, and the maximum iteration count is ITER_NUM.

[0051] (2) Verification Node Update: m×P verification node processing units work in parallel. Each clock cycle first reads confidence information from the confidence information storage block IMB. The read / write address order for each RAM block is floor(b) i,j / P),floor(b i,j / P)+1,…0,1,…floor(b i,j / P)-1; then the read confidence information is sent to the verification node processing unit after passing through the data alignment module to calculate and update the confidence information passed to the variable node; finally, after passing through the data alignment module, the result is written back to the confidence information storage block IMB.

[0052] (3) Variable Node Update: n×P variable node processing units operate in parallel. Each clock cycle first reads confidence information and information reception information from the confidence information storage block IMB and the channel reception information storage block CMB. The read / write address order for each RAM block is 0, 1, 2, ..., L / P. Then, the read confidence information is sent to the variable node processing unit after passing through the data alignment module, and the channel reception information is also sent to the variable node processing unit. The variable node processing unit calculates and updates the confidence information and hard decision information passed to the verification node. Finally, the results are written back to the confidence information storage block IMB through the data alignment module, and the hard decision information is stored in the hard decision information storage block HDMB. The iteration count is incremented by 1.

[0053] (4) Termination decision: If the number of iterations reaches the maximum number of iterations ITER_NUM, then terminate the iteration and execute step (5); otherwise, jump to step (2) to continue iterative decoding.

[0054] (5) Decoding output: Read the hard decision results from the hard decision information storage block HDMB. The read address order of each RAM block is 0, 1, 2, ... L / P. Output P hard decision results as decoding results every clock cycle.

[0055] In a practical application of this decoder, the CCSDS near-Earth satellite communication application uses a quasi-cyclic (8176,7154) LDPC code with a code rate of 7 / 8. This code is a QC-LDPC code, and its parity check matrix H consists of 2×16 sub-matrices, i.e., m=2, n=16, as shown in Equation (2).

[0056]

[0057] In the formula, A i,j (i = 1, 2; j = 1, 2, ..., 16) is a cyclic matrix of size L × L = 511 × 511, that is, each cyclic matrix A i,j Both can be obtained by cyclically shifting the row vectors of the first row of the matrix to the right. Circular matrix A i,j The row weight is 2, and the column weight is also 2, i.e., cir weight =2, therefore the row weight and column weight of the parity check matrix H are 32 and 4 respectively, and the position of 1 in each circular matrix is ​​b. i,j See Table 7-1 of CCSDS 131.0-B-2 standard.

[0058] In the NMSA algorithm, the choice of α value affects decoding performance. It can be calculated using density evolution, and the calculation process reveals that α is related to code rate, line weight, and signal-to-noise ratio. In hardware implementation, the continuous and infinitely precise decoding soft information needs to be quantized, i.e., mapped to a message set with finite size and precision. Quantization is easy to implement in hardware and reduces hardware resource consumption, but it introduces errors, causing a certain loss in decoding performance. To reduce this loss, appropriate quantization parameters need to be selected. Furthermore, the number of iterations also significantly affects decoding performance. Generally, decoding performance increases with the number of iterations, but stops increasing once the number of iterations reaches a certain value. Through software simulation, this invention selects α = 0.75 and adopts a (6,2) quantization scheme (i.e., Q = 6, where 1 is the sign bit, 3 are the integer bits, and 2 are the fractional bits), with 10 iterations (ITER_NUM).

[0059] To achieve efficient decoding and avoid memory access conflicts, submatrix A... i,j The system is split into two unit matrices corresponding to different variable node groups and the same check node group. A distributed storage strategy is used to store the confidence information transmitted between the variable node group and the check node group corresponding to each unit matrice. Simultaneously, the parallelism is enhanced by setting P=7, storing the confidence information of the 7 rows (columns) of the split unit matrices at the same memory address. This significantly increases the amount of data read / write and node computation per operation, allowing simultaneous processing of updates for 112 variable nodes or 14 check nodes. The channel reception information storage block (CMB) of this invention consists of 16 RAMs, each with a 42-bit width and a depth of 73. The confidence information storage block consists of 64 RAMs, each with a 42-bit width and a depth of 73. The hard decision information storage block (HDMB) consists of 16 RAMs, each with a 7-bit width and a depth of 73.

[0060] Because the enhanced parallel architecture LDPC decoder stores 7 data points in each RAM address, memory access conflicts can occur. This can be mitigated by using methods such as... Figure 2 The data alignment module shown avoids memory access conflicts. Each time data is read from RAM (messages updated by the arithmetic unit), it concatenates the data read from the previous moment (messages updated by the arithmetic unit). The position of the output window is determined based on the offset value, and seven consecutive data points are selected and sent to the arithmetic unit (stored in memory). The offset value is calculated using mod(b) i,j 7) Determine and store in the lookup table, where b i,j Submatrix A i,j The cyclic shift value.

[0061] The decoding process is as follows:

[0062] (1) Initialization: First, the received channel information frame is stored in each RAM block of the channel reception information storage block (CMB). Then, the received channel information is divided into 16 segments and stored sequentially in each RAM block of the confidence information storage block (IMB). The data in CMB and IMB are stored in column order. The initialization iteration count is 0, and the maximum iteration count is 10.

[0063] (2) Verification Node Update: 14 verification node processing units operate in parallel. Each clock cycle first reads confidence information from the confidence information storage block IMB. The read / write address order for each RAM block is floor(b) i,j / 7), floor(b i,j / 7)+1,…0,1,…floor(b i,j / 7)-1; then the read confidence information is sent to the verification node processing unit after passing through the data alignment module to calculate and update the confidence information passed to the variable node; finally, after passing through the data alignment module, the result is written back to the confidence information storage block IMB.

[0064] (3) Variable Node Update: 112 variable node processing units operate in parallel. Each clock cycle first reads confidence information and channel reception information from the confidence information storage block IMB and the channel reception information storage block CMB, with the read / write address sequence for each RAM block being 0, 1, 2, ... 72. Then, the read confidence information is sent to the variable node processing unit after passing through the data alignment module, and the channel reception information is also sent to the variable node processing unit. The variable node processing unit calculates and updates the confidence information and hard decision information passed to the verification node. Finally, the results are written back to the confidence information storage block IMB through the data alignment module, and the hard decision information is stored in the hard decision information storage block HDMB. The iteration count is incremented by 1.

[0065] (4) Termination decision: If the number of iterations reaches the maximum number of iterations of 10, the iteration is terminated and step (5) is executed; otherwise, step (2) is skipped to continue iterative decoding.

[0066] (5) Decoding output: Read the hard decision results from the hard decision information storage block HDMB. The read address order of each RAM block is 0, 1, 2, ... 72. Output 7 hard decision results as decoding results every clock cycle.

[0067] This invention improves the decoding data throughput by splitting the multi-diagonal matrix and using a distributed storage strategy to store confidence information separately, while storing multiple confidence information in the same memory address. This significantly increases the amount of memory read / write data and node computation, and improves the decoding data throughput. The data alignment module effectively avoids memory access conflicts. FPGA implementation results show that the decoder can achieve a throughput of 1.02Gbps at a working clock of 250MHz, which can meet the high-speed data transmission requirements of LEO satellites.

[0068] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to the embodiments, those skilled in the art should understand that modifications or equivalent substitutions to the technical solutions of the present invention do not depart from the spirit and scope of the technical solutions of the present invention, and all such modifications or substitutions should be covered within the scope of the claims of the present invention.

Claims

1. An enhanced partially parallel architecture high-speed LDPC decoder, the decoder comprising a computation unit, a channel received information storage module, a confidence information storage module, a hard decision storage module, a data alignment module, and a controller; The computation unit is used to read the information from the channel received information storage module and the confidence information storage module to complete the verification node update and variable node update operations during the decoding process, and output the decoding result. The channel receiving information storage module is used to receive and buffer externally input LDPC decoding soft information; The confidence information storage module is used to store the node update confidence information calculated by the computing unit during the decoding process. The hard decision storage module is used to store the hard decision results calculated by the arithmetic unit during the decoding process. The data alignment module, used to avoid memory access conflicts during decoding, is configured to: concatenate the current data read from the storage module with the previous data, and select consecutive data from the concatenated data based on an offset value, sending it to the processing unit; wherein the offset value is determined by... Determine and store in the lookup table. Submatrix Circular shift values, multiple submatrices Construct the LDPC code check matrix; To enhance parallelism; The controller is used to coordinate the work of each module and complete the decoding process.

2. The enhanced partially parallel architecture high-speed LDPC decoder according to claim 1, characterized in that, The channel reception information storage module consists of It consists of 1 RAM, each RAM having a bit width of 1. Bit, depth is ; in, n The number of columns in the submatrices contained in the LDPC code check matrix; The number of quantization bits; L Let be the order of the submatrix of the LDPC code check matrix.

3. The enhanced partially parallel architecture high-speed LDPC decoder according to claim 2, characterized in that, The confidence information storage module consists of It consists of 1 RAM, each RAM having a bit width of 1. Bit, depth is ; in, m The number of rows in the submatrix contained in the LDPC code check matrix; The row and column weights of the submatrix of the LDPC code check matrix.

4. The enhanced partially parallel architecture high-speed LDPC decoder according to claim 3, characterized in that, The hard decision storage module is composed of It consists of 1 RAM, each RAM having a bit width of 1. Depth is .

5. The enhanced partially parallel architecture high-speed LDPC decoder according to claim 4, characterized in that, The computation unit includes a verification node update module and a variable node update module.

6. The enhanced partially parallel architecture high-speed LDPC decoder according to claim 5, characterized in that, The verification node update module is composed of The system consists of a verification node processing unit; the verification node processing unit includes a symbol solution subunit, a minimum and second minimum value solution subunit, and a correction factor subunit.

7. The enhanced partially parallel architecture high-speed LDPC decoder according to claim 5, characterized in that, The variable node update module is composed of It consists of variable node processing units and is implemented using a tree-structured cascaded accumulator.

8. A decoding method for an enhanced partially parallel architecture high-speed LDPC decoder, implemented based on the decoder of any one of claims 1 to 7, the method comprising: Step 1: Initialization: First, the received LDPC code information is stored in each RAM block of the channel receive information storage module. Then, the received channel information is divided into... The data in the channel reception information storage module and the confidence information storage module are stored sequentially in each RAM block, and the data in the channel reception information storage module and the confidence information storage module are stored in column order; the initial iteration count is 0, and the maximum iteration count is ITER_NUM; ITER_NUM>1, and the specific iteration count is determined according to the decoding performance; The LDPC code check matrix is ​​composed of Each row and column weight is of Order submatrix constitute; Step 2: Verify node update: using Each verification node processing unit operates in parallel; each clock cycle first reads confidence information from the confidence information storage block, and the read / write address order for each RAM block is as follows: in, Submatrix The cyclic shift value; To enhance parallelism; floor This is the floor function; Then, the read confidence information is sent to the verification node processing unit after passing through the data alignment module to calculate and update the confidence information passed to the variable node; finally, after passing through the data alignment module, the result is written back to the confidence information storage module. Step 3: Variable node update: using Each variable node processing unit operates in parallel; each clock cycle first reads confidence information and channel reception information from the confidence information storage module and the channel reception information storage module, with the read / write address sequence for each RAM block as follows: Then, the read confidence information is sent to the variable node processing unit after passing through the data alignment module, and the channel received information is also sent to the variable node processing unit. The variable node processing unit calculates and updates the confidence information and hard decision information passed to the verification node. Finally, the result is written back to the confidence information storage module through the data alignment module, and the hard decision information is stored in the hard decision information storage module. The iteration count is incremented by 1. Step 4: Termination decision: If the number of iterations reaches the maximum number of iterations ITER_NUM, then terminate the iteration and execute step 5; otherwise, jump to step 2 to continue iterative decoding. Step 5: Decoding Output: Read the hard decision result from the hard decision information storage module. The read address order for each RAM block is as follows: Output per clock cycle The hard decision result is output as the decoding result.

9. The decoding method for the enhanced partially parallel architecture high-speed LDPC decoder according to claim 8, characterized in that, The maximum number of iterations is 10.

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