Molded semiconductor chip package with stepped molding layer

Abstract

This invention discloses various molded semiconductor chip packages. In one aspect, a semiconductor chip package (200) includes a wiring substrate (225) and a semiconductor chip (215, 220) mounted on and electrically connected to the wiring substrate. The semiconductor chip has a plurality of side surfaces. A molding layer (230) at least partially encapsulates the semiconductor chip. The molding layer has a support surface (243) and a vertical surface (244) adjacent to at least some of the side surfaces.

Description

[0001] A typical fan-out semiconductor chip package consists of a semiconductor chip mounted on a redistribution layer (RDL) structure, which is composed of one or more metallization layers dispersed in a polymer such as polyimide. The chip is electrically connected to the conductor structure of the RDL structure via solder bumps. The chip itself is encapsulated in a molding material that is typically planarized to form a flat upper surface. Solder balls are attached to the underside of the RDL structure to enable the fan-out package to connect to other circuit boards, such as system boards. Silicon, typically used in semiconductor chips, exhibits a certain coefficient of thermal expansion (CTE). Typical molding compounds and polyimides have CTEs that are sometimes significantly different from those of silicon. To help mitigate CTE mismatch, an underlayer filler material is typically inserted between the semiconductor chip and the underlying RDL structure.

[0002] The process of mounting a chip onto an RDL structure and encapsulating it in molding material is often referred to as “wafer reassembly” because many such chips are mounted on electrically discrete but physically connected RDL structures. In conventional processes, the combination of chip, molding layer, and underlying RDL structure is diced from adjacent such combinations to form a molded semiconductor chip package. A conventional dicing process requires cutting a single slit along the four dicing streets of each package, through the molding layer and the RDL structure. This single-cut process yields a molding layer with substantially continuous sidewalls. Attached Figure Description

[0003] The foregoing and other advantages of the present invention will become apparent from the following detailed description and with reference to the accompanying drawings, wherein:

[0004] Figure 1 This is a partially exploded drawing view of an exemplary conventional semiconductor chip package;

[0005] Figure 2 yes Figure 1 A drawn view of a small portion of the corner of a standard-sized package;

[0006] Figure 3 yes Figure 1 A sectional view taken along section 3-3;

[0007] Figure 4 This is a cross-sectional view of a small portion of a conventional reconstructed wafer and a conventional dicing process;

[0008] Figure 5 This is a partially exploded drawing view of an exemplary new arrangement of a molded chip package including a stepped molding layer;

[0009] Figure 6 yes Figure 5 A sectional view taken along section 6-6;

[0010] Figure 7 It is shown at a higher magnification. Figure 6 A small part;

[0011] Figure 8 It is a cross-sectional view of a small portion of a reconstructed wafer on which multiple semiconductor chips are mounted.

[0012] Figure 9 It is similar to Figure 8 The cross-sectional view shows an exemplary molding of the molding layer;

[0013] Figure 10 It is similar to Figure 9 A cross-sectional view, but showing an exemplary grinding process for planarizing the molded layer;

[0014] Figure 11 It is similar to Figure 10 The cross-sectional view shows an exemplary wide cutout formation in the molded layer;

[0015] Figure 12 It is shown Figure 11 A drawing view showing the cuts made and the results of the additional slicing operations to be performed;

[0016] Figure 13 It is similar to Figure 11 The cross-sectional view shows a second, narrower cutout formed in the molding layer;

[0017] Figure 14 It is similar to Figure 11 A cross-sectional view, but showing the wide cutout formation in the reconstructed wafer prior to interconnect attachment;

[0018] Figure 15 It is similar to Figure 14 The cross-sectional view shows an exemplary grinding process and interconnections on the molded layer;

[0019] Figure 16 It is similar to Figure 15 The cross-sectional view shows an exemplary narrow cut formation;

[0020] Figure 17 This is a cross-sectional view showing an exemplary double cut formed using a single cutting blade;

[0021] Figure 18 It is a cross-sectional view showing a small portion of the reconstructed wafer and the initial positioning of the molded cover to facilitate stepped molding;

[0022] Figure 19 It is similar to Figure 18 The cross-sectional view shows the positioning of the molded cover and the molding of the stepped molding layers;

[0023] Figure 20 It is similar to Figure 19 A cross-sectional view, but showing the molded state of the molded layer;

[0024] Figure 21 It is similar to Figure 20 The cross-sectional view shows an exemplary slice of the reconstructed wafer;

[0025] Figure 22 It is similar to Figure 21 A cross-sectional view, but showing a single slice cut from the opposite side of the reconstructed wafer;

[0026] Figure 23 This is a cross-sectional view illustrating an alternative exemplary molded semiconductor chip package;

[0027] Figure 24 This is a cross-sectional view showing another alternative exemplary arrangement of a molded semiconductor chip package;

[0028] Figure 25 This is a cross-sectional view of another alternative exemplary arrangement of a molded semiconductor chip package; and

[0029] Figure 26 This is a cross-sectional view illustrating various alternative exemplary cut formation and cutting techniques. Detailed Implementation

[0030] The mass production packaging process described in the background art results in flat, continuous molding layer sidewalls that surround the periphery of the mounted chip, including its corners. Molded packages undergo various thermal cycling steps during testing and actual operation. These thermal cycling steps generate stress, particularly at the corners of the chip. These stresses can lead to various defects in the chip, such as multiple cracks originating from the corners and extending into the chip interior. If not controlled, these cracks can cause device failure. Part of the reason the molding layer exerts such stress on the semiconductor chip, particularly at or near the corners, is the human factor in the dicing process used to dice the molded package from a reconstructed wafer that is formally part of it. The dicing process results in relatively thick sidewalls of the molding layer. Thick sidewalls have sufficient material to exert significant stress at the corners of the chip when subjected to thermal cycling. The combination of thick molding layer sidewalls and thermal stress also increases the risk of molding material cracking near the chip corners.

[0031] The arrangement disclosed in this invention provides a molded semiconductor chip package with a stepped molding layer that reduces the amount of molding material on the side surfaces and corners near the chip, which are at least partially encapsulated by the molding layer. In this way, mechanical stress on the chip and the corners of the molding layer during thermal cycling is reduced. This invention discloses various techniques for fabricating stepped molding layers. Further details will now be described.

[0032] According to one aspect of the invention, a semiconductor chip package includes a wiring substrate and a semiconductor chip mounted on and electrically connected to the wiring substrate. The semiconductor chip has a plurality of side surfaces. A molding layer at least partially encapsulates the semiconductor chip. The molding layer has a tread and a riser, the riser abutting at least some of the side surfaces.

[0033] Semiconductor chip packaging, in which the vertical surface is narrower than the supporting surface.

[0034] Semiconductor chip packaging, wherein the wiring substrate includes a redistribution layer (RDL) structure.

[0035] Semiconductor chip packaging, wherein the wiring substrate includes an interposer layer.

[0036] A semiconductor chip package includes another semiconductor chip mounted on a wiring substrate, and the wiring substrate includes another molded layer that houses interconnect chips that connect the semiconductor chip to the other semiconductor chip.

[0037] A semiconductor chip package, wherein the semiconductor chip includes four side surfaces and a vertical facet is adjacent to all four side surfaces.

[0038] A semiconductor chip package includes another semiconductor chip mounted on a wiring substrate and at least partially encapsulated by a molding layer.

[0039] Semiconductor chip package, wherein the wiring substrate includes multiple interconnect structures to electrically connect the semiconductor chip package to another electronic device.

[0040] According to another aspect of the invention, the reconstructed wafer includes a plurality of semiconductor chip packages. Each of the semiconductor chip packages includes: a wiring substrate; a semiconductor chip having a plurality of side surfaces and mounted on and electrically connected to the wiring substrate; and a molding layer that at least partially encapsulates the semiconductor chip, the molding layer having a support surface and a vertical surface, the vertical surface being adjacent to at least some of the side surfaces.

[0041] Reconstruct the wafer, where the vertical facet is narrower than the supporting facet.

[0042] Reconstruct the wafer, wherein the wiring substrate includes a redistribution layer (RDL) structure.

[0043] Reconstruct the wafer, wherein the wiring substrate includes an interposer.

[0044] Reconstructed wafers, wherein each of the semiconductor chip packages includes another semiconductor chip mounted on a wiring substrate, the wiring substrate including another molded layer that houses interconnect chips connecting the semiconductor chip to the other semiconductor chip.

[0045] Reconstruct a wafer, wherein each of the semiconductor chips includes four side surfaces and each of the vertical surfaces is adjacent to all four side surfaces of each of the semiconductor chips.

[0046] Reconstructed wafers, wherein each of the semiconductor chip packages includes another semiconductor chip mounted on a wiring substrate and at least partially encapsulated by a molding layer.

[0047] Reconstructed wafers, in which each of the wiring substrates includes multiple interconnect structures for electrical connection to another electronic device.

[0048] According to another aspect of the present invention, a method of manufacturing a semiconductor chip package includes: mounting a semiconductor chip having a plurality of side surfaces on a wiring substrate and electrically connecting the semiconductor chip to the mounting substrate. A molding layer is molded on the wiring substrate to at least partially encapsulate the semiconductor chip. The molding layer has a support surface and a vertical surface, the vertical surface abutting at least some of the side surfaces.

[0049] The method involves creating the support surface and the vertical surface during molding.

[0050] The method includes creating a support surface and a vertical surface by sawing a first slit having a first width to set the width of the vertical surface and sawing a second slit aligned with the first slit and having a second width narrower than the first width to set the width of the support surface.

[0051] The method involves sawing a first cut and a second cut into the same side of the molding layer.

[0052] The method involves sawing a first cut and a second cut into opposite sides of the molding layer.

[0053] In this method, the wiring substrate and the molding layer include a reconstructed wafer.

[0054] In this method, the vertical surface is narrower than the supporting surface.

[0055] In this method, the wiring substrate includes a redistribution layer (RDL) structure.

[0056] In this method, the wiring substrate includes an interposer layer.

[0057] The method includes mounting another semiconductor chip on a wiring substrate, the wiring substrate including another molded layer that houses interconnect chips that connect the semiconductor chip to the other semiconductor chip.

[0058] In this method, the semiconductor chip includes four side surfaces and a vertical surface adjacent to all four side surfaces.

[0059] The method includes mounting another semiconductor chip on a wiring substrate and encapsulating the other semiconductor chip at least partially with a molding layer.

[0060] In the accompanying figures described below, the reference numerals are often repeated when the same element appears in multiple figures. Now turn to the figures, specifically to... Figure 1 The figure shows a partially exploded drawing view of an exemplary standard-size fan-out semiconductor chip package (molded package) 100, which is designed to be mounted on a package substrate 105 and electrically connected to the package substrate via a plurality of solder balls 110. In this conventional arrangement, the molded package 100 includes two semiconductor chips 115 and 120 mounted on an RDL structure 125 and partially encapsulated by a molding layer 130. An underlayer filler 132 is disposed between the RDL structure 125 and the package substrate 105 to reduce the effect of the difference in the coefficient of thermal expansion (CTE) of the semiconductor chips 115 and 120, the RDL structure 125 and the package substrate 105. Additional details of the RDL structure 125 will be described below in conjunction with the following figures. The semiconductor chip 115 is a generally rectangular structure including four corner portions 135a, 135b, 135c and 135d. The semiconductor chip 120 is similarly rectangular and includes four corner portions 140a, 140b, 140c and 140d. The molding layer 130 and RDL structure 125, together with semiconductor chips 115 and 120, are formally part of a reconstructed wafer (not shown) and are then monocut. Therefore, the molding layer 130 is also a rectangular structure with corners 145a, 145b, 145c, and 145d. The molding layer 130 has undergone a polishing process to expose the tops of chips 115 and 120. Corners 145a and 145b of the molding layer 130 are located near corners 135a and 135b of chip 115, respectively, and corners 145c and 145d of the molding layer 130 are located near corners 140c and 140d of chip 120, respectively.

[0061] During certain types of testing and actual operation, the molded package 100 may undergo thermal cycling. This thermal cycling generates bending, torsion, and other types of stress in both the RDL structure 125 and the molding layer 130. This repeated buckling and torsion imposes significant stress on the semiconductor chips 115 and 120 and the molding layer 130, specifically at the corners 135a and 135b of chip 115 near the molding layer 130, and at the corners 140c and 145d of chip 120 near the molding layer 130. Here, for illustrative purposes, the thermal stresses applied to the corners 135b and 140c of chips 115 and 120, and to the corners 145c and 145d of the molding layer, are schematically shown and labeled 150.

[0062] Figure 2 It is relative to Figure 1 The enlarged view in the figure shows a drawing view of the corner 140c of the semiconductor chip 120 and the corner 145c of the molding layer 130. Note that a portion of the underlying RDL structure 125L, the underlayer filler 132, and the package substrate 105 are also shown. As described above, thermal cycling of the package 100 generates stress 150, specifically at the corners of the chip, such as the corner 140c of the chip 120. These stresses can cause various defects in the chip 120, such as multiple cracks 155 originating from the corner 140c and extending into the interior of the chip 120. If not controlled, these cracks 155 can lead to device failure of the chip 120. Other types of defects that may occur include sheet peeling, bulk shedding, etc. Part of the reason why the molding layer 130 applies such stresses on the semiconductor chip 120, particularly at the corners or corner 140c, is due to the human factor of the dicing process used to dice the molded package 100 from a reconstructed wafer (not shown), which is formally part of it. The dicing process yields a relatively thick sidewall 160 for the molding layer 130. The sidewall 160 surrounds three sides of each of the semiconductor chips 115 and 120. The sidewall 160 has a width x1 and contains sufficient material to withstand thermal cycling at the corners 140c and... Figure 1 Significant stress of 150 is applied to the corners of the other chips shown.

[0063] Now we will combine Figure 3 The figure describes other details of the standard-sized package 100. Figure 1 A cross-sectional view taken along section 3-3. Semiconductor chips 115 and 120 are electrically connected to RDL structure 125 via multiple solder bumps 165. Each of the semiconductor chips 115 is provided with an underlayer filler material layer 170 to buffer the effects of CTE differences between chips 115 and 120 and other structures in package 100 (specifically RDL structure 125). RDL structure 125 consists of multiple conductor traces 175 scattered in a multilayer dielectric material 180. Various conductors of RDL structure 125 are connected to solder balls 110. Underlayer filler 132 performs the same function, i.e., mitigates the effects of CTE differences between the molded package 100 and the underlying package substrate 105. As described above... Figure 2 The sidewall 160 of the molding layer 130 has a width 160, which is a function of the way the molding package 100 is cut from the reconstructed wafer (not shown).

[0064] As just mentioned, the molded package 100 is initially manufactured as part of a reconstructed wafer, then diced, and in this way, the aforementioned sidewall 160 with a certain lateral dimension x1 is obtained. Now, let's turn to... Figure 4This figure is a cross-sectional view showing a standard-sized package 100 as part of a conventional remodeling wafer 185 during a single-piece dicing process. An adjacent molded package 187 of the remodeling wafer 185 is shown to the right of the molded package 100. Only a small portion of the remodeling wafer 185 is shown; it should be understood that the remodeling wafer 185 may include notches in such molded packages 100 and 187. The remodeling wafer 185 includes multiple slicing channels between the molded packages, such as slicing channel 188 between molded packages 100 and 187. The molded package 100 is cut from the remodeling wafer 185 by multiple sawing moves of a slicing blade 189 at slicing channels 188 and other (not visible) slicing channels. Here, the slicing blade 189 has a width x2 adapted to cut a slit 191 with a lateral dimension x3 at the slicing channel 188, which passes through the molding layer 130 and eventually down through the RDL structure 125, where x3 > x2. This slicing operation is typically performed four times: two parallel slices in one direction and two parallel slices in a direction perpendicular to the first slice direction, in order to cut the molded package 100 into individual pieces, and so on for the molded package 187. It should be noted that the slicing operation is performed using a single vertical cut at each slice trace 188 to obtain a cut 191 with a lateral dimension x3 and other similar cuts, such that when the molded package 100 is cut into individual pieces, the aforementioned sidewall 160 with a dimension x1 is formed, and a corresponding sidewall 192 is defined around the molded package 187.

[0065] Now for reference Figure 5 An exemplary new arrangement of the molded package 200 can be understood, and the figure is a partially exploded drawing view. Here, the molded package 200 is shown exploded from the lower package substrate 205. The package substrate 205 may be a ball grid array, pin grid array, planar gate array, or other type of interconnect scheme for connection to some other electronic device or circuit board. In this exemplary arrangement, the molded package 200 is electrically connected to the package substrate 205 via a plurality of interconnect structures 210, which may be solder balls, bumps, microbumps, conductive pillars, or other types of interconnect structures. In this exemplary arrangement, the molded package 200 includes two semiconductor chips 215 and 220 mounted on a wiring substrate 225 and partially encapsulated by a molding layer 230. In this arrangement, the wiring substrate 225 may be an RDL structure. Other arrangements disclosed herein may use an interposer or another molding layer as the wiring substrate. A bottom filler 232 is disposed between the wiring substrate 225 and the packaging substrate 205 to reduce the impact of the difference in the coefficient of thermal expansion (CTE) of the semiconductor chips 215 and 220, the wiring substrate 225, and the packaging substrate 205. Additional details of the wiring substrate 225 will be described below in conjunction with the accompanying drawings.

[0066] Semiconductor chip 215 has a generally rectangular structure, including four corners 235a, 235b, 235c, and 235d defined by the intersections of the four side surfaces 237a, 237b, 237c, and 237d. Semiconductor chip 220 is similarly rectangular and includes four corners 240a, 240b, 240c, and 240d defined by the intersections of the respective side surfaces 242a, 242b, 242c, and 242d. Of course, one or both of chips 215 and 220 may have a square coverage area. Semiconductor chips 215 and 220 are at least partially encapsulated by a molding layer 230 molded on a wiring substrate 225. As detailed below, the molding layer 230 and the wiring substrate 225, together with the semiconductor chips 215 and 220, are fabricated on a reconstructed wafer (not shown) and then diced. The molding layer 230 has undergone an optional polishing process to optionally expose the top of chips 215 and 220.

[0067] exist Figures 1 to 3 In the aforementioned standard-size packaging design, the molding layer 130 has continuous, substantially vertical sidewalls. However, in Figure 5 In the new exemplary arrangement shown, the molding layer 230 is a stepped arrangement including a support surface 243 and a vertical surface 244 projecting upward from the support surface 243. The vertical surface 244 has the form of a peripheral wall extending around the periphery of the combination of chips 215 and 220, specifically around the side surfaces 237a, 237b, and 237d of chip 215 and the side surfaces 242b, 242c, and 242d of chip 220. Reference can also be made to... Figure 6 To understand the other details of molded layer 230, the diagram is... Figure 5A cross-sectional view taken along section 6-6. First, note that semiconductor chips 215 and 220 are electrically connected to wiring substrate 225 via multiple interconnect structures 265. Interconnect structures 265 can be solder bumps, solder microbumps, conductive pillars, or other types of interconnect structures. Underlying filler 270 is positioned between chips 215 and 220 and the underlying wiring substrate 225. Wiring substrate 225 may include multiple conductive traces 275 and vias (not shown) and multilayer dielectric material 280, such as polyimide, various epoxy resins, or other types of dielectric materials. Underlying filler 270 and underlying filler 232 are used to mitigate various CTE problems associated with chips 215 and 220 and the underlying RDL 225 and the molded package 200 and the underlying package substrate 205. Here, the vertical surfaces 244 near the side surfaces 237a and 242c of chips 215 and 220, respectively, are visible. As briefly described above, the vertical surface 244 has a relatively thin lateral dimension x4, which means that the molding material of the molding layer 230 has a much smaller volume near the corners 235a and 235b (and to a lesser extent near corners 235b and 235c) of the chip 215 and near the corners 240c and 240d (and to a lesser extent near corners 240a and 240b) of the chip 220, and thus reduces the stress associated with thermal cycling on those corners 235a, 235b, 235c, 235d, 240a, 240b, 240c, and 240d. Note that the support surface 243 protrudes above the underlying filler 270 of the chip 220. This is intentional and will be described in detail below. Note the position of the dashed rectangle 282. Figure 6 The portion defined by dashed rectangle 282 in Figure 7 It is shown at a higher magnification.

[0068] You can refer to this now. Figure 7 To understand other details of the molding layer 230, as just mentioned, the diagram is... Figure 6 An enlarged view of the portion defined by the small dashed rectangle 282. Note that, due to... Figure 6 The location of the dashed rectangle 282 is a trace among the traces 275 below a small portion of the semiconductor chip 220, its underlying filler 270, molding 230, and wiring substrate 225. Figure 7 All of these are visible. As mentioned above, the vertical surface 244 has a certain lateral dimension x4, which is preferably larger than... Figure 1The lateral dimension x1 of the standard molded layer 130 shown is much smaller. The vertical surface 244 has a height z1 above the support surface 243, and the support surface 243 has a lateral dimension x5. The height z1 of the vertical surface 244 is chosen to ensure that the corners 283 of the bottom filler 270 are not damaged during the manufacture of the molded package 100. In this exemplary arrangement, the lateral dimension x4 of the vertical surface 244 is smaller than the lateral dimension x5 of the support surface 243. However, the lateral dimension x4 of the vertical surface 244 may be equal to or different from the lateral dimension x5 of the support surface 243.

[0069] Now you can refer to Figure 8 , Figure 9 , Figure 10 , Figure 11 , Figure 12 and Figure 13 And first refer to Figure 8 To understand the exemplary method used to manufacture the molded package 200. Figure 8 This is a cross-sectional view of a small portion of a reconstructed wafer 285 including semiconductor chips 215 and 220 mounted on an extended wiring substrate 225. A general coverage area of ​​the molded package 200 is shown, and an adjacent molded package, labeled 287, is shown, which includes semiconductor chips 288 and 289. Semiconductor chips 215, 220, 288, and 289 can be any of a variety of integrated circuits. An incomplete list of examples includes processors, such as microprocessors, graphics processing units, accelerated processing units combining aspects of both, memory devices, systems-on-a-chip, application-specific integrated circuits, etc. As described above, chips 215 and 220 are electrically connected to the underlying wiring substrate 225 via interconnect structure 265 and protected against CTE issues by corresponding underfill 270. Chips 288 and 289 are similarly connected to the wiring substrate 225 via interconnect structure 290 and protected against CTE issues by corresponding underfill 291. Up to this point, chips 215, 220, 288, and 289, and wiring substrate 225, have undergone multiple process steps required for integrated circuit and RDL manufacturing. Chips 215, 220, 288, and 289 have been diced from a larger semiconductor workpiece (not shown) and mounted on wiring substrate 225, with interconnect structure 210 mounted on its opposite side. It should be understood that at this stage, there may be scribe lines on such molded packages 200 and 287 that form part of the reconstructed wafer 285. The initial processing of the reconstructed wafer 285 described above is a post-die process. However, those skilled in the art will understand that a die-first process can be used in conjunction with the techniques described herein.

[0070] Next and as Figure 9 As shown, a molding layer 230 is applied to the reconstructed wafer 285 to encapsulate semiconductor chips 215, 220, 288, and 289, and to the reconstructed wafer 285. Figure 9 The other chips that are not visible in the middle. The molding layer 230 can be applied using well-known compression molding techniques that utilize various molding materials. Some commercial examples include Nagase R4601 or R460, Sumitomo EME-G750 series or EME-G760 series, etc.

[0071] Next and as Figure 10 As shown, an optional polishing process is performed on the molding layer 230 to optionally expose the top of the semiconductor chips 215, 220, 288 and 289. Figure 10 A slice trace 294 can be seen between molded packages 200 and 287. Of course, many other such slice traces (not visible) exist throughout the entire extent of the reconstructed wafer 285. This will now be combined with... Figure 11 , Figure 12 and Figure 13 An exemplary cutting process is described to cut the molded package 200 into individual pieces and produce the aforementioned stepped molding layer 230.

[0072] First refer to Figure 11 The reconstructed wafer 285 is mounted on the slicing protective tape 295. When the slicing protective tape 295 is in place, a first slicing step is performed using a slicing saw blade 303 with a width x6 to cut a kerf 306 at the slicing trace 294. The kerf 306 does not extend to the wiring substrate 225, but rather to a desired height z1 equal to the vertical plane 244 (see [link to product details]). Figure 7 The depth of the cut 306. The cut 306 forms a corresponding but oppositely positioned vertical surface 309 to the vertical surface 244 and the molding layer 230 (where the molding package 287 is located). The width x6 of the slicing blade 303 is selected to be less than the width of the gap between adjacent chips 220 and 288. The width x6 of the slicing blade 303 sets the width x4 of the vertical surface 244 (see...). Figure 7 The corresponding width of the vertical surface 309 may be equal to or may not be equal to width x4, depending on the centering of the slicing blade 303 between chips 220 and 288 and the blade oscillation during slicing.

[0073] It can still be referenced now. Figure 12To understand further details of the slicing operation, this figure is a drawing view of a portion of the reconstructed wafer 285, including the molding 230, the underlying wiring substrate 225, and the slicing protective tape 295. A notch 306 cuts into the molding layer 230 between semiconductor chips 220 and 288 and other chips also on one or the other side of the notch 306, but not separately labeled. The notch 306 cuts with a certain lateral dimension x7 depending on the width, construction (toothed, ground, etc.) and cutting oscillation of the slicing blade 303. The lateral dimension x7 is chosen to form the aforementioned vertical surfaces 244 and 309 (see [reference]) of the molding layer 230, which preferably have a lateral dimension x4. Figure 7 It should be noted that semiconductor chips 215 and 220 are separated from adjacent chips by one or more slicing channels 311 and 312, as well as another slicing channel 316, which is substantially parallel to the slicing channel 294 that has been cut by slicing channel 306. Of course, after cutting slicing channel 306, the slicing blade 303 moves on another slicing channel (such as slicing channel 316), and a similar cut is made to the same depth and width as slicing channel 306, and vice versa, although slicing channels 311 and 312 are in the vertical direction.

[0074] Next and as Figure 13 As shown, a second slicing step is performed to cut a slit 321 approximately centered at the bottom of the cut 306 and extending through the entire depth of the molding layer 230 using a slicing saw blade 319. The selected slicing blade 319 has a width x8 less than x6 and is used to completely slice the single-molded package 200 from the reconstructed wafer 285. Similarly, slicing traces 294, 311, 312, and 316 (see...) Figure 12 Four separate cuts are performed on each of the components to complete the dicing of the molded package 200. Using a dicing blade 319 having a width x6 and a lateral dimension x8 smaller than that of blade 303, and making the cut substantially in the middle of the dicing path, the dicing can be performed to form the aforementioned vertical surface 244 and support surface 243 of the molded part 230 surrounding chips 215 and 220. Similar vertical surfaces 309 and support surfaces 326 surrounding semiconductor chips 288 and 289 are also formed through this second dicing step. After dicing, the dicing protective tape 295 can be removed, and the molded package 200 is formed.

[0075] In the above arrangement, the interconnection structure 210 (see Figure 8 The attachment of ) precedes the severance. However, in Figures 14 to 17 In the alternative process flow shown, the interconnect structure 210 plays an intermediate role in the cutting process. First, refer to... Figure 14The figure is a cross-sectional view showing a reconstructed wafer 285 mounted on a carrier wafer 328 with the wiring substrate 225 facing down. The carrier wafer 328 may be made of glass, semiconductor, etc., and is attached via a release layer (not shown). The carrier wafer 328 serves as a support substrate for fabricating the wiring substrate 225, mounting semiconductor chips 215, 220, 288, and 289 (and other unseen items) of molded packages 200 and 287, respectively, and applying the molding layer 230. This method can be performed using materials and techniques disclosed elsewhere herein. After molding the molding layer 230 but before its optional grinding, a cut 306 is made using a slicing blade 303. This slicing step is similar to... Figure 11 and Figure 12 The slicing step is shown. However, because the molding layer 230 is not ground at this time, the cut 306 will be initially smaller than the desired size. Figure 11 and Figure 12 It shows a deeper level.

[0076] Next and as Figure 15 As shown, molding layer 230 is polished to expose the tops of semiconductor chips 215, 220, 288, and 289. Next, a well-known layering process is used to release... Figure 14 The carrier wafer 328 is shown, and the interconnect structure 210 is attached to the wiring substrate 225 at the locations of the molded packages 200 and 287. The depth of the notch 331 is reduced by grinding. The reconstructed wafer 285 is now ready to be attached to the slicing protective tape. Optionally, the grinding of the molded layer 230 can be performed after the connection or fabrication of the interconnect structure 210.

[0077] Next and as Figure 16 As shown, the reconstructed wafer 285 is attached to the aforementioned slicing protective tape 295. A second slicing operation is performed using a slicing blade 319 to cut slits 321, and finally, as described above, molded packages 200 and 287 are sliced ​​from the reconstructed wafer 285. As described above, the slicing operation shown between chips 220 and 288 is performed multiple times on multiple intersecting slicing traces to completely slice molded packages 200 and 287. Using a two-step slicing process, a molding layer 230 is formed having the aforementioned upright surface 244 and support surface 243, which, as described above, surround chips 215 and 220 in a manner similar to chips 288 and 289. Molded packages 200 and 287 are then layered from the slicing protective tape 295.

[0078] exist Figure 17 In another alternative exemplary method shown, a single slicing operation is performed using an alternative exemplary slicing blade 341 with a double width providing two cutting surfaces 343 and 346 to form the desired stepped configuration of the 230 molding layers. Figure 17The slicing blade 341 is shown before and during the cutting operation. The outermost radial portion 347 of the blade 341 includes a cutting surface 343 and has a width x9 suitable for making a narrow kerf 321, and the innermost radial portion 348 of the blade 341 includes a cutting surface 346 and has a width x9. 10 Width greater than x9 allows the blade 341 to engage with the molding layer 230, and through a single slicing operation, the narrow cutting surface 343 forms a narrow, deep cut 321 that penetrates not only the molding layer 230 but also the entire RDL 225 to achieve the slicing purpose, while the wider cutting surface 346 forms a shallower but wider cut 306 that surrounds the aforementioned vertical surfaces 244 and support surfaces 243 of chips 215 and 220. After additional such cuts and slicing, the vertical surfaces 309 and support surfaces 326 will surround chips 288 and 289. After slicing, the slicing protective tape 295 can be layered using techniques described elsewhere herein.

[0079] In another exemplary method, the molding layer 230 is molded to have a stepped structure. Reference can now be made to... Figure 18 , Figure 19 and Figure 20 To understand this exemplary method, see below. Figure 18 As shown, a reconstructed wafer 285 can be mounted onto a slice protectant tape 295 or a carrier wafer (not shown), and then a molding process is performed to apply molding material 230, but using a molding cap 401 positioned above semiconductor chips 215, 220, 288, and 289. The cap 401 has multiple stepped cavities, two of which are visible and labeled 404 and 408, respectively. Stepped cavities 404 and 408 are defined by downwardly projecting peripheral walls, three of which are visible and labeled 411a, 411b, and 411c, respectively. Cavities 404 and 408 share peripheral wall 411b. In practice, when viewed from below, cavities 404 and 408 (along with other unseen cavities) will resemble a waffle pattern. Cavity 404 is designed to accommodate the heights of chips 215 and 220, while cavity 408 is designed to accommodate the heights of chips 288 and 289 when cover 401 is positioned close to reconstructed wafer 285 just before molding. Peripheral wall 411b has a mirror profile of the desired stepped cutout typically formed using a dual-slice process, and so do the other peripheral walls 411a and 411c. Figure 19 As shown, the cover is positioned above the reconstructed wafer 285 to leave space around chips 215, 220, 288, and 289, in which molding material 230 can flow during molding. However, the presence of stepped peripheral walls 411a, 411b, and 411c, having a stepped shape, allows molding material 230 to advance around chips 220 and 288 to automatically form a stepped molding structure between chips 220 and 288, and in fact around chips 215, 220, 288, and 289.

[0080] After the molding process and as Figure 20 As shown, remove Figure 19 The molded cover 401 is shown, and as previously described, the molding process itself forms the aforementioned molded layer 230 with stepped grooves 413. These stepped grooves form adjacent to and surrounding the vertical surfaces 244 and support surfaces 243 of semiconductor chips 215 and 220, and the corresponding vertical surfaces 309 and support surfaces 326 of the molded layer 230 adjacent to semiconductor chips 288 and 289. Similarly, other grooves (not labeled) are formed adjacent to chips 215 and 289 and elsewhere.

[0081] Next and as Figure 21 As shown, a slicing step is performed using, for example, a saw blade 319, to cut down into the trench 413 and other areas, thereby penetrating the entire depth of any molding and wiring substrate 225 at the bottom of the trench 413, to cut the single-molded packages 200 and 293 as described above.

[0082] It should be understood that, in cases involving Figures 18 to 21 In the slicing step or even the aforementioned process of structured molding, the cutting action is performed from the top facing the semiconductor chip 215, 220, etc. However, it should be understood that for any disclosed process, the actual single-slicing step that cuts through a portion of the RDL structure and molding may be performed from the RDL structure side rather than the chip side. In this regard, attention will now turn to Figure 22 This figure is a cross-sectional view of the reconstructed wafer 285, although it is mounted on the carrier wafer 423. In this arrangement, instead of mounting the RDL structure side of the reconstructed wafer 285 on some carrier substrate, the molding layer side 425 near chips 215, 220, 288, and 289 is mounted on the carrier wafer 423. Before mounting the reconstructed wafer 285 on the carrier wafer 423, a process is used... Figure 11 The technique shown uses a cutting blade 303 to cut a notch 306 in the molded component 230. After the notch 306 is formed and mounted to the carrier wafer 423, a second full dicing step is performed using a slicing blade 319 (although from below, i.e., upward through the wiring substrate 225) to cut a notch 429 that penetrates to the notch 306. At this point, the molded packages 200 and 287 can be separated from the carrier substrate 423 using well-known techniques.

[0083] In the aforementioned exemplary arrangement, the molded package 200 typically includes side-by-side semiconductor chips 215 and 220 arranged in a 2.5D configuration. However, those skilled in the art will understand that the aforementioned techniques can be used to fabricate various types of molded packages to form molded layers with stepped structures that achieve the beneficial effect of stress reduction. For example, and as... Figure 23As shown, the molded package 500 may include a single semiconductor chip 515, a wiring structure 525 mounted on a package substrate 505, and a molding layer 530 having the aforementioned stepped structure including a support surface 543 and a vertical surface 544. For the single chip 515, the support surface 543 may be wider than or equal to the aforementioned vertical surface 243. In other aspects, the molded package 500 may be substantially similar to the package 200 described above.

[0084] In yet another illustrative arrangement, Figure 24 The molded semiconductor chip package 600 shown may include a plurality of semiconductor chips 615 and 620 in a 2.5D arrangement mounted as an interposer on a wiring structure 627. The wiring structure (interposer) 627 may be made of silicon, other types of semiconductors, or even glass structures, and is electrically connected to the package substrate 605 via an interconnect structure 610. Similarly, the molding layer 630 is formed together with the aforementioned support surface 643 and vertical surface 644 to provide stress reduction as described above.

[0085] like Figure 25 As shown, another exemplary semiconductor chip package 700, which can be mounted on a package substrate 705, may include semiconductor chips 715 and 720 interconnected by interconnect chips 722 encapsulated in a molding layer 726. A thin RDL structure 727 is formed on the molding layer 726. Semiconductor chips 715 and 720 include interconnects 728, some of which are connected to the thin RDL structure 727 and others are connected to the interconnect chips 722. The molding layer 726, the thin RDL structure 727, and the interconnect chips 722 provide a wiring substrate. A second molding 730 may be formed to at least partially encapsulate chips 715 and 720 and uses techniques described elsewhere herein to form the aforementioned support surface 743 and elevation surface 744 to provide stress reduction. The molding layer 729 may be filled with a plurality of conductive pillars 733 connected to the package substrate 705 via an interconnect structure 734. The thin RDL structure 728 provides wiring between the semiconductor chips 715 and 720 and the conductive pillars 733.

[0086] In the aforementioned exemplary arrangements and techniques, stepped slicing is performed using mechanical sawing with a slicing blade. However, those skilled in the art will understand that other slicing techniques can be used. Attention will now turn to... Figure 26 The image is similar to Figure 13 The sectional view shows various optional cut formation and cutting techniques. Figure 26A reconstructed wafer 285 is shown, in which semiconductor chips 215 and 220 of molded package 200, semiconductor chips 288 and 289 of adjacent molded package 287, and molding layer 230 are located on RDL structure 225. The reconstructed wafer 285 is mounted on slicing protective tape 295. Using, for example, a laser 811, a waterjet polisher 813 or a sandblaster 817, some combination of these methods, or even one or more of these techniques combined with some combination of mechanical sawing, a wide kerf 306 can be cut in the molding layer 230, and a narrow kerf 321 can be cut in the molding layer 230 and cut through the RDL structure 225. These represent only three possible alternative dicing techniques. Similarly, slicing traces 294, 311, 312, and 316 (see...) Figure 12 Four separate cuts are performed on each of the molded packages 200 and 287 to complete the dicing. The dicing steps can be performed to form the aforementioned vertical surfaces 244 and support surfaces 243 surrounding the molded layers 230 of the chips 215 and 220, and similar vertical surfaces 309 and support surfaces 326 surrounding the semiconductor chips 288 and 289. After dicing, the cut protective tape 295 can be removed, and the molded packages 200 and 287 are formed.

[0087] While the invention may have various modifications and alternatives, specific embodiments are shown by way of example in the accompanying drawings and described in detail herein. However, it should be understood that the invention is not intended to be limited to the specific forms disclosed. Rather, the invention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined by the appended claims.

Claims

1. A semiconductor chip package, comprising: Wiring substrate; A semiconductor chip mounted on and electrically connected to the wiring substrate, the semiconductor chip having multiple side surfaces; The bottom filler between the wiring substrate and the semiconductor chip, wherein the bottom filler is in contact with the semiconductor chip; as well as A molding layer that at least partially encapsulates the semiconductor chip, the molding layer having a support surface and a vertical surface, the vertical surface being adjacent to at least some of the plurality of side surfaces of the semiconductor chip, wherein the top surface of the support surface is higher than the top surface of the underlying filler, and wherein the support surface is in contact with the side surface of the underlying filler.

2. The semiconductor chip package according to claim 1, wherein the vertical surface is narrower than the supporting surface.

3. The semiconductor chip package according to claim 1, wherein the wiring substrate includes a redistribution layer (RDL) structure.

4. The semiconductor chip package of claim 1, wherein a portion of the top surface of the support surface laterally overlaps with and is located above the top edge of the bottom filler.

5. The semiconductor chip package of claim 1, further comprising another semiconductor chip mounted on the wiring substrate, the wiring substrate including another molded layer accommodating interconnect chips connecting the semiconductor chip to the other semiconductor chip.

6. The semiconductor chip package of claim 1, wherein the semiconductor chip includes four side surfaces and the vertical surface is adjacent to all four side surfaces.

7. The semiconductor chip package of claim 1, comprising another semiconductor chip mounted on the wiring substrate and at least partially encapsulated by the molding layer.

8. The semiconductor chip package of claim 1, wherein the wiring substrate includes a plurality of interconnect structures for electrically connecting the semiconductor chip package to another electronic device.

9. A reconstructed wafer, comprising: Multiple semiconductor chip packages, each of which includes: a wiring substrate, A semiconductor chip having multiple side surfaces is mounted on and electrically connected to the wiring substrate. The underlying filler between the wiring substrate and the semiconductor chip, the underlying filler being in contact with the semiconductor chip, and A molding layer that at least partially encapsulates the semiconductor chip, the molding layer having a support surface and a vertical surface, the vertical surface being adjacent to at least some of the plurality of side surfaces of the semiconductor chip, wherein the top surface of the support surface is higher than the top surface of the underlying filler, and wherein the support surface is in contact with the side surface of the underlying filler.

10. The reconstructed wafer of claim 9, wherein the vertical surface is narrower than the supporting surface.

11. The reconstructed wafer of claim 9, wherein the wiring substrate comprises a redistribution layer (RDL) structure.

12. The reconstructed wafer of claim 9, wherein a portion of the top surface of the support surface laterally overlaps with and is located above the top edge of the bottom filler.

13. The reconfigured wafer of claim 9, wherein each of the semiconductor chip packages includes another semiconductor chip mounted on the wiring substrate, the wiring substrate including another molded layer that houses interconnect chips connecting the semiconductor chip to the other semiconductor chip.

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