Array substrate and display device

Abstract

The present disclosure provides an array substrate and a display device. The array substrate comprises a plurality of initialization signal lines (51) and a plurality of connection lines (IO), wherein the initialization signal lines (51) are arranged on a first conductive layer, extending along a first direction and arranged at intervals along a second direction; the connection lines (10) are arranged on a second conductive layer, extending along a second direction and arranged at intervals along the first direction; the first conductive layer and the second conductive layer are the same layer or different layers; the projections of at least one initialization signal line (51) and at least one connection line (10) on a base substrate intersect and are electrically connected, so that the projections of the initialization signal lines (51) and the connection lines (10) on the base substrate form a grid structure. The present disclosure can improve the problem of excessive IR drop and reduce the pressure on the wiring space.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to an array substrate and a display device. Background Art

[0002] OLED (Organic Light Emitting Diode) display technology is recognized by the industry as the third generation display technology for its advantages such as light weight, self-luminescence, wide viewing angle, fast response speed, low brightness and low power consumption. It has been widely used in the field of high-performance displays.

[0003] As the requirements for the PPI (pixel density) of display panels become higher and higher, the wiring pressure on the panel is also increasing. It is necessary to consider both the tight arrangement of various lines and the minimization of the mutual influence between various lines. Therefore, higher requirements are put forward for wiring design.

[0004] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field.

[0005] Public Content

[0006] The purpose of the present disclosure is to provide an array substrate and a display device.

[0007] According to one aspect of the present disclosure, an array substrate is provided, wherein a plurality of pixel units are arranged in an array, wherein the pixel unit includes a plurality of sub-pixels, and the array substrate includes:

[0008] A plurality of initialization signal lines are provided on the first conductive layer on the base substrate, extending along the first direction and arranged at intervals along the second direction, and are used to provide initialization signals to each of the sub-pixels; the first direction and the second direction intersect;

[0009] A plurality of connecting lines are provided on the second conductive layer on the base substrate, extending along the second direction and arranged at intervals along the first direction;

[0010] Wherein, the first conductive layer and the second conductive layer are the same layer or different layers;

[0011] The projections of at least one of the initialization signal lines and at least one of the connection lines on the base substrate intersect and are electrically connected, so that the projections of the initialization signal lines and the connection lines on the base substrate form a grid structure.

[0012] In an exemplary embodiment of the present disclosure, the array substrate includes a base substrate and a first source-drain electrode layer, a second source-drain electrode layer, and an anode layer stacked in sequence on the base substrate; at least one of the first conductive layer and the second conductive layer is the first source-drain electrode layer, and the other is the first source-drain electrode layer or the anode layer; the first direction is a row direction, and the second direction is a column direction;

[0013] The array substrate further includes:

[0014] Data lines, provided in the second source-drain electrode layer, extending along the column direction and arranged at intervals along the row direction, for providing data signals to each of the sub-pixels;

[0015] The power lines are arranged in the second source-drain electrode layer, extending along the column direction and arranged at intervals along the row direction, and are used to provide power signals to each of the sub-pixels.

[0016] In an exemplary embodiment of the present disclosure, the first conductive layer and the second conductive layer are both the first source and drain layers, the initialization signal lines extend in a row direction, the connection lines extend in a column direction, and each of the initialization signal lines is connected to each of the connection lines and crosses in a grid shape.

[0017] In an exemplary embodiment of the present disclosure, the first conductive layer is a first source-drain layer, and the second conductive layer is an anode layer; the initialization signal line is provided in the first source-drain layer, extends along the row direction and is arranged at intervals along the column direction; the connecting line is provided in the anode layer, extends along the column direction and is arranged at intervals along the row direction; each of the initialization signal lines is electrically connected to each of the connecting lines through a via, and the projections of the multiple initialization signal lines and the multiple connecting lines on the substrate are intersected in a grid shape.

[0018] In an exemplary embodiment of the present disclosure, the first conductive layer is an anode layer, and the second conductive layer is a first source and drain layer; the initialization signal line is provided in the anode layer, extends along the row direction and is arranged at intervals along the column direction; the connecting line is provided in the first source and drain layer, extends along the column direction and is arranged at intervals along the row direction; each of the initialization signal lines is electrically connected to each of the connecting lines through a via, and the projections of the multiple initialization signal lines and the multiple connecting lines on the substrate are crossed in a grid shape.

[0019] In an exemplary embodiment of the present disclosure, a plurality of seventh conductive connection parts are further provided on the second source-drain electrode layer, and the seventh conductive connection parts are distributed in the sub-pixel region where the projection of the initialization signal line and the connection line intersect;

[0020] The seventh conductive connection portion is connected to the initialization signal line through a via hole, and the seventh conductive connection portion is connected to the connection line through another via hole, so that the initialization signal line and the connection line are electrically connected through the seventh conductive connection portion.

[0021] In an exemplary embodiment of the present disclosure, the array substrate further includes a first gate line layer and a second gate line layer disposed on the base substrate;

[0022] The sub-pixel further includes a sub-pixel driving circuit, the sub-pixel driving circuit includes a capacitor and a driving transistor, the capacitor includes a first electrode plate and a second electrode plate, the first electrode plate is arranged on the first gate line layer, and the second electrode plate is arranged on the second gate line layer; the first electrode plate of the capacitor is multiplexed as the gate of the driving transistor, and the first stage of the driving transistor is connected to the power line;

[0023] A plurality of third conductive connecting portions are also disposed on the first source-drain electrode layer, and the third conductive connecting portions are distributed in each sub-pixel region;

[0024] The third conductive connection portion is connected to the first stage of the driving transistor through a via hole, and the third conductive connection portion is also connected to the power line through a via hole, so that the power line is electrically connected to the first stage of the driving transistor through the third conductive connection portion.

[0025] In an exemplary embodiment of the present disclosure, the array substrate further comprises a plurality of scan lines, which are arranged in the first gate line layer, extend along the row direction and are arranged at intervals along the column direction, and are used to provide scan signals to each of the sub-pixels;

[0026] The sub-pixel driving circuit further includes a first transistor, a gate of the first transistor is connected to the scan line, a first stage of the first transistor is connected to the data line, and a second stage of the first transistor is connected to the second plate of the capacitor;

[0027] A plurality of fourth conductive connecting portions are also disposed on the first source-drain electrode layer, and the fourth conductive connecting portions are distributed in each sub-pixel region;

[0028] The fourth conductive connection portion is connected to the first stage of the first transistor through a via hole, and the fourth conductive connection portion is also connected to the data line through a via hole, so that the data line is electrically connected to the first stage of the first transistor through the fourth conductive connection portion.

[0029] In an exemplary embodiment of the present disclosure, the sub-pixel includes an anode disposed in the anode layer; the array substrate further includes a plurality of reset signal lines, the reset signal lines are disposed in the first gate line layer, extend along the row direction and are arranged at intervals along the column direction, and are used to provide a reset signal to each of the sub-pixels;

[0030] The sub-pixel driving circuit further includes an eighth transistor, a gate of the eighth transistor is connected to the reset signal line, a first stage of the eighth transistor is electrically connected to the initialization signal line, and a second stage of the eighth transistor is electrically connected to the anode of the sub-pixel;

[0031] A plurality of fifth conductive connection parts are further provided on the first source-drain electrode layer, and a plurality of sixth conductive connection parts are further provided on the second source-drain electrode layer, and the fifth conductive connection parts and the sixth conductive connection parts are both distributed in each sub-pixel region;

[0032] Among them, the fifth conductive connection part and the second level of the eighth transistor are connected through a via, the fifth conductive connection part and the sixth conductive connection part are connected through a via, and the sixth conductive connection part and the anode are connected through a via, so that the second level of the eighth transistor is electrically connected to the anode of the sub-pixel.

[0033] In an exemplary embodiment of the present disclosure, the array substrate further comprises a plurality of light emitting control signal lines, the light emitting control signal lines are provided in the first gate line layer, extend along the row direction and are arranged at intervals along the column direction, and are used to provide light emitting control signals to each of the sub-pixels;

[0034] The sub-pixel driving circuit further includes a second transistor and a ninth transistor, wherein the gate of the second transistor is connected to the scanning line, the first stage of the second transistor is connected to the second stage of the driving transistor, and the second stage of the second transistor is connected to the first plate of the capacitor; the gate of the ninth transistor is connected to the light emitting control signal line, and the first stage of the ninth transistor is electrically connected to the first plate of the capacitor;

[0035] A plurality of first conductive connecting portions are also disposed on the first source-drain electrode layer, and the first conductive connecting portions are distributed in each sub-pixel region;

[0036] Among them, the first conductive connection part and the second level of the second transistor and the first level of the ninth transistor are connected through a via, and the first conductive connection part is also connected to the first plate of the capacitor through a via, so that the second level of the second transistor and the first level of the ninth transistor are electrically connected to the first plate of the capacitor.

[0037] In an exemplary embodiment of the present disclosure, the sub-pixel driving circuit further includes a fifth transistor and a sixth transistor, the gate of the fifth transistor is connected to the reset signal line, the first stage of the fifth transistor is electrically connected to the initialization signal line, and the second stage of the fifth transistor is electrically connected to the second plate of the capacitor; the gate of the sixth transistor is connected to the light emitting control signal line, the first stage of the sixth transistor is electrically connected to the initialization signal line, and the second stage of the sixth transistor is electrically connected to the second plate of the capacitor;

[0038] A plurality of second conductive connecting portions are also disposed on the first source-drain electrode layer, and the second conductive connecting portions are distributed in each sub-pixel region;

[0039] Among them, the second conductive connection part and the second level of the first transistor, the second level of the fifth transistor, and the second level of the sixth transistor are connected through a via, and the second conductive connection part is also connected to the second electrode plate of the capacitor through a via, so that the second level of the first transistor, the second level of the fifth transistor, and the second level of the sixth transistor are electrically connected to the second electrode plate of the capacitor.

[0040] In an exemplary embodiment of the present disclosure, the sub-pixel driving circuit further includes:

[0041] a fourth transistor, wherein a gate of the fourth transistor is connected to the reset signal line, a first stage of the fourth transistor is electrically connected to the initialization signal line, and a second stage of the fourth transistor is electrically connected to the first plate of the capacitor;

[0042] A seventh transistor, wherein a gate of the seventh transistor is connected to the light emitting control signal line, a first level of the seventh transistor is electrically connected to a second level of the driving transistor, and a second level of the seventh transistor is electrically connected to an anode of the sub-pixel.

[0043] In an exemplary embodiment of the present disclosure, the array substrate further includes:

[0044] A plurality of power leads are arranged in the second gate line layer, extending along the row direction and arranged at intervals along the column direction. The power leads in each sub-pixel region in the same row are connected to one power lead through a via hole.

[0045] Wherein, the third conductive connection portion is also connected to the power line through a via hole, so that the power line is electrically connected to the power lead.

[0046] In an exemplary embodiment of the present disclosure, the number of the connection lines is equal to the number of sub-pixels in the row direction, and in the row direction, the initialization signal line and each of the connection lines are electrically connected through a via hole in each sub-pixel region;

[0047] Alternatively, the number of the connection lines is less than the number of sub-pixels in the row direction, and in the row direction, the initialization signal line is electrically connected to each of the connection lines in a partial sub-pixel region through a via hole.

[0048] According to another aspect of the present disclosure, a display device is provided, comprising the array substrate described above.

[0049] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] The accompanying drawings herein are incorporated into the specification and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification are used to explain the principles of the present disclosure. Obviously, the accompanying drawings described below are only some embodiments of the present disclosure, and for ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without creative work.

[0051] Figure 1 A schematic diagram of the positional relationship between the initialization signal line and the connection line in one implementation manner;

[0052] Figure 2 It is a schematic diagram of a 9T1C sub-pixel circuit structure;

[0053] Figure 3 for Figure 2 A timing diagram of the sub-pixel circuit structure shown;

[0054] Figure 4 is a schematic structural diagram of an active layer in a first embodiment;

[0055] Figure 5 Schematic diagram of the stacking of active layer and first gate line layer in the first embodiment;

[0056] Figure 6 Schematic diagram of the stacking of the active layer, the first gate line layer, and the second gate line layer in the first embodiment;

[0057] Figure 7 Schematic diagram of the stacking of the active layer, the first gate line layer, the second gate line layer, and the first source and drain electrode layer in the first embodiment;

[0058] Figure 8 Schematic diagram of the film layer stacking of the active layer, the first gate line layer, the second gate line layer, the first source and drain electrode layer, and the second source and drain electrode layer in the first embodiment;

[0059] Fig. 9 is a schematic structural diagram of the first gate line layer in the first embodiment;

[0060] Fig.10 is a schematic structural diagram of the second gate line layer in the first embodiment;

[0061] Fig.11 is a schematic structural diagram of the first source and drain layer in the first implementation mode;

[0062] Fig.12 is a schematic structural diagram of the second source and drain layer in the first embodiment;

[0063] Fig.13 for Figure 8 Cross-section along the AA direction;

[0064] Fig.14 is a schematic diagram of an array structure of multiple sub-pixels in a first embodiment;

[0065] Fig.15 Schematic diagram of the film stacking of the active layer, the first gate line layer, the second gate line layer, and the first source and drain electrode layer in the second embodiment;

[0066] Fig.16 Schematic diagram of the film stacking of the active layer, the first gate line layer, the second gate line layer, the first source and drain electrode layer, and the second source and drain electrode layer in the second embodiment;

[0067] Fig.17 is a schematic structural diagram of the first source and drain layer in the second embodiment;

[0068] Fig.18 is a schematic structural diagram of a second source-drain electrode layer in a second embodiment;

[0069] Fig.19 is a schematic structural diagram of the anode layer in the second embodiment;

[0070] Fig. 20 for Fig.16 Cross-section along the BB direction;

[0071] Fig.21 is a schematic diagram of an array structure of multiple sub-pixels in a second implementation manner;

[0072] Fig. 22 Schematic diagram of the film stacking of the active layer, the first gate line layer, the second gate line layer, and the first source and drain electrode layer in the third embodiment;

[0073] Fig.23 Schematic diagram of the film layer stacking of the active layer, the first gate line layer, the second gate line layer, the first source and drain electrode layer, and the second source and drain electrode layer in the third embodiment;

[0074] Fig.24 is a schematic structural diagram of the first source and drain layer in the third embodiment;

[0075] Fig.25 is a schematic structural diagram of the second source and drain layer in the third embodiment;

[0076] Fig.26 is a schematic structural diagram of the anode layer in the third embodiment;

[0077] Fig. 27 for Fig.23 Schematic diagram of the cross section along CC direction;

[0078] Fig.28 FIG. 4 is a schematic diagram of an array structure of multiple sub-pixels in a third embodiment.

[0079] In the figure: active layer 100, active layer; 200, first gate insulating layer; 300, first gate line layer; 400, second gate insulating layer; 500, second gate line layer; 500', second gate line layer; 600, first dielectric layer; 700, first source and drain electrode layer; 800, first dielectric layer; 900, first source and drain electrode layer; 1000, passivation layer; 1100, anode layer;

[0080] 31. Scan line; 32. Reset signal line; 33. Light-emitting control signal line; 51. Initialization signal line; 510. Signal segment; 511. Main segment; 512. Extension segment; 52. Power lead; 71. Data line; 72. Power line; 73. Third conductive connection part; 74. Second conductive connection part; 75. First conductive connection part; 76. Fourth conductive connection part; 77. Fifth conductive connection part; 78. Sixth conductive connection part; 79. Seventh conductive connection part; 80. Via; 91. Anode; 10. Connecting line. DETAILED DESCRIPTION

[0081] Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in a variety of forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that the present disclosure will be comprehensive and complete and fully convey the concepts of the example embodiments to those skilled in the art. The same reference numerals in the figures represent the same or similar structures, and thus their detailed description will be omitted. In addition, the drawings are only schematic illustrations of the present disclosure and are not necessarily drawn to scale.

[0082] Although relative terms such as "upper" and "lower" are used in this specification to describe the relative relationship of one component of the illustration to another component, these terms are used in this specification only for convenience, such as according to the orientation of the examples described in the drawings. It is understood that if the device of the illustration is turned upside down, the component described as "upper" will become the component "lower". When a structure is "on" other structures, it may mean that the structure is formed integrally on the other structure, or that the structure is "directly" disposed on the other structure, or that the structure is "indirectly" disposed on the other structure through another structure.

[0083] The terms "a", "an", "the", "said" and "at least one" are used to indicate the presence of one or more elements / components / etc.; the terms "including" and "having" are used to express an open-ended inclusive meaning and mean that additional elements / components / etc. may exist in addition to the listed elements / components / etc.; the terms "first", "second" and "third" etc. are used merely as labels and are not intended to limit the quantity of their objects.

[0084] In an embodiment of the present disclosure, an array substrate is provided. Figure 1 , the array substrate is arrayed with a plurality of pixel units along the row direction and the column direction, and the pixel unit includes a plurality of sub-pixels. The array substrate includes a plurality of initialization signal lines 51 and a plurality of connection lines 10. The plurality of initialization signal lines 51 are arranged in the first conductive layer, extending in the row direction and arranged at intervals in the column direction, and each initialization signal line 51 is used to provide an initialization signal to each sub-pixel in the extension direction thereof. The plurality of connection lines 10 are arranged in the second conductive layer, extending in the column direction and arranged at intervals in the row direction. In the figure, the horizontal direction is the row direction, and the vertical direction is the column direction as an example. The projections of at least one initialization signal line 51 and at least one connection line 10 on the substrate substrate intersect and are electrically connected, so that the projections of the initialization signal line 51 and the connection line 10 on the substrate substrate intersect to form a grid structure.

[0085] The crisscrossed initialization signal lines 51 and connection lines 10 are connected into a grid structure, which increases the paths of the initialization signal. The initialization signal can be transmitted to each sub-pixel through more paths, thereby reducing the problem of excessive IR drop caused by a single current transmission path.

[0086] In the embodiment of the present disclosure, the number of connection lines 10 may be equal to the number of sub-pixels in the row direction, or may be less than the number of sub-pixels in the row direction.

[0087] Specifically, when the number of connection lines 10 is less than the number of sub-pixels in the row direction, it means that in the row direction, the initialization signal line 51 is electrically connected to each connection line 10 in a part of the sub-pixel region. Figure 1, the number of connection lines 10 is half the number of sub-pixels in the row direction, and one connection line is provided for each sub-pixel, so for each sub-pixel, the initialization signal line 51 is electrically connected to a connection line 10. Therefore, one of every two adjacent sub-pixels in the row direction is provided with a connection line 10, while the other is not provided with a connection line 10. In other embodiments, when the number of connection lines 10 is less than the number of sub-pixels in the row direction, different numbers of sub-pixels may be spaced between two adjacent connection lines 10.

[0088] When the number of connection lines 10 is equal to the number of sub-pixels in the row direction, it means that in the row direction, the initialization signal line 51 is electrically connected to each connection line 10 in each sub-pixel region. Therefore, a connection line 10 is provided in each sub-pixel in the row direction. As long as the projections of the plurality of connection lines 10 and the plurality of initialization signal lines 51 on the substrate can form a grid structure, it will be sufficient.

[0089] It is understandable that the more the number of connecting wires 10 is, the denser the grid is, the more transmission paths of the initialization signal is, and the lower the IR drop is, but the wiring space pressure will also be greater, and the manufacturing process will be more difficult. Therefore, the specific number can be set according to the actual situation.

[0090] It should be noted that, taking the example that the initialization signal line 51 extends in the row direction and the connection line extends in the column direction, the horizontal arrangement of the initialization signal line 51 means that the main structure of the initialization signal line 51 extends in the horizontal direction. In actual products, there may be parts that are not completely horizontally arranged, such as turning to avoid other circuit structures, or extending in other directions to facilitate connection with other lines, etc., as long as the overall direction of the initialization signal line 51 is in the horizontal direction. Similarly, the longitudinal arrangement of the connection line 10 means that the main structure of the connection line 10 extends in the longitudinal direction, and the overall direction is in the longitudinal direction.

[0091] The array substrate of this embodiment is described in detail below:

[0092] In this implementation, each pixel unit is composed of four sub-pixels of RGBG, and each sub-pixel is driven by a separate sub-pixel driving circuit.

[0093] Figure 2 A 9T1C sub-pixel circuit structure is shown. The sub-pixel circuit structure includes a capacitor and nine TFT transistors T1 to T9. In this embodiment, the third transistor T3 is a driving transistor, and the other transistors are switch transistors.

[0094] refer to Figure 2, the capacitor includes a first plate Cst1 and a second plate Cst2, the first plate Cst1 is arranged on the first gate line layer 300, and the second plate Cst2 is arranged on the second gate line layer 500. The first plate Cst1 is connected to the node N2, and the second plate Cst2 is connected to the node N1. The gate 3g of the driving transistor T3 (the third transistor) is reused by the first plate Cst1 of the capacitor, and the source 3s is connected to the power line 72; the gate 1g of the first transistor T1 is connected to the scan line 31, the source 1s is connected to the data line 71, and the drain 1d is connected to the node N1. The gate 2g of the second transistor T2 is connected to the scan line 31, the source 2s is connected to the drain 3d of the driving transistor T3, and the drain 2d is connected to the node N2. The gate 4g of the fourth transistor T4 is connected to the reset signal line 32, the source 4s is electrically connected to the initialization signal line 51, and the drain 4d is connected to the node N2. The gate 5g of the fifth transistor T5 is connected to the reset signal line 32, the source 5s is electrically connected to the initialization signal line 51, and the drain 5d is connected to the node N1. The gate 6g of the sixth transistor T6 is connected to the light emission control signal line 33, the source 6s is electrically connected to the initialization signal line 51, and the drain 6d is connected to the node N1. The gate 7g of the seventh transistor T7 is connected to the light emission control signal line 33, the source 7s is electrically connected to the drain 3d of the driving transistor T3, and the drain 7d is electrically connected to the anode 91 of the sub-pixel. The gate 8g of the eighth transistor T8 is connected to the reset signal line 32, the source 8s is electrically connected to the initialization signal line 51, and the drain 8d is electrically connected to the anode 91 of the sub-pixel. The gate 9g of the ninth transistor T9 is connected to the light emission control signal line 33, and the source 9s is connected to the node N2.

[0095] Among them, the initialization signal provided by the initialization signal line 51 is Vint, the reset signal provided by the reset signal line 32 is Reset, the light control signal provided by the light control signal line 33 is EM, the scanning signal provided by the scanning line 31 is gate, the data signal provided by the data line 71 is data, and the power signal provided by the power line 72 is ELVDD.

[0096] refer to Figure 3 As shown in the timing diagram, the specific working principle of the sub-pixel compensation circuit is as follows:

[0097] In the first stage, the reset signal Reset is at a low level. The fourth transistor T4 is turned on, and the initial signal Vint initializes the N2 point. At this time, the potential of the N2 point is the initial signal Vint. The fifth transistor T5 is turned on, and the initial signal Vint is written to the N1 point. The eighth transistor T8 is turned on to release the residual charge displayed in the previous frame. The initial signal Vint is written to reduce the voltage difference between the anode and cathode of the OLED device, reduce the brightness of the OLED device at low grayscale, and improve the contrast of the pixel.

[0098] In the second stage, the signal Gate of the scanning line 31 is at a low level. The first transistor T1 is turned on, and the potential of the N1 point is Vdata, and the data signal voltage is written into the N1 point. The second transistor T2 is turned on, and the diode connection of the driving transistor T3 is sampled. The potential of the N2 point rises to ELVDD+Vth, and the driving transistor T3 gradually changes from the on state to the off state, and the threshold voltage Vth of the driving transistor T3 is compensated.

[0099] In the third stage, the light-emitting control signal EM is at a low level. The sixth transistor T6 is turned on, and the potential of the N1 point is the initial signal Vint. The ninth transistor T9 is turned on, and the leakage of the N2 point is reduced during the light-emitting stage. As the potential of the N1 point jumps, the potential of the N2 point becomes ELVDD+Vth+Vint-Vdata. The seventh transistor T7 is turned on, the driving current is output, and the OLED device emits light. The current calculation formula of the OLED device is:

[0100]

[0101] Through the above circuit, the threshold voltage Vth of the driving transistor T3 can be compensated in the sampling stage, thereby eliminating the influence of the difference in DTFT threshold voltage Vth of different pixels on the uniformity of display brightness.

[0102] In this embodiment, Vint can be used as an initialization signal or as a reference signal when writing data.

[0103] In this embodiment, the sub-pixel driving circuit of each sub-pixel is prepared on a substrate. An active layer 100, a first gate line layer 300, a second gate line layer 500, a first source-drain electrode layer 700, a second source-drain electrode layer 900, and an anode layer 1100 are stacked on the substrate. These film layers are used to form various signal lines or wires to provide corresponding electrical signals to each sub-pixel driving circuit. The two film layers are insulated by an insulating layer, for example, a first gate insulating layer 200 is arranged between the active layer 100 and the first gate line layer 300, a second gate insulating layer 400 is arranged between the first gate line layer 300 and the second gate line layer 500, a first dielectric layer 600 is arranged between the second gate line layer 500 and the first source-drain electrode layer 700, a second dielectric layer 800 is arranged between the first source-drain electrode layer 700 and the second source-drain electrode layer 900, and a passivation layer 1000 is further arranged above the second source-drain electrode layer 900. The anode layer 1100, organic light emitting layer, cathode layer and other film layers of the sub-pixel are arranged above the passivation layer 1000 to form an OLED light emitting device, and the OLED light emitting devices of each sub-pixel are separated by the pixel defining layer. In this embodiment, only the passivation layer 1000 is arranged between the second source and drain layer 900 and the anode layer 1100 for explanation, and in other embodiments, other film layers such as a planarization layer may also be arranged.

[0104] Figure 4-Figure 8 1 shows a schematic diagram of a film stack of an active layer 100, a first gate line layer 300, a second gate line layer 500, a first source and drain electrode layer 700, and a second source and drain electrode layer 900 in a sub-pixel region in a first embodiment. Figure 9-12 The schematic diagram of the structure of each layer of the first gate line layer 300, the second gate line layer 500, the first source and drain electrode layer 700, and the second source and drain electrode layer 900 in a sub-pixel area is shown. Fig.13 Shows Figure 8 Schematic diagram of the cross section along the AA direction.

[0105] refer to Figure 4 The active layer 100 is used to set the channel region (1g-9g), the first level (1s-9s) and the second level (1d-9d) of each TFT transistor.

[0106] refer to Figure 5 and Fig. 9 The first gate line layer 300 is used to set the gates (such as 1g to 9g) of each transistor in the sub-pixel driving circuit, the first electrode Cst1 of the capacitor, and multiple scan lines 31, multiple reset signal lines 32, multiple light-emitting control signal lines 33 and other structures. Multiple scan lines 31 are arranged at intervals along the column direction and extend along the row direction, and are used to provide scan signals to each sub-pixel located in the same row in the row direction. Multiple reset signal lines 32 are arranged at intervals along the column direction and extend along the row direction, and are used to provide reset signals to each sub-pixel located in the same row in the row direction. Multiple light-emitting control signal lines 33 extend along the row direction and are arranged at intervals along the column direction, and are used to provide light-emitting control signals to each sub-pixel located in the same row in the row direction. Among them, in each sub-pixel area, the reset signal line 32 is located at the top, the scan line 31 is located at the bottom, the light-emitting control signal line 33 is located between the reset signal line 32 and the scan line 31, and the first electrode Cst1 of the capacitor is located between the light-emitting control signal line 33 and the scan line 31. In the column direction, the reset signal line 32 of the next level sub-pixel can be connected to the scan line 31 of the previous level sub-pixel, so that the scan signal of the previous level sub-pixel can be used as the reset signal of the next level sub-pixel, thereby avoiding the introduction of a dedicated signal line for the reset signal and effectively reducing the wiring space.

[0107] refer to Figure 6 and Fig.10The second gate line layer 500 is used to set a structure such as a second electrode plate Cst2 of a capacitor, and the second electrode plate Cst2 of the capacitor corresponds to the first electrode plate Cst1 in the thickness direction of the array substrate. In this embodiment, the second gate line layer 500 also includes a plurality of power leads 52, which extend in the row direction and are arranged at intervals in the column direction. The power leads 52 are used to connect the power lines 72 in each sub-pixel area of ​​the same row through vias, thereby forming a grid-like structure between the power leads 52 and the projections of the power lines 72, which can reduce the voltage drop of the power supply voltage.

[0108] refer to Figure 7 , Fig.11 and Fig.13 In this embodiment, the first conductive layer and the second conductive layer are both in the first source-drain layer 700, that is, the initialization signal line 51 and the connecting line 10 are both arranged in the first source-drain layer 700, the initialization signal line 51 extends in the row direction, and the connecting line 10 extends in the column direction, and each initialization signal line 51 is connected to each connecting line 10 and crosses in a grid shape. That is to say, in this embodiment, there are initialization signal lines 51 and connecting lines 10 in each sub-pixel area. In the prior art, the initialization signal line 51 is often set in the gate layer, and the initialization signal is easily affected by the gate drive signal. The initialization signal line 51 and the connecting line 10 disclosed in the present invention are in the first source-drain layer 700, which can reduce the parasitic capacitance between the initialization signal and the gate drive signal, enhance the anti-interference ability, and improve the product display uniformity. The initialization signal line 51 is also connected to the source 5s of the fifth transistor T5 and the source 6s of the sixth transistor T6 through a via hole penetrating the first gate insulating layer 200, the second gate insulating layer 400, and the first dielectric layer 600, and is further connected to the source 4s of the fourth transistor T4 and the source 8s of the eighth transistor T8. It should be noted that the connection line 10 shown in the figure is bent to avoid other structures, but it does not affect its overall extension direction which is longitudinal.

[0109] refer to Figure 8 and Fig.12, the power line 72 and the data line 71 are both arranged in the second source-drain layer 900. The power line 72 extends in the column direction and is arranged at intervals in the row direction, and is used to provide power signals to each sub-pixel located in the same column. The power line 72 is connected to the power lead 52 through a via to realize the gridding of the power line. The data line 71 extends in the column direction and is arranged at intervals in the row direction, and is used to provide data signals to each sub-pixel located in the same column. Among them, the projections of the power line 72 and the data line 71 on the array substrate have no overlap with the first plate Cst1 and the second plate Cst2 of the capacitor. The present disclosure arranges the power line 72 and the data line 71 in the second source-drain layer 900, and arranges them in layers with the initialization signal line 51 and the connection line 10, which can reduce the parasitic capacitance between the power line 72, the data line 71 and other nodes, enhance the stability of the power signal and the data signal, and is more suitable for high-frequency driven display products.

[0110] Continue to refer Figure 7 and Fig.11 , a plurality of first conductive connection parts 75 are also provided on the first source-drain electrode layer 700, and each first conductive connection part 75 is provided on the source-drain electrode layer 700 and distributed in each sub-pixel region. As shown in the figure, in each sub-pixel region, the projection of the first conductive connection part 75 on the substrate overlaps with the projection of 2d of the second transistor T2 and the projection of the first stage 9s of the ninth transistor T9, and is connected through a via hole penetrating the first gate insulating layer 200, the second gate insulating layer 400, and the first dielectric layer 600. The projection of the first conductive connection part 75 on the substrate also overlaps with the projection of the first electrode plate Cst1 of the capacitor, and is connected through a via hole penetrating the second gate insulating layer 400 and the first dielectric layer 600. That is to say, 2d and 9s are both electrically connected to the first electrode plate Cst1 of the capacitor through the first conductive connection part 75. In each sub-pixel region, the first conductive connection part 75 is located on the right side of the connecting line 10,

[0111] A plurality of second conductive connection parts 74 are also provided on the first source-drain electrode layer 700, and each second conductive connection part 74 is provided on the source-drain electrode layer 700 and distributed in each sub-pixel region. As shown in the figure, in each sub-pixel region, the projection of the second conductive connection part 74 on the substrate overlaps with the projection of the drain 1d of the first transistor T1, the drain 5d of the fifth transistor T5, and the drain 6d of the sixth transistor T6, and is connected through a via hole penetrating the first gate insulating layer 200, the second gate insulating layer 400, and the first dielectric layer 600. The projection of the second conductive connection part 74 on the substrate also overlaps with the projection of the second electrode plate Cst2 of the capacitor, and is connected through a via hole penetrating the first dielectric layer 600, that is, 1d, 5d, and 6d are all electrically connected to the second electrode plate Cst2 of the capacitor through the second conductive connection part 74. In each sub-pixel region, the second conductive connection part 74 is located on the right side of the first conductive connection part 75.

[0112] A plurality of third conductive connection parts 73 are also provided on the first source-drain electrode layer 700, and each third conductive connection part 73 is distributed in each sub-pixel region. As shown in the figure, in each sub-pixel region, the projection of the third conductive connection part 73 on the substrate overlaps with the projection of the source 3s of the driving transistor T3, and is connected through a via hole penetrating the first gate insulating layer 200, the second gate insulating layer 400, and the first dielectric layer 600. The projection of the third conductive connection part 73 on the substrate also overlaps with the projection of the power line 72, and is connected through a via hole penetrating the second dielectric layer 800. In other words, the third conductive connection part 73 is used to connect the source 3s of the driving transistor T3 and the power line 72. The projection of the third conductive connection part 73 on the substrate also overlaps with the projection of the power lead 52, and is connected through a via hole penetrating the first dielectric layer 600 to connect the power line 72 with the power lead 52. It should be noted that in each sub-pixel region, the third conductive connection part 73 is located on the right side of the second conductive connection part 74.

[0113] A plurality of fourth conductive connection parts 76 are also provided on the first source-drain electrode layer 700, and each fourth conductive connection part 76 is provided on the first source-drain electrode layer 700 and distributed in each sub-pixel region. As shown in the figure, in each sub-pixel region, the projection of the fourth conductive connection part 76 on the substrate overlaps with the projection of the source 1s of the first transistor T1, and is connected through a via hole penetrating the first gate insulating layer 200, the second gate insulating layer 400, and the first dielectric layer 600. The projection of the fourth conductive connection part 76 on the substrate also overlaps with the projection of the data line 71, and is connected through a via hole penetrating the second dielectric layer 800. In other words, the fourth conductive connection part 76 is used to connect the source 1s of the first transistor T1 and the data line 71. In each sub-pixel region, the fourth conductive connection part 76 is located on the right side of the third conductive connection part 73.

[0114] A plurality of fifth conductive connection parts 77 are also provided on the first source-drain electrode layer 700, and each fifth conductive connection part 77 is provided on the first source-drain electrode layer 700 and distributed in each sub-pixel region. As shown in the figure, in each sub-pixel region, the projection of the fifth conductive connection part 77 on the substrate overlaps with the projection of the drain 8d of the eighth transistor T8, and is connected through a via hole penetrating the first gate insulating layer 200, the second gate insulating layer 400, and the first dielectric layer 600. The projection of the fifth conductive connection part 77 on the substrate also overlaps with the projection of the sixth conductive connection part 78 provided on the second source-drain electrode layer 900, and is connected to the sixth conductive connection part 78 through a via hole penetrating the second dielectric layer 800. The projection of the sixth conductive connection part 78 on the substrate also overlaps with the projection of the anode of the sub-pixel, and is connected through a via hole provided on the passivation layer 1000. That is, the drain 8d of the eighth transistor T8 is connected to the anode through the fifth conductive connection part 77 and the sixth conductive connection part 78 in sequence, thereby driving the pixel anode. In each sub-pixel region, the fifth conductive connection portion 77 is located on the right side of the connection line 10 and the first conductive connection portion 75 .

[0115] It should be noted that Fig.11 The circular structure located at the lower left corner of the first source-drain layer 700 in the sub-pixel region is the right half of the fourth conductive connection portion 76 of the adjacent sub-pixel on the left, and the right half of the fourth conductive connection portion 76 of this sub-pixel region is located at the lower left corner of the adjacent sub-pixel on the right. Fig.12 The longitudinal line located on the left side of the second source-drain electrode layer 900 in the sub-pixel region is the data line 71 of the left adjacent sub-pixel. The data line 71 of this sub-pixel region can also be regarded as being located in the right adjacent sub-pixel.

[0116] Fig.14 A schematic diagram of the structure of an array of eight sub-pixels is shown, in which only the initialization signal line 51 and the connection line 10 in the first source-drain electrode layer 700 are shown, and other conductive connection parts are not shown. In this embodiment, the number of connection lines 10 is the same as the number of sub-pixels in the row direction, that is, a longitudinal connection line 10 is provided for each column of sub-pixels.

[0117] In this embodiment, since the first source-drain layer 700 is dry-etched, the initialization signal line 51 and the connection line 10 are arranged in the first source-drain layer 700, which can improve the etching yield. In addition, the material resistance of the first source-drain layer 700 is low, which is conducive to improving IR drop.

[0118] Figure 15-16 FIG. 4 shows a schematic diagram of a film stack of a first source-drain electrode layer 700 and a second source-drain electrode layer 900 in a sub-pixel region in a second embodiment. Figure 17-Figure 19The schematic diagram of the structure of each layer of the first source-drain electrode layer 700, the second source-drain electrode layer 900, and the anode layer 1100 in a sub-pixel region is shown. Figure 4 , Fig. 9 , Fig.10 The same, so the relevant drawings and descriptions are omitted here. Fig. 20 Shows Fig.16 Schematic diagram of the cross section along the BB direction.

[0119] refer to Fig.15 and Fig.17 , the first conductive layer is the first source-drain electrode layer 700, that is, the initialization signal line 51 is provided in the first source-drain electrode layer 700, extending in the row direction and arranged at intervals in the column direction. In this embodiment, the initialization signal line 51 is located above the sub-pixel area, and its projection on the substrate overlaps with the reset signal line 32. Since the reset signal line 32 is located in the first gate line layer 300 and the initialization signal line 51 is located in the first source-drain electrode layer 700, there are more film layers between the reset signal line 32 and the initialization signal line 51, and even if there is an overlap, parasitic capacitance is not easily generated, which can ensure the stability of the signal. The first source-drain electrode layer 700 is also provided with Fig.11 The same first to fifth conductive connecting parts have the same structure and function as Fig.11 The same as in, no further description is given here.

[0120] refer to Fig.19 , the anode layer 1100 is used to set the anode 91 of the OLED light-emitting device, which is located in the opening of the pixel definition layer. The opening is also provided with an organic light-emitting layer and a cathode layer. The film structure of the OLED light-emitting device can adopt a conventional structure, which will not be described here. The figure shows a schematic diagram of the anode layer 1100 structure of an RGBG pixel structure.

[0121] In this embodiment, the second conductive layer is the anode layer 1100, that is, the connection line 10 is disposed in the anode layer 1100, passes through the gap between two anodes 91 in the longitudinal direction, and is insulated from any anode 91. The connection line 10 is covered by the pixel definition layer to avoid contact with other film layers above.

[0122] In order to realize the connection between the initialization signal line 51 and the connection line 10, refer to Fig.15 , Fig.17 and Fig. 20 A seventh conductive connection part 79 is provided on the second source-drain electrode layer 900, and multiple seventh conductive connection parts 79 are distributed in the sub-pixel area where the projection of the initialization signal line 51 and the connection line 10 intersect. In other words, the second source-drain electrode layer 900 of all sub-pixels is not necessarily provided with the seventh conductive connection part 79, but the seventh conductive connection part 79 is provided in the sub-pixel where the initialization signal line 51 and the connection line 10 are connected. Fig.17 900 indicates the first source-drain layer structure provided with the seventh conductive connection portion 79, and 900′ indicates the first source-drain layer structure without the seventh conductive connection portion 79. In the sub-pixel region provided with the seventh conductive connection portion 79, the projection of the seventh conductive connection portion 79 on the substrate substrate has an overlapping region with the projection of the initialization signal line 51, and is connected through a via hole provided on the second dielectric layer 800. The projection of the seventh conductive connection portion 79 on the substrate substrate has an overlapping region with the projection of the connection line 10, and is connected through a via hole provided on the passivation layer 1000, thereby making the initialization signal line 51 and the connection line 10 electrically connected through the seventh conductive connection portion 79.

[0123] The second source and drain layer 900 is also provided with Fig.12 The same power line 72, data line 71 and sixth conductive connection portion 78, whose structure and function are the same as Fig.12 The same as in, no further description is given here.

[0124] Fig.21 Shows Fig.16 The schematic diagram of the structure of the eight sub-pixels array arrangement shown in the figure only shows the initialization signal line 51 in the first source-drain layer 700, the seventh conductive connection part 79 in the second source-drain layer 900, and the connection line 10 of the anode layer 1100, and other circuit structures are not shown. It can be seen from the figure that in this embodiment, the number of connection lines 10 is half of the number of sub-pixels in the row direction, that is, one of every two adjacent sub-pixels in the row direction is provided with a connection line 10, and the other is not provided with a connection line 10. In addition, in this embodiment, each connection line 10 is not arranged through the same column of sub-pixels, but is arranged in a bend in two adjacent columns of sub-pixels. Specifically, in the upper row of sub-pixels, the connection line 10 is connected to the initialization signal line 51 in the left sub-pixel, and in the lower row of sub-pixels, the connection line 10 is bent to the initialization signal line 51 in the right sub-pixel, which is to avoid the pixels on the anode layer 1100. It should be noted that although the connection line 10 is bent in the longitudinal direction, since its overall direction is still longitudinal, it is regarded as extending in the longitudinal direction.

[0125] Figure 22-Figure 23 FIG. 4 shows a schematic diagram of a film stack of a first source-drain electrode layer 700 and a second source-drain electrode layer 900 in a sub-pixel region in a third embodiment. Figure 24-26 The schematic diagram of the structure of each layer of the first source-drain electrode layer 700, the second source-drain electrode layer 900, and the anode layer 1100 in a sub-pixel region is shown. Figure 4 , Fig. 9 , Fig.10 The same, so the relevant drawings and descriptions are omitted here. Fig. 27 Shows Fig.23 Schematic diagram of the cross section along the CC direction.

[0126] refer to Fig. 22 and Fig.24 In this embodiment, the second conductive layer is the first source-drain electrode layer 700, that is, the connecting wires 10 are provided in the first source-drain electrode layer 700, extending along the column direction and arranged at intervals along the row direction. The connecting wires 10 are located on the left side of the sub-pixel region. Fig.26 In this embodiment, the number of connecting lines is half the number of sub-pixels in the row direction, that is, one of every two adjacent sub-pixels in the row direction is provided with a connecting line 10, while the other is not provided with a connecting line 10. Therefore, Fig.24 700 is a schematic diagram of the structure of the first source-drain layer provided with the connecting wire 10, and 700' is a schematic diagram of the structure of the first source-drain layer without the connecting wire 10. Fig.11 The same first to fifth conductive connection parts are all located on the right side of the connection line 10 , and their structures and functions are the same as those described above, which will not be described again.

[0127] refer to Fig.26 The schematic diagram of the anode layer 1100 structure of the RGBG pixel structure shown in the figure, in this embodiment, the first conductive layer is the anode layer 1100, that is, the initialization signal line 51 is arranged in the anode layer 1100, passes through the gap between two rows of sub-pixels in the lateral direction, and is insulated from any anode 91. The initialization signal line 51 is covered by the pixel definition layer to avoid contact with other film layers above. In order to avoid the pixel opening area, the initialization signal line 51 is bent, but its overall extension direction is still lateral.

[0128] In order to realize the connection between the initialization signal line 51 and the connection line 10, refer to Fig.23 , Fig.25 and Fig. 27 A seventh conductive connection part 79 is provided on the second source-drain electrode layer 900, and multiple seventh conductive connection parts 79 are distributed in the sub-pixel area where the projection of the initialization signal line 51 and the connection line 10 intersect. In other words, the second source-drain electrode layer 900 of all sub-pixels is not necessarily provided with the seventh conductive connection part 79, but the seventh conductive connection part 79 is provided in the sub-pixel where the initialization signal line 51 and the connection line 10 are connected. Fig.25900 indicates a second source-drain layer structure provided with the seventh conductive connection portion 79, and 900′ indicates a second source-drain layer structure without the seventh conductive connection portion 79. In the sub-pixel region provided with the seventh conductive connection portion 79, the projection of the seventh conductive connection portion 79 on the base substrate has an overlapping area with the projection of the connection line 10, and is connected through a via hole provided on the second dielectric layer 800. The projection of the seventh conductive connection portion 79 on the base substrate also has an overlapping area with the projection of the initialization signal line 51, and is connected through a via hole provided on the passivation layer 1000, thereby making the initialization signal line 51 and the connection line 10 electrically connected through the seventh conductive connection portion 79.

[0129] In addition, since the initialization signal line 51 also needs to be connected to the source 5s of the fifth transistor T5, in the sub-pixel region where the connecting line 10 is provided, the projection of the connecting line 10 on the substrate also has an overlapping area with the projection of the source 5s of the fifth transistor T5, and the connecting line 10 is connected to the source 5s of the fifth transistor T5 through a via hole penetrating the first gate insulating layer 200, the second gate insulating layer 400, and the first dielectric layer 600. Since the initialization signal line 51 and the connecting line 10 are electrically connected, the initialization signal line 51 is connected to the source 5s of the fifth transistor T5 in sequence through the seventh conductive connection portion 79, the connecting line, and the source 5s of the fifth transistor T5. In this embodiment, the wiring arrangement of other lines of the second source and drain layer 900 is also the same as that of the previous embodiment.

[0130] The second source and drain layer 900 is also provided with Fig.12 The same power line 72, data line 71 and sixth conductive connection portion 78, whose structure and function are the same as Fig.12 The same as in, no further description is given here.

[0131] Fig.28 The schematic diagram of the structure of the arrangement of eight sub-pixels in an array is shown, in which only the connection line 10 in the first source-drain electrode layer 700, the seventh conductive connection portion 79 in the second source-drain electrode layer 700, and the initialization signal line 51 in the anode layer 1100 are shown, and other circuit structures are not shown. In this embodiment, the number of the connection lines 10 is the same as the number of sub-pixels in the row direction, that is, each column of sub-pixels is provided with a longitudinal connection line 10 and a seventh conductive connection portion 79.

[0132] The above embodiments give a variety of setting positions and connection methods of the initialization signal lines and connecting lines of the present disclosure. The various structures of the present disclosure can take into account the requirements of PPI and performance of different products while reasonably wiring. It can be understood that the setting positions and connection methods of the initialization signal lines and connecting lines can be arbitrarily combined to adapt to the requirements of PPI, process feasibility and display performance of the display panel. In addition, the above embodiments are described by taking the pixel circuit structure of 9T1C as an example. When the array substrate adopts other pixel circuit structures, the initialization signal lines and connecting lines can also be set in the form of a dual source and drain layer of the present disclosure to form a grid, which can also reduce IR drop and relieve wiring pressure. In addition, each of the above pixel units is composed of four RGBG sub-pixels, and only one algorithm is used as an example for arrangement. The structure of the initialization signal lines and connecting lines in a grid-like layered connection disclosed in the present disclosure can also be applied to RGBG pixel structures arranged by other algorithms. Further, when the pixel unit adopts other settings, such as RGB, RGBW, etc., the initialization signal lines and connecting lines can also be connected in a grid-like manner through a dual source and drain layer, which can also reduce IR drop and relieve wiring pressure.

[0133] The embodiment of the present disclosure further provides a display device, which includes the array substrate of the above embodiment. Since the display device includes the above array substrate, it has the same beneficial effects, and the present disclosure will not repeat them here.

[0134] The present disclosure does not impose any specific restrictions on the applicability of display devices, which can be any product or component with flexible display function, such as televisions, laptops, tablet computers, wearable display devices, mobile phones, car displays, navigation, e-books, digital photo frames, advertising light boxes, etc.

[0135] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. The present disclosure is intended to cover any variations, uses or adaptations of the present disclosure, which follow the general principles of the present disclosure and include common knowledge or customary techniques in the art that are not disclosed in the present disclosure. The description and examples are intended to be exemplary only, and the true scope and spirit of the present disclosure are indicated by the appended claims.

Claims

1. An array substrate, wherein a plurality of pixel units are arranged in an array, wherein the pixel unit comprises a plurality of sub-pixels, wherein: The array substrate comprises: A plurality of initialization signal lines are provided on the first conductive layer on the base substrate, extending along the first direction and arranged at intervals along the second direction, and are used to provide initialization signals to each of the sub-pixels; the first direction and the second direction intersect; A plurality of connecting lines are provided on the second conductive layer on the base substrate, extending along the second direction and arranged at intervals along the first direction; Wherein, the first conductive layer and the second conductive layer are the same layer or different layers; The projections of at least one of the initialization signal lines and at least one of the connection lines on the substrate intersect and are electrically connected, so that the projections of the initialization signal lines and the connection lines on the substrate form a grid structure; The array substrate comprises a base substrate and a first source-drain electrode layer, a second source-drain electrode layer, and an anode layer stacked in sequence on the base substrate; at least one of the first conductive layer and the second conductive layer is the first source-drain electrode layer, and the other is the first source-drain electrode layer or the anode layer; the first direction is a row direction, and the second direction is a column direction; The array substrate further includes: Data lines, provided in the second source-drain electrode layer, extending along the column direction and arranged at intervals along the row direction, for providing data signals to each of the sub-pixels; The power lines are arranged in the second source-drain electrode layer, extending along the column direction and arranged at intervals along the row direction, and are used to provide power signals to each of the sub-pixels.

2. The array substrate according to claim 1, wherein: The first conductive layer and the second conductive layer are both the first source and drain layers. The initialization signal lines extend in a row direction, and the connection lines extend in a column direction. Each of the initialization signal lines is connected to each of the connection lines and crosses to form a grid.

3. The array substrate according to claim 1, wherein: The first conductive layer is a first source-drain layer, and the second conductive layer is an anode layer; the initialization signal line is arranged in the first source-drain layer, extends along the row direction and is arranged at intervals along the column direction; the connecting line is arranged in the anode layer, extends along the column direction and is arranged at intervals along the row direction; each of the initialization signal lines is electrically connected to each of the connecting lines through a via, and the projections of the multiple initialization signal lines and the multiple connecting lines on the substrate are crossed in a grid shape.

4. The array substrate according to claim 1, wherein: The first conductive layer is an anode layer, and the second conductive layer is a first source and drain layer; the initialization signal line is arranged in the anode layer, extends along the row direction and is arranged at intervals along the column direction; the connecting line is arranged in the first source and drain layer, extends along the column direction and is arranged at intervals along the row direction; each of the initialization signal lines is electrically connected to each of the connecting lines through a via, and the projections of the multiple initialization signal lines and the multiple connecting lines on the substrate are crossed in a grid shape.

5. The array substrate according to claim 3 or 4, wherein: A plurality of seventh conductive connection parts are also provided on the second source-drain electrode layer, and the seventh conductive connection parts are distributed in the sub-pixel region where the projections of the initialization signal line and the connection line intersect; The seventh conductive connection portion is connected to the initialization signal line through a via hole, and the seventh conductive connection portion is connected to the connection line through another via hole, so that the initialization signal line and the connection line are electrically connected through the seventh conductive connection portion.

6. The array substrate according to any one of claims 2 to 5, wherein: The array substrate further comprises a first gate line layer and a second gate line layer disposed on the base substrate; The sub-pixel further includes a sub-pixel driving circuit, the sub-pixel driving circuit includes a capacitor and a driving transistor, the capacitor includes a first electrode plate and a second electrode plate, the first electrode plate is arranged on the first gate line layer, and the second electrode plate is arranged on the second gate line layer; the first electrode plate of the capacitor is multiplexed as the gate of the driving transistor, and the first stage of the driving transistor is connected to the power line; A plurality of third conductive connecting portions are also disposed on the first source-drain electrode layer, and the third conductive connecting portions are distributed in each sub-pixel region; The third conductive connection portion is connected to the first stage of the driving transistor through a via hole, and the third conductive connection portion is also connected to the power line through a via hole, so that the power line is electrically connected to the first stage of the driving transistor through the third conductive connection portion.

7. The array substrate according to claim 6, wherein: The array substrate further comprises a plurality of scan lines, which are arranged on the first gate line layer, extend along the row direction and are arranged at intervals along the column direction, and are used to provide scan signals to each of the sub-pixels; The sub-pixel driving circuit further includes a first transistor, a gate of the first transistor is connected to the scan line, a first stage of the first transistor is connected to the data line, and a second stage of the first transistor is connected to the second plate of the capacitor; A plurality of fourth conductive connecting portions are also disposed on the first source-drain electrode layer, and the fourth conductive connecting portions are distributed in each sub-pixel region; The fourth conductive connection portion is connected to the first stage of the first transistor through a via hole, and the fourth conductive connection portion is also connected to the data line through a via hole, so that the data line is electrically connected to the first stage of the first transistor through the fourth conductive connection portion.

8. The array substrate according to claim 7, wherein: The sub-pixel includes an anode disposed in the anode layer; the array substrate further includes a plurality of reset signal lines, which are disposed in the first gate line layer, extend along the row direction and are arranged at intervals along the column direction, and are used to provide reset signals to each of the sub-pixels; The sub-pixel driving circuit further includes an eighth transistor, a gate of the eighth transistor is connected to the reset signal line, a first stage of the eighth transistor is electrically connected to the initialization signal line, and a second stage of the eighth transistor is electrically connected to the anode of the sub-pixel; A plurality of fifth conductive connection parts are further provided on the first source-drain electrode layer, and a plurality of sixth conductive connection parts are further provided on the second source-drain electrode layer, and the fifth conductive connection parts and the sixth conductive connection parts are both distributed in each sub-pixel region; Among them, the fifth conductive connection part and the second level of the eighth transistor are connected through a via, the fifth conductive connection part and the sixth conductive connection part are connected through a via, and the sixth conductive connection part and the anode are connected through a via, so that the second level of the eighth transistor is electrically connected to the anode of the sub-pixel.

9. The array substrate according to claim 8, wherein: The array substrate further comprises a plurality of light-emitting control signal lines, which are arranged in the first gate line layer, extend along the row direction and are arranged at intervals along the column direction, and are used to provide light-emitting control signals to each of the sub-pixels; The sub-pixel driving circuit further includes a second transistor and a ninth transistor, wherein the gate of the second transistor is connected to the scanning line, the first stage of the second transistor is connected to the second stage of the driving transistor, and the second stage of the second transistor is connected to the first plate of the capacitor; the gate of the ninth transistor is connected to the light emitting control signal line, and the first stage of the ninth transistor is electrically connected to the first plate of the capacitor; A plurality of first conductive connecting portions are also disposed on the first source-drain electrode layer, and the first conductive connecting portions are distributed in each sub-pixel region; Among them, the first conductive connection part and the second level of the second transistor and the first level of the ninth transistor are connected through a via, and the first conductive connection part is also connected to the first plate of the capacitor through a via, so that the second level of the second transistor and the first level of the ninth transistor are electrically connected to the first plate of the capacitor.

10. The array substrate according to claim 9, wherein: The sub-pixel driving circuit further includes a fifth transistor and a sixth transistor, wherein the gate of the fifth transistor is connected to the reset signal line, the first stage of the fifth transistor is electrically connected to the initialization signal line, and the second stage of the fifth transistor is electrically connected to the second plate of the capacitor; the gate of the sixth transistor is connected to the light emitting control signal line, the first stage of the sixth transistor is electrically connected to the initialization signal line, and the second stage of the sixth transistor is electrically connected to the second plate of the capacitor; A plurality of second conductive connecting portions are also disposed on the first source-drain electrode layer, and the second conductive connecting portions are distributed in each sub-pixel region; Among them, the second conductive connection part and the second level of the first transistor, the second level of the fifth transistor, and the second level of the sixth transistor are connected through a via, and the second conductive connection part is also connected to the second electrode plate of the capacitor through a via, so that the second level of the first transistor, the second level of the fifth transistor, and the second level of the sixth transistor are electrically connected to the second electrode plate of the capacitor.

11. The array substrate according to claim 10, wherein: The sub-pixel driving circuit further includes: a fourth transistor, wherein a gate of the fourth transistor is connected to the reset signal line, a first stage of the fourth transistor is electrically connected to the initialization signal line, and a second stage of the fourth transistor is electrically connected to the first plate of the capacitor; A seventh transistor, wherein a gate of the seventh transistor is connected to the light emitting control signal line, a first level of the seventh transistor is electrically connected to a second level of the driving transistor, and a second level of the seventh transistor is electrically connected to an anode of the sub-pixel.

12. The array substrate according to claim 6, wherein: The array substrate further includes: A plurality of power leads are provided in the second gate line layer, extending along the row direction and arranged at intervals along the column direction, and the power leads in each of the sub-pixel regions in the same row are connected to one of the power leads through a via hole; Wherein, the third conductive connection portion is also connected to the power line through a via hole, so that the power line is electrically connected to the power lead.

13. The array substrate according to claim 1, wherein: The number of the connection lines is equal to the number of sub-pixels in the row direction, and in the row direction, the initialization signal line and each of the connection lines are electrically connected through a via hole in each sub-pixel region; Alternatively, the number of the connection lines is less than the number of sub-pixels in the row direction, and in the row direction, the initialization signal line is electrically connected to each of the connection lines in a partial sub-pixel region through a via hole.

14. A display device, wherein: The invention comprises the array substrate according to any one of claims 1 to 13.

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