Semiconductor device

Abstract

The present invention provides a semiconductor device comprising: an active portion (102) disposed on a semiconductor substrate (10); a plurality of trench portions having gate conductive portions (44), wherein the plurality of trench portions in the active portion extend along a predetermined extension direction and are arranged along a predetermined arrangement direction, wherein the ratio of the width (Wg) of the gate conductive portions in the arrangement direction to the trench length (Lt) in the extension direction is 1000 or more; a first control pad (110) which, when viewed from above, protrudes from a predetermined first outer periphery (151) of the semiconductor substrate toward the inside of the semiconductor substrate; and a first well region (115) disposed below the first control pad and configured to cover the first control pad when viewed from above, wherein, when viewed from above, the shortest distance (R1a) between the first well region and the trench center position (TP), which is the center of the length in the extension direction of the plurality of trench portions, is 1000 μm or more.

Description

Technical Field

[0001] This invention relates to semiconductor devices. Background Technology

[0002] Previously, semiconductor devices with a well region disposed below the control pads were known, and the semiconductor device had multiple trench portions.

[0003] Existing technical documents

[0004] Patent documents

[0005] Patent Document 1: International Publication No. 2019 / 078166

[0006] Patent Document 2: Japanese Patent Application Publication No. 2020-077674

[0007] Patent Document 3: Japanese Patent Application Publication No. 2019-186510

[0008] Patent Document 4: International Publication No. 2018 / 154963 Summary of the Invention

[0009] Technical issues

[0010] It is preferable to avoid damage to semiconductor devices.

[0011] Technical solution

[0012] In a first aspect of the present invention, a semiconductor device is provided, comprising: an active portion disposed on a semiconductor substrate; a plurality of trench portions having gate conductive portions, wherein the plurality of trench portions in the active portion extend along a predetermined extension direction and are arranged in a predetermined arrangement direction, the aspect ratio of the width of the gate conductive portions in the arrangement direction to the trench length in the extension direction is 1000 or more; a first control pad, which, when viewed from above, protrudes from a predetermined first outer periphery of the semiconductor substrate toward the inside of the semiconductor substrate; and a first well region disposed below the first control pad and configured to cover the first control pad when viewed from above, wherein, when viewed from above, the shortest distance between the first well region and the center position of a trench that is the center of the length in the extension direction of the plurality of trench portions is 1000 μm or more.

[0013] The shortest distance can be over 1500μm.

[0014] The shortest distance can be over 2000μm.

[0015] The conductive part shape ratio of multiple trenches can be 3000 or more and 1×10 6 the following.

[0016] Multiple trench portions may include gate trench portions set to a gate potential. The conductivity aspect ratio of the gate trench portions may be 5000 or higher and 3 × 10⁻⁶. 5 the following.

[0017] The first control pad may include an anode pad, a cathode pad, and a sensing pad.

[0018] The first well region is rectangular when viewed from above, and its three sides are positioned opposite the active part.

[0019] The first well region may have a corner protruding from the first outer periphery. The shortest distance may be the distance between the corner of the first well region and the center of the trench.

[0020] The distance L1a from the central imaginary line to the corner of the first well region is more than 40% of the length from the central imaginary line to the outer periphery of the semiconductor substrate in a direction orthogonal to the central imaginary line, wherein the central imaginary line is orthogonal to the first outer periphery and passes through the center of the first outer periphery.

[0021] The first trap region is configured to be symmetrical with respect to a central imaginary line, which is orthogonal to the first outer perimeter and passes through the center of the first outer perimeter.

[0022] The first trap region is configured to be asymmetrical with respect to the central imaginary line, which is orthogonal to the first outer perimeter and passes through the center of the first outer perimeter.

[0023] The first pit region may have a notch that is partially cut off when viewed from above.

[0024] The semiconductor device may include: a second control pad, which, when viewed from above, protrudes inward from a second outer periphery opposite to a first outer periphery toward the inside of a semiconductor substrate; and a second well region, disposed below the second control pad and configured to cover the second control pad when viewed from above. The second well region may have a corner protruding from the second outer periphery. The distance L1a may be longer than the distance L2a in the extending direction from the central imaginary line to the corner of the second well region.

[0025] The second control pad may include a gate pad for setting multiple trench portions to gate potentials.

[0026] The active part can include both a transistor part and a diode part. The corner of the first well region can be located in the transistor part when viewed from above.

[0027] Multiple trench sections can have dummy trench regions set to emitter potentials. The corner of the first well region can be located in a dummy trench region when viewed from above.

[0028] The active part can include both a transistor part and a diode part. When viewed from above, the corner of the first well region can be located in the diode part.

[0029] The semiconductor device may have a protective film disposed on the top of the semiconductor substrate. The diode section may have a lifetime control area on the front side of the semiconductor substrate. When viewed from above, the protective film may be disposed away from the diode section.

[0030] When viewed from above, the direction of extension can be parallel to the first outer perimeter.

[0031] When viewed from above, the direction of extension can be orthogonal to the first outer perimeter.

[0032] It should be noted that the above description of the invention does not list all the essential features of the invention. Furthermore, sub-combinations of these feature groups can also constitute an invention. Attached Figure Description

[0033] Figure 1A An example of a top view of a semiconductor device 100 according to an embodiment.

[0034] Figure 1B An enlarged view of the upper surface of the semiconductor device 100.

[0035] Figure 1C It means Figure 1B A diagram of an example of the a-a' section.

[0036] Figure 1D This is a diagram illustrating the layout of the upper surface of the semiconductor device 100.

[0037] Figure 2A An enlarged view of the upper surface of the semiconductor device 100.

[0038] Figure 2B An enlarged view of the upper surface of the semiconductor device 100.

[0039] Figure 2C An enlarged view of the upper surface of the semiconductor device 100.

[0040] Figure 2D This illustrates an example of the configuration of a semiconductor device 100 having a notch 118.

[0041] Figure 2E This illustrates an example of the configuration of a semiconductor device 100 having a notch 118.

[0042] Figure 3 This is an example of a top view of a semiconductor device 100 with a protective film 180.

[0043] Figure 4A This is an example of a top view of the semiconductor device 100 in the embodiment.

[0044] Figure 4BThis is an example of a top view of the semiconductor device 100 in the embodiment.

[0045] Figure 5 This is a schematic diagram of the electric field strength E(R) when an avalanche breakdown occurs near corner 111 in the off state.

[0046] Figure 6A This is a graph showing the dependence of the shortest distance R on the electric field strength near corner 111.

[0047] Figure 6B This is a graph showing the relationship between the shortest distance R1a and the failure rate (%) of the cutoff tolerance.

[0048] Figure 6C This indicates the rated voltage V. rate With rated current density J rate A diagram showing the relationships between them.

[0049] Symbol Explanation

[0050] 10…Semiconductor substrate, 12…Emitter region, 14…Base region, 15…Contact region, 16…Accumulation region, 18…Drift region, 20…Buffer zone, 21…Front side, 22…Collector region, 23…Back side, 24…Collector, 25…Connection portion, 30…Dummy trench portion, 31…Extension portion, 32…Dummy insulating film, 33…Connection portion, 34…Dummy conductive portion, 38…Interlayer insulating film, 40…Gate trench portion, 41…Extension portion, 42…Gate insulating film, 43…Connection portion, 44…Gate conductive portion, 50…Gate metal layer, 52…Emitter, 54…Contact hole, 55…Contact hole, 56…Contact hole, 70…Transistor portion, 71…Mesa portion, 80…Diode portion, 81…Mesa portion, 82…Cathode 90…Boundary, 91…Square surface, 92…Boundary, 100…Semiconductor device, 102…Active part, 104…Outer periphery, 110…First control pad, 111…Corner, 112…Anode pad, 114…Cathode pad, 115…Well region, 116…Sensing pad, 118…Notch, 120…Second control pad, 121…Corner, 122…Gate pad, 125…Well region, 130…Lifetime control region, 135…Well region, 140…Temperature sensing part, 142…Temperature sensing wiring, 145…Well region, 150…Outer periphery, 151…First outer periphery, 152…Second outer periphery, 170…Invalid region, 172…Dummy trench region, 180…Protective film, 185…Unprotected area Detailed Implementation

[0051] The present invention will now be described through embodiments thereof, but these embodiments do not limit the invention as defined in the claims. Furthermore, not all combinations of the features described in the embodiments are necessarily required for the solution of the invention.

[0052] In this specification, one side parallel to the depth direction of the semiconductor substrate is referred to as "upper," and the other side as "lower." One of the two main surfaces of the substrate, layer, or other component is referred to as the upper surface, and the other as the lower surface. The directions of "upper" and "lower" are not limited to the direction of gravity or the direction when mounting the semiconductor device.

[0053] In this specification, orthogonal coordinate axes of X, Y, and Z are sometimes used to illustrate technical matters. Orthogonal coordinate axes merely determine the relative positions of constituent elements and do not limit specific directions. For example, the Z-axis does not necessarily represent the height direction relative to the ground. It should be noted that the +Z-axis direction and the -Z-axis direction are mutually opposite directions. When the Z-axis direction is not specified as positive or negative, it refers to a direction parallel to the +Z-axis and -Z-axis.

[0054] In this specification, orthogonal axes parallel to the upper and lower surfaces of the semiconductor substrate are designated as the X-axis and Y-axis. An axis perpendicular to the upper and lower surfaces of the semiconductor substrate is designated as the Z-axis. In this specification, the direction of the Z-axis is sometimes referred to as the depth direction. Additionally, in this specification, including the X-axis and Y-axis, the direction parallel to the upper and lower surfaces of the semiconductor substrate is sometimes referred to as the horizontal direction.

[0055] In this specification, the terms "same" or "equal" may also include cases with errors caused by manufacturing deviations, etc. Such errors are, for example, within 10%.

[0056] In this specification, the conductivity type of a doped region containing impurities is described as P-type or N-type. In this specification, impurities sometimes specifically refer to either an N-type donor or a P-type acceptor, and are sometimes referred to as dopant. In this specification, doping refers to introducing donors or acceptors into a semiconductor substrate to create a semiconductor exhibiting N-type conductivity or a semiconductor exhibiting P-type conductivity.

[0057] In this specification, doping concentration refers to the concentration of donors or acceptors under thermal equilibrium conditions. In this specification, net doping concentration refers to the concentration obtained by adding the donor concentration (as positive ions) and the acceptor concentration (as negative ions), taking into account charge polarity. For example, if the donor concentration is set to N... D Set the acceptor concentration to N A Then the net doping concentration at any position is N. D -N AIn this specification, net doping concentration is sometimes referred to simply as doping concentration.

[0058] Donors have the function of supplying electrons to semiconductors. Acceptors have the function of receiving electrons from semiconductors. Donors and acceptors are not limited to impurities themselves. For example, VOH defects, formed by the bonding of vacancies (V), oxygen (O), and hydrogen (H) in semiconductors, function as electron-supplying donors. In this specification, VOH defects are sometimes referred to as hydrogen donors.

[0059] In this specification, when referred to as P+ or N+ type, it means a higher doping concentration than P- or N- type; when referred to as P- or N- type, it means a lower doping concentration than P- or N- type. Similarly, when referred to as P++ or N++ type, it means a higher doping concentration than P+ or N+ type. Unless otherwise stated, the units used herein are SI units. Sometimes cm or μm are used to express length, but all calculations can be performed after conversion to meters (m).

[0060] Figure 1A This is an example of a top view of a semiconductor device 100 according to an embodiment. The semiconductor device 100 is a semiconductor chip including a transistor section 70 and a diode section 80. The semiconductor device 100 can be mounted in a module such as an IPM (Intelligent Power Module).

[0061] The transistor section 70 is the region in the semiconductor device 100 where transistor operation is performed. The transistor section 70 includes transistors such as IGBTs (Insulated Gate Bipolar Transistors). The diode section 80 is the region in the semiconductor device 100 where diode operation, such as allowing current to flow back through the circuit, is performed. The diode section 80 includes diodes such as freewheeling diodes (FWDs). In this example, the semiconductor device 100 is a reverse-conducting IGBT (RC-IGBT) with both the transistor section 70 and the diode section 80 on the same chip. It should be noted that in the various figures, the symbol I is sometimes used to denote the region of the transistor section 70, and the symbol F is used to denote the region of the diode section 80.

[0062] The semiconductor substrate 10 can be a silicon substrate, a silicon carbide substrate, or a gallium nitride semiconductor substrate, etc. In this example, the semiconductor substrate 10 is a silicon substrate. The semiconductor substrate 10 has an active portion 102 and an outer peripheral portion 104. In this specification, the outer peripheral end of the semiconductor substrate 10 when viewed from above is defined as the outer peripheral end 150. Viewing from above refers to the view from the side of the front surface of the semiconductor substrate 10 in a direction perpendicular to the front surface (Z-axis direction).

[0063] Transistor portions 70 and diode portions 80 can be arranged alternately and periodically in the XY plane. A gate metal layer 50 can be provided above the semiconductor substrate 10 in the region between the transistor portions 70 and diode portions 80. It should be noted that in this example, the transistor portions 70 and diode portions 80 have trench portions extending along the Y-axis direction and arranged along the X-axis direction. However, the transistor portions 70 and diode portions 80 may also have trench portions extending along the X-axis direction and arranged along the Y-axis direction. It should be noted that boundary portions 90 and 92 (described later) can be provided in the region adjacent to the transistor portions 70 or diode portions 80. Boundary portion 92 can be the region in the active portion 102 located between the diode portion 80 and the gate metal layer 50 when viewed from above. In this example, boundary portion 92 is provided in the region between the diode portion 80 and the gate metal layer 50 in the Y-axis direction and between the transistor portions 70 in the X-axis direction. A collector region 22 (described later) can be provided on the back side of the semiconductor substrate 10 in boundary portion 92.

[0064] The active section 102 includes a transistor section 70 and a diode section 80. The active section 102 is the region where the main current flows between the front and back sides of the semiconductor substrate 10 when the semiconductor device 100 is controlled to be in a conducting state. That is, it is the region where current flows from the front to the back side of the semiconductor substrate 10 along the depth direction within the semiconductor substrate 10, or from the back side to the front side along the depth direction within the semiconductor substrate 10. In this specification, the transistor section 70 and the diode section 80 are referred to as a component section or component area, respectively.

[0065] It should be noted that, when viewed from above, the area sandwiched between the two component sections is also designated as the active section 102. In this example, the area sandwiched between the component sections and on which the gate metal layer 50 is disposed is also included in the active section 102.

[0066] The gate metal layer 50 is formed of a metal-containing material. For example, the gate metal layer 50 is formed of aluminum, an aluminum-silicon alloy, or an aluminum-silicon-copper alloy. The gate metal layer 50 is electrically connected to the gate conductive portion of the transistor portion 70 and supplies a gate voltage to the transistor portion 70. The gate metal layer 50 is disposed such that it surrounds the outer periphery of the active portion 102 when viewed from above. The gate metal layer 50 is electrically connected to the gate pad 122 disposed on the outer peripheral portion 104. The gate metal layer 50 may be disposed along the outer peripheral end 150 of the semiconductor substrate 10. In addition, the gate metal layer 50 may be disposed around the temperature sensing portion 140 and between the transistor portion 70 and the diode portion 80 when viewed from above. In this example, the gate metal layer 50 is shown in bold.

[0067] The outer peripheral portion 104 is the region between the active portion 102 and the outer peripheral end 150 of the semiconductor substrate 10 when viewed from above. When viewed from above, the outer peripheral portion 104 can be configured to surround the active portion 102. One or more metal pads for connecting the semiconductor device 100 to an external device via wires or the like can be disposed in the outer peripheral portion 104. It should be noted that the outer peripheral portion 104 may have an edge termination structure. The edge termination structure mitigates the electric field concentration on the front side of the semiconductor substrate 10. For example, the edge termination structure may have a protective ring, a field plate, a surface electric field reduction region, and a structure combining these.

[0068] A front electrode is disposed above the semiconductor substrate 10. The front electrode includes the emitter 52, which will be described later. The front electrode may include a first control pad 110 and a second control pad 120. The front electrode can be connected to external electrodes of the semiconductor device 100 via wire bonding or the like. It should be noted that the number and location of the front electrodes are not limited to this example.

[0069] When viewed from above, the first control pad 110 protrudes inward from a predetermined first outer periphery 151 of the semiconductor substrate 10. The first control pad 110 protruding inward from the first outer periphery 151 means that the outer periphery 104 extends inward towards the active portion 102. In other words, the active portion 102 is provided on either the positive or negative side of the first control pad 110 in the Y-axis direction. In this example, the first control pad 110 includes an anode pad 112, a cathode pad 114, and a sensing pad 116.

[0070] The second control pad 120, when viewed from above, protrudes inward from the second outer periphery 152 toward the semiconductor substrate 10. The second outer periphery 152 is the edge of the outer peripheral end 150 opposite to the first outer periphery 151. It should be noted that, in this example, the first outer periphery 151 and the second outer periphery 152, when viewed from above, are parallel to the extension direction of the trench portion (the Y-axis direction in this example). The second control pad 120 in this example includes a gate pad 122.

[0071] The well region 115 is disposed below the first control pad 110 and covers the first control pad 110 when viewed from above. In this example, the well region 115 is rectangular when viewed from above, and its three sides are disposed opposite to the active portion 102. The well region 115 has corner portions 111 that protrude from the first outer periphery 151.

[0072] The well region 125 is disposed below the second control pad 120 and covers the second control pad 120 when viewed from above. In this example, the well region 125 is rectangular when viewed from above, and its three sides are disposed opposite to the active portion 102. The well region 125 has corner portions 121 that protrude from the second outer periphery 152.

[0073] When viewed from above, well region 135 is positioned to cover the gate metal layer 50. In this example, well region 135 is positioned to cover the gate metal layer 50 along the outer periphery 104. Well region 135 may be connected to well region 115.

[0074] When viewed from above, well region 145 is configured to cover the gate metal layer 50. In this example, well region 145 may further cover the temperature sensing section 140 and the temperature sensing wiring 142. Well region 145 may be connected to well region 115 and well region 125.

[0075] Well regions 115, 125, 135, and 145 are regions of a second conductivity type disposed on the front side of the semiconductor substrate 10. For example, well regions 115, 125, 135, and 145 are P+ type. By providing well regions 115, 125, 135, and 145, holes within the semiconductor substrate 10 are easily extracted, making latch-up less likely. This improves the durability of the semiconductor device 100.

[0076] The gate pad 122 is electrically connected to the gate metal layer 50. The gate pad 122 is electrically connected to the gate conductive portion of the transistor section 70 via the gate metal layer 50. The gate pad 122 is set to a gate potential. In this example, the gate pad 122 is rectangular when viewed from above. In one example, the gate pad 122 may have one side with a diameter of 1000 μm or more and 1500 μm or less, but is not limited to this.

[0077] The anode pad 112 is electrically connected to the anode region of the temperature sensing unit 140. The anode pad 112 is electrically connected to the anode region of the temperature sensing unit 140 via the temperature sensing wiring 142. In this example, the anode pad 112 is rectangular when viewed from above. In one example, the anode pad 112 may have a short side of 500 μm or more and 900 μm or less, and a long side of 1000 μm or more and 1500 μm or less, but is not limited to this.

[0078] The cathode pad 114 is electrically connected to the cathode region of the temperature sensing unit 140. The cathode pad 114 is electrically connected to the cathode region of the temperature sensing unit 140 via temperature sensing wiring 142. In this example, the cathode pad 114 is rectangular when viewed from above. The cathode pad 114 can also have the same shape as the anode pad 112 when viewed from above.

[0079] A temperature sensing unit 140 is disposed above the active part 102 to detect the temperature of the semiconductor substrate 10. In this example, the temperature sensing unit 140 detects the temperature of the active part 102. The temperature sensing unit 140 may have a diode formed of a semiconductor material such as polysilicon. The temperature sensing unit 140 is used to detect the temperature of the semiconductor device 100 and protect the semiconductor chip from overheating. The temperature sensing unit 140 has a long side in the X-axis direction and a short side in the Y-axis direction, but is not limited thereto.

[0080] In this example, the temperature sensing unit 140 is positioned near the center of the active unit 102 when viewed from above. The temperature sensing unit 140 can be positioned in either the transistor unit 70 or the diode unit 80. That is, a collector region of a second conductivity type or a cathode region of a first conductivity type can be provided on the back side of the semiconductor substrate 10 where the temperature sensing unit 140 is provided.

[0081] Temperature sensing wiring 142 electrically connects the anode pad 112 and the cathode pad 114 to the temperature sensing unit 140. Temperature sensing wiring 142 is provided above the active unit 102, extending from the temperature sensing unit 140 to the outer periphery 104. Temperature sensing wiring 142 can be made of the same material as the front electrode. In a top view, the area of ​​the semiconductor substrate 10 overlapping the temperature sensing unit 140 and temperature sensing wiring 142 can be configured with a P+ type well region.

[0082] Figure 1B This is an enlarged view of the upper surface of the semiconductor device 100. In this example, Figure 1B express Figure 1A A magnified view of region A.

[0083] The transistor section 70 can be a region obtained by projecting a collector region 22 disposed on the back side of the semiconductor substrate 10 onto the front side of the semiconductor substrate 10. The collector region 22 has a second conductivity type. As an example, the collector region 22 in this example is P+ type. The transistor section 70 includes a boundary section 90 located at the boundary between the transistor section 70 and the diode section 80.

[0084] The diode section 80 can be a region obtained by projecting the cathode region 82 disposed on the back side of the semiconductor substrate 10 onto the front side of the semiconductor substrate 10. The cathode region 82 has a first conductivity type. As an example, the cathode region 82 in this example is of the N+ type.

[0085] In this example, the semiconductor device 100 has a gate trench 40, a dummy trench 30, an emitter region 12, a base region 14, a contact region 15, and a well region 145 on the front side of the semiconductor substrate 10. In addition, the semiconductor device 100 in this example has an emitter 52 and a gate metal layer 50 disposed on the upper part of the front side of the semiconductor substrate 10.

[0086] The emitter 52 is disposed above the gate trench portion 40, the dummy trench portion 30, the emitter region 12, the base region 14, the contact region 15, and the well region 145. Additionally, the gate metal layer 50 is disposed above the gate trench portion 40 and the well region 145.

[0087] The emitter 52 and the gate metal layer 50 are formed of a metal-containing material. For example, at least a portion of the emitter 52 may be formed of aluminum, an aluminum-silicon alloy, or an aluminum-silicon-copper alloy. The emitter 52 may have a barrier metal formed of titanium, titanium compounds, or the like in the layer beneath the region formed of aluminum. The emitter 52 and the gate metal layer 50 are disposed separately from each other.

[0088] The emitter 52 and the gate metal layer 50 are disposed above the semiconductor substrate 10, separated by an interlayer insulating film 38. Figure 1A The interlayer insulating film 38 is omitted. Contact holes 54, 55 and 56 are provided through the interlayer insulating film 38.

[0089] Contact hole 55 connects the gate metal layer 50 to the gate conductive portion within the transistor section 70. A plug made of tungsten or the like may also be formed inside contact hole 55. Contact hole 56 connects the emitter 52 to the dummy conductive portion within the dummy trench section 30. A plug made of tungsten or the like may also be formed inside contact hole 56.

[0090] The connection portion 25 electrically connects the front electrode, such as the emitter 52 or the gate metal layer 50, to a conductive portion formed inside the trench portion. In one example, the connection portion 25 is disposed between the gate metal layer 50 and the gate conductive portion. The connection portion 25 is also disposed between the emitter 52 and the dummy conductive portion. The connection portion 25 comprises a conductive material such as polysilicon doped with impurities. In this example, the connection portion 25 is polysilicon (N+) doped with N-type impurities. The connection portion 25 is disposed above the front side of the semiconductor substrate 10 through an insulating film such as an oxide film.

[0091] The gate trench portions 40 are arranged at predetermined intervals along a predetermined arrangement direction (X-axis direction in this example). In this example, the gate trench portions 40 may have two extension portions 41 extending along an extension direction parallel to the front surface of the semiconductor substrate 10 and perpendicular to the arrangement direction (Y-axis direction in this example), and a connection portion 43 connecting the two extension portions 41. The gate trench portions 40 are set to a gate potential.

[0092] The connection portion 43 is preferably at least partially formed in a curved shape. By connecting the ends of the two extension portions 41 of the gate trench portion 40, the electric field concentration at the ends of the extension portions 41 can be mitigated. In the connection portion 43 of the gate trench portion 40, the gate metal layer 50 can be connected to the gate conductive portion.

[0093] The dummy trench portion 30 is a trench portion electrically connected to the emitter 52. The dummy trench portions 30, like the gate trench portions 40, are arranged at predetermined intervals along a predetermined arrangement direction (the X-axis direction in this example). In this example, the dummy trench portions 30 can be U-shaped on the front side of the semiconductor substrate 10, similar to the gate trench portions 40. That is, the dummy trench portion 30 can have two extension portions 31 extending along the extension direction and a connecting portion 33 connecting the two extension portions 31.

[0094] The transistor section 70 in this example has a structure in which two gate trench sections 40 and three dummy trench sections 30 are repeatedly arranged. That is, the transistor section 70 in this example has gate trench sections 40 and dummy trench sections 30 in a 2:3 ratio. For example, the transistor section 70 has an extension section 31 between two extension sections 41. In addition, the transistor section 70 has two extension sections 31 adjacent to the gate trench sections 40.

[0095] However, the ratio of the gate trench portion 40 to the dummy trench portion 30 is not limited to this example. The ratio of the gate trench portion 40 to the dummy trench portion 30 can be 1:1 or 2:4. Alternatively, a so-called full gate trench structure can be used, in which the transistor portion 70 is entirely composed of gate trench portions 40 without any dummy trench portions 30.

[0096] Well region 145 is a second conductivity type region located further on the front side of the semiconductor substrate 10 than drift region 18 described later. Well region 145 is an example of a well region located on the edge side of the semiconductor device 100. As an example, well region 145 is P+ type. Well region 145 is formed within a predetermined range from the end of the active region on the side where the gate metal layer 50 is disposed. The diffusion depth of well region 145 can be deeper than the depth of gate trench portion 40 and dummy trench portion 30. A portion of the gate metal layer 50 side of gate trench portion 40 and dummy trench portion 30 is formed in well region 145. The bottom of the end of the extending direction of gate trench portion 40 and dummy trench portion 30 can be covered by well region 145. Well region 145 can be formed simultaneously with well region 115 and well region 125. The diffusion depths of well region 115, well region 125, well region 135 and well region 145 can be the same or substantially the same. The well region 145 can be configured to cover the gate metal layer 50 when viewed from above. The well region 145 can be electrically connected to the emitter 52 at a position closer to the outer peripheral portion 104 than the transistor portion 70 or the diode portion 80.

[0097] The contact hole 54 is a portion that opens the interlayer insulating film 38, exposing the front surface 21 of the semiconductor substrate 10. The contact hole 54 is formed in the transistor section 70 above each region of the emitter region 12 and the contact region 15. The emitter region 12 or the contact region 15 is electrically connected to the emitter 52 through the contact hole 54.

[0098] In the diode section 80, a contact hole 54 is provided above the base region 14. The base region 14 in the diode section 80 can contact the emitter 52 via the contact hole 54. On the front side 21 where the contact hole 54 is formed, a high-concentration layer with the same conductivity as the base region 14 can be provided between the base region 14 and the emitter 52 to reduce contact resistance.

[0099] At the boundary portion 90, a contact hole 54 is provided above the contact area 15. The contact hole 54 may not be provided above the well area 145, which is located at both ends in the Y-axis direction. Thus, one or more contact holes 54 are formed in the interlayer insulating film 38. The one or more contact holes 54 may be provided extending along the extension direction.

[0100] The boundary portion 90 is a region disposed in the transistor portion 70 and adjacent to the diode portion 80. The boundary portion 90 may have a contact area 15. In this example, the boundary portion 90 does not have an emitter area 12. In one example, the trench portion of the boundary portion 90 is a dummy trench portion 30. In this example, the boundary portion 90 is configured such that both ends in the X-axis direction are dummy trench portions 30.

[0101] Mesa-faces 71, 91, and 81 are mesa-faces provided adjacent to the trench portions in a plane parallel to the front surface of the semiconductor substrate 10. A mesa-face refers to the portion of the semiconductor substrate 10 sandwiched between two adjacent trench portions, and can be the portion extending from the front surface of the semiconductor substrate 10 to the deepest bottom of each trench portion. An extension portion of each trench portion can be defined as a single trench portion. In other words, the area sandwiched between two extension portions can be considered a mesa-face.

[0102] The mesa portion 71 is disposed adjacent to at least one of the dummy trench portion 30 or the gate trench portion 40 in the transistor portion 70. The mesa portion 71 may have an emitter region 12, a base region 14, a contact region 15, and a well region 145 on the front side of the semiconductor substrate 10. In the mesa portion 71, the emitter region 12 and the contact region 15 may be alternately disposed in the extending direction.

[0103] A mesa 91 is provided at the boundary 90. The mesa 91 may have a contact area 15 or a well area 145 on the front side of the semiconductor substrate 10.

[0104] The mesa 81 is disposed in the diode portion 80 in a region held by the adjacent dummy trench portion 30. The mesa 81 may have a base region 14, a contact region 15, or a well region 145 on the front side of the semiconductor substrate 10.

[0105] The base region 14 is a region of a second conductivity type disposed on the front side of the semiconductor substrate 10 in the transistor section 70 and the diode section 80. As an example, the base region 14 is P-type. The base region 14 can be disposed at both ends of the mesa 71 and mesa 91 in the Y-axis direction on the front side of the semiconductor substrate 10. It should be noted that... Figure 1A This only indicates one end of the base region 14 along the Y-axis. The doping concentration of the base region 14 can be lower than that of the well region 145.

[0106] Emitter region 12 is a region of the first conductivity type with a doping concentration higher than that of drift region 18. As an example, emitter region 12 in this example is N+ type. An example of the dopant for emitter region 12 is arsenic (As). Emitter region 12 is provided on the front side of mesa 71 in contact with gate trench portion 40. Emitter region 12 can be provided in the X-axis direction extending from one of the two trench portions holding mesa 71 to the other. Emitter region 12 is also provided below contact hole 54.

[0107] Furthermore, the emission area 12 may or may not contact the dummy groove portion 30. In this example, the emission area 12 contacts the dummy groove portion 30. The emission area 12 may not be provided on the platform surface 91 of the boundary portion 90.

[0108] Contact region 15 is a region of the second conductivity type with a higher doping concentration than the base region 14. As an example, contact region 15 in this example is P+ type. The thickness of contact region 15 in the depth direction is less than the thickness of the base region 14 in the depth direction. In this example, contact region 15 is disposed on the front side of mesa 71 and mesa 91. Contact region 15 can be disposed from one of the two trench portions clamping mesa 71 or mesa 91 to the other in the X-axis direction. Contact region 15 may or may not contact the gate trench portion 40. Additionally, contact region 15 may or may not contact the dummy trench portion 30. In this example, contact region 15 contacts both the dummy trench portion 30 and the gate trench portion 40. Contact region 15 is also disposed below contact hole 54. It should be noted that contact region 15 may also be disposed on mesa 81.

[0109] The trench length Lt is the length of the multiple trench portions along their extension direction. In this example, the trench length Lt corresponds to the distance between the gate metal layer 50 disposed on the positive side of the trench portion in the Y-axis direction and the gate metal layer 50 disposed on the negative side of the trench portion in the Y-axis direction. The trench length Lt can be 2000 μm or more, 3000 μm or more, 4000 μm or more, 4600 μm or more, or 6000 μm or more. Alternatively, the trench length Lt can be 50000 μm or less, 30000 μm or less, or 20000 μm or less.

[0110] Figure 1C It means Figure 1B The figure shows an example of the a-a' cross-section. The a-a' cross-section is the XZ plane passing through the emitter region 12 in the transistor section 70. In this example, the semiconductor device 100 has a semiconductor substrate 10, an interlayer insulating film 38, an emitter 52, and a collector 24 in the a-a' cross-section. The emitter 52 is formed above the semiconductor substrate 10 and the interlayer insulating film 38.

[0111] Drift region 18 is a region of the first conductivity type disposed in the semiconductor substrate 10. As an example, drift region 18 in this example is N-type. Drift region 18 can be a region remaining in the semiconductor substrate 10 where no other doped regions have been formed. That is, the doping concentration of drift region 18 can be the doping concentration of the semiconductor substrate 10.

[0112] Buffer 20 is a region of the first conductivity type disposed below drift region 18. As an example, buffer 20 in this example is N-type. The doping concentration of buffer 20 is higher than that of drift region 18. Buffer 20 can function as a field cutoff layer to prevent the depletion layer extending from the back side of base region 14 from reaching the collector region 22 of the second conductivity type and the cathode region 82 of the first conductivity type.

[0113] The collector region 22 is disposed below the buffer zone 20 in the transistor section 70. The cathode region 82 is disposed below the buffer zone 20 in the diode section 80. The boundary between the collector region 22 and the cathode region 82 can serve as the boundary between the transistor section 70 and the diode section 80.

[0114] Collector 24 is formed on the back side 23 of semiconductor substrate 10. Collector 24 is formed of conductive material such as metal.

[0115] The base region 14 is a second conductivity type region disposed above the drift region 18 in the mesa 71, mesa 91, and mesa 81. The base region 14 may be disposed in contact with the gate trench portion 40. The base region 14 may also be disposed in contact with the dummy trench portion 30.

[0116] The emitter region 12 is disposed in the mesa 71 between the base region 14 and the front surface 21. The emitter region 12 may be disposed in contact with the gate trench portion 40. The emitter region 12 may or may not be in contact with the dummy trench portion 30. It should be noted that the emitter region 12 may not be disposed in the mesa 91.

[0117] The contact area 15 is disposed above the base region 14 in the mesa 71. The contact area 15 is disposed in contact with the gate trench portion 40 in the mesa 91. In other cross-sections, the contact area 15 may be disposed on the front surface 21 of the mesa 71.

[0118] The accumulation region 16 is a first conductivity type region located further on the front side 21 of the semiconductor substrate 10 than the drift region 18. As an example, the accumulation region 16 in this example is N+ type. The donor concentration of the accumulation region 16 is greater than that of the drift region 18. The accumulation region 16 is provided in both the transistor section 70 and the diode section 80. In this example, the accumulation region 16 is also provided in the boundary section 90. Therefore, the semiconductor device 100 can avoid mask deviation of the accumulation region 16.

[0119] Furthermore, the accumulation region 16 is provided in contact with the gate trench portion 40. The accumulation region 16 may or may not be provided in contact with the dummy trench portion 30. The doping concentration of the accumulation region 16 is higher than that of the drift region 18. By providing the accumulation region 16, the carrier injection promotion effect (IE effect) can be improved, and the turn-on voltage of the transistor portion 70 can be reduced.

[0120] One or more gate trenches 40 and one or more dummy trenches 30 are disposed on the front side 21. Each trench extends from the front side 21 to the drift region 18. In the region where at least one of the emitter region 12, base region 14, contact region 15, and accumulation region 16 is disposed, each trench also extends through these regions to reach the drift region 18. The trench extending through the doped region is not limited to being manufactured in the order of forming the doped region and then forming the trench. The case where the doped region is formed between the trenches after the trench is formed is also included in the case where the trench extends through the doped region.

[0121] The gate trench portion 40 has a gate trench formed on the front side 21, a gate insulating film 42, and a gate conductive portion 44. The gate insulating film 42 is formed by covering the inner wall of the gate trench. The gate insulating film 42 can be formed by oxidizing or nitriding the semiconductor on the inner wall of the gate trench. The gate conductive portion 44 is formed inside the gate trench at a position closer to the inner side of the gate insulating film 42. The gate insulating film 42 insulates the gate conductive portion 44 from the semiconductor substrate 10. The gate conductive portion 44 is formed of a conductive material such as polysilicon. The gate trench portion 40 is covered on the front side 21 by an interlayer insulating film 38.

[0122] The gate conductive portion 44 includes a region in the depth direction of the semiconductor substrate 10 that is opposed to the base region 14 adjacent to the mesa 71 side, separated by the gate insulating film 42. If a predetermined voltage is applied to the gate conductive portion 44, a channel formed by an electron inversion layer is formed on the surface layer of the interface in the base region 14 that contacts the gate trench.

[0123] The width of the gate trench 40 can be greater than 0.5 μm or less than 2.0 μm. In this example, the width of the gate trench 40 is 1.0 μm. The thickness of the gate insulating film 42 can be greater than 0.05 μm or less than 0.2 μm. In this example, the thickness of the gate insulating film 42 is 0.1 μm.

[0124] The width Wg of the gate conductive portion 44 is simply the width of the gate trench portion 40 minus the thickness of the gate insulating film 42 (that is, the thickness of two layers of the gate insulating film 42). The width of the gate trench portion 40 can be constant in the depth direction, or it can increase or decrease. The width Wg of the gate conductive portion 44 can be set to the width of the gate conductive portion 44 at the same depth as the depth where the doping concentration reaches its peak in the base region 14. Alternatively, the width Wg of the gate conductive portion 44 can be set to the width of the gate conductive portion 44 at the depth of the contact between the base region 14 and the emitter region 12, i.e., the pn junction depth.

[0125] The dummy trench portion 30 may have the same structure as the gate trench portion 40. The dummy trench portion 30 has a dummy trench formed on the front side 21, a dummy insulating film 32, and a dummy conductive portion 34. The dummy insulating film 32 is formed by covering the inner wall of the dummy trench. The dummy conductive portion 34 is formed inside the dummy trench and is located further inside the dummy insulating film 32. The dummy insulating film 32 insulates the dummy conductive portion 34 from the semiconductor substrate 10. The dummy trench portion 30 is covered on the front side 21 by an interlayer insulating film 38.

[0126] An interlayer insulating film 38 is disposed on the front side 21. An emitter 52 is disposed above the interlayer insulating film 38. One or more contact holes 54 are provided on the interlayer insulating film 38 for electrically connecting the emitter 52 to the semiconductor substrate 10. Contact holes 55 and 56 can also be provided in a manner that penetrates through the interlayer insulating film 38.

[0127] The lifetime control region 130 can be provided on the front side 21 of the semiconductor substrate 10 in the diode section 80. The front side 21 of the semiconductor substrate 10 can refer to the region that is closer to the front side 21 than the center in the depth direction of the semiconductor substrate 10. In addition, when lifetime control regions are provided at different depth positions of the semiconductor substrate 10, the lifetime control region closest to the front side 21 can be designated as the lifetime control region 130.

[0128] The lifetime control region 130 can be a region intentionally introduced with lifetime inhibitors by injecting impurities or the like into the interior of the semiconductor substrate 10. The lifetime of electron or hole carriers in a region where lifetime inhibitors have been intentionally introduced is shorter than the lifetime of carriers in a region where lifetime inhibitors have not been intentionally introduced. Lifetime inhibitors are carrier recombination centers, which can be lattice defects, vacancies, multiple vacancies, dangling bonds formed by vacancies, or recombination defects or dislocations between these and elements constituting the semiconductor substrate 10. Furthermore, lifetime inhibitors can be rare gases such as helium or neon, or elements such as hydrogen, or transition metals such as platinum or gold.

[0129] By providing a lifetime control region 130 in the diode section 80, the carrier lifetime in the diode section 80 can be adjusted, reducing losses during reverse recovery. It should be noted that the lifetime control region 130 can also be formed by electron beam irradiation. Under electron beam irradiation, due to the strong transmission force, the lifetime inhibitor becomes approximately uniformly distributed from the front side 21 to the back side 23 when irradiated from the front side 21 of the semiconductor substrate 10 and when irradiated from the back side 23. However, if any location on the front side 21 is considered as the lifetime control region 130, the same discussion applies as with other lifetime inhibitors.

[0130] In this example, a lifetime control region 130 is also provided at the boundary 90. Therefore, during reverse recovery of the diode section 80, the flow of holes from the base region 14 of the transistor section 70 to the cathode region 82 of the diode section 80 can be suppressed, thereby reducing reverse recovery losses. It should be noted that the lifetime control region 130 may also terminate midway through the boundary 90, rather than being provided throughout the entire boundary 90.

[0131] Figure 1D This is a diagram illustrating the layout of the upper surface of the semiconductor device 100. Figure 1D In order to illustrate the structure of the semiconductor device 100, a portion of its structure has been omitted.

[0132] The central imaginary line VL is orthogonal to the first outer periphery 151 and passes through the center of the first outer periphery 151. In this example, the central imaginary line VL is an imaginary line that passes through the center of the semiconductor substrate 10 in the Y-axis direction and extends in the X-axis direction. Distance Ha is the length of the semiconductor substrate 10 in the direction orthogonal to the central imaginary line VL, corresponding to the lengths of the first outer periphery 151 and the second outer periphery 152. Distance Hb is the length of the semiconductor substrate 10 in the direction parallel to the central imaginary line VL. In this example, distance Hb is longer than distance Ha, but it can be the same as or shorter than distance Ha. Distance Hc is the distance from the central imaginary line VL to the outer periphery 150 of the semiconductor substrate 10 in the direction orthogonal to the central imaginary line VL. That is, distance Hc is half the length of distance Ha.

[0133] The trap region 115 includes two corners, corner 111a and corner 111b. Corner 111a and corner 111b are located in regions opposite to each other, separated by a central imaginary line VL. The corner farther from the central imaginary line VL is designated as corner 111a, and the corner closer to the central imaginary line VL is designated as corner 111b.

[0134] Distance L1a is the distance extending from the central imaginary line VL to the corner 111a. In this example, distance L1a is the distance in the asymmetrically arranged well region 115 to the corner 111a on the side furthest from the central imaginary line VL. Distance L1b is the distance extending from the central imaginary line VL to the corner 111b. Distance L1a may be the same as or different from distance L1b. In this example, distance L1a is greater than distance L1b. That is, in this example, the well region 115 is asymmetrically arranged relative to the central imaginary line VL. Distance L1a can be more than 30% or 40% of distance Hc. Distance L1a can be less than 90% or 80% of distance Hc.

[0135] The trap region 125 includes two corner portions: corner portion 121a and corner portion 121b. In the extending direction, the corner portion on the side where corner portion 121a is located is designated as corner portion 121a, and the corner portion on the side where corner portion 121b is located is designated as corner portion 121b. That is, corner portion 121b is located on the opposite side to corner portion 121a, separated by a central imaginary line VL. It should be noted that in... Figure 1D Although corners 111a, 111b, 121a, and 121b are described as right angles, the front ends of the corners can be curved. Alternatively, the front angles of the corners can be removed, making them polygonal. This suppresses the increase in electric field intensity at the corners. The same applies to the other corners of the well region 125. The same applies to corner 111 in this example.

[0136] Distance L2a is the distance extending from the central imaginary line VL to the corner 121a. Distance L2b is the distance extending from the central imaginary line VL to the corner 121b. In this example, distances L2a and L2b are equal. That is, the trap region 125 is set symmetrically with respect to the central imaginary line VL. Distance L1a can be longer or shorter than distance L2a.

[0137] The shortest distance R1a is the shortest distance between the trap region 115 and the center position TP of the trench when viewed from above. The center position TP is the central position of the trench length Lt of the multiple trench sections. The shortest distance R1a can also be the shortest distance between the corner 111a and the center position TP. If the distance L1a increases, the shortest distance R1a becomes shorter, and the corner 111a becomes closer to the center position TP. The shortest distance R1a can be greater than 1000 μm, greater than 1500 μm, or greater than 2000 μm.

[0138] Increasing the trench length Lt makes it easier for filament current to be generated near the center position TP of the trench due to gate delay. On the other hand, the longer the trench length Lt, the larger the operating area can be, and the better the control of large currents can be achieved. Therefore, by setting the minimum distance R1a within an appropriate range, component damage can be avoided even if the trench length Lt is relatively long.

[0139] Also considering the width Wg of the gate conductive portion, the ratio obtained by dividing the trench length Lt by the width Wg is set as the conductive portion shape ratio α. A larger conductive portion shape ratio α results in a larger operating area and better suppression of large currents. The conductive portion shape ratio α can be 1000 or higher, 3000 or higher, 5000 or higher, or even 6000 or higher. The conductive portion shape ratio α can be 1×10⁻⁶. 6 The following can be 3×10 5 The following can also be 1×10 5 The value can also be 50,000 or less. If the conductivity shape ratio α is within these ranges, the trench length Lt can be within or outside the range described above. The mesa width in the alignment direction can be less than the width of the gate trench portion 40 in the alignment direction. It should be noted that the conductivity shape ratio α can be determined by comprehensively considering the delay time caused by the charging and discharging of the gate, in addition to the current characteristics. In the semiconductor device 100 of this example, by appropriately setting the minimum distance R1a, even a long trench length Lt can prevent device damage, so a wider range of conductivity shape ratios α can be used. It should be noted that the value of the conductivity shape ratio α can also be used in combination with any of the values ​​of the minimum distances R1a, R1b, R2a, and R2b disclosed in this example.

[0140] The shortest distance R1b is the shortest distance between the well region 115 and the center position TP of the trench of the active part 102 adjacent to the well region 115 in the extension direction. In this example, the shortest distance R1b is longer than the shortest distance R1a. The shortest distance R1b can be 1000 μm or more, 1500 μm or more, or 2000 μm or more.

[0141] The shortest distance R2a is the shortest distance between the well region 125 and the center position TP of the trench of the active part 102 adjacent to the well region 125 in the extending direction when viewed from above. The shortest distance R2a can also be the shortest distance between the corner part 121a and the center position TP of the trench. The shortest distance R2a can be 1000 μm or more, 1500 μm or more, or 2000 μm or more.

[0142] The shortest distance R2b is the shortest distance between the well region 125 and the center position TP of the trench of the active part 102 adjacent to the well region 125 in the extension direction. In this example, the shortest distance R2b is longer than the shortest distance R2a. The shortest distance R2b can be 1000 μm or more, 1500 μm or more, or 2000 μm or more.

[0143] If current concentration occurs near the P-type well region, current may flow into the well region, damaging the device. If an imbalance in the gate signal occurs during turn-off, current concentrates in the center of the trench, generating filament current. If this filament current flows into the P-type well region with its strong electric field, the electric field may be applied to the oxide film, causing insulation breakdown, a short circuit between the collector and emitter, and device damage.

[0144] In this example, the semiconductor device 100, by setting the shortest distances R1a and R2a to 1500 μm or more, can suppress the inflow of filament current into the P-type well region. This prevents damage to components near the P-type well region and thus improves cutoff tolerance.

[0145] Figure 2A This is an enlarged view of the upper surface of the semiconductor device 100. In this example, it shows... Figure 1A This is an enlarged view of region B. In this example, corner 111 is located in transistor section 70 when viewed from above. "Located in transistor section 70" can mean that corner 111 is located on the mesa 71 held by gate trench section 40. Gate trench section 40 can be provided above well region 115. In this example, corner 111 is adjacent to base region 14 of transistor section 70. Gate trench section 40 extends to gate metal layer 50. Gate metal layer 50 is provided along the outer periphery of well region 115, but is not limited thereto.

[0146] Figure 2B This is an enlarged view of the upper surface of the semiconductor device 100. In this example, the semiconductor device 100 shows a case where the corner 111 is located in the dummy trench region 172.

[0147] The dummy trench region 172 is a region where multiple trench portions are set to emitter potential. In this example, the dummy trench region 172 includes dummy trench portions 30 set to emitter potential. The dummy trench region 172 in this example has a mesa surface 71 with emitter regions 12 and contact regions 15 alternately arranged. Emitter regions 12 may or may not be provided in the dummy trench region 172. The dummy trench region 172 does not allow current to flow through the gate trench portion 40, therefore no main current flows. Therefore, the concentration of main current at the front surface 21 is minimal in the dummy trench region 172.

[0148] Corner 111 is located in dummy trench region 172 when viewed from above. Corner 111 being located in dummy trench region 172 can mean that the trench portion closest to corner 111 is a dummy trench portion 30. Alternatively, corner 111 being located in dummy trench region 172 can mean that at least one dummy trench portion 30 is provided between corner 111 and gate trench portion 40. In this example, corner 111 is provided adjacent to base region 14 between two adjacent dummy trench portions 30.

[0149] In this example, the semiconductor device 100 is able to suppress current concentration near the corner 111 by covering the vicinity of the corner 111 with a dummy trench region 172.

[0150] Figure 2C This is an enlarged view of the upper surface of the semiconductor device 100. In this example, the semiconductor device 100 has a corner portion 111 located within the diode portion 80. The dummy trench portion 30 extends to the inner side of the well region 115. That is, the negative end of the dummy trench portion 30 in the Y-axis direction is located within the well region 115.

[0151] Corner 111 is located on diode section 80 when viewed from above. In this example, corner 111 is disposed adjacent to base region 14 between two adjacent dummy trench sections 30. In this example, semiconductor device 100 can suppress current concentration near corner 111 by covering the vicinity of corner 111 with diode section 80.

[0152] Figure 2D This illustrates an example of the configuration of a semiconductor device 100 having a notch 118. In this example, the notch 118 is provided in the well region 115. In this example, the corner portion 111 is located in the transistor portion 70 when viewed from above.

[0153] The notch 118 is a region formed by cutting away a portion of the corner of the well region 115 when viewed from above. Although the notch 118 in this example is a rounded shape where the corner of the well region 115 is cut off, the shape of the notch 118 is not limited to this example. When the well region 115 has a notch 118, the outermost protruding position on the arc of the notch 118 can be set as the corner 111. By providing the notch 118, the distance between the well region 115 and the center position TP of the trench can be increased. As a result, it is easier to avoid damage to the semiconductor device 100.

[0154] The notch length N1 is the distance connecting the ends of the regions in the well region 115 where the notch 118 is formed. The notch length N1 can be 10 μm or more, 30 μm or more, 50 μm or more, or 100 μm or more. The notch length N1 can also be 1000 μm or less, 500 μm or less, or 200 μm or less. In one example, the notch length N1 is 100 μm. By increasing the notch length N1, the increase in electric field strength near the corner 111 can be suppressed. This suppresses the enhancement of avalanche breakdown caused by filament current. The radius of curvature of the notch 118 can be 10 μm or more, 20 μm or more, 50 μm or more, or 100 μm or more. The radius of curvature of the notch 118 can also be 1000 μm or less, 500 μm or less, or 200 μm or less.

[0155] Figure 2E This illustrates an example of the configuration of a semiconductor device 100 having a notch 118. In this example, the notch 118 is provided in the well region 115. In this example, the corner portion 111 is located in the diode portion 80 when viewed from above. The shape of the notch 118 can be... Figure 2D The same embodiment applies. Because the notch 118 in this example is located in the diode section 80, it is easy to further increase the distance between the well region 115 and the center position TP of the trench, thus easily avoiding damage to the semiconductor device 100.

[0156] It should be noted that, Figures 2A-2E The structure near the corner 111 of the well region 115 has been described, but the same structure can also be provided for the corner 121 of the well region 125. That is, the corner 121 can be located in the transistor section 70, the dummy trench region 172, or the diode section 80. Furthermore, Figures 2A-2E The corner 111 can be either corner 111a or corner 111b.

[0157] Figure 3 This is an example of a top view of a semiconductor device 100 with a protective film 180. The semiconductor device 100 in this example has an invalid region 170.

[0158] The invalid region 170 is a region that does not function as a transistor section 70. The invalid region 170 can be a dummy trench region 172 or a diode section 80. By providing the invalid region 170 around the corner 111, it is possible to suppress the flow of filament current to the well region 115. In this example, the invalid region 170 is also provided around the corner 121, thereby suppressing the flow of filament current to the well region 125.

[0159] A protective film 180 is disposed above the semiconductor substrate 10. For example, the protective film 180 is an insulating protective film such as polyimide. The protective film 180 prevents solder on the pads from flowing to other pads. When viewed from above, the protective film 180 is disposed in the area where the transistor portion 70 is formed. In other words, the protective film 180 can be disposed away from the ineffective region 170. For example, when viewed from above, the protective film 180 is disposed away from the diode portion 80. In this example, the area where the protective film 180 is disposed is indicated by a shaded line.

[0160] The unprotected area 185 is the area where the protective film 180 is not provided when viewed from above. In the unprotected area 185, front electrodes such as the emitter 52 can be exposed. At least one of a transistor section 70, a diode section 80, or a dummy trench region 172 can be formed in the unprotected area 185. It should be noted that the unprotected area 185 is not shaded.

[0161] Here, the lifetime control region 130 of the diode section 80 is sometimes formed after the protective film 180 is formed. However, if the protective film 180 is provided above the diode section 80, it is sometimes difficult to control the position of the lifetime control region 130 in the depth direction using the protective film 180. In this example, the protective film 180 is provided to avoid the diode section 80, which enables accurate control of the position of the lifetime control region 130 in the depth direction.

[0162] Figure 4A This is an example of a top view of the semiconductor device 100 in this embodiment. The semiconductor device 100 in this example is... Figure 1A The difference between the semiconductor device 100 and the one described above is that the semiconductor device 100 in this example has a well region 115 that is symmetrically arranged with respect to the central imaginary line VL. The well region 115 is symmetrically arranged with respect to the central imaginary line VL in the extending direction. As a result, the shortest distance R1 between the well region 115 and the center position TP of the trench can be increased.

[0163] Figure 4B This is an example of a top view of the semiconductor device 100 in this embodiment. The semiconductor device 100 in this example is... Figure 1A The difference in the embodiment is that the position of the control pad is set in relation to the extension direction of the trench.

[0164] A first control pad 110 is provided protruding inward from a first outer periphery 151 extending along the X-axis direction towards the inside of the semiconductor substrate 10. A second control pad 120 is provided protruding inward from a second outer periphery 152 extending along the X-axis direction towards the inside of the semiconductor substrate 10.

[0165] Multiple trench portions extend along the extension direction (Y-axis direction) when viewed from above. That is, in this example, the extension direction is orthogonal to the first outer periphery 151 when viewed from above. Therefore, the multiple trench portions have an extension direction in the same direction as the protrusion direction (Y-axis direction) of the first control pad 110 and the second control pad 120. In this case, by ensuring that the shortest distance R1a between the corner 111 and the trench center position TP satisfies the same conditions as in other embodiments, current concentration at the corner 111 can also be avoided. Similarly, by ensuring that the shortest distance R2a between the corner 121 and the trench center position TP satisfies the same conditions as in other embodiments, current concentration at the corner 121 can be avoided.

[0166] Figure 5 This is a schematic diagram illustrating the electric field strength E(R) when an avalanche breakdown occurs near corner 111 in the off state. E(R) represents the electric field strength at a distance R from corner 111. R is not limited to... Figure 5 The direction recorded can be any orientation in the top-view plane (the xy plane of the figure). In this example, R represents the distance from corner 111 in the direction of trench extension. At a position sufficiently far from corner 111, regardless of whether it is affected by corner 111 of the well region, the electric field intensity E(R) converges to the maximum electric field intensity Em calculated by the planar junction approximation. If the distance R is close to corner 111, the electric field intensity increases according to Poisson's formula shown in equation (1) due to the influence of corner 111 of the well region 115.

[0167] divE=(q / (ε0ε r ))(p+N D (1)

[0168] Here, q is the elementary charge, ε0 is the permittivity of vacuum, and ε r Where N is the relative permittivity, p is the hole concentration, and N is the relative permittivity. D Donor concentration.

[0169] E is the electric field (vector).

[0170] |E|=E.

[0171] In the off state, the electron and acceptor concentrations within the depletion layer of drift region 18 are sufficiently small to be negligible. That is, near corner 111, the slope (divE) of the electric field intensity E increases due to the curvature of the electric field in the xy plane of the upper surface. Therefore, the electric field intensity E itself also increases. Consequently, E(R) is larger than Em the closer it is to corner 111.

[0172] Based on the above, it is assumed that the electric field strength E(R) follows an exponential function of R. If the peak electric field strength Ep is reached at corner 111, then the electric field strength E(R) is expressed by the following formula.

[0173] E(R)=Ep×exp(-R / ΔR)+Em…Formula (2)

[0174] Ep is the peak electric field intensity at corner 111, and ΔR is the characteristic length of the electric field intensity decay. As an example, Ep can be the critical electric field intensity. In this example, Ep is set to 6E5 (V / cm). As an example, ΔR is approximately 200μm to 400μm. In this example, ΔR is 300μm. However, ΔR is not limited to this range.

[0175] Without distortion of the electric field in the xy plane, E(R) becomes the planar bonding approximation value Em. Em sets the average donor concentration of the drift layer as N. D0 Let the applied voltage be V. According to Poisson's formula, Em is expressed by the following equation.

[0176] Em={2V(q / (ε0ε r (P+N) D0 )} 0.5 …Formula (3)

[0177] Regarding the hole concentration p, for example, assuming the transistor section 70 is turned off, let's assume the rated current J flows. rate The situation regarding the current on the left and right. Because a voltage is applied during turn-off, the velocity of holes within the depletion layer (i.e., the space charge region) can be v. sat Under saturation, the hole concentration p satisfies the following equation (4).

[0178] p = J rate / (qv sat ...Equation (4)

[0179] V sat For example, the number of holes in silicon is 8 × 10. 6 (cm / s). In this example, it is set to N. D0 =5E13 / cm 3 Applied voltage V = 600V, rated current density J rate =500A / cm 2Em is 2.83E5 (V / cm).

[0180] Figure 6A This is a graph showing the dependence of the electric field intensity E(R) at a distance R from corner 111 on the distance R. The vertical axis represents the ratio E(R) / Em, which is normalized to the electric field intensity E(R) (V / cm) and the maximum electric field intensity Em, and the horizontal axis represents the distance R (μm) from corner 111.

[0181] The electrolytic intensity E(R) exhibits a maximum electric field strength of approximately Em within a distance R greater than 1500 μm. Conversely, as the distance R becomes shorter than 1500 μm, the electrolytic intensity E(R) increases sharply. If the distance R is shorter than 1500 μm, the ratio of electric field strength E(R) / Em is greater than 1.1. Avalanche breakdown is a critical phenomenon, and the collisional ionization coefficient is strongly dependent on the electric field strength. Therefore, if the electric field strength ratio E(R) / Em is greater than 1.1, the collisional ionization coefficient is greater than 2, the collisional ionization rate increases, and avalanche breakdown occurs strongly. In the case where the distance R is less than 1000 μm, the electric field strength ratio E(R) / Em is greater than 1.1. That is, it can be considered that avalanche breakdown is more likely to occur in regions with distances shorter than 1000 μm than in regions with distances greater than 1000 μm. Furthermore, at distances R greater than 1500 μm, the electric field strength ratio E(R) / Em is less than 1.01. That is, in regions with distances R greater than 1500 μm, the increase in electric field strength caused by spatial distortion (bending) is sufficiently small. Based on the above, in regions with distances R shorter than 1000 μm, the impact ionization rate of avalanche breakdown becomes higher. In this example, it is highest at corner 111 (R = 0).

[0182] Here, the distance R can be replaced by the shortest distance R1a from the corner 111 to the center position TP of the trench. That is, the shortest distance R1a from the corner 111 to the center position TP of the trench can be 1000μm or more, or it can be 1500μm or more. It should be noted that although the example describes replacing the distance R with the shortest distance R1a, it is also possible to replace the distance R with the shortest distance R1b, the shortest distance R2a, or the shortest distance R2b for the explanation.

[0183] If the gate voltage changes from + to - during turn-off, the potential is transferred from the gate metal layer 50 to the gate conductive portion 44. When the gate conductive portion 44 is made of polysilicon, its resistivity is higher than when it is made of an aluminum alloy or similar material. On the other hand, the charging and discharging of the MOS capacitor is required to eliminate (or form) the inversion layer of the MOS gate. During the charging and discharging of the MOS capacitor, a delay time is generated based on the electrostatic capacitance determined by the thickness of the gate insulating film 42 and the resistance of the gate conductive portion 44. The longer the length from the position of the gate metal layer 50 to the trench center position TP, the greater the resistance of the gate conductive portion 44. Therefore, the delay time required to charge the MOS capacitor at the trench center position TP becomes longer. Due to this increased delay time, the gate cutoff near the trench center position TP slows down, and charge carriers concentrate at the trench center position TP, generating a filament current. On the other hand, during turn-off, the depletion layer extends into the drift region 18, and the filament current exists in the depletion layer. Because a large number of charge carriers (holes) remain in the filament current, the slope of the electric field strength in the depletion layer increases, thus increasing the electric field strength. Consequently, due to the high current density (especially hole current), the impact ionization rate also increases, enhancing avalanche breakdown.

[0184] If the trench center position TP is located in a region less than 1000 μm from the corner 111, then the shortest distance R1a is less than 1000 μm. In this case, during the turn-off period, the electric field strength E(R1a) at the trench center position TP is more than 1.1 times that of Em. Therefore, at the trench center position TP, the electric field strength increases not only due to the filament current but also due to the spatial distortion of the electric field. Consequently, the impact ionization rate increases not only near the corner 111 but also at the trench center position TP, making avalanche breakdown more likely. As a result, positive current feedback occurs in the region including the corner 111 and the trench center position TP, increasing the likelihood of damage. Therefore, by setting the shortest distance R1a to be longer than 1000 μm, the distance R from the corner 111 at the trench center position TP is set to be 1000 μm or more. Therefore, by making the electric field strength E(R1a) less than 1.1 times Em, the enhanced avalanche breakdown at the corner 111 and the center position TP of the trench can be suppressed, and damage during shutdown can be prevented. Furthermore, the minimum distance R1a can also be set to 1500 μm or more.

[0185] Furthermore, the larger the conductive portion shape ratio α, the smaller the width Wg of the gate conductive portion 44, and the longer the trench length Lt. Therefore, the resistance of the gate conductive portion 44 from the position of the gate metal layer 50 to the center position TP of the trench increases. In other words, the charging and discharging of the gate conductive portion 44 near the center position TP of the trench generates a delay time, which easily leads to filament current. Therefore, within the range of the aforementioned conductive portion shape ratio α, the shortest distance R1a is set to 1000 μm or more. This can suppress the enhancement of avalanche breakdown at the corner 111 and the center position TP of the trench, and prevent damage during turn-off. The shortest distance R1a can be 1500 μm or more, 2000 μm or more, 3000 μm or more, or 5000 μm or more. The shortest distance R1a can be less than 20000 μm, less than 15000 μm, or less than 10000 μm.

[0186] Figure 6B This is a graph showing the relationship between the shortest distance R1a and the failure rate (%) of the cutoff tolerance. The failure rate of the cutoff tolerance refers to the proportion of semiconductor devices damaged due to shutdown. The cutoff current density and applied voltage can vary; for example, the conditions described above can be used. In this example, the failure rate of the cutoff tolerance is shown when the conductor shape ratio α is 6250 and when the conductor shape ratio α is 8750.

[0187] With a conductive portion shape ratio α of 6250, the trench length Lt is 5000 μm, and the width Wg of the gate conductive portion 44 is 0.8 μm. With a minimum distance R1a of 500 μm, the defect rate for cutoff tolerance is 50%. When the minimum distance R1a is 1000 μm, the defect rate decreases to 14%; when it is 1500 μm, the defect rate is 5%; and when it is 2000 μm, the defect rate is 2%.

[0188] With a conductive portion shape ratio α of 8750, the trench length Lt is 7000 μm, and the width Wg of the gate conductive portion 44 is 0.8 μm. When the shortest distance R1a is 500 μm, the defect rate for cutoff tolerance is 62%. When the shortest distance R1a is 1000 μm, the defect rate for cutoff tolerance decreases to 21%. Furthermore, when the shortest distance R1a is 1500 μm or more, the defect rate is significantly reduced to below 8%. Since the defect rate for cutoff tolerance can be below 30%, the shortest distance R1a can be 1000 μm or more, 1500 μm or more, 2000 μm or more, 3000 μm or more, or 5000 μm or more. It should be noted that although the shortest distance R1a has been described in this example, the shortest distances R1b, R2a, or R2b can also be described in the same way.

[0189] Figure 6C This indicates the rated voltage V. rate With rated current density J rate A graph showing the relationship between the two. The vertical axis represents the rated current density (J). rate (A / cm 2 The horizontal axis represents the rated voltage (V). In one example, the semiconductor device 100 can be designed to meet the following requirements: Figure 6C The rated voltage V of the clamping range between the upper limit P1 and the lower limit P2 rate and rated current density J rate .

[0190] For example, semiconductor device 100 can be designed to meet 400 (A / cm) at a rated voltage of 600 (V). 2 ) or above and 800 (A / cm 2 The rated current density is below 1200V. Additionally, the semiconductor device 100 can be designed to meet a current density of 300A / cm² at a rated voltage of 1200V. 2 ) or above and 600 (A / cm 2 The rated current density is below 1700V. The semiconductor device 100 can be designed to meet 200 A / cm² at a rated voltage of 1700V. 2 ) or above and 400 (A / cm 2 The rated current density is below 1.

[0191] Even when the trench length Lt is set to 2000 μm or more to achieve such characteristics, the semiconductor device 100 in this example can avoid device damage caused by filament current flowing into the P-type well region by appropriately setting the distance between the P-type well region and the center position TP of the trench.

[0192] The present invention has been described above using embodiments, but the technical scope of the present invention is not limited to the scope described in the above embodiments. It will be apparent to those skilled in the art that various modifications or improvements can be made to the above embodiments. As can be seen from the claims, such modifications or improvements can also be included within the technical scope of the present invention.

[0193] It should be noted that the execution order of the actions, processes, steps, and stages in the apparatus and methods shown in the claims, specification, and drawings can be implemented in any order unless specifically stated as "before" or "earlier," and as long as the output of the preceding process is not used in the subsequent process. Even if the flow of actions in the claims, specification, and drawings is described using terms such as "firstly" or "next" for convenience, it does not mean that the actions must be performed in that order.

Claims

1. A semiconductor device, characterized by comprising: have: The active part is disposed on the semiconductor substrate; Multiple trench portions having gate conductive portions are provided in the active portion, the multiple trench portions extending along a predetermined extension direction and arranged in a predetermined arrangement direction, the conductive portion shape ratio being 1000 or more, the conductive portion shape ratio being a ratio obtained by dividing the trench length in the extension direction by the width of the gate conductive portion in the arrangement direction. The first control pad, when viewed from above, protrudes from a predetermined first outer periphery of the semiconductor substrate toward the inside of the semiconductor substrate; as well as A first well region is disposed below the first control pad and configured to cover the first control pad when viewed from above. When viewed from above, the shortest distance between the first well region and the center of the trench is more than 1000 μm, and the center of the trench is the center of the length of the plurality of trench portions in the extension direction.

2. The semiconductor device according to claim 1, characterized in that, The shortest distance is 1500μm or more.

3. The semiconductor device according to claim 1, characterized in that, The shortest distance is 2000μm or more.

4. The semiconductor device according to any one of claims 1 to 3, characterized in that, The conductive portion shape ratio of the plurality of groove portions is 3000 or more and 1 x 10 6 The following.

5. The semiconductor device according to any one of claims 1 to 3, characterized in that, The plurality of trench portions includes a gate trench portion set to a gate potential. The shape ratio of the conductive portion of the gate trench portion is 5000 or more and 3 x 10 5 The following.

6. The semiconductor device according to any one of claims 1 to 3, characterized in that, The first control pad includes an anode pad, a cathode pad, and a sensing pad.

7. The semiconductor device according to any one of claims 1 to 3, characterized in that, The first well region is rectangular when viewed from above, and its three sides are arranged opposite to the active part.

8. The semiconductor device according to any one of claims 1 to 3, characterized in that, The first trap region has a corner portion that protrudes from the first outer periphery. The shortest distance is the distance between the corner of the first well area and the center of the trench.

9. The semiconductor device according to claim 8, characterized in that, The distance L1a from the central imaginary line to the corner of the first well region is more than 40% of the length from the central imaginary line to the outer periphery of the semiconductor substrate in a direction orthogonal to the central imaginary line, the central imaginary line being orthogonal to the first outer periphery and passing through the center of the first outer periphery.

10. The semiconductor device according to any one of claims 1 to 3, characterized in that, The first trap region is configured to be symmetrical with respect to a central imaginary line, which is orthogonal to the first outer perimeter and passes through the center of the first outer perimeter.

11. The semiconductor device according to any one of claims 1 to 3, characterized in that, The first trap region is configured to be asymmetrical with respect to a central imaginary line, which is orthogonal to the first outer perimeter and passes through the center of the first outer perimeter.

12. The semiconductor device according to any one of claims 1 to 3, characterized in that, The first well region has a notch that is partially cut off when viewed from above.

13. The semiconductor device according to claim 9, wherein have: A second control pad, when viewed from above, protrudes inward from a second outer periphery opposite to the first outer periphery toward the inside of the semiconductor substrate; and A second well region is disposed below the second control pad and configured to cover the second control pad when viewed from above. The second trap region has a corner portion that protrudes from the second outer periphery. The distance L1a is longer than the distance L2a in the extending direction from the central imaginary line to the corner of the second well region.

14. The semiconductor device according to claim 13, characterized in that, The second control pad includes a gate pad for setting the plurality of trench portions to a gate potential.

15. The semiconductor device according to any one of claims 1 to 3, characterized in that, The active part includes a transistor part and a diode part. When viewed from above, the corner of the first well region is located in the transistor section.

16. The semiconductor device according to any one of claims 1 to 3, characterized in that, The plurality of trench portions have a dummy trench region set as the emitter potential. When viewed from above, the corner of the first well region is located in the dummy trench region.

17. The semiconductor device according to any one of claims 1 to 3, characterized in that, The active part includes a transistor part and a diode part. When viewed from above, the corner of the first well region is located in the diode section.

18. The semiconductor device according to claim 17, characterized in that, The semiconductor device includes a protective film disposed above the semiconductor substrate. The diode portion has a lifetime control region on the front side of the semiconductor substrate. When viewed from above, the protective film is positioned to avoid the diode portion.

19. The semiconductor device according to any one of claims 1 to 3, characterized in that, When viewed from above, the direction of extension is parallel to the first outer periphery.

20. The semiconductor device according to any one of claims 1 to 3, characterized in that, When viewed from above, the direction of extension is orthogonal to the first outer periphery.

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