Delay adjusting device, delay control method, computer device and storage medium

Abstract

The application relates to a time delay adjusting device, a time delay control method, a computer device and a storage medium, wherein the time delay adjusting device comprises a time delay module and a control module; the time delay module is configured with a time clock signal input end, a time clock signal output end and a control signal input end; the time clock signal input end is used for inputting a time clock signal; the time clock signal output end is used for outputting the time clock signal after time delay processing; the control module connected with the control signal input end of the time delay module generates a time delay adjusting instruction according to a time delay demand; the time delay adjusting instruction is used for controlling the time delay module to perform time delay processing on the time clock signal to adjust a time delay value of the time clock signal, so that the time delay value of the time clock signal meets a preset time clock balance demand; the time delay value of the time clock signal is adjustable, the time delay value is linearly distributed, the time clock balance efficiency is improved, and the fast convergence of a time sequence is ensured.

Description

Technical Field

[0001] This application relates to the field of chip design, and in particular to a delay adjustment device, a delay control method, a computer device, and a storage medium. Background Technology

[0002] As chip technology continues to develop and chip applications become increasingly diverse, the demand for chip functionality is increasing. Larger chips consisting of hundreds of millions or billions of transistors are becoming more and more common, and clock signal balance is crucial for the design of large chips.

[0003] Existing techniques for achieving clock signal balance mainly involve adding or removing clock buffers at the end of the clock network or at the clock input port of the component module, which cannot meet the clock requirements of large chips. Summary of the Invention

[0004] Therefore, it is necessary to provide a delay adjustment device, a delay control method, a computer device, and a storage medium to address the aforementioned technical problems.

[0005] A delay adjustment device, comprising:

[0006] The delay module is configured with a clock signal input terminal, a clock signal output terminal, and a control signal input terminal. The clock signal input terminal is used to input a clock signal, and the clock signal output terminal is used to output the clock signal after delay processing.

[0007] The control module is connected to the control signal input terminal of the delay module and is used to generate a delay adjustment command according to the delay requirement. The delay adjustment command is used to control the delay module to perform delay processing on the clock signal to adjust the delay value of the clock signal so that the delay value of the clock signal meets the preset clock balance requirement.

[0008] In one embodiment, the delay module includes:

[0009] A first clock buffer unit, the input terminal of the first clock buffer unit is connected to the clock signal input terminal, the first clock buffer unit is used to receive the clock signal, and perform a first delay processing on the clock signal through multiple first transmission links, the delay parameters of different first transmission links are different, and each first transmission link is connected to an output terminal of the first clock buffer unit;

[0010] A multiplexing unit is provided, wherein the input terminals of the multiplexing unit are respectively connected to the multiple output terminals of the first clock buffer unit, the controlled terminal of the multiplexing unit is connected to the control signal output terminal of the control module, the multiplexing unit is used to receive the delay adjustment command, and select to receive the clock signal output from the first transmission link according to the delay adjustment command, and the output terminal of the multiplexing unit is used to output the clock signal.

[0011] In one embodiment, the multiplexing unit is further configured to select a second transmission link through which the clock signal is transmitted in the multiplexing unit according to the delay adjustment instruction, so as to perform a second delay processing on the clock signal; the delay adjustment device further includes:

[0012] The second clock buffer unit has its input terminal connected to the output terminal of the multiplexing unit and its output terminal connected to the clock signal output terminal. The second clock buffer unit is used to perform a third delay processing on the clock signal after receiving the clock signal after the second delay processing and then output the clock signal.

[0013] In one embodiment, the first transmission link, the second transmission link, and the second clock buffer unit construct a target delay link, such that the clock signal is transmitted in the target delay link to adjust the delay value of the clock signal.

[0014] In one embodiment, the multiplexing unit includes a multi-stage multiplexer, with the output of the current stage multiplexer connected to the input of the next stage multiplexer; the input of the primary multiplexer is connected to the output of the first clock buffer unit, and the output of the final stage multiplexer is connected to the input of the second clock buffer unit.

[0015] The first clock buffer unit includes multiple levels of clock buffers. The output of the current level clock buffer is connected to the input of the next level clock buffer and the input of the primary multiplexer, respectively. The outputs of every two adjacent levels of the clock buffer are connected to the input of the same primary multiplexer.

[0016] In one embodiment, the multi-level clock buffers are of the same type, and the multi-level multiplexers are of the same type.

[0017] In one embodiment, each current-level clock buffer is connected to the next-level clock buffer and the primary multiplexer via a buffered transmission line.

[0018] In one embodiment, it further includes:

[0019] Decoupling module;

[0020] In the delay module, there is a gap between each pair of adjacent devices, and the gap is equipped with the decoupling module to make the delay value of the clock signal change linearly, so that the delay value of the clock signal meets the preset clock balance requirement.

[0021] In one embodiment, the decoupling module includes a decoupling capacitor composed of transistors.

[0022] In one embodiment, the control module, the delay module, and the decoupling module are all manufactured using a 10nm to 40nm process technology.

[0023] A delay control method, comprising:

[0024] A delay adjustment instruction is generated based on the delay requirement. The delay adjustment instruction is used to control the delay module to perform delay processing on the received clock signal to adjust the delay value of the clock signal so that the delay value of the clock signal meets the preset clock balance requirement.

[0025] The delay module is configured with a clock signal input terminal and a clock signal output terminal. The clock signal input terminal is used to input a clock signal, and the clock signal output terminal is used to output the clock signal after delay processing.

[0026] A computer device includes a memory and a processor, wherein the memory stores a computer program that, when executed by the processor, causes the processor to perform the steps of the method described above.

[0027] A computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the method described above.

[0028] The aforementioned delay adjustment device, delay control method, computer equipment, and storage medium, wherein the delay adjustment device includes a delay module and a control module. The delay module is configured with a clock signal input terminal, a clock signal output terminal, and a control signal input terminal. The clock signal input terminal is used to input a clock signal, and the clock signal output terminal is used to output the clock signal after delay processing. The control module, connected to the control signal input terminal of the delay module, generates a delay adjustment command according to the delay requirements. The delay adjustment command is used to control the delay module to perform delay processing on the clock signal to adjust the delay value of the clock signal so that the delay value of the clock signal meets the preset clock balance requirements. This achieves the adjustability of the clock signal delay value, so that the delay value is linearly distributed, thereby improving the clock balance efficiency and ensuring rapid convergence of timing. Attached Figure Description

[0029] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0030] Figure 1 This is a schematic block diagram of the delay adjustment device in one embodiment;

[0031] Figure 2 This is a schematic block diagram of the specific structure of the delay module in one embodiment;

[0032] Figure 3 This is a schematic block diagram of the specific structure of the delay module in one embodiment;

[0033] Figure 4 This is a schematic diagram of the delay module in one embodiment;

[0034] Figure 5 This is a schematic diagram of the layout of the delay adjustment device in one embodiment. Detailed Implementation

[0035] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0036] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0037] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising,” “including,” or “having,” etc., specify the presence of the stated feature, whole, step, operation, component, part, or combination thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof.

[0038] See Figure 1 This is a schematic block diagram of the delay adjustment device in one embodiment.

[0039] In this embodiment, the application scenarios of the delay adjustment device include global clock balancing scenarios and local clock balancing scenarios for large chips; such as Figure 1 As shown, the delay adjustment device includes a delay module 120 and a control module 140.

[0040] The delay module 120 is configured with a clock signal input terminal, a clock signal output terminal and a control signal input terminal. The clock signal input terminal is used to input a clock signal, and the clock signal output terminal is used to output the clock signal after delay processing.

[0041] Optionally, the delay module 120 may be a standard delay unit combination for receiving a clock signal, performing delay processing on the clock signal to increase the delay value of the clock signal, and outputting the delayed clock signal; the standard delay unit combination may be composed of multiple standard delay units connected in a certain order.

[0042] Optionally, the clock signal input terminal may be a port connected to the standard delay unit combination and used to input a clock signal to the standard delay unit combination; the clock signal output terminal may be a port connected to the standard delay unit combination and used to output the delayed clock signal to the standard delay unit combination.

[0043] Optionally, the control signal may be a signal used to control the delay module to perform delay processing on the clock signal, and the control signal may be a voltage signal or a current signal; the control signal input terminal may be a port connected to the standard delay unit combination and used to input control signals to the standard delay unit combination.

[0044] The control module 140 is connected to the control signal input terminal of the delay module 120 and is used to generate a delay adjustment command according to the delay requirement. The delay adjustment command is used to control the delay module 120 to perform delay processing on the clock signal to adjust the delay value of the clock signal so that the delay value of the clock signal meets the preset clock balance requirement.

[0045] Optionally, the control module 140 may be a controller for generating delay adjustment instructions based on the delay requirements of the current application scenario; the delay requirements may be the delay value requirements of the clock signal under a global clock balance scenario or a local clock balance scenario; the delay adjustment instructions may be instructions for adjusting the delay value of the clock signal so that the delay value of the clock signal meets the preset clock balance requirements.

[0046] Optionally, the preset clock balance requirement may be a delay value pre-set in a global clock balance scenario or a local clock balance scenario to achieve a clock balance state for the clock signal; the delay processing may be a process of adjusting the delay value of the clock signal using the standard delay unit combination so that the delay value of the clock signal meets the preset clock balance requirement.

[0047] Specifically, when a large-chip integrated circuit requires global clock balancing, the control module generates a delay adjustment command based on the delay requirements under the global clock balancing scenario, and inputs the delay adjustment command to the delay module via the control signal input terminal. The delay module performs delay processing on the clock signal input to the delay module according to the delay adjustment command to adjust the delay value of the clock signal, so that the delay value of the clock signal meets the delay value pre-set for achieving clock balancing under the global clock balancing scenario; thus realizing the adjustability of the clock signal delay value, making the delay value linearly distributed, thereby improving clock balancing efficiency and ensuring rapid timing convergence.

[0048] The delay adjustment device provided in this embodiment includes a delay module and a control module. The delay module is configured with a clock signal input terminal, a clock signal output terminal, and a control signal input terminal. The clock signal input terminal is used to input a clock signal, and the clock signal output terminal is used to output the clock signal after delay processing. The control module, connected to the control signal input terminal of the delay module, generates a delay adjustment command according to the delay requirements. The delay adjustment command is used to control the delay module to perform delay processing on the clock signal to adjust the delay value of the clock signal so that the delay value of the clock signal meets the preset clock balance requirements. This achieves the adjustability of the clock signal delay value, so that the delay value is linearly distributed, thereby improving the clock balance efficiency and ensuring rapid convergence of timing.

[0049] See Figure 2 This is a schematic block diagram of the specific structure of the delay module in one embodiment.

[0050] In this embodiment, as Figure 2 As shown, the delay module includes a first clock buffer unit 220 and a multiplexing unit 240.

[0051] A first clock buffer unit 220 is configured to receive the clock signal and perform a first delay processing on the clock signal through multiple first transmission links. The delay parameters of different first transmission links are different, and each first transmission link is connected to an output of the first clock buffer unit 220.

[0052] Optionally, the first clock buffer unit 220 may be a multi-level clock buffer for receiving the clock signal and performing a first delay processing on the clock signal through multiple first transmission links.

[0053] Optionally, the input terminal of the first clock buffer unit 220 may be a port connected to the multi-level clock buffer and used to input clock signals into the multi-level clock buffer; the output terminal of the first clock buffer unit 220 may be a port connected to the multi-level clock buffer and used to output clock signals for delay processing.

[0054] Optionally, the first transmission link may be the transmission link in the first clock buffer unit 220 used to transmit the clock signal for performing a first delay processing on the clock signal; the first delay processing may be the process of adjusting the delay value of the clock signal using the multi-level clock buffer so that the delay value of the clock signal meets the preset clock balance requirements.

[0055] It should be noted that different first transmission links have different delay parameters, and the magnitude of the delay parameter can determine the magnitude of the delay value of the clock signal during transmission on the first transmission link. Therefore, when the delay requirements in the global clock balancing scenario or the local clock balancing scenario are different, the clock signal can select different first transmission links to meet the preset clock balancing requirements.

[0056] A multiplexing unit 240 is provided, with its input terminals connected one-to-one with the multiple output terminals of the first clock buffer unit 220, and its controlled terminal connected to the control signal output terminal of the control module. The multiplexing unit 240 is used to receive the delay adjustment command and select the clock signal output from the first transmission link according to the delay adjustment command. The output terminal of the multiplexing unit 240 is used to output the clock signal.

[0057] Optionally, the multiplexing unit 240 may be a multiplexer for receiving the delay adjustment instruction, selecting to receive the clock signal output from the first transmission link and outputting the clock signal according to the delay adjustment instruction.

[0058] Optionally, the input terminal of the multiplexing unit 240 may be a port connected to the multiplexer and used to receive the clock signal output from the first transmission link; the controlled terminal of the multiplexing unit 240 may be a port connected to the control signal output terminal of the control module and used to receive the delay adjustment command.

[0059] It should be noted that the multiplexer includes multiple input terminals, and the delay parameters of the clock signals output from different input terminals can be the same or different. Therefore, when the delay requirements in the global clock balance scenario or the local clock balance scenario are different, the multiplexer selects different input terminals to receive the clock signal output from the first transmission link according to the delay adjustment instruction, and outputs clock signals with different delay parameters to meet the preset clock balance requirements.

[0060] The delay adjustment device provided in this embodiment receives the clock signal through a first clock buffer unit whose input terminal is connected to the clock signal input terminal, and performs a first delay processing on the clock signal through multiple first transmission links; a multiplexer unit whose input terminal is connected to each of the multiple output terminals of the first clock buffer unit and whose controlled terminal is connected to the control signal output terminal of the control module receives the delay adjustment command and selects to receive the clock signal output from the first transmission link according to the delay adjustment command, and the output terminal of the multiplexer unit outputs the clock signal; thereby realizing the adjustability of the clock signal delay value so that the delay value is linearly distributed, thereby improving the clock balancing efficiency and ensuring the rapid convergence of timing.

[0061] In one embodiment, the multiplexing unit further selects a second transmission link through which the clock signal is transmitted in the multiplexing unit according to the delay adjustment instruction, so as to perform a second delay processing on the clock signal; such as Figure 3 As shown, the delay adjustment device includes a first clock buffer unit 320 and a multiplexing unit 340, and the delay adjustment device also includes a second clock buffer unit 360.

[0062] A first clock buffer unit 320 is configured to receive the clock signal and perform a first delay processing on the clock signal through multiple first transmission links. The delay parameters of different first transmission links are different, and each first transmission link is connected to an output of the first clock buffer unit 320.

[0063] A multiplexing unit 340 is provided, with its input terminals connected one-to-one with the multiple output terminals of the first clock buffer unit 320. The controlled terminal of the multiplexing unit 340 is connected to the control signal output terminal of the control module. The multiplexing unit 340 is used to receive the delay adjustment command and select the clock signal output from the first transmission link according to the delay adjustment command. The output terminal of the multiplexing unit 340 is used to output the clock signal.

[0064] In this embodiment, the first clock buffer unit 320 and the multiplexing unit 340 are executed in Figure 2 In the corresponding embodiment, the first clock buffer unit 220 and the multiplexing unit 240 are described in detail. Figure 2 as well as Figure 2 The relevant descriptions in the corresponding embodiments will not be repeated here.

[0065] The second clock buffer unit 360 has its input terminal connected to the output terminal of the multiplexing unit and its output terminal connected to the clock signal output terminal. The second clock buffer unit is used to perform a third delay processing on the clock signal after receiving the clock signal after the second delay processing and then output the clock signal.

[0066] Optionally, the second clock buffer unit 360 may be a clock buffer used to perform a third delay processing on the clock signal after receiving the clock signal after the second delay processing and output the clock signal.

[0067] Optionally, the second transmission link may be a transmission link in the second clock buffer unit 360 used to transmit the clock signal for a second delay processing of the clock signal; the second delay processing may be a process of adjusting the delay value of the clock signal using the multiplexer so that the delay value of the clock signal meets the preset clock balance requirements.

[0068] It should be noted that different second transmission links have different delay parameters, and the magnitude of these delay parameters determines the magnitude of the clock signal's delay value during transmission through the second transmission link. Therefore, when the delay requirements differ under the global clock balancing scenario or the local clock balancing scenario, the clock signal can select different second transmission links to meet the preset clock balancing requirements.

[0069] Optionally, the third delay processing may be a process of adjusting the delay value of the clock signal using the clock buffer so that the delay value of the clock signal meets the preset clock balance requirements.

[0070] It should be noted that the multi-level clock buffers used to form the first clock buffer unit and the clock buffers used to form the second clock buffer unit are of the same type; the number of clock buffers forming the first clock buffer unit is at least 2, while the number of clock buffers forming the second clock buffer unit 360 is at least 1; specifically, the clock buffer can be one type of clock buffer from TSMC's 10nm to 40nm standard cell library.

[0071] Specifically, the multiplexing unit 340 includes a multi-stage multiplexer, with the output of the current stage multiplexer connected to the input of the next stage multiplexer; the input of the primary multiplexer is connected to the output of the first clock buffer unit, and the output of the final stage multiplexer is connected to the input of the second clock buffer unit; the multi-stage multiplexers are of the same type, specifically, the multiplexer can be a certain clock multiplexer from TSMC's 10nm to 40nm standard cell library.

[0072] See Figure 4 This is a schematic diagram of the delay module in one embodiment.

[0073] In this embodiment, as Figure 4 As shown, the delay module includes a first clock buffer unit, a multiplexer unit, and a second clock buffer unit; the first clock buffer unit is a multi-level clock buffer composed of 16 clock buffers, the multiplexer unit is a multi-level multiplexer composed of 15 multiplexers, and the second clock buffer unit is a clock buffer BUF_OUT.

[0074] Optionally, each current-level clock buffer is connected to the next-level clock buffer and the primary multiplexer via a buffer transmission line, and the output of the primary multiplexer is connected to the input of the next-level multiplexer.

[0075] Optionally, the first clock buffer unit includes multiple levels of clock buffers. The output of the current level clock buffer is connected to the input of the next level clock buffer and the input of the primary multiplexer, respectively. The outputs of every two adjacent levels of the clock buffer are connected to the input of the same primary multiplexer.

[0076] like Figure 4As shown, the 16 clock buffers are BUF_0, BUF_1, ..., BUF_15; the 15 multiplexers are MUX_3_0, MUX_3_1, ..., MUX_3_7, MUX_2_0, MUX_2_1, MUX_2_2, MUX_2_3, MUX_1_0, MUX_1_1, MUX_0_0 (hereinafter abbreviated as MUX_M_N, for example, MUX_1_N includes MUX_1_0 and MUX_0_0).

[0077] like Figure 4 As shown, the clock signal input terminal of the delay module is the clk_in interface, the clock signal output terminal of the delay module is the clk_out interface, and the control signal input terminals of the delay module are four types of interfaces: S3, S2, S1, and S0. When a large-chip integrated circuit requires global clock balancing, the clock signal enters from the clk_in interface, which is the clock signal input terminal. After delay processing, it exits from the clk_out interface, which is the clock signal output terminal.

[0078] Optionally, interface S3 controls the selection of input signals for all MUX_3_N. When interface S3 outputs 0, all MUX_3_N selects the input signal of its input interface labeled 0 to transmit to the output terminal; when interface S3 outputs 1, all MUX_3_N selects its first input terminal to transmit the clock signal to the output terminal; and so on. The same applies to interface S2 for MUX_2_N, interface S1 for MUX_1_N, and interface S0 for MUX_0_N.

[0079] The clock signal is input through the clk_in interface, and then passes through a series of TSMC standard delay units (as described above, such as...). Figure 1 As shown, when the clk_out interface outputs, a clock signal with a delay value compared to the clk_in interface is obtained. The delay value can be adjusted through four interfaces: S3, S2, S1, and S0.

[0080] Continue reading Figure 4 The total delay between the clk_out interface output and the clk_in interface input is denoted as T. Depending on the adjustment of the four interfaces S3, S2, S1, and S0, all four can output 0 or 1, and the corresponding total delay is recorded as T_S3S2S1S0. For example, when S3 outputs 0, S2 outputs 1, S1 outputs 1, and S0 outputs 0, the corresponding total delay is recorded as T_0110.

[0081] When S3 outputs 0, S2 outputs 0, S1 outputs 0, and S0 outputs 0, only BUF_0, MUX_3_0, MUX_2_0, MUX_1_0, MUX_0_0, and BUF_OUT are active in the clock signal output and input connection link to construct the target delay link. At this time, the delay value is the minimum, which is the delay of one clock buffer BUF_X (abbreviated as T_A). Figure 4 The total delay is the sum of the delays of the four MUX_M_N (multiplexers) (the delay of each MUX_M_N is denoted as T_M, so the delay of the four MUX_M_N is 4*T_M), and the delay of one BUF_OUT (denoted as T_B). The total delay value is then expressed as T_0000 = T_A + 4*T_M + T_B.

[0082] When S3 outputs 1, S2 outputs 0, S1 outputs 0, and S0 outputs 0, BUF_0, BUF_1, MUX_3_0, MUX_2_0, MUX_1_0, and MUX_0_0 function in the clock signal output and input connection link to construct the target delay link. At this time, the delay value is 2 BUF_X (standard delay units) and... Figure 4 The total delay is the sum of the delays of the four MUX_M_N (multiplexers) and the delay of the 1 BUF_OUT, and is expressed as T_1000 = 2*T_A + 4*T_M + T_B.

[0083] Similarly, when S3 outputs 1, S2 outputs 1, S1 outputs 1, and S0 outputs 1, the delay value is at its maximum, which is the sum of the delays of 16 BUF_X and 4 MUX_M_N (multiplexers), plus the delay of 1 BUF_OUT, specifically expressed as T_1111 = 16 * T_A + 4 * T_M + T_B. Therefore, from T_0000 to T_1111, there are a total of 16 delay value options, and the difference between adjacent delay values ​​is the delay T_A of one clock buffer BUF_X, thus achieving linear selection of the clock signal delay value.

[0084] In addition, the buffered transmission lines are BUF_0_net, BUF_1_net, ..., BUF_15_net, MUX_3_0_net, MUX_3_1_net, ..., MUX_3_7_net, MUX_2_0_net, MUX_2_1_net, MUX_2_2_net, MUX_2_3_net, MUX_1_0_net, MUX_1_1_net, and MUX_0_0_net.

[0085] When S3 outputs 1, S2 outputs 0, S1 outputs 1, and S0 outputs 0, the clock signal output through BUF_5 will be transmitted through MUX_3_2, MUX_2_1, MUX_1_1, MUX_0_0, and BUF_OUT. The specific target delay link is as follows: The clock signal is input from interface clk_in to BUF_0, transmitted through BUF_0_net to BUF_1, then through BUF_1_net to BUF_2, then through BUF_2_net to BUF_3, then through BUF_3_net to BUF_4, then through BUF_4_net to BUF_5, then through BUF_5_net to the second input of MUX_3_2, then from the output of MUX_3_2 through MUX_3_net to the first input of MUX_2_1, then from the output of MUX_2_1 through MUX_2_1_net to the second input of MUX_1_0, then from the output of MUX_1_0 through MUX_1_0_net to the first input of MUX_0_0, then through MUX_0_0_net to the input of BUF_OUT, and finally output through interface clk_out after delay processing.

[0086] The delay adjustment device provided in this embodiment constructs a target delay link through the first transmission link, the second transmission link, and the second clock buffer unit, so that the clock signal is transmitted in the target delay link to adjust the delay value of the clock signal; thereby realizing the adjustability of the clock signal delay value so that the delay value is linearly distributed, thereby improving the clock balancing efficiency and ensuring the rapid convergence of timing.

[0087] See Figure 5 This is a schematic diagram of the layout of the delay adjustment device in one embodiment.

[0088] In this embodiment, the delay adjustment device includes a delay module and a decoupling module; such as Figure 5 As shown, the delay module includes a first clock buffer unit, a multiplexer unit, and a second clock buffer unit; the first clock buffer unit is a multi-level clock buffer composed of 16 clock buffers, the multiplexer unit is a multi-level multiplexer composed of 15 multiplexers, and the second clock buffer unit is a clock buffer BUF_OUT; the delay module includes 16 clock buffers BUF_0, BUF_1, ..., BUF_15, and 15 multiplexers MUX_3_0, MUX_3_1, ..., MUX_3_7, MUX_2_0, MUX_2_1, MUX_2_2, MUX_2_3, MUX_1_0, MUX_1_1, MUX_0_0; the decoupling module is FI.

[0089] In this delay module, there is a gap between each pair of adjacent devices, and the gap is equipped with the decoupling module to make the delay value of the clock signal change linearly, so that the delay value of the clock signal meets the preset clock balance requirement.

[0090] Optionally, the decoupling module may be a decoupling unit with energy storage function disposed between multiple standard delay units; specifically, the decoupling module is a decoupling unit from TSMC's 10nm to 40nm standard cell library, and the decoupling unit may be a decoupling capacitor composed of MOS transistors. This layout not only greatly facilitates wiring and ensures uniform delay values ​​for the clock signal, but also minimizes problems caused by voltage drop.

[0091] In one embodiment, the delay adjustment device includes the control module, the delay module, and the decoupling module, all of which are fabricated using 10nm to 40nm process technology.

[0092] In one embodiment, the wiring of the delay module uses only 5 metal layers, including a first metal layer M1, a second metal layer M2, a third metal layer M3, a fourth metal layer VIA1, and a fifth metal layer VIA2. The first metal layer M1 is connected to the second metal layer M2 through the fourth metal layer VIA1, and the second metal layer M2 is connected to the third metal layer M3 through the fifth metal layer VIA2.

[0093] Optionally, the second metal layer M2 and the third metal layer M3 are provided with a clock signal input terminal, a clock signal output terminal and a control signal input terminal of the delay module.

[0094] It should be noted that when designing integrated circuit chips using the same process, the delay module can be conveniently invoked to balance the global or local clocks on the integrated circuit chip. Only the clock signal input, clock signal output, and control signal input terminals of the delay module need to be connected as required. Since the delay module only uses these few metal layers, it occupies very little wiring resources, while other metal layers are not occupied. This provides ample wiring space for designs that utilize the delay module. Besides saving wiring resources, the wiring also ensures that signal line lengths are as consistent as possible, maximizing the linear distribution of delay values.

[0095] This application also provides a delay control method, the delay control method comprising: generating a delay adjustment instruction according to a delay requirement, the delay adjustment instruction being used to control a delay module to perform delay processing on a received clock signal to adjust the delay value of the clock signal so that the delay value of the clock signal meets a preset clock balance requirement; wherein, the delay module is configured with a clock signal input terminal and a clock signal output terminal, the clock signal input terminal being used to input a clock signal, and the clock signal output terminal being used to output the clock signal after delay processing.

[0096] In this embodiment, the steps are performed at Figure 1 In the corresponding embodiment, the control module 140 is described in detail. Figure 1 as well as Figure 1 The relevant descriptions in the corresponding embodiments will not be repeated here.

[0097] The delay control method provided in this embodiment generates a delay adjustment instruction based on the delay requirement. The delay adjustment instruction is used to control the delay module to perform delay processing on the received clock signal to adjust the delay value of the clock signal so that the delay value of the clock signal meets the preset clock balance requirement; thereby realizing the adjustability of the clock signal delay value so that the delay value is linearly distributed, thereby improving the clock balance efficiency and ensuring the rapid convergence of timing.

[0098] The division of the various modules in the above-described delay adjustment device is only for illustrative purposes. In other embodiments, the delay adjustment device can be divided into different modules as needed to complete all or part of the functions of the above-described delay adjustment device.

[0099] Specific limitations regarding the delay adjustment device can be found in the limitations of the delay control method described above, and will not be repeated here. Each module in the aforementioned delay adjustment device can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in hardware or independently of the processor in the computer device, or stored in software in the memory of the computer device, so that the processor can call and execute the operations corresponding to each module.

[0100] This application also provides a computer device, including a memory and a processor. The memory stores a computer program, and when the computer program is executed by the processor, the processor performs the steps of the method as described in the above embodiments.

[0101] This application also provides a computer-readable storage medium. One or more non-volatile computer-readable storage media containing computer-executable instructions, which, when executed by one or more processors, cause the processors to perform the steps of a delay control method.

[0102] The delay adjustment device, delay control method, computer equipment, and storage medium provided in the above embodiments enable the adjustability of the clock signal delay value so that the delay value is linearly distributed, thereby improving the clock balancing efficiency and ensuring the rapid convergence of timing. They have significant economic value and practical application value.

[0103] Any references to memory, storage, databases, or other media used in this application may include non-volatile and / or volatile memory. Non-volatile memory may include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memory may include random access memory (RAM), which is used as external cache memory. By way of illustration and not limitation, RAM is available in a variety of forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), dual data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), RAMbus direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and RAMbus dynamic RAM (RDRAM).

[0104] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0105] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A time delay adjustment device, characterized by, include: The delay module is configured with a clock signal input terminal, a clock signal output terminal, and a control signal input terminal. The clock signal input terminal is used to input a clock signal, and the clock signal output terminal is used to output the clock signal after delay processing. The control module is connected to the control signal input terminal of the delay module and is used to generate a delay adjustment command according to the delay requirements. The delay adjustment command is used to control the delay module to perform delay processing on the clock signal to adjust the delay value of the clock signal so that the delay value of the clock signal meets the preset clock balance requirements. The delay module includes: A first clock buffer unit, the input terminal of the first clock buffer unit is connected to the clock signal input terminal, the first clock buffer unit is used to receive the clock signal, and perform a first delay processing on the clock signal through multiple first transmission links, the delay parameters of different first transmission links are different, and each first transmission link is connected to an output terminal of the first clock buffer unit; A multiplexing unit is provided, wherein the input terminals of the multiplexing unit are respectively connected to the multiple output terminals of the first clock buffer unit, the controlled terminal of the multiplexing unit is connected to the control signal output terminal of the control module, the multiplexing unit is used to receive the delay adjustment command, and select to receive the clock signal output by the first transmission link according to the delay adjustment command, and the output terminal of the multiplexing unit is used to output the clock signal. The multiplexing unit is further configured to select a second transmission link for transmitting the clock signal in the multiplexing unit according to the delay adjustment instruction, so as to perform a second delay processing on the clock signal; The delay adjustment device further includes: The second clock buffer unit has its input terminal connected to the output terminal of the multiplexing unit and its output terminal connected to the clock signal output terminal. The second clock buffer unit is used to perform a third delay processing on the clock signal after receiving the clock signal after the second delay processing and then output the clock signal.

2. The delay adjustment apparatus according to claim 1, characterized by The first transmission link, the second transmission link, and the second clock buffer unit construct a target delay link, so that the clock signal is transmitted in the target delay link to adjust the delay value of the clock signal.

3. The delay adjustment apparatus of claim 1, wherein The multiplexing unit includes multiplexers of different stages. The output of the current stage multiplexer is connected to the input of the next stage multiplexer. The input of the primary multiplexer is connected to the output of the first clock buffer unit, and the output of the final stage multiplexer is connected to the input of the second clock buffer unit. The first clock buffer unit includes multiple levels of clock buffers. The output of the current level clock buffer is connected to the input of the next level clock buffer and the input of the primary multiplexer, respectively. The outputs of every two adjacent levels of the clock buffer are connected to the input of the same primary multiplexer.

4. The delay adjustment apparatus of claim 3, wherein The multi-level clock buffers are all of the same type, and the multi-level multiplexers are all of the same type.

5. The delay adjustment apparatus of claim 3, wherein Each current-level clock buffer is connected to the next-level clock buffer and the primary multiplexer via a buffered transmission line.

6. The delay adjustment apparatus of claim 3, wherein Also includes: Decoupling module; In the delay module, there is a gap between each pair of adjacent devices, and the gap is equipped with the decoupling module to make the delay value of the clock signal change linearly, so that the delay value of the clock signal meets the preset clock balance requirement.

7. The delay adjustment apparatus of claim 6, wherein The decoupling module includes decoupling capacitors composed of transistors.

8. The delay adjustment apparatus of claim 6, wherein The control module, the delay module, and the decoupling module are all manufactured using 10nm to 40nm process technology.

9. A delay control method, characterized in that, The delay control method is executed by the delay adjustment device according to any one of claims 1-8, and the delay control method includes: A delay adjustment instruction is generated based on the delay requirement. The delay adjustment instruction is used to control the delay module to perform delay processing on the received clock signal to adjust the delay value of the clock signal so that the delay value of the clock signal meets the preset clock balance requirement. The delay module is configured with a clock signal input terminal and a clock signal output terminal. The clock signal input terminal is used to input a clock signal, and the clock signal output terminal is used to output the clock signal after delay processing. The delay module is also configured with: A first clock buffer unit, the input terminal of the first clock buffer unit is connected to the clock signal input terminal, the first clock buffer unit is used to receive the clock signal, and perform a first delay processing on the clock signal through multiple first transmission links, the delay parameters of different first transmission links are different, and each first transmission link is connected to an output terminal of the first clock buffer unit; A multiplexing unit is provided, wherein the input terminals of the multiplexing unit are respectively connected to the multiple output terminals of the first clock buffer unit, the controlled terminal of the multiplexing unit is connected to the control signal output terminal of the control module, the multiplexing unit is used to receive the delay adjustment command, and select to receive the clock signal output by the first transmission link according to the delay adjustment command, and the output terminal of the multiplexing unit is used to output the clock signal. The multiplexing unit is further configured to select a second transmission link for transmitting the clock signal in the multiplexing unit according to the delay adjustment instruction, so as to perform a second delay processing on the clock signal; The second clock buffer unit has its input terminal connected to the output terminal of the multiplexing unit and its output terminal connected to the clock signal output terminal. The second clock buffer unit is used to perform a third delay processing on the clock signal after receiving the clock signal after the second delay processing and then output the clock signal.

10. A computer device, characterized in that, The method includes a memory and a processor, wherein the memory stores a computer program that, when executed by the processor, causes the processor to perform the steps of the method as described in claim 9.

11. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the steps of the method as described in claim 9.

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